History log of /linux-master/drivers/iio/adc/ad7944.c
Revision Date Author Comments
# 64ce7d43 25-Apr-2024 David Lechner <dlechner@baylibre.com>

iio: adc: ad7944: add support for chain mode

This adds support for the chain mode of the AD7944 ADC. This mode allows
multiple ADCs to be daisy-chained together. Data from all of the ADCs in
is read by reading multiple words from the first ADC in the chain.

Each chip in the chain adds an extra IIO input voltage channel to the
IIO device.

Only the wiring configuration where the SPI controller CS line is
connected to the CNV pin of all of the ADCs in the chain is supported
in this patch.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20240425-iio-ad7944-chain-mode-v1-1-9d9220ff21e1@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


# 61c8031a 12-Apr-2024 David Lechner <dlechner@baylibre.com>

iio: adc: ad7944: Consolidate spi_sync() wrapper

Since commit 6020ca4de8e5 ("iio: adc: ad7944: use spi_optimize_message()"),
The helper functions wrapping spi_sync() for 3-wire and 4-wire modes are
virtually identical. Since gpiod_set_value_cansleep() does a NULL check
internally, we can consolidate the two functions into one and avoid
switch statements at the call sites.

The default cases of the removed switch statement were just to make the
compiler happy and are not reachable since the mode is validated in the
probe function. So removing those should be safe.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20240412-ad7944-consolidate-msg-v1-1-7fdeff89172f@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


# 6020ca4d 28-Mar-2024 David Lechner <dlechner@baylibre.com>

iio: adc: ad7944: use spi_optimize_message()

This modifies the ad7944 driver to use spi_optimize_message() to reduce
CPU usage and increase the max sample rate by avoiding repeating
validation of the spi message on each transfer.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20240328-ad7944-spi-optimize-message-v2-1-a142b2576379@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


# 27eea477 25-Mar-2024 David Lechner <dlechner@baylibre.com>

iio: adc: ad7944: simplify adi,spi-mode property parsing

This simplifies the adi,spi-mode property parsing by using
device_property_match_property_string() instead of two separate
functions. Also, the error return value is now more informative
in cases where there was a problem parsing the property.

Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20240325-ad7944-cleanups-v3-1-3a19120cdd06@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


# 346ae0e8 13-Mar-2024 David Lechner <dlechner@baylibre.com>

iio: adc: ad7944: Add support for "3-wire mode"

This adds support for AD7944 ADCs wired in "3-wire mode". (NOTE: 3-wire
is the datasheet name for this wiring configuration and has nothing to
do with SPI_3WIRE.)

In the 3-wire mode, the SPI controller CS line can be wired to the CNV
line on the ADC and used to trigger conversions rather that using a
separate GPIO line.

The turbo/chain mode compatibility check at the end of the probe
function is technically can't be triggered right now but adding it now
anyway so that we don't forget to add it later when support for
daisy-chaining is added.

Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20240314-mainline-ad7944-3-wire-mode-v2-1-d469da0705d2@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>


# d1efcf88 04-Mar-2024 David Lechner <dlechner@baylibre.com>

iio: adc: ad7944: add driver for AD7944/AD7985/AD7986

This adds a driver for the Analog Devices Inc. AD7944, AD7985, and
AD7986 ADCs. These are a family of pin-compatible ADCs that can sample
at rates up to 2.5 MSPS.

The initial driver adds support for sampling at lower rates using the
usual IIO triggered buffer and can handle all 3 possible reference
voltage configurations.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240304-ad7944-mainline-v5-2-f0a38cea8901@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>