1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2023 Intel Corporation 4 */ 5 6#include "gt/intel_context.h" 7#include "gt/intel_engine_pm.h" 8#include "gt/intel_gpu_commands.h" 9#include "gt/intel_gt.h" 10#include "gt/intel_ring.h" 11#include "intel_gsc_uc_heci_cmd_submit.h" 12 13struct gsc_heci_pkt { 14 u64 addr_in; 15 u32 size_in; 16 u64 addr_out; 17 u32 size_out; 18}; 19 20static int emit_gsc_heci_pkt(struct i915_request *rq, struct gsc_heci_pkt *pkt) 21{ 22 u32 *cs; 23 24 cs = intel_ring_begin(rq, 8); 25 if (IS_ERR(cs)) 26 return PTR_ERR(cs); 27 28 *cs++ = GSC_HECI_CMD_PKT; 29 *cs++ = lower_32_bits(pkt->addr_in); 30 *cs++ = upper_32_bits(pkt->addr_in); 31 *cs++ = pkt->size_in; 32 *cs++ = lower_32_bits(pkt->addr_out); 33 *cs++ = upper_32_bits(pkt->addr_out); 34 *cs++ = pkt->size_out; 35 *cs++ = 0; 36 37 intel_ring_advance(rq, cs); 38 39 return 0; 40} 41 42int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, u64 addr_in, 43 u32 size_in, u64 addr_out, 44 u32 size_out) 45{ 46 struct intel_context *ce = gsc->ce; 47 struct i915_request *rq; 48 struct gsc_heci_pkt pkt = { 49 .addr_in = addr_in, 50 .size_in = size_in, 51 .addr_out = addr_out, 52 .size_out = size_out 53 }; 54 int err; 55 56 if (!ce) 57 return -ENODEV; 58 59 rq = i915_request_create(ce); 60 if (IS_ERR(rq)) 61 return PTR_ERR(rq); 62 63 if (ce->engine->emit_init_breadcrumb) { 64 err = ce->engine->emit_init_breadcrumb(rq); 65 if (err) 66 goto out_rq; 67 } 68 69 err = emit_gsc_heci_pkt(rq, &pkt); 70 71 if (err) 72 goto out_rq; 73 74 err = ce->engine->emit_flush(rq, 0); 75 76out_rq: 77 i915_request_get(rq); 78 79 if (unlikely(err)) 80 i915_request_set_error_once(rq, err); 81 82 i915_request_add(rq); 83 84 if (!err) { 85 /* 86 * Start timeout for i915_request_wait only after considering one possible 87 * pending GSC-HECI submission cycle on the other (non-privileged) path. 88 */ 89 if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS)) 90 drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm, 91 "Delay in gsc-heci-priv submission to gsccs-hw"); 92 if (i915_request_wait(rq, 0, msecs_to_jiffies(GSC_HECI_REPLY_LATENCY_MS)) < 0) 93 err = -ETIME; 94 } 95 96 i915_request_put(rq); 97 98 if (err) 99 drm_err(&gsc_uc_to_gt(gsc)->i915->drm, 100 "Request submission for GSC heci cmd failed (%d)\n", 101 err); 102 103 return err; 104} 105 106void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header, 107 u8 heci_client_id, u32 message_size, 108 u64 host_session_id) 109{ 110 host_session_id &= ~HOST_SESSION_MASK; 111 if (host_session_id && heci_client_id == HECI_MEADDRESS_PXP) 112 host_session_id |= HOST_SESSION_PXP_SINGLE; 113 114 header->validity_marker = GSC_HECI_VALIDITY_MARKER; 115 header->heci_client_id = heci_client_id; 116 header->host_session_handle = host_session_id; 117 header->header_version = MTL_GSC_HEADER_VERSION; 118 header->message_size = message_size; 119} 120 121static void 122emit_gsc_heci_pkt_nonpriv(u32 *cmd, struct intel_gsc_heci_non_priv_pkt *pkt) 123{ 124 *cmd++ = GSC_HECI_CMD_PKT; 125 *cmd++ = lower_32_bits(pkt->addr_in); 126 *cmd++ = upper_32_bits(pkt->addr_in); 127 *cmd++ = pkt->size_in; 128 *cmd++ = lower_32_bits(pkt->addr_out); 129 *cmd++ = upper_32_bits(pkt->addr_out); 130 *cmd++ = pkt->size_out; 131 *cmd++ = 0; 132 *cmd++ = MI_BATCH_BUFFER_END; 133} 134 135int 136intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc, 137 struct intel_context *ce, 138 struct intel_gsc_heci_non_priv_pkt *pkt, 139 u32 *cmd, int timeout_ms) 140{ 141 struct intel_engine_cs *engine; 142 struct i915_gem_ww_ctx ww; 143 struct i915_request *rq; 144 int err, trials = 0; 145 146 i915_gem_ww_ctx_init(&ww, false); 147retry: 148 err = i915_gem_object_lock(pkt->bb_vma->obj, &ww); 149 if (err) 150 goto out_ww; 151 err = i915_gem_object_lock(pkt->heci_pkt_vma->obj, &ww); 152 if (err) 153 goto out_ww; 154 err = intel_context_pin_ww(ce, &ww); 155 if (err) 156 goto out_ww; 157 158 rq = i915_request_create(ce); 159 if (IS_ERR(rq)) { 160 err = PTR_ERR(rq); 161 goto out_unpin_ce; 162 } 163 164 emit_gsc_heci_pkt_nonpriv(cmd, pkt); 165 166 err = i915_vma_move_to_active(pkt->bb_vma, rq, 0); 167 if (err) 168 goto out_rq; 169 err = i915_vma_move_to_active(pkt->heci_pkt_vma, rq, EXEC_OBJECT_WRITE); 170 if (err) 171 goto out_rq; 172 173 engine = rq->context->engine; 174 if (engine->emit_init_breadcrumb) { 175 err = engine->emit_init_breadcrumb(rq); 176 if (err) 177 goto out_rq; 178 } 179 180 err = engine->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0); 181 if (err) 182 goto out_rq; 183 184 err = ce->engine->emit_flush(rq, 0); 185 if (err) 186 drm_err(&gsc_uc_to_gt(gsc)->i915->drm, 187 "Failed emit-flush for gsc-heci-non-priv-pkterr=%d\n", err); 188 189out_rq: 190 i915_request_get(rq); 191 192 if (unlikely(err)) 193 i915_request_set_error_once(rq, err); 194 195 i915_request_add(rq); 196 197 if (!err) { 198 /* 199 * Start timeout for i915_request_wait only after considering one possible 200 * pending GSC-HECI submission cycle on the other (privileged) path. 201 */ 202 if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS)) 203 drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm, 204 "Delay in gsc-heci-non-priv submission to gsccs-hw"); 205 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 206 msecs_to_jiffies(timeout_ms)) < 0) 207 err = -ETIME; 208 } 209 210 i915_request_put(rq); 211 212out_unpin_ce: 213 intel_context_unpin(ce); 214out_ww: 215 if (err == -EDEADLK) { 216 err = i915_gem_ww_ctx_backoff(&ww); 217 if (!err) { 218 if (++trials < 10) 219 goto retry; 220 else 221 err = -EAGAIN; 222 } 223 } 224 i915_gem_ww_ctx_fini(&ww); 225 226 return err; 227} 228