1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __KVM_X86_VMX_NESTED_H 3#define __KVM_X86_VMX_NESTED_H 4 5#include "kvm_cache_regs.h" 6#include "hyperv.h" 7#include "vmcs12.h" 8#include "vmx.h" 9 10/* 11 * Status returned by nested_vmx_enter_non_root_mode(): 12 */ 13enum nvmx_vmentry_status { 14 NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */ 15 NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */ 16 NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */ 17 NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */ 18}; 19 20void vmx_leave_nested(struct kvm_vcpu *vcpu); 21void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps); 22void nested_vmx_hardware_unsetup(void); 23__init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *)); 24void nested_vmx_set_vmcs_shadowing_bitmap(void); 25void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu); 26enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 27 bool from_vmentry); 28bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu); 29void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 30 u32 exit_intr_info, unsigned long exit_qualification); 31void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu); 32int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); 33int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata); 34int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 35 u32 vmx_instruction_info, bool wr, int len, gva_t *ret); 36void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); 37bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, 38 int size); 39 40static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) 41{ 42 return to_vmx(vcpu)->nested.cached_vmcs12; 43} 44 45static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu) 46{ 47 return to_vmx(vcpu)->nested.cached_shadow_vmcs12; 48} 49 50/* 51 * Note: the same condition is checked against the state provided by userspace 52 * in vmx_set_nested_state; if it is satisfied, the nested state must include 53 * the VMCS12. 54 */ 55static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu) 56{ 57 struct vcpu_vmx *vmx = to_vmx(vcpu); 58 59 /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */ 60 return vmx->nested.current_vmptr != -1ull || 61 nested_vmx_is_evmptr12_set(vmx); 62} 63 64static inline u16 nested_get_vpid02(struct kvm_vcpu *vcpu) 65{ 66 struct vcpu_vmx *vmx = to_vmx(vcpu); 67 68 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid; 69} 70 71static inline unsigned long nested_ept_get_eptp(struct kvm_vcpu *vcpu) 72{ 73 /* return the page table to be shadowed - in our case, EPT12 */ 74 return get_vmcs12(vcpu)->ept_pointer; 75} 76 77static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) 78{ 79 return nested_ept_get_eptp(vcpu) & VMX_EPTP_AD_ENABLE_BIT; 80} 81 82/* 83 * Return the cr0/4 value that a nested guest would read. This is a combination 84 * of L1's "real" cr0 used to run the guest (guest_cr0), and the bits shadowed 85 * by the L1 hypervisor (cr0_read_shadow). KVM must emulate CPU behavior as 86 * the value+mask loaded into vmcs02 may not match the vmcs12 fields. 87 */ 88static inline unsigned long nested_read_cr0(struct vmcs12 *fields) 89{ 90 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | 91 (fields->cr0_read_shadow & fields->cr0_guest_host_mask); 92} 93static inline unsigned long nested_read_cr4(struct vmcs12 *fields) 94{ 95 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | 96 (fields->cr4_read_shadow & fields->cr4_guest_host_mask); 97} 98 99static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) 100{ 101 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low); 102} 103 104/* 105 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE 106 * to modify any valid field of the VMCS, or are the VM-exit 107 * information fields read-only? 108 */ 109static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu) 110{ 111 return to_vmx(vcpu)->nested.msrs.misc_low & 112 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; 113} 114 115static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu) 116{ 117 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS; 118} 119 120static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu) 121{ 122 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high & 123 CPU_BASED_MONITOR_TRAP_FLAG; 124} 125 126static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu) 127{ 128 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 129 SECONDARY_EXEC_SHADOW_VMCS; 130} 131 132static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) 133{ 134 return vmcs12->cpu_based_vm_exec_control & bit; 135} 136 137static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) 138{ 139 return (vmcs12->cpu_based_vm_exec_control & 140 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 141 (vmcs12->secondary_vm_exec_control & bit); 142} 143 144static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) 145{ 146 return vmcs12->pin_based_vm_exec_control & 147 PIN_BASED_VMX_PREEMPTION_TIMER; 148} 149 150static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12) 151{ 152 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING; 153} 154 155static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) 156{ 157 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; 158} 159 160static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12) 161{ 162 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); 163} 164 165static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) 166{ 167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); 168} 169 170static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) 171{ 172 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_XSAVES); 173} 174 175static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) 176{ 177 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); 178} 179 180static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) 181{ 182 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 183} 184 185static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) 186{ 187 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); 188} 189 190static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) 191{ 192 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); 193} 194 195static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) 196{ 197 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 198} 199 200static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) 201{ 202 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; 203} 204 205static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) 206{ 207 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); 208} 209 210static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) 211{ 212 return nested_cpu_has_vmfunc(vmcs12) && 213 (vmcs12->vm_function_control & 214 VMX_VMFUNC_EPTP_SWITCHING); 215} 216 217static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12) 218{ 219 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS); 220} 221 222static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12) 223{ 224 return vmcs12->vm_exit_controls & 225 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER; 226} 227 228static inline bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) 229{ 230 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu)); 231} 232 233/* 234 * In nested virtualization, check if L1 asked to exit on external interrupts. 235 * For most existing hypervisors, this will always return true. 236 */ 237static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu) 238{ 239 return get_vmcs12(vcpu)->pin_based_vm_exec_control & 240 PIN_BASED_EXT_INTR_MASK; 241} 242 243static inline bool nested_cpu_has_encls_exit(struct vmcs12 *vmcs12) 244{ 245 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING); 246} 247 248/* 249 * if fixed0[i] == 1: val[i] must be 1 250 * if fixed1[i] == 0: val[i] must be 0 251 */ 252static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) 253{ 254 return ((val & fixed1) | fixed0) == val; 255} 256 257static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 258{ 259 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 260 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 261 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 262 263 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 264 SECONDARY_EXEC_UNRESTRICTED_GUEST && 265 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) 266 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); 267 268 return fixed_bits_valid(val, fixed0, fixed1); 269} 270 271static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 272{ 273 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 274 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 275 276 return fixed_bits_valid(val, fixed0, fixed1); 277} 278 279static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) 280{ 281 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0; 282 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1; 283 284 return fixed_bits_valid(val, fixed0, fixed1) && 285 __kvm_is_valid_cr4(vcpu, val); 286} 287 288/* No difference in the restrictions on guest and host CR4 in VMX operation. */ 289#define nested_guest_cr4_valid nested_cr4_valid 290#define nested_host_cr4_valid nested_cr4_valid 291 292extern struct kvm_x86_nested_ops vmx_nested_ops; 293 294#endif /* __KVM_X86_VMX_NESTED_H */ 295