1/*
2 * Copyright 2010-2012 Haiku, Inc. All rights reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Francois Revol
7 *		Ithamar R. Adema, ithamar.adema@team-embedded.nl
8 *		Alexander von Gluck, kallisti5@unixzen.com
9 */
10#ifndef _ARCH_ARM_ARM_MMU_H
11#define _ARCH_ARM_ARM_MMU_H
12
13
14/*
15 * generic arm mmu definitions
16 */
17
18/*
19 * L1 defines for the page directory (page table walk methods)
20 */
21#define ARM_MMU_L1_TYPE_FAULT			0x0
22	// MMU Fault
23	// 31                                                  2 10
24	// |                                                    |00|
25#define ARM_MMU_L1_TYPE_SECTION			0x2
26	// Single step table walk, 4096 entries
27	// 1024K pages, 16K consumed
28	// 31                   20 19   12 11  10 9 8      5 432 10
29	// | page table address   |  0?   |  AP  |0| domain |1CB|10|
30#define ARM_MMU_L1_TYPE_FINE			0x3
31	// Three(?) step table walk, 1024 entries
32	// 1K, 4K, 64K pages, 4K consumed
33	// 31                           12 11     9 8      5 432 10
34	// | page table address           |   0?   | domain |100|11|
35#define ARM_MMU_L1_TYPE_COARSE			0x1
36	// Two step table walk, 256 entries
37	// 4K(Haiku), 64K pages, 1K consumed
38	// 31                                  10 9 8      5 432 10
39	// | page table address                  |0| domain |000|01|
40
41#define ARM_MMU_L1_FLAG_PXN				0x00000004
42
43// the domain is not used so and the ? is implementation specified... have not
44// found it in the cortex A8 reference... so I set t to 0
45// page table must obviously be on multiple of 1KB
46
47#define ARM_MMU_L2_TYPE_LARGE			0x1
48#define ARM_MMU_L2_TYPE_SMALLNEW		0x2
49#define ARM_MMU_L2_TYPE_SMALLEXT		0x3
50
51#define ARM_MMU_L2_FLAG_XN				0x001
52#define ARM_MMU_L2_FLAG_B				0x004
53#define ARM_MMU_L2_FLAG_C				0x008
54#define ARM_MMU_L2_FLAG_AP0				0x010
55#define ARM_MMU_L2_FLAG_AP1				0x020
56#define ARM_MMU_L2_FLAG_TEX0			0x040
57#define ARM_MMU_L2_FLAG_TEX1			0x080
58#define ARM_MMU_L2_FLAG_TEX2			0x100
59#define ARM_MMU_L2_FLAG_AP2				0x200
60#define ARM_MMU_L2_FLAG_S				0x400
61#define ARM_MMU_L2_FLAG_NG				0x800
62
63#define ARM_MMU_L2_FLAG_HAIKU_SWDBM		ARM_MMU_L2_FLAG_TEX2
64	// reuse TEX[2] for software-emulated Dirty Bit Modifier
65
66#define ARM_MMU_L2_FLAG_HAIKU_KERNEL_RW	(ARM_MMU_L2_FLAG_TEX2 | ARM_MMU_L2_FLAG_AP0)
67	// allow read and write for kernel only
68	// set Accessed and Modified flag during early page mapping
69	// as the exception handler may be not available yet
70
71#define ARM_MMU_L1_TABLE_ENTRY_COUNT	4096
72#define ARM_MMU_L1_TABLE_SIZE			(ARM_MMU_L1_TABLE_ENTRY_COUNT \
73											* sizeof(uint32))
74
75#define ARM_MMU_L2_COARSE_ENTRY_COUNT	256
76#define ARM_MMU_L2_COARSE_TABLE_SIZE	(ARM_MMU_L2_COARSE_ENTRY_COUNT \
77											* sizeof(uint32))
78
79#define ARM_MMU_L2_FINE_ENTRY_COUNT		1024
80#define ARM_MMU_L2_FINE_TABLE_SIZE		(ARM_MMU_L2_FINE_ENTRY_COUNT \
81											* sizeof(uint32))
82
83/*
84 * definitions for CP15 r1
85 */
86
87#define CR_R1_MMU						0x1		// enable MMU
88#define CP_R1_XP						0x800000
89	// if XP=0 then use backwards comaptible translation tables
90
91
92#define VADDR_TO_PDENT(va)				((va) >> 20)
93#define VADDR_TO_PTENT(va)				(((va) & 0xff000) >> 12)
94#define VADDR_TO_PGOFF(va)				((va) & 0x0fff)
95
96#define ARM_PDE_ADDRESS_MASK			0xfffffc00
97#define ARM_PDE_TYPE_MASK				0x00000003
98
99#define ARM_PTE_ADDRESS_MASK			0xfffff000
100#define ARM_PTE_TYPE_MASK				0x00000003
101
102#define ARM_PTE_PROTECTION_MASK			0x00000121	// SWDBM, AP[1], XN
103#define ARM_PTE_MEMORY_TYPE_MASK		0x0000004c	// TEX[0], B, C
104
105#endif /* _ARCH_ARM_ARM_MMU_H */
106