1/*
2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *      Alexander von Gluck, kallisti5@unixzen.com
7 */
8#ifndef RADEON_HD_PLL_H
9#define RADEON_HD_PLL_H
10
11
12#include <Accelerant.h>
13#include <SupportDefs.h>
14
15
16#define MAX_TOLERANCE 10
17
18#define PLL_MIN_DEFAULT 16000
19#define PLL_MAX_DEFAULT 400000
20#define PLL_REFERENCE_DEFAULT 27000
21
22/* limited by the number of bits available */
23#define FB_DIV_MIN 4
24#define FB_DIV_LIMIT 2048
25#define REF_DIV_MIN 2
26#define REF_DIV_LIMIT 1024
27#define POST_DIV_MIN 2
28#define POST_DIV_LIMIT 127
29
30/* pll flags */
31#define PLL_USE_BIOS_DIVS        (1 << 0)
32#define PLL_NO_ODD_POST_DIV      (1 << 1)
33#define PLL_USE_REF_DIV          (1 << 2)
34#define PLL_LEGACY               (1 << 3)
35#define PLL_PREFER_LOW_REF_DIV   (1 << 4)
36#define PLL_PREFER_HIGH_REF_DIV  (1 << 5)
37#define PLL_PREFER_LOW_FB_DIV    (1 << 6)
38#define PLL_PREFER_HIGH_FB_DIV   (1 << 7)
39#define PLL_PREFER_LOW_POST_DIV  (1 << 8)
40#define PLL_PREFER_HIGH_POST_DIV (1 << 9)
41#define PLL_USE_FRAC_FB_DIV      (1 << 10)
42#define PLL_PREFER_CLOSEST_LOWER (1 << 11)
43#define PLL_USE_POST_DIV         (1 << 12)
44#define PLL_IS_LCD               (1 << 13)
45#define PLL_PREFER_MINM_OVER_MAXP (1 << 14)
46
47
48struct pll_info {
49	/* pixel clock to be programmed (kHz)*/
50	uint32 pixelClock;
51
52	/* flags for the current clock */
53	uint32 flags;
54
55	/* pll id */
56	uint32 id;
57
58	/* reference frequency */
59	uint32 referenceFreq;
60
61	/* fixed dividers */
62	uint32 postDiv;
63	uint32 referenceDiv;
64	uint32 feedbackDiv;
65	uint32 feedbackDivFrac;
66
67	/* pll in/out limits */
68	uint32 pllInMin;
69	uint32 pllInMax;
70	uint32 pllOutMin;
71	uint32 pllOutMax;
72	uint32 lcdPllOutMin;
73	uint32 lcdPllOutMax;
74	uint32 bestVco;
75
76	/* divider limits */
77	uint32 minRefDiv;
78	uint32 maxRefDiv;
79	uint32 minPostDiv;
80	uint32 maxPostDiv;
81	uint32 minFeedbackDiv;
82	uint32 maxFeedbackDiv;
83	uint32 minFeedbackDivFrac;
84	uint32 maxFeedbackDivFrac;
85
86	/* spread spectrum info */
87	uint8 ssType;
88	uint8 ssDelay;
89	uint8 ssRange;
90	uint8 ssReferenceDiv;
91	uint16 ssPercentage;
92	uint16 ssStep;
93	/* asic spread spectrum */
94	uint16 ssRate;
95	uint16 ssAmount;
96
97	/* pixel clock to be used in pll calculations (kHz) */
98	uint32 adjustedClock;
99};
100
101
102void pll_external_init();
103status_t pll_external_set(uint32 clock);
104status_t pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID);
105status_t pll_compute(pll_info* pll);
106void pll_setup_flags(pll_info* pll, uint8 crtcID);
107status_t pll_limit_probe(pll_info* pll);
108status_t pll_ppll_ss_probe(pll_info* pll, uint32 ssID);
109status_t pll_asic_ss_probe(pll_info* pll, uint32 ssID);
110status_t pll_set(display_mode* mode, uint8 crtcID);
111status_t pll_pick(uint32 connectorIndex);
112
113
114#endif /* RADEON_HD_PLL_H */
115