radeon_hd: Fix DisplayPort link training

* Original changes by Bill Randle
* Includes a large number of modifications
and cleanups.
* Add a "currentMode" to the gDisplay to
enable easier checking of intended changes.
(we pass the display_mode around quite a
bit, adding a "currentMode" allows code
to know the intended display mode being set
without passing the mode pointer around as
much)

radeon_hd: Become Spread Spectrum aware

* Enable Spread Spectrum when requested
* Tested working across several cards, does
have regression potential though.

radeon_hd: rework some pll code

* Force fractional feedback divider on APU's
* Spread Spectrum is now probed more correctly
across multiple encoders and cards
* SS still disabled however.

radeon_hd: reorganize some pll code

* Move DisplayPort external pixel clock out of pll
as this frequency is card-wide.
* Add new function to pull display clock frequency
and other card-wide settings.
* Set displayDefault frequency card-wide
* My DisplayPort LVDS bridge laptop now kind of works
(a clock somewhere seems a little off though)

radeon_hd: pick a PLL based on connector

* was static PLL 1

radeon_hd: display port improvements

* Remove non-generic radeon dp_get_lane_count
* Set lane count and link rate at set_display_mode
* Pass entire mode to pll_set vs only pixel clock for DP code
* Add helpers for DP config data to common code
* Obtain more correct link rate

radeon_hd: Add spread spectrum control functions

* Store SS information with PLL
* Probe SS information for PLL
* Disable SS more correctly
* May resolve mode setting issues on newer cards

Complete code for DIG transmitter control

* Record external clock frequency (aka, DP non-pll)
* Add function to control DIG transmitter
* Cleanup duplicated is external code in encoder mode set

Pointer style cleanup; Variable consolidation

Include file style cleanup, no functional change

* add function to make pll flag adjustments
* bug fix of improper unit conversion


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42858 a95241bf-73f2-0310-859d-f6bbb57e9c96

* add function to probe pll timing limits from AtomBIOS
* rename *_* pll vars to match style guidelines
* refactor PLL calculation to be easier to read with
more central 10kHz unit conversions
* limited mode switching has been seen working including
a perfect 1280x1024@75


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42855 a95241bf-73f2-0310-859d-f6bbb57e9c96

* first shot at fixing pll calculations
AtomBIOS wants number of 10Khz Units
* better debugging after modeset on current
CRTC status


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42853 a95241bf-73f2-0310-859d-f6bbb57e9c96

* style fixes, no functional change...
automatic crtc_id -> crtcID
automatic pll_id -> pllID
automatic encoder_id -> encoderID
automatic connector_index -> connectorIndex
automatic encoder_flags -> encoderFlags


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42831 a95241bf-73f2-0310-859d-f6bbb57e9c96

* move pll info into pll_info struct.
* reduce the number of unique storage uint32's


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42826 a95241bf-73f2-0310-859d-f6bbb57e9c96

* move pll info onto encoder
* add atombios PLL adjustment code
* add initial PLL clock flags


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42819 a95241bf-73f2-0310-859d-f6bbb57e9c96

* introduce mc control calls
* malloc storage for mc state info
* redo pll range struct
* change to ATOM_ENCODER_MODE for connector info
* redo pll calculations to match AtomBIOS requirements
* some structure changes
* no longer init already posted AtomBIOS as it
causes an infinite loop of AtomBIOS calls


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42644 a95241bf-73f2-0310-859d-f6bbb57e9c96

* lots of changes
* add missing header for some radeon registers
* begin removing now un-needed direct register calls
* move and refactor crtc functions
* fix function naming to be clearer
* create more AtomBIOS style calls
* this will eat your cat at the moment, don't bother testing


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42582 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Final (hopefully?) calculation for blank start/end
* Lets actually call PLLPower after PLLSet
* Improve screen blanking function
* Detect DAC/PLL to use separately from CRT id
* Add DACSense that senses displays on DACA/DACB
* Grab CRT in PLL code via gRegister crtid
* Set overscan to 0 for now
* Setting extended video modes now kinda works sometimes :-/


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42397 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Break DAC code into sperate source file
* Implement assigning DAC A/B to crt
* Clean up mode change code
* Still some pixel clock wierdness


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42205 a95241bf-73f2-0310-859d-f6bbb57e9c96

* malloc an array of pointers to hold active crt info, mode, limits, etc.
Plan to move gRegister into the crt struct at some point.
* Few style fixes
* Added function to probe edid of attached monitors and populate CRT info
* Disable VGA control modifications temporarly while I hammer out some issues.
* Fix radeon card model checks (bitwise & is not |)
* Finally fix? blanking start / end calculations using porch
* Use mask for setting sync polarity
* Add overscan (8 pixels is default?)
* Disable PLLSet/Power for the moment as it seems to muck things up.
* is_mode_supported now validates if a mode line is with the monitors
h/v sync frequencies (how does is_mode_supported know what crt the os wants?)
* PLL Write/Read don't actually use the PLL Write/Read functions (thanks AMD!)
* Added better PLL legacy (r600-r610) support
* Consistantly give no DCCG on legacy cards.
* Tracing!


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42191 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Repair style issue using uintNN_t vs uintNN
* Make index numbering consistant (0-n vs 1-n)
* Add a little more tracing to PLLCalibrate because
we were missing a failure situation


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42158 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Define default PLL ranges
* Add crtid to register struct
* Disable VGA mode on FrameBuffer set (enables extended mode setting)
* Disable blanking calculations and setting more gracefully via if 0
* Add a *large* amount of code to Set/Calculate/Calibrate PLL
* Disable PLL on removal of accel.
* Remove junk comments on overscan
* Enable pixel clock limit pulling
* write32AtMask style cleanup
* Rename ReadMC to be more consistant
(I need to adjust naming for these MMIO calls)
* Implement read/write MC. (so many hardcoded oneoffs AMD)
* Implement write32PLLAtMask MMIO call


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42146 a95241bf-73f2-0310-859d-f6bbb57e9c96

radeon_hd: Become Spread Spectrum aware

* Enable Spread Spectrum when requested
* Tested working across several cards, does
have regression potential though.

radeon_hd: rework some pll code

* Force fractional feedback divider on APU's
* Spread Spectrum is now probed more correctly
across multiple encoders and cards
* SS still disabled however.

radeon_hd: reorganize some pll code

* Move DisplayPort external pixel clock out of pll
as this frequency is card-wide.
* Add new function to pull display clock frequency
and other card-wide settings.
* Set displayDefault frequency card-wide
* My DisplayPort LVDS bridge laptop now kind of works
(a clock somewhere seems a little off though)

radeon_hd: pick a PLL based on connector

* was static PLL 1

radeon_hd: display port improvements

* Remove non-generic radeon dp_get_lane_count
* Set lane count and link rate at set_display_mode
* Pass entire mode to pll_set vs only pixel clock for DP code
* Add helpers for DP config data to common code
* Obtain more correct link rate

radeon_hd: Add spread spectrum control functions

* Store SS information with PLL
* Probe SS information for PLL
* Disable SS more correctly
* May resolve mode setting issues on newer cards

Complete code for DIG transmitter control

* Record external clock frequency (aka, DP non-pll)
* Add function to control DIG transmitter
* Cleanup duplicated is external code in encoder mode set

Pointer style cleanup; Variable consolidation

Include file style cleanup, no functional change

* add function to make pll flag adjustments
* bug fix of improper unit conversion


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42858 a95241bf-73f2-0310-859d-f6bbb57e9c96

* add function to probe pll timing limits from AtomBIOS
* rename *_* pll vars to match style guidelines
* refactor PLL calculation to be easier to read with
more central 10kHz unit conversions
* limited mode switching has been seen working including
a perfect 1280x1024@75


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42855 a95241bf-73f2-0310-859d-f6bbb57e9c96

* first shot at fixing pll calculations
AtomBIOS wants number of 10Khz Units
* better debugging after modeset on current
CRTC status


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42853 a95241bf-73f2-0310-859d-f6bbb57e9c96

* style fixes, no functional change...
automatic crtc_id -> crtcID
automatic pll_id -> pllID
automatic encoder_id -> encoderID
automatic connector_index -> connectorIndex
automatic encoder_flags -> encoderFlags


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42831 a95241bf-73f2-0310-859d-f6bbb57e9c96

* move pll info into pll_info struct.
* reduce the number of unique storage uint32's


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42826 a95241bf-73f2-0310-859d-f6bbb57e9c96

* move pll info onto encoder
* add atombios PLL adjustment code
* add initial PLL clock flags


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42819 a95241bf-73f2-0310-859d-f6bbb57e9c96

* introduce mc control calls
* malloc storage for mc state info
* redo pll range struct
* change to ATOM_ENCODER_MODE for connector info
* redo pll calculations to match AtomBIOS requirements
* some structure changes
* no longer init already posted AtomBIOS as it
causes an infinite loop of AtomBIOS calls


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42644 a95241bf-73f2-0310-859d-f6bbb57e9c96

* lots of changes
* add missing header for some radeon registers
* begin removing now un-needed direct register calls
* move and refactor crtc functions
* fix function naming to be clearer
* create more AtomBIOS style calls
* this will eat your cat at the moment, don't bother testing


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42582 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Final (hopefully?) calculation for blank start/end
* Lets actually call PLLPower after PLLSet
* Improve screen blanking function
* Detect DAC/PLL to use separately from CRT id
* Add DACSense that senses displays on DACA/DACB
* Grab CRT in PLL code via gRegister crtid
* Set overscan to 0 for now
* Setting extended video modes now kinda works sometimes :-/


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42397 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Break DAC code into sperate source file
* Implement assigning DAC A/B to crt
* Clean up mode change code
* Still some pixel clock wierdness


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42205 a95241bf-73f2-0310-859d-f6bbb57e9c96

* malloc an array of pointers to hold active crt info, mode, limits, etc.
Plan to move gRegister into the crt struct at some point.
* Few style fixes
* Added function to probe edid of attached monitors and populate CRT info
* Disable VGA control modifications temporarly while I hammer out some issues.
* Fix radeon card model checks (bitwise & is not |)
* Finally fix? blanking start / end calculations using porch
* Use mask for setting sync polarity
* Add overscan (8 pixels is default?)
* Disable PLLSet/Power for the moment as it seems to muck things up.
* is_mode_supported now validates if a mode line is with the monitors
h/v sync frequencies (how does is_mode_supported know what crt the os wants?)
* PLL Write/Read don't actually use the PLL Write/Read functions (thanks AMD!)
* Added better PLL legacy (r600-r610) support
* Consistantly give no DCCG on legacy cards.
* Tracing!


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42191 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Repair style issue using uintNN_t vs uintNN
* Make index numbering consistant (0-n vs 1-n)
* Add a little more tracing to PLLCalibrate because
we were missing a failure situation


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42158 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Define default PLL ranges
* Add crtid to register struct
* Disable VGA mode on FrameBuffer set (enables extended mode setting)
* Disable blanking calculations and setting more gracefully via if 0
* Add a *large* amount of code to Set/Calculate/Calibrate PLL
* Disable PLL on removal of accel.
* Remove junk comments on overscan
* Enable pixel clock limit pulling
* write32AtMask style cleanup
* Rename ReadMC to be more consistant
(I need to adjust naming for these MMIO calls)
* Implement read/write MC. (so many hardcoded oneoffs AMD)
* Implement write32PLLAtMask MMIO call


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42146 a95241bf-73f2-0310-859d-f6bbb57e9c96