local_apic.c revision 151979
1121986Sjhb/*- 2121986Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121986Sjhb * Copyright (c) 1996, by Steve Passe 4121986Sjhb * All rights reserved. 5121986Sjhb * 6121986Sjhb * Redistribution and use in source and binary forms, with or without 7121986Sjhb * modification, are permitted provided that the following conditions 8121986Sjhb * are met: 9121986Sjhb * 1. Redistributions of source code must retain the above copyright 10121986Sjhb * notice, this list of conditions and the following disclaimer. 11121986Sjhb * 2. The name of the developer may NOT be used to endorse or promote products 12121986Sjhb * derived from this software without specific prior written permission. 13121986Sjhb * 3. Neither the name of the author nor the names of any co-contributors 14121986Sjhb * may be used to endorse or promote products derived from this software 15121986Sjhb * without specific prior written permission. 16121986Sjhb * 17121986Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18121986Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19121986Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20121986Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21121986Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22121986Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23121986Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24121986Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25121986Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26121986Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27121986Sjhb * SUCH DAMAGE. 28121986Sjhb */ 29121986Sjhb 30121986Sjhb/* 31121986Sjhb * Local APIC support on Pentium and later processors. 32121986Sjhb */ 33121986Sjhb 34121986Sjhb#include <sys/cdefs.h> 35121986Sjhb__FBSDID("$FreeBSD: head/sys/i386/i386/local_apic.c 151979 2005-11-02 20:11:47Z jhb $"); 36121986Sjhb 37147565Speter#include "opt_hwpmc_hooks.h" 38147565Speter 39151979Sjhb#include "opt_ddb.h" 40151979Sjhb 41121986Sjhb#include <sys/param.h> 42121986Sjhb#include <sys/systm.h> 43121986Sjhb#include <sys/bus.h> 44121986Sjhb#include <sys/kernel.h> 45151979Sjhb#include <sys/lock.h> 46151979Sjhb#include <sys/mutex.h> 47121986Sjhb#include <sys/pcpu.h> 48141538Sjhb#include <sys/smp.h> 49121986Sjhb 50121986Sjhb#include <vm/vm.h> 51121986Sjhb#include <vm/pmap.h> 52121986Sjhb 53121986Sjhb#include <machine/apicreg.h> 54121986Sjhb#include <machine/cputypes.h> 55121986Sjhb#include <machine/frame.h> 56121986Sjhb#include <machine/intr_machdep.h> 57121986Sjhb#include <machine/apicvar.h> 58121986Sjhb#include <machine/md_var.h> 59121986Sjhb#include <machine/smp.h> 60121986Sjhb#include <machine/specialreg.h> 61121986Sjhb 62151979Sjhb#ifdef DDB 63151979Sjhb#include <sys/interrupt.h> 64151979Sjhb#include <ddb/ddb.h> 65151979Sjhb#endif 66151979Sjhb 67121986Sjhb/* 68121986Sjhb * We can handle up to 60 APICs via our logical cluster IDs, but currently 69121986Sjhb * the physical IDs on Intel processors up to the Pentium 4 are limited to 70121986Sjhb * 16. 71121986Sjhb */ 72121986Sjhb#define MAX_APICID 16 73121986Sjhb 74122690Sjhb/* Sanity checks on IDT vectors. */ 75139240SjhbCTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 76139240SjhbCTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 77139240SjhbCTASSERT(APIC_LOCAL_INTS == 240); 78122690SjhbCTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 79122690Sjhb 80143034Sjhb#define LAPIC_TIMER_HZ_DIVIDER 2 81143034Sjhb#define LAPIC_TIMER_STATHZ_DIVIDER 15 82143034Sjhb#define LAPIC_TIMER_PROFHZ_DIVIDER 3 83141538Sjhb 84151979Sjhb/* Magic IRQ values for the timer and syscalls. */ 85151979Sjhb#define IRQ_TIMER (NUM_IO_INTS + 1) 86151979Sjhb#define IRQ_SYSCALL (NUM_IO_INTS + 2) 87151979Sjhb 88121986Sjhb/* 89121986Sjhb * Support for local APICs. Local APICs manage interrupts on each 90121986Sjhb * individual processor as opposed to I/O APICs which receive interrupts 91121986Sjhb * from I/O devices and then forward them on to the local APICs. 92121986Sjhb * 93121986Sjhb * Local APICs can also send interrupts to each other thus providing the 94121986Sjhb * mechanism for IPIs. 95121986Sjhb */ 96121986Sjhb 97121986Sjhbstruct lvt { 98121986Sjhb u_int lvt_edgetrigger:1; 99121986Sjhb u_int lvt_activehi:1; 100121986Sjhb u_int lvt_masked:1; 101121986Sjhb u_int lvt_active:1; 102121986Sjhb u_int lvt_mode:16; 103121986Sjhb u_int lvt_vector:8; 104121986Sjhb}; 105121986Sjhb 106121986Sjhbstruct lapic { 107121986Sjhb struct lvt la_lvts[LVT_MAX + 1]; 108121986Sjhb u_int la_id:8; 109121986Sjhb u_int la_cluster:4; 110121986Sjhb u_int la_cluster_id:2; 111121986Sjhb u_int la_present:1; 112141538Sjhb u_long *la_timer_count; 113141538Sjhb u_long la_hard_ticks; 114141538Sjhb u_long la_stat_ticks; 115141538Sjhb u_long la_prof_ticks; 116121986Sjhb} static lapics[MAX_APICID]; 117121986Sjhb 118121986Sjhb/* XXX: should thermal be an NMI? */ 119121986Sjhb 120121986Sjhb/* Global defaults for local APIC LVT entries. */ 121121986Sjhbstatic struct lvt lvts[LVT_MAX + 1] = { 122121986Sjhb { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 123121986Sjhb { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 124139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 125139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 126145256Sjkoshy { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 127139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 128121986Sjhb}; 129121986Sjhb 130121986Sjhbstatic inthand_t *ioint_handlers[] = { 131121986Sjhb NULL, /* 0 - 31 */ 132121986Sjhb IDTVEC(apic_isr1), /* 32 - 63 */ 133121986Sjhb IDTVEC(apic_isr2), /* 64 - 95 */ 134121986Sjhb IDTVEC(apic_isr3), /* 96 - 127 */ 135121986Sjhb IDTVEC(apic_isr4), /* 128 - 159 */ 136121986Sjhb IDTVEC(apic_isr5), /* 160 - 191 */ 137122690Sjhb IDTVEC(apic_isr6), /* 192 - 223 */ 138122690Sjhb IDTVEC(apic_isr7), /* 224 - 255 */ 139121986Sjhb}; 140121986Sjhb 141151979Sjhb/* Include IDT_SYSCALL to make indexing easier. */ 142151979Sjhbstatic u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 143151979Sjhb 144141538Sjhbstatic u_int32_t lapic_timer_divisors[] = { 145141538Sjhb APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 146141538Sjhb APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 147141538Sjhb}; 148141538Sjhb 149121986Sjhbvolatile lapic_t *lapic; 150141538Sjhbstatic u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 151121986Sjhb 152139245Sjhbstatic void lapic_enable(void); 153141538Sjhbstatic void lapic_timer_enable_intr(void); 154141538Sjhbstatic void lapic_timer_oneshot(u_int count); 155141538Sjhbstatic void lapic_timer_periodic(u_int count); 156141538Sjhbstatic void lapic_timer_set_divisor(u_int divisor); 157139245Sjhbstatic uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 158139245Sjhb 159121986Sjhbstatic uint32_t 160121986Sjhblvt_mode(struct lapic *la, u_int pin, uint32_t value) 161121986Sjhb{ 162121986Sjhb struct lvt *lvt; 163121986Sjhb 164121986Sjhb KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 165121986Sjhb if (la->la_lvts[pin].lvt_active) 166121986Sjhb lvt = &la->la_lvts[pin]; 167121986Sjhb else 168121986Sjhb lvt = &lvts[pin]; 169121986Sjhb 170121986Sjhb value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 171121986Sjhb APIC_LVT_VECTOR); 172121986Sjhb if (lvt->lvt_edgetrigger == 0) 173121986Sjhb value |= APIC_LVT_TM; 174121986Sjhb if (lvt->lvt_activehi == 0) 175121986Sjhb value |= APIC_LVT_IIPP_INTALO; 176121986Sjhb if (lvt->lvt_masked) 177121986Sjhb value |= APIC_LVT_M; 178121986Sjhb value |= lvt->lvt_mode; 179121986Sjhb switch (lvt->lvt_mode) { 180121986Sjhb case APIC_LVT_DM_NMI: 181121986Sjhb case APIC_LVT_DM_SMI: 182121986Sjhb case APIC_LVT_DM_INIT: 183121986Sjhb case APIC_LVT_DM_EXTINT: 184121986Sjhb if (!lvt->lvt_edgetrigger) { 185121986Sjhb printf("lapic%u: Forcing LINT%u to edge trigger\n", 186121986Sjhb la->la_id, pin); 187121986Sjhb value |= APIC_LVT_TM; 188121986Sjhb } 189121986Sjhb /* Use a vector of 0. */ 190121986Sjhb break; 191121986Sjhb case APIC_LVT_DM_FIXED: 192121986Sjhb value |= lvt->lvt_vector; 193121986Sjhb break; 194121986Sjhb default: 195121986Sjhb panic("bad APIC LVT delivery mode: %#x\n", value); 196121986Sjhb } 197121986Sjhb return (value); 198121986Sjhb} 199121986Sjhb 200121986Sjhb/* 201121986Sjhb * Map the local APIC and setup necessary interrupt vectors. 202121986Sjhb */ 203121986Sjhbvoid 204121986Sjhblapic_init(uintptr_t addr) 205121986Sjhb{ 206121986Sjhb 207121986Sjhb /* Map the local APIC and setup the spurious interrupt handler. */ 208121986Sjhb KASSERT(trunc_page(addr) == addr, 209121986Sjhb ("local APIC not aligned on a page boundary")); 210121986Sjhb lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t)); 211121986Sjhb setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 212121986Sjhb GSEL(GCODE_SEL, SEL_KPL)); 213121986Sjhb 214121986Sjhb /* Perform basic initialization of the BSP's local APIC. */ 215139245Sjhb lapic_enable(); 216151979Sjhb ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 217121986Sjhb 218121986Sjhb /* Set BSP's per-CPU local APIC ID. */ 219121986Sjhb PCPU_SET(apic_id, lapic_id()); 220121986Sjhb 221141538Sjhb /* Local APIC timer interrupt. */ 222141538Sjhb setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 223141538Sjhb GSEL(GCODE_SEL, SEL_KPL)); 224151979Sjhb ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 225141538Sjhb 226141538Sjhb /* XXX: error/thermal interrupts */ 227121986Sjhb} 228121986Sjhb 229121986Sjhb/* 230121986Sjhb * Create a local APIC instance. 231121986Sjhb */ 232121986Sjhbvoid 233121986Sjhblapic_create(u_int apic_id, int boot_cpu) 234121986Sjhb{ 235121986Sjhb int i; 236121986Sjhb 237132156Sjhb if (apic_id >= MAX_APICID) { 238121986Sjhb printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 239121986Sjhb if (boot_cpu) 240121986Sjhb panic("Can't ignore BSP"); 241121986Sjhb return; 242121986Sjhb } 243121986Sjhb KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 244121986Sjhb apic_id)); 245121986Sjhb 246121986Sjhb /* 247121986Sjhb * Assume no local LVT overrides and a cluster of 0 and 248121986Sjhb * intra-cluster ID of 0. 249121986Sjhb */ 250121986Sjhb lapics[apic_id].la_present = 1; 251121986Sjhb lapics[apic_id].la_id = apic_id; 252121986Sjhb for (i = 0; i < LVT_MAX; i++) { 253121986Sjhb lapics[apic_id].la_lvts[i] = lvts[i]; 254121986Sjhb lapics[apic_id].la_lvts[i].lvt_active = 0; 255121986Sjhb } 256121986Sjhb 257121986Sjhb#ifdef SMP 258121986Sjhb cpu_add(apic_id, boot_cpu); 259121986Sjhb#endif 260121986Sjhb} 261121986Sjhb 262121986Sjhb/* 263121986Sjhb * Dump contents of local APIC registers 264121986Sjhb */ 265121986Sjhbvoid 266121986Sjhblapic_dump(const char* str) 267121986Sjhb{ 268121986Sjhb 269121986Sjhb printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 270121986Sjhb printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 271121986Sjhb lapic->id, lapic->version, lapic->ldr, lapic->dfr); 272121986Sjhb printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 273121986Sjhb lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 274139245Sjhb printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 275139245Sjhb lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 276139245Sjhb lapic->lvt_pcint); 277121986Sjhb} 278121986Sjhb 279121986Sjhbvoid 280121986Sjhblapic_setup(void) 281121986Sjhb{ 282121986Sjhb struct lapic *la; 283121986Sjhb u_int32_t value, maxlvt; 284121986Sjhb register_t eflags; 285141538Sjhb char buf[MAXCOMLEN + 1]; 286121986Sjhb 287121986Sjhb la = &lapics[lapic_id()]; 288121986Sjhb KASSERT(la->la_present, ("missing APIC structure")); 289121986Sjhb eflags = intr_disable(); 290121986Sjhb maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 291121986Sjhb 292139240Sjhb /* Initialize the TPR to allow all interrupts. */ 293139240Sjhb lapic_set_tpr(0); 294121986Sjhb 295121986Sjhb /* Use the cluster model for logical IDs. */ 296121986Sjhb value = lapic->dfr; 297121986Sjhb value &= ~APIC_DFR_MODEL_MASK; 298121986Sjhb value |= APIC_DFR_MODEL_CLUSTER; 299121986Sjhb lapic->dfr = value; 300121986Sjhb 301121986Sjhb /* Set this APIC's logical ID. */ 302121986Sjhb value = lapic->ldr; 303121986Sjhb value &= ~APIC_ID_MASK; 304121986Sjhb value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT | 305121986Sjhb 1 << la->la_cluster_id) << APIC_ID_SHIFT; 306121986Sjhb lapic->ldr = value; 307121986Sjhb 308121986Sjhb /* Setup spurious vector and enable the local APIC. */ 309139245Sjhb lapic_enable(); 310139245Sjhb 311139245Sjhb /* Program LINT[01] LVT entries. */ 312139245Sjhb lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 313139245Sjhb lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 314145256Sjkoshy#ifdef HWPMC_HOOKS 315145256Sjkoshy /* Program the PMC LVT entry if present. */ 316145256Sjkoshy if (maxlvt >= LVT_PMC) 317145256Sjkoshy lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 318145256Sjkoshy#endif 319139245Sjhb 320141538Sjhb /* Program timer LVT and setup handler. */ 321141538Sjhb lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 322150696Sjhb snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 323141538Sjhb intrcnt_add(buf, &la->la_timer_count); 324141538Sjhb if (PCPU_GET(cpuid) != 0) { 325141538Sjhb KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 326141538Sjhb lapic_id())); 327141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 328141538Sjhb lapic_timer_periodic(lapic_timer_period); 329141538Sjhb lapic_timer_enable_intr(); 330141538Sjhb } 331139245Sjhb 332150176Sjhb /* XXX: Error and thermal LVTs */ 333141538Sjhb 334121986Sjhb intr_restore(eflags); 335121986Sjhb} 336121986Sjhb 337141538Sjhb/* 338141538Sjhb * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 339141538Sjhb * that it can drive hardclock, statclock, and profclock. This function 340141538Sjhb * returns true if it is able to use the local APIC timer to drive the 341141538Sjhb * clocks and false if it is not able. 342141538Sjhb */ 343141538Sjhbint 344141538Sjhblapic_setup_clock(void) 345141538Sjhb{ 346141538Sjhb u_long value; 347141538Sjhb 348141538Sjhb /* Can't drive the timer without a local APIC. */ 349141538Sjhb if (lapic == NULL) 350141538Sjhb return (0); 351141538Sjhb 352141538Sjhb /* Start off with a divisor of 2 (power on reset default). */ 353141538Sjhb lapic_timer_divisor = 2; 354141538Sjhb 355141538Sjhb /* Try to calibrate the local APIC timer. */ 356141538Sjhb do { 357141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 358141538Sjhb lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 359141538Sjhb DELAY(2000000); 360141538Sjhb value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 361141538Sjhb if (value != APIC_TIMER_MAX_COUNT) 362141538Sjhb break; 363141538Sjhb lapic_timer_divisor <<= 1; 364141538Sjhb } while (lapic_timer_divisor <= 128); 365141538Sjhb if (lapic_timer_divisor > 128) 366141538Sjhb panic("lapic: Divisor too big"); 367141538Sjhb value /= 2; 368141538Sjhb if (bootverbose) 369141538Sjhb printf("lapic: Divisor %lu, Frequency %lu hz\n", 370141538Sjhb lapic_timer_divisor, value); 371141538Sjhb 372141538Sjhb /* 373141538Sjhb * We will drive the timer at a small multiple of hz and drive 374141538Sjhb * both of the other timers with similarly small but relatively 375141538Sjhb * prime divisors. 376141538Sjhb */ 377141538Sjhb lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 378141538Sjhb stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 379141538Sjhb profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 380141538Sjhb lapic_timer_period = value / lapic_timer_hz; 381141538Sjhb 382141538Sjhb /* 383141538Sjhb * Start up the timer on the BSP. The APs will kick off their 384141538Sjhb * timer during lapic_setup(). 385141538Sjhb */ 386141538Sjhb lapic_timer_periodic(lapic_timer_period); 387141538Sjhb lapic_timer_enable_intr(); 388141538Sjhb return (1); 389141538Sjhb} 390141538Sjhb 391121986Sjhbvoid 392121986Sjhblapic_disable(void) 393121986Sjhb{ 394121986Sjhb uint32_t value; 395121986Sjhb 396121986Sjhb /* Software disable the local APIC. */ 397121986Sjhb value = lapic->svr; 398121986Sjhb value &= ~APIC_SVR_SWEN; 399121986Sjhb lapic->svr = value; 400121986Sjhb} 401121986Sjhb 402139245Sjhbstatic void 403139245Sjhblapic_enable(void) 404139245Sjhb{ 405139245Sjhb u_int32_t value; 406139245Sjhb 407139245Sjhb /* Program the spurious vector to enable the local APIC. */ 408139245Sjhb value = lapic->svr; 409139245Sjhb value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 410139245Sjhb value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 411139245Sjhb lapic->svr = value; 412139245Sjhb} 413139245Sjhb 414121986Sjhbint 415121986Sjhblapic_id(void) 416121986Sjhb{ 417121986Sjhb 418121986Sjhb KASSERT(lapic != NULL, ("local APIC is not mapped")); 419121986Sjhb return (lapic->id >> APIC_ID_SHIFT); 420121986Sjhb} 421121986Sjhb 422121986Sjhbint 423121986Sjhblapic_intr_pending(u_int vector) 424121986Sjhb{ 425121986Sjhb volatile u_int32_t *irr; 426121986Sjhb 427121986Sjhb /* 428121986Sjhb * The IRR registers are an array of 128-bit registers each of 429121986Sjhb * which only describes 32 interrupts in the low 32 bits.. Thus, 430121986Sjhb * we divide the vector by 32 to get the 128-bit index. We then 431121986Sjhb * multiply that index by 4 to get the equivalent index from 432121986Sjhb * treating the IRR as an array of 32-bit registers. Finally, we 433121986Sjhb * modulus the vector by 32 to determine the individual bit to 434121986Sjhb * test. 435121986Sjhb */ 436121986Sjhb irr = &lapic->irr0; 437121986Sjhb return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 438121986Sjhb} 439121986Sjhb 440121986Sjhbvoid 441121986Sjhblapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 442121986Sjhb{ 443121986Sjhb struct lapic *la; 444121986Sjhb 445121986Sjhb KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 446121986Sjhb __func__, apic_id)); 447121986Sjhb KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 448121986Sjhb __func__, cluster)); 449121986Sjhb KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 450121986Sjhb ("%s: intra cluster id %u too big", __func__, cluster_id)); 451121986Sjhb la = &lapics[apic_id]; 452121986Sjhb la->la_cluster = cluster; 453121986Sjhb la->la_cluster_id = cluster_id; 454121986Sjhb} 455121986Sjhb 456121986Sjhbint 457121986Sjhblapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 458121986Sjhb{ 459121986Sjhb 460121986Sjhb if (pin > LVT_MAX) 461121986Sjhb return (EINVAL); 462121986Sjhb if (apic_id == APIC_ID_ALL) { 463121986Sjhb lvts[pin].lvt_masked = masked; 464121986Sjhb if (bootverbose) 465121986Sjhb printf("lapic:"); 466121986Sjhb } else { 467121986Sjhb KASSERT(lapics[apic_id].la_present, 468121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 469121986Sjhb lapics[apic_id].la_lvts[pin].lvt_masked = masked; 470121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 471121986Sjhb if (bootverbose) 472121986Sjhb printf("lapic%u:", apic_id); 473121986Sjhb } 474121986Sjhb if (bootverbose) 475121986Sjhb printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 476121986Sjhb return (0); 477121986Sjhb} 478121986Sjhb 479121986Sjhbint 480121986Sjhblapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 481121986Sjhb{ 482121986Sjhb struct lvt *lvt; 483121986Sjhb 484121986Sjhb if (pin > LVT_MAX) 485121986Sjhb return (EINVAL); 486121986Sjhb if (apic_id == APIC_ID_ALL) { 487121986Sjhb lvt = &lvts[pin]; 488121986Sjhb if (bootverbose) 489121986Sjhb printf("lapic:"); 490121986Sjhb } else { 491121986Sjhb KASSERT(lapics[apic_id].la_present, 492121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 493121986Sjhb lvt = &lapics[apic_id].la_lvts[pin]; 494121986Sjhb lvt->lvt_active = 1; 495121986Sjhb if (bootverbose) 496121986Sjhb printf("lapic%u:", apic_id); 497121986Sjhb } 498121986Sjhb lvt->lvt_mode = mode; 499121986Sjhb switch (mode) { 500121986Sjhb case APIC_LVT_DM_NMI: 501121986Sjhb case APIC_LVT_DM_SMI: 502121986Sjhb case APIC_LVT_DM_INIT: 503121986Sjhb case APIC_LVT_DM_EXTINT: 504121986Sjhb lvt->lvt_edgetrigger = 1; 505121986Sjhb lvt->lvt_activehi = 1; 506121986Sjhb if (mode == APIC_LVT_DM_EXTINT) 507121986Sjhb lvt->lvt_masked = 1; 508121986Sjhb else 509121986Sjhb lvt->lvt_masked = 0; 510121986Sjhb break; 511121986Sjhb default: 512121986Sjhb panic("Unsupported delivery mode: 0x%x\n", mode); 513121986Sjhb } 514121986Sjhb if (bootverbose) { 515121986Sjhb printf(" Routing "); 516121986Sjhb switch (mode) { 517121986Sjhb case APIC_LVT_DM_NMI: 518121986Sjhb printf("NMI"); 519121986Sjhb break; 520121986Sjhb case APIC_LVT_DM_SMI: 521121986Sjhb printf("SMI"); 522121986Sjhb break; 523121986Sjhb case APIC_LVT_DM_INIT: 524121986Sjhb printf("INIT"); 525121986Sjhb break; 526121986Sjhb case APIC_LVT_DM_EXTINT: 527121986Sjhb printf("ExtINT"); 528121986Sjhb break; 529121986Sjhb } 530121986Sjhb printf(" -> LINT%u\n", pin); 531121986Sjhb } 532121986Sjhb return (0); 533121986Sjhb} 534121986Sjhb 535121986Sjhbint 536128930Sjhblapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 537121986Sjhb{ 538121986Sjhb 539128930Sjhb if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 540121986Sjhb return (EINVAL); 541121986Sjhb if (apic_id == APIC_ID_ALL) { 542128930Sjhb lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 543121986Sjhb if (bootverbose) 544121986Sjhb printf("lapic:"); 545121986Sjhb } else { 546121986Sjhb KASSERT(lapics[apic_id].la_present, 547121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 548121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 549128930Sjhb lapics[apic_id].la_lvts[pin].lvt_activehi = 550128930Sjhb (pol == INTR_POLARITY_HIGH); 551121986Sjhb if (bootverbose) 552121986Sjhb printf("lapic%u:", apic_id); 553121986Sjhb } 554121986Sjhb if (bootverbose) 555140254Sjhb printf(" LINT%u polarity: %s\n", pin, 556128930Sjhb pol == INTR_POLARITY_HIGH ? "high" : "low"); 557121986Sjhb return (0); 558121986Sjhb} 559121986Sjhb 560121986Sjhbint 561128930Sjhblapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 562121986Sjhb{ 563121986Sjhb 564128930Sjhb if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 565121986Sjhb return (EINVAL); 566121986Sjhb if (apic_id == APIC_ID_ALL) { 567128930Sjhb lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 568121986Sjhb if (bootverbose) 569121986Sjhb printf("lapic:"); 570121986Sjhb } else { 571121986Sjhb KASSERT(lapics[apic_id].la_present, 572121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 573128930Sjhb lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 574128930Sjhb (trigger == INTR_TRIGGER_EDGE); 575121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 576121986Sjhb if (bootverbose) 577121986Sjhb printf("lapic%u:", apic_id); 578121986Sjhb } 579121986Sjhb if (bootverbose) 580121986Sjhb printf(" LINT%u trigger: %s\n", pin, 581128930Sjhb trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 582121986Sjhb return (0); 583121986Sjhb} 584121986Sjhb 585139240Sjhb/* 586139240Sjhb * Adjust the TPR of the current CPU so that it blocks all interrupts below 587139240Sjhb * the passed in vector. 588139240Sjhb */ 589121986Sjhbvoid 590139240Sjhblapic_set_tpr(u_int vector) 591139240Sjhb{ 592139240Sjhb#ifdef CHEAP_TPR 593139240Sjhb lapic->tpr = vector; 594139240Sjhb#else 595139240Sjhb u_int32_t tpr; 596139240Sjhb 597139240Sjhb tpr = lapic->tpr & ~APIC_TPR_PRIO; 598139240Sjhb tpr |= vector; 599139240Sjhb lapic->tpr = tpr; 600139240Sjhb#endif 601139240Sjhb} 602139240Sjhb 603139240Sjhbvoid 604122572Sjhblapic_eoi(void) 605122572Sjhb{ 606122572Sjhb 607122572Sjhb lapic->eoi = 0; 608122572Sjhb} 609122572Sjhb 610122572Sjhbvoid 611121986Sjhblapic_handle_intr(struct intrframe frame) 612121986Sjhb{ 613121986Sjhb struct intsrc *isrc; 614121986Sjhb 615121986Sjhb if (frame.if_vec == -1) 616121986Sjhb panic("Couldn't get vector from ISR!"); 617121986Sjhb isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec)); 618121986Sjhb intr_execute_handlers(isrc, &frame); 619121986Sjhb} 620121986Sjhb 621141538Sjhbvoid 622141538Sjhblapic_handle_timer(struct clockframe frame) 623141538Sjhb{ 624141538Sjhb struct lapic *la; 625141538Sjhb 626141538Sjhb la = &lapics[PCPU_GET(apic_id)]; 627141538Sjhb (*la->la_timer_count)++; 628141538Sjhb critical_enter(); 629141538Sjhb 630141538Sjhb /* Fire hardclock at hz. */ 631141538Sjhb la->la_hard_ticks += hz; 632141538Sjhb if (la->la_hard_ticks >= lapic_timer_hz) { 633141538Sjhb la->la_hard_ticks -= lapic_timer_hz; 634143034Sjhb if (PCPU_GET(cpuid) == 0) 635141538Sjhb hardclock(&frame); 636143034Sjhb else 637141538Sjhb hardclock_process(&frame); 638141538Sjhb } 639141538Sjhb 640141538Sjhb /* Fire statclock at stathz. */ 641141538Sjhb la->la_stat_ticks += stathz; 642141538Sjhb if (la->la_stat_ticks >= lapic_timer_hz) { 643141538Sjhb la->la_stat_ticks -= lapic_timer_hz; 644141538Sjhb statclock(&frame); 645141538Sjhb } 646141538Sjhb 647141538Sjhb /* Fire profclock at profhz, but only when needed. */ 648141538Sjhb la->la_prof_ticks += profhz; 649141538Sjhb if (la->la_prof_ticks >= lapic_timer_hz) { 650141538Sjhb la->la_prof_ticks -= lapic_timer_hz; 651141538Sjhb if (profprocs != 0) 652141538Sjhb profclock(&frame); 653141538Sjhb } 654141538Sjhb critical_exit(); 655141538Sjhb} 656141538Sjhb 657141538Sjhbstatic void 658141538Sjhblapic_timer_set_divisor(u_int divisor) 659141538Sjhb{ 660141538Sjhb 661141538Sjhb KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 662141538Sjhb KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 663141538Sjhb sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 664141538Sjhb lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 665141538Sjhb} 666141538Sjhb 667141538Sjhbstatic void 668141538Sjhblapic_timer_oneshot(u_int count) 669141538Sjhb{ 670141538Sjhb u_int32_t value; 671141538Sjhb 672141538Sjhb value = lapic->lvt_timer; 673141538Sjhb value &= ~APIC_LVTT_TM; 674141538Sjhb value |= APIC_LVTT_TM_ONE_SHOT; 675141538Sjhb lapic->lvt_timer = value; 676141538Sjhb lapic->icr_timer = count; 677141538Sjhb} 678141538Sjhb 679141538Sjhbstatic void 680141538Sjhblapic_timer_periodic(u_int count) 681141538Sjhb{ 682141538Sjhb u_int32_t value; 683141538Sjhb 684141538Sjhb value = lapic->lvt_timer; 685141538Sjhb value &= ~APIC_LVTT_TM; 686141538Sjhb value |= APIC_LVTT_TM_PERIODIC; 687141538Sjhb lapic->lvt_timer = value; 688141538Sjhb lapic->icr_timer = count; 689141538Sjhb} 690141538Sjhb 691141538Sjhbstatic void 692141538Sjhblapic_timer_enable_intr(void) 693141538Sjhb{ 694141538Sjhb u_int32_t value; 695141538Sjhb 696141538Sjhb value = lapic->lvt_timer; 697141538Sjhb value &= ~APIC_LVT_M; 698141538Sjhb lapic->lvt_timer = value; 699141538Sjhb} 700141538Sjhb 701151979Sjhb/* Request a free IDT vector to be used by the specified IRQ. */ 702121986Sjhbu_int 703151979Sjhbapic_alloc_vector(u_int irq) 704121986Sjhb{ 705121986Sjhb u_int vector; 706121986Sjhb 707121986Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 708151979Sjhb 709151979Sjhb /* 710151979Sjhb * Search for a free vector. Currently we just use a very simple 711151979Sjhb * algorithm to find the first free vector. 712151979Sjhb */ 713151979Sjhb mtx_lock_spin(&icu_lock); 714151979Sjhb for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 715151979Sjhb if (ioint_irqs[vector] != 0) 716151979Sjhb continue; 717151979Sjhb ioint_irqs[vector] = irq; 718151979Sjhb mtx_unlock_spin(&icu_lock); 719151979Sjhb return (vector + APIC_IO_INTS); 720151979Sjhb } 721151979Sjhb mtx_unlock_spin(&icu_lock); 722151979Sjhb panic("Couldn't find an APIC vector for IRQ %u", irq); 723121986Sjhb} 724121986Sjhb 725151979Sjhbvoid 726151979Sjhbapic_enable_vector(u_int vector) 727151979Sjhb{ 728151979Sjhb 729151979Sjhb KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 730151979Sjhb KASSERT(ioint_handlers[vector / 32] != NULL, 731151979Sjhb ("No ISR handler for vector %u", vector)); 732151979Sjhb setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 733151979Sjhb GSEL(GCODE_SEL, SEL_KPL)); 734151979Sjhb} 735151979Sjhb 736151979Sjhb/* Release an APIC vector when it's no longer in use. */ 737151979Sjhbvoid 738151979Sjhbapic_free_vector(u_int vector, u_int irq) 739151979Sjhb{ 740151979Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 741151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 742151979Sjhb ("Vector %u does not map to an IRQ line", vector)); 743151979Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 744151979Sjhb KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 745151979Sjhb mtx_lock_spin(&icu_lock); 746151979Sjhb ioint_irqs[vector - APIC_IO_INTS] = 0; 747151979Sjhb mtx_unlock_spin(&icu_lock); 748151979Sjhb} 749151979Sjhb 750151979Sjhb/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 751121986Sjhbu_int 752121986Sjhbapic_idt_to_irq(u_int vector) 753121986Sjhb{ 754121986Sjhb 755122690Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 756151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 757121986Sjhb ("Vector %u does not map to an IRQ line", vector)); 758151979Sjhb return (ioint_irqs[vector - APIC_IO_INTS]); 759121986Sjhb} 760121986Sjhb 761151979Sjhb#ifdef DDB 762121986Sjhb/* 763151979Sjhb * Dump data about APIC IDT vector mappings. 764151979Sjhb */ 765151979SjhbDB_SHOW_COMMAND(apic, db_show_apic) 766151979Sjhb{ 767151979Sjhb struct intsrc *isrc; 768151979Sjhb int quit, i, verbose; 769151979Sjhb u_int irq; 770151979Sjhb 771151979Sjhb quit = 0; 772151979Sjhb if (strcmp(modif, "vv") == 0) 773151979Sjhb verbose = 2; 774151979Sjhb else if (strcmp(modif, "v") == 0) 775151979Sjhb verbose = 1; 776151979Sjhb else 777151979Sjhb verbose = 0; 778151979Sjhb db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 779151979Sjhb for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) { 780151979Sjhb irq = ioint_irqs[i]; 781151979Sjhb if (irq != 0 && irq != IRQ_SYSCALL) { 782151979Sjhb db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 783151979Sjhb if (irq == IRQ_TIMER) 784151979Sjhb db_printf("lapic timer\n"); 785151979Sjhb else if (irq < NUM_IO_INTS) { 786151979Sjhb isrc = intr_lookup_source(irq); 787151979Sjhb if (isrc == NULL || verbose == 0) 788151979Sjhb db_printf("IRQ %u\n", irq); 789151979Sjhb else 790151979Sjhb db_dump_intr_event(isrc->is_event, 791151979Sjhb verbose == 2); 792151979Sjhb } else 793151979Sjhb db_printf("IRQ %u ???\n", irq); 794151979Sjhb } 795151979Sjhb } 796151979Sjhb} 797151979Sjhb#endif 798151979Sjhb 799151979Sjhb/* 800121986Sjhb * APIC probing support code. This includes code to manage enumerators. 801121986Sjhb */ 802121986Sjhb 803121986Sjhbstatic SLIST_HEAD(, apic_enumerator) enumerators = 804121986Sjhb SLIST_HEAD_INITIALIZER(enumerators); 805121986Sjhbstatic struct apic_enumerator *best_enum; 806121986Sjhb 807121986Sjhbvoid 808121986Sjhbapic_register_enumerator(struct apic_enumerator *enumerator) 809121986Sjhb{ 810121986Sjhb#ifdef INVARIANTS 811121986Sjhb struct apic_enumerator *apic_enum; 812121986Sjhb 813121986Sjhb SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 814121986Sjhb if (apic_enum == enumerator) 815121986Sjhb panic("%s: Duplicate register of %s", __func__, 816121986Sjhb enumerator->apic_name); 817121986Sjhb } 818121986Sjhb#endif 819121986Sjhb SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 820121986Sjhb} 821121986Sjhb 822121986Sjhb/* 823123133Sjhb * Probe the APIC enumerators, enumerate CPUs, and initialize the 824123133Sjhb * local APIC. 825121986Sjhb */ 826121986Sjhbstatic void 827121986Sjhbapic_init(void *dummy __unused) 828121986Sjhb{ 829121986Sjhb struct apic_enumerator *enumerator; 830123133Sjhb uint64_t apic_base; 831121986Sjhb int retval, best; 832121986Sjhb 833121986Sjhb /* We only support built in local APICs. */ 834121986Sjhb if (!(cpu_feature & CPUID_APIC)) 835121986Sjhb return; 836121986Sjhb 837123133Sjhb /* Don't probe if APIC mode is disabled. */ 838123133Sjhb if (resource_disabled("apic", 0)) 839123133Sjhb return; 840123133Sjhb 841121986Sjhb /* First, probe all the enumerators to find the best match. */ 842121986Sjhb best_enum = NULL; 843121986Sjhb best = 0; 844121986Sjhb SLIST_FOREACH(enumerator, &enumerators, apic_next) { 845121986Sjhb retval = enumerator->apic_probe(); 846121986Sjhb if (retval > 0) 847121986Sjhb continue; 848121986Sjhb if (best_enum == NULL || best < retval) { 849121986Sjhb best_enum = enumerator; 850121986Sjhb best = retval; 851121986Sjhb } 852121986Sjhb } 853121986Sjhb if (best_enum == NULL) { 854121986Sjhb if (bootverbose) 855121986Sjhb printf("APIC: Could not find any APICs.\n"); 856121986Sjhb return; 857121986Sjhb } 858121986Sjhb 859121986Sjhb if (bootverbose) 860121986Sjhb printf("APIC: Using the %s enumerator.\n", 861121986Sjhb best_enum->apic_name); 862121986Sjhb 863121986Sjhb /* 864121986Sjhb * To work around an errata, we disable the local APIC on some 865121986Sjhb * CPUs during early startup. We need to turn the local APIC back 866121986Sjhb * on on such CPUs now. 867121986Sjhb */ 868121986Sjhb if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 869121986Sjhb (cpu_id & 0xff0) == 0x610) { 870121986Sjhb apic_base = rdmsr(MSR_APICBASE); 871121986Sjhb apic_base |= APICBASE_ENABLED; 872121986Sjhb wrmsr(MSR_APICBASE, apic_base); 873121986Sjhb } 874123133Sjhb 875123133Sjhb /* Second, probe the CPU's in the system. */ 876123133Sjhb retval = best_enum->apic_probe_cpus(); 877123133Sjhb if (retval != 0) 878123133Sjhb printf("%s: Failed to probe CPUs: returned %d\n", 879123133Sjhb best_enum->apic_name, retval); 880123133Sjhb 881123133Sjhb /* Third, initialize the local APIC. */ 882121986Sjhb retval = best_enum->apic_setup_local(); 883121986Sjhb if (retval != 0) 884121986Sjhb printf("%s: Failed to setup the local APIC: returned %d\n", 885121986Sjhb best_enum->apic_name, retval); 886123432Sjeff#ifdef SMP 887123432Sjeff /* Last, setup the cpu topology now that we have probed CPUs */ 888123432Sjeff mp_topology(); 889123432Sjeff#endif 890121986Sjhb} 891123133SjhbSYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL) 892121986Sjhb 893121986Sjhb/* 894121986Sjhb * Setup the I/O APICs. 895121986Sjhb */ 896121986Sjhbstatic void 897121986Sjhbapic_setup_io(void *dummy __unused) 898121986Sjhb{ 899121986Sjhb int retval; 900121986Sjhb 901121986Sjhb if (best_enum == NULL) 902121986Sjhb return; 903121986Sjhb retval = best_enum->apic_setup_io(); 904121986Sjhb if (retval != 0) 905121986Sjhb printf("%s: Failed to setup I/O APICs: returned %d\n", 906121986Sjhb best_enum->apic_name, retval); 907121986Sjhb 908121986Sjhb /* 909121986Sjhb * Finish setting up the local APIC on the BSP once we know how to 910121986Sjhb * properly program the LINT pins. 911121986Sjhb */ 912121986Sjhb lapic_setup(); 913121986Sjhb if (bootverbose) 914121986Sjhb lapic_dump("BSP"); 915121986Sjhb} 916121986SjhbSYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 917121986Sjhb 918121986Sjhb#ifdef SMP 919121986Sjhb/* 920121986Sjhb * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 921139240Sjhb * private to the sys/i386 code. The public interface for the rest of the 922121986Sjhb * kernel is defined in mp_machdep.c. 923121986Sjhb */ 924121986Sjhbint 925121986Sjhblapic_ipi_wait(int delay) 926121986Sjhb{ 927121986Sjhb int x, incr; 928121986Sjhb 929121986Sjhb /* 930121986Sjhb * Wait delay loops for IPI to be sent. This is highly bogus 931121986Sjhb * since this is sensitive to CPU clock speed. If delay is 932121986Sjhb * -1, we wait forever. 933121986Sjhb */ 934121986Sjhb if (delay == -1) { 935121986Sjhb incr = 0; 936121986Sjhb delay = 1; 937121986Sjhb } else 938121986Sjhb incr = 1; 939121986Sjhb for (x = 0; x < delay; x += incr) { 940121986Sjhb if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 941121986Sjhb return (1); 942121986Sjhb ia32_pause(); 943121986Sjhb } 944121986Sjhb return (0); 945121986Sjhb} 946121986Sjhb 947121986Sjhbvoid 948121986Sjhblapic_ipi_raw(register_t icrlo, u_int dest) 949121986Sjhb{ 950121986Sjhb register_t value, eflags; 951121986Sjhb 952121986Sjhb /* XXX: Need more sanity checking of icrlo? */ 953121986Sjhb KASSERT(lapic != NULL, ("%s called too early", __func__)); 954121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 955121986Sjhb ("%s: invalid dest field", __func__)); 956121986Sjhb KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 957121986Sjhb ("%s: reserved bits set in ICR LO register", __func__)); 958121986Sjhb 959121986Sjhb /* Set destination in ICR HI register if it is being used. */ 960121986Sjhb eflags = intr_disable(); 961121986Sjhb if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 962121986Sjhb value = lapic->icr_hi; 963121986Sjhb value &= ~APIC_ID_MASK; 964121986Sjhb value |= dest << APIC_ID_SHIFT; 965121986Sjhb lapic->icr_hi = value; 966121986Sjhb } 967121986Sjhb 968121986Sjhb /* Program the contents of the IPI and dispatch it. */ 969121986Sjhb value = lapic->icr_lo; 970121986Sjhb value &= APIC_ICRLO_RESV_MASK; 971121986Sjhb value |= icrlo; 972121986Sjhb lapic->icr_lo = value; 973121986Sjhb intr_restore(eflags); 974121986Sjhb} 975121986Sjhb 976125317Sjeff#define BEFORE_SPIN 1000000 977121986Sjhb#ifdef DETECT_DEADLOCK 978121986Sjhb#define AFTER_SPIN 1000 979121986Sjhb#endif 980121986Sjhb 981121986Sjhbvoid 982121986Sjhblapic_ipi_vectored(u_int vector, int dest) 983121986Sjhb{ 984121986Sjhb register_t icrlo, destfield; 985121986Sjhb 986121986Sjhb KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 987121986Sjhb ("%s: invalid vector %d", __func__, vector)); 988121986Sjhb 989121986Sjhb icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 990121986Sjhb APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 991121986Sjhb destfield = 0; 992121986Sjhb switch (dest) { 993121986Sjhb case APIC_IPI_DEST_SELF: 994121986Sjhb icrlo |= APIC_DEST_SELF; 995121986Sjhb break; 996121986Sjhb case APIC_IPI_DEST_ALL: 997121986Sjhb icrlo |= APIC_DEST_ALLISELF; 998121986Sjhb break; 999121986Sjhb case APIC_IPI_DEST_OTHERS: 1000121986Sjhb icrlo |= APIC_DEST_ALLESELF; 1001121986Sjhb break; 1002121986Sjhb default: 1003121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1004121986Sjhb ("%s: invalid destination 0x%x", __func__, dest)); 1005121986Sjhb destfield = dest; 1006121986Sjhb } 1007121986Sjhb 1008125317Sjeff /* Wait for an earlier IPI to finish. */ 1009150176Sjhb if (!lapic_ipi_wait(BEFORE_SPIN)) { 1010150176Sjhb if (panicstr != NULL) 1011150176Sjhb return; 1012150176Sjhb else 1013150176Sjhb panic("APIC: Previous IPI is stuck"); 1014150176Sjhb } 1015121986Sjhb 1016121986Sjhb lapic_ipi_raw(icrlo, destfield); 1017121986Sjhb 1018121986Sjhb#ifdef DETECT_DEADLOCK 1019121986Sjhb /* Wait for IPI to be delivered. */ 1020121986Sjhb if (!lapic_ipi_wait(AFTER_SPIN)) { 1021121986Sjhb#ifdef needsattention 1022121986Sjhb /* 1023121986Sjhb * XXX FIXME: 1024121986Sjhb * 1025121986Sjhb * The above function waits for the message to actually be 1026121986Sjhb * delivered. It breaks out after an arbitrary timeout 1027121986Sjhb * since the message should eventually be delivered (at 1028121986Sjhb * least in theory) and that if it wasn't we would catch 1029121986Sjhb * the failure with the check above when the next IPI is 1030121986Sjhb * sent. 1031121986Sjhb * 1032139240Sjhb * We could skip this wait entirely, EXCEPT it probably 1033121986Sjhb * protects us from other routines that assume that the 1034121986Sjhb * message was delivered and acted upon when this function 1035121986Sjhb * returns. 1036121986Sjhb */ 1037121986Sjhb printf("APIC: IPI might be stuck\n"); 1038121986Sjhb#else /* !needsattention */ 1039121986Sjhb /* Wait until mesage is sent without a timeout. */ 1040121986Sjhb while (lapic->icr_lo & APIC_DELSTAT_PEND) 1041121986Sjhb ia32_pause(); 1042121986Sjhb#endif /* needsattention */ 1043121986Sjhb } 1044121986Sjhb#endif /* DETECT_DEADLOCK */ 1045121986Sjhb} 1046121986Sjhb#endif /* SMP */ 1047