local_apic.c revision 151979
1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/i386/i386/local_apic.c 151979 2005-11-02 20:11:47Z jhb $"); 36 37#include "opt_hwpmc_hooks.h" 38 39#include "opt_ddb.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/smp.h> 49 50#include <vm/vm.h> 51#include <vm/pmap.h> 52 53#include <machine/apicreg.h> 54#include <machine/cputypes.h> 55#include <machine/frame.h> 56#include <machine/intr_machdep.h> 57#include <machine/apicvar.h> 58#include <machine/md_var.h> 59#include <machine/smp.h> 60#include <machine/specialreg.h> 61 62#ifdef DDB 63#include <sys/interrupt.h> 64#include <ddb/ddb.h> 65#endif 66 67/* 68 * We can handle up to 60 APICs via our logical cluster IDs, but currently 69 * the physical IDs on Intel processors up to the Pentium 4 are limited to 70 * 16. 71 */ 72#define MAX_APICID 16 73 74/* Sanity checks on IDT vectors. */ 75CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 76CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 77CTASSERT(APIC_LOCAL_INTS == 240); 78CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 79 80#define LAPIC_TIMER_HZ_DIVIDER 2 81#define LAPIC_TIMER_STATHZ_DIVIDER 15 82#define LAPIC_TIMER_PROFHZ_DIVIDER 3 83 84/* Magic IRQ values for the timer and syscalls. */ 85#define IRQ_TIMER (NUM_IO_INTS + 1) 86#define IRQ_SYSCALL (NUM_IO_INTS + 2) 87 88/* 89 * Support for local APICs. Local APICs manage interrupts on each 90 * individual processor as opposed to I/O APICs which receive interrupts 91 * from I/O devices and then forward them on to the local APICs. 92 * 93 * Local APICs can also send interrupts to each other thus providing the 94 * mechanism for IPIs. 95 */ 96 97struct lvt { 98 u_int lvt_edgetrigger:1; 99 u_int lvt_activehi:1; 100 u_int lvt_masked:1; 101 u_int lvt_active:1; 102 u_int lvt_mode:16; 103 u_int lvt_vector:8; 104}; 105 106struct lapic { 107 struct lvt la_lvts[LVT_MAX + 1]; 108 u_int la_id:8; 109 u_int la_cluster:4; 110 u_int la_cluster_id:2; 111 u_int la_present:1; 112 u_long *la_timer_count; 113 u_long la_hard_ticks; 114 u_long la_stat_ticks; 115 u_long la_prof_ticks; 116} static lapics[MAX_APICID]; 117 118/* XXX: should thermal be an NMI? */ 119 120/* Global defaults for local APIC LVT entries. */ 121static struct lvt lvts[LVT_MAX + 1] = { 122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 126 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 128}; 129 130static inthand_t *ioint_handlers[] = { 131 NULL, /* 0 - 31 */ 132 IDTVEC(apic_isr1), /* 32 - 63 */ 133 IDTVEC(apic_isr2), /* 64 - 95 */ 134 IDTVEC(apic_isr3), /* 96 - 127 */ 135 IDTVEC(apic_isr4), /* 128 - 159 */ 136 IDTVEC(apic_isr5), /* 160 - 191 */ 137 IDTVEC(apic_isr6), /* 192 - 223 */ 138 IDTVEC(apic_isr7), /* 224 - 255 */ 139}; 140 141/* Include IDT_SYSCALL to make indexing easier. */ 142static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 143 144static u_int32_t lapic_timer_divisors[] = { 145 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 146 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 147}; 148 149volatile lapic_t *lapic; 150static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 151 152static void lapic_enable(void); 153static void lapic_timer_enable_intr(void); 154static void lapic_timer_oneshot(u_int count); 155static void lapic_timer_periodic(u_int count); 156static void lapic_timer_set_divisor(u_int divisor); 157static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 158 159static uint32_t 160lvt_mode(struct lapic *la, u_int pin, uint32_t value) 161{ 162 struct lvt *lvt; 163 164 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 165 if (la->la_lvts[pin].lvt_active) 166 lvt = &la->la_lvts[pin]; 167 else 168 lvt = &lvts[pin]; 169 170 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 171 APIC_LVT_VECTOR); 172 if (lvt->lvt_edgetrigger == 0) 173 value |= APIC_LVT_TM; 174 if (lvt->lvt_activehi == 0) 175 value |= APIC_LVT_IIPP_INTALO; 176 if (lvt->lvt_masked) 177 value |= APIC_LVT_M; 178 value |= lvt->lvt_mode; 179 switch (lvt->lvt_mode) { 180 case APIC_LVT_DM_NMI: 181 case APIC_LVT_DM_SMI: 182 case APIC_LVT_DM_INIT: 183 case APIC_LVT_DM_EXTINT: 184 if (!lvt->lvt_edgetrigger) { 185 printf("lapic%u: Forcing LINT%u to edge trigger\n", 186 la->la_id, pin); 187 value |= APIC_LVT_TM; 188 } 189 /* Use a vector of 0. */ 190 break; 191 case APIC_LVT_DM_FIXED: 192 value |= lvt->lvt_vector; 193 break; 194 default: 195 panic("bad APIC LVT delivery mode: %#x\n", value); 196 } 197 return (value); 198} 199 200/* 201 * Map the local APIC and setup necessary interrupt vectors. 202 */ 203void 204lapic_init(uintptr_t addr) 205{ 206 207 /* Map the local APIC and setup the spurious interrupt handler. */ 208 KASSERT(trunc_page(addr) == addr, 209 ("local APIC not aligned on a page boundary")); 210 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t)); 211 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 212 GSEL(GCODE_SEL, SEL_KPL)); 213 214 /* Perform basic initialization of the BSP's local APIC. */ 215 lapic_enable(); 216 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 217 218 /* Set BSP's per-CPU local APIC ID. */ 219 PCPU_SET(apic_id, lapic_id()); 220 221 /* Local APIC timer interrupt. */ 222 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 223 GSEL(GCODE_SEL, SEL_KPL)); 224 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 225 226 /* XXX: error/thermal interrupts */ 227} 228 229/* 230 * Create a local APIC instance. 231 */ 232void 233lapic_create(u_int apic_id, int boot_cpu) 234{ 235 int i; 236 237 if (apic_id >= MAX_APICID) { 238 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 239 if (boot_cpu) 240 panic("Can't ignore BSP"); 241 return; 242 } 243 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 244 apic_id)); 245 246 /* 247 * Assume no local LVT overrides and a cluster of 0 and 248 * intra-cluster ID of 0. 249 */ 250 lapics[apic_id].la_present = 1; 251 lapics[apic_id].la_id = apic_id; 252 for (i = 0; i < LVT_MAX; i++) { 253 lapics[apic_id].la_lvts[i] = lvts[i]; 254 lapics[apic_id].la_lvts[i].lvt_active = 0; 255 } 256 257#ifdef SMP 258 cpu_add(apic_id, boot_cpu); 259#endif 260} 261 262/* 263 * Dump contents of local APIC registers 264 */ 265void 266lapic_dump(const char* str) 267{ 268 269 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 270 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 271 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 272 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 273 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 274 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 275 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 276 lapic->lvt_pcint); 277} 278 279void 280lapic_setup(void) 281{ 282 struct lapic *la; 283 u_int32_t value, maxlvt; 284 register_t eflags; 285 char buf[MAXCOMLEN + 1]; 286 287 la = &lapics[lapic_id()]; 288 KASSERT(la->la_present, ("missing APIC structure")); 289 eflags = intr_disable(); 290 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 291 292 /* Initialize the TPR to allow all interrupts. */ 293 lapic_set_tpr(0); 294 295 /* Use the cluster model for logical IDs. */ 296 value = lapic->dfr; 297 value &= ~APIC_DFR_MODEL_MASK; 298 value |= APIC_DFR_MODEL_CLUSTER; 299 lapic->dfr = value; 300 301 /* Set this APIC's logical ID. */ 302 value = lapic->ldr; 303 value &= ~APIC_ID_MASK; 304 value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT | 305 1 << la->la_cluster_id) << APIC_ID_SHIFT; 306 lapic->ldr = value; 307 308 /* Setup spurious vector and enable the local APIC. */ 309 lapic_enable(); 310 311 /* Program LINT[01] LVT entries. */ 312 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 313 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 314#ifdef HWPMC_HOOKS 315 /* Program the PMC LVT entry if present. */ 316 if (maxlvt >= LVT_PMC) 317 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 318#endif 319 320 /* Program timer LVT and setup handler. */ 321 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 322 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 323 intrcnt_add(buf, &la->la_timer_count); 324 if (PCPU_GET(cpuid) != 0) { 325 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 326 lapic_id())); 327 lapic_timer_set_divisor(lapic_timer_divisor); 328 lapic_timer_periodic(lapic_timer_period); 329 lapic_timer_enable_intr(); 330 } 331 332 /* XXX: Error and thermal LVTs */ 333 334 intr_restore(eflags); 335} 336 337/* 338 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 339 * that it can drive hardclock, statclock, and profclock. This function 340 * returns true if it is able to use the local APIC timer to drive the 341 * clocks and false if it is not able. 342 */ 343int 344lapic_setup_clock(void) 345{ 346 u_long value; 347 348 /* Can't drive the timer without a local APIC. */ 349 if (lapic == NULL) 350 return (0); 351 352 /* Start off with a divisor of 2 (power on reset default). */ 353 lapic_timer_divisor = 2; 354 355 /* Try to calibrate the local APIC timer. */ 356 do { 357 lapic_timer_set_divisor(lapic_timer_divisor); 358 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 359 DELAY(2000000); 360 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 361 if (value != APIC_TIMER_MAX_COUNT) 362 break; 363 lapic_timer_divisor <<= 1; 364 } while (lapic_timer_divisor <= 128); 365 if (lapic_timer_divisor > 128) 366 panic("lapic: Divisor too big"); 367 value /= 2; 368 if (bootverbose) 369 printf("lapic: Divisor %lu, Frequency %lu hz\n", 370 lapic_timer_divisor, value); 371 372 /* 373 * We will drive the timer at a small multiple of hz and drive 374 * both of the other timers with similarly small but relatively 375 * prime divisors. 376 */ 377 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 378 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 379 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 380 lapic_timer_period = value / lapic_timer_hz; 381 382 /* 383 * Start up the timer on the BSP. The APs will kick off their 384 * timer during lapic_setup(). 385 */ 386 lapic_timer_periodic(lapic_timer_period); 387 lapic_timer_enable_intr(); 388 return (1); 389} 390 391void 392lapic_disable(void) 393{ 394 uint32_t value; 395 396 /* Software disable the local APIC. */ 397 value = lapic->svr; 398 value &= ~APIC_SVR_SWEN; 399 lapic->svr = value; 400} 401 402static void 403lapic_enable(void) 404{ 405 u_int32_t value; 406 407 /* Program the spurious vector to enable the local APIC. */ 408 value = lapic->svr; 409 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 410 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 411 lapic->svr = value; 412} 413 414int 415lapic_id(void) 416{ 417 418 KASSERT(lapic != NULL, ("local APIC is not mapped")); 419 return (lapic->id >> APIC_ID_SHIFT); 420} 421 422int 423lapic_intr_pending(u_int vector) 424{ 425 volatile u_int32_t *irr; 426 427 /* 428 * The IRR registers are an array of 128-bit registers each of 429 * which only describes 32 interrupts in the low 32 bits.. Thus, 430 * we divide the vector by 32 to get the 128-bit index. We then 431 * multiply that index by 4 to get the equivalent index from 432 * treating the IRR as an array of 32-bit registers. Finally, we 433 * modulus the vector by 32 to determine the individual bit to 434 * test. 435 */ 436 irr = &lapic->irr0; 437 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 438} 439 440void 441lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 442{ 443 struct lapic *la; 444 445 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 446 __func__, apic_id)); 447 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 448 __func__, cluster)); 449 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 450 ("%s: intra cluster id %u too big", __func__, cluster_id)); 451 la = &lapics[apic_id]; 452 la->la_cluster = cluster; 453 la->la_cluster_id = cluster_id; 454} 455 456int 457lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 458{ 459 460 if (pin > LVT_MAX) 461 return (EINVAL); 462 if (apic_id == APIC_ID_ALL) { 463 lvts[pin].lvt_masked = masked; 464 if (bootverbose) 465 printf("lapic:"); 466 } else { 467 KASSERT(lapics[apic_id].la_present, 468 ("%s: missing APIC %u", __func__, apic_id)); 469 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 470 lapics[apic_id].la_lvts[pin].lvt_active = 1; 471 if (bootverbose) 472 printf("lapic%u:", apic_id); 473 } 474 if (bootverbose) 475 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 476 return (0); 477} 478 479int 480lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 481{ 482 struct lvt *lvt; 483 484 if (pin > LVT_MAX) 485 return (EINVAL); 486 if (apic_id == APIC_ID_ALL) { 487 lvt = &lvts[pin]; 488 if (bootverbose) 489 printf("lapic:"); 490 } else { 491 KASSERT(lapics[apic_id].la_present, 492 ("%s: missing APIC %u", __func__, apic_id)); 493 lvt = &lapics[apic_id].la_lvts[pin]; 494 lvt->lvt_active = 1; 495 if (bootverbose) 496 printf("lapic%u:", apic_id); 497 } 498 lvt->lvt_mode = mode; 499 switch (mode) { 500 case APIC_LVT_DM_NMI: 501 case APIC_LVT_DM_SMI: 502 case APIC_LVT_DM_INIT: 503 case APIC_LVT_DM_EXTINT: 504 lvt->lvt_edgetrigger = 1; 505 lvt->lvt_activehi = 1; 506 if (mode == APIC_LVT_DM_EXTINT) 507 lvt->lvt_masked = 1; 508 else 509 lvt->lvt_masked = 0; 510 break; 511 default: 512 panic("Unsupported delivery mode: 0x%x\n", mode); 513 } 514 if (bootverbose) { 515 printf(" Routing "); 516 switch (mode) { 517 case APIC_LVT_DM_NMI: 518 printf("NMI"); 519 break; 520 case APIC_LVT_DM_SMI: 521 printf("SMI"); 522 break; 523 case APIC_LVT_DM_INIT: 524 printf("INIT"); 525 break; 526 case APIC_LVT_DM_EXTINT: 527 printf("ExtINT"); 528 break; 529 } 530 printf(" -> LINT%u\n", pin); 531 } 532 return (0); 533} 534 535int 536lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 537{ 538 539 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 540 return (EINVAL); 541 if (apic_id == APIC_ID_ALL) { 542 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 543 if (bootverbose) 544 printf("lapic:"); 545 } else { 546 KASSERT(lapics[apic_id].la_present, 547 ("%s: missing APIC %u", __func__, apic_id)); 548 lapics[apic_id].la_lvts[pin].lvt_active = 1; 549 lapics[apic_id].la_lvts[pin].lvt_activehi = 550 (pol == INTR_POLARITY_HIGH); 551 if (bootverbose) 552 printf("lapic%u:", apic_id); 553 } 554 if (bootverbose) 555 printf(" LINT%u polarity: %s\n", pin, 556 pol == INTR_POLARITY_HIGH ? "high" : "low"); 557 return (0); 558} 559 560int 561lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 562{ 563 564 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 565 return (EINVAL); 566 if (apic_id == APIC_ID_ALL) { 567 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 568 if (bootverbose) 569 printf("lapic:"); 570 } else { 571 KASSERT(lapics[apic_id].la_present, 572 ("%s: missing APIC %u", __func__, apic_id)); 573 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 574 (trigger == INTR_TRIGGER_EDGE); 575 lapics[apic_id].la_lvts[pin].lvt_active = 1; 576 if (bootverbose) 577 printf("lapic%u:", apic_id); 578 } 579 if (bootverbose) 580 printf(" LINT%u trigger: %s\n", pin, 581 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 582 return (0); 583} 584 585/* 586 * Adjust the TPR of the current CPU so that it blocks all interrupts below 587 * the passed in vector. 588 */ 589void 590lapic_set_tpr(u_int vector) 591{ 592#ifdef CHEAP_TPR 593 lapic->tpr = vector; 594#else 595 u_int32_t tpr; 596 597 tpr = lapic->tpr & ~APIC_TPR_PRIO; 598 tpr |= vector; 599 lapic->tpr = tpr; 600#endif 601} 602 603void 604lapic_eoi(void) 605{ 606 607 lapic->eoi = 0; 608} 609 610void 611lapic_handle_intr(struct intrframe frame) 612{ 613 struct intsrc *isrc; 614 615 if (frame.if_vec == -1) 616 panic("Couldn't get vector from ISR!"); 617 isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec)); 618 intr_execute_handlers(isrc, &frame); 619} 620 621void 622lapic_handle_timer(struct clockframe frame) 623{ 624 struct lapic *la; 625 626 la = &lapics[PCPU_GET(apic_id)]; 627 (*la->la_timer_count)++; 628 critical_enter(); 629 630 /* Fire hardclock at hz. */ 631 la->la_hard_ticks += hz; 632 if (la->la_hard_ticks >= lapic_timer_hz) { 633 la->la_hard_ticks -= lapic_timer_hz; 634 if (PCPU_GET(cpuid) == 0) 635 hardclock(&frame); 636 else 637 hardclock_process(&frame); 638 } 639 640 /* Fire statclock at stathz. */ 641 la->la_stat_ticks += stathz; 642 if (la->la_stat_ticks >= lapic_timer_hz) { 643 la->la_stat_ticks -= lapic_timer_hz; 644 statclock(&frame); 645 } 646 647 /* Fire profclock at profhz, but only when needed. */ 648 la->la_prof_ticks += profhz; 649 if (la->la_prof_ticks >= lapic_timer_hz) { 650 la->la_prof_ticks -= lapic_timer_hz; 651 if (profprocs != 0) 652 profclock(&frame); 653 } 654 critical_exit(); 655} 656 657static void 658lapic_timer_set_divisor(u_int divisor) 659{ 660 661 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 662 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 663 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 664 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 665} 666 667static void 668lapic_timer_oneshot(u_int count) 669{ 670 u_int32_t value; 671 672 value = lapic->lvt_timer; 673 value &= ~APIC_LVTT_TM; 674 value |= APIC_LVTT_TM_ONE_SHOT; 675 lapic->lvt_timer = value; 676 lapic->icr_timer = count; 677} 678 679static void 680lapic_timer_periodic(u_int count) 681{ 682 u_int32_t value; 683 684 value = lapic->lvt_timer; 685 value &= ~APIC_LVTT_TM; 686 value |= APIC_LVTT_TM_PERIODIC; 687 lapic->lvt_timer = value; 688 lapic->icr_timer = count; 689} 690 691static void 692lapic_timer_enable_intr(void) 693{ 694 u_int32_t value; 695 696 value = lapic->lvt_timer; 697 value &= ~APIC_LVT_M; 698 lapic->lvt_timer = value; 699} 700 701/* Request a free IDT vector to be used by the specified IRQ. */ 702u_int 703apic_alloc_vector(u_int irq) 704{ 705 u_int vector; 706 707 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 708 709 /* 710 * Search for a free vector. Currently we just use a very simple 711 * algorithm to find the first free vector. 712 */ 713 mtx_lock_spin(&icu_lock); 714 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 715 if (ioint_irqs[vector] != 0) 716 continue; 717 ioint_irqs[vector] = irq; 718 mtx_unlock_spin(&icu_lock); 719 return (vector + APIC_IO_INTS); 720 } 721 mtx_unlock_spin(&icu_lock); 722 panic("Couldn't find an APIC vector for IRQ %u", irq); 723} 724 725void 726apic_enable_vector(u_int vector) 727{ 728 729 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 730 KASSERT(ioint_handlers[vector / 32] != NULL, 731 ("No ISR handler for vector %u", vector)); 732 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 733 GSEL(GCODE_SEL, SEL_KPL)); 734} 735 736/* Release an APIC vector when it's no longer in use. */ 737void 738apic_free_vector(u_int vector, u_int irq) 739{ 740 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 741 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 742 ("Vector %u does not map to an IRQ line", vector)); 743 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 744 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 745 mtx_lock_spin(&icu_lock); 746 ioint_irqs[vector - APIC_IO_INTS] = 0; 747 mtx_unlock_spin(&icu_lock); 748} 749 750/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 751u_int 752apic_idt_to_irq(u_int vector) 753{ 754 755 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 756 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 757 ("Vector %u does not map to an IRQ line", vector)); 758 return (ioint_irqs[vector - APIC_IO_INTS]); 759} 760 761#ifdef DDB 762/* 763 * Dump data about APIC IDT vector mappings. 764 */ 765DB_SHOW_COMMAND(apic, db_show_apic) 766{ 767 struct intsrc *isrc; 768 int quit, i, verbose; 769 u_int irq; 770 771 quit = 0; 772 if (strcmp(modif, "vv") == 0) 773 verbose = 2; 774 else if (strcmp(modif, "v") == 0) 775 verbose = 1; 776 else 777 verbose = 0; 778 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 779 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) { 780 irq = ioint_irqs[i]; 781 if (irq != 0 && irq != IRQ_SYSCALL) { 782 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 783 if (irq == IRQ_TIMER) 784 db_printf("lapic timer\n"); 785 else if (irq < NUM_IO_INTS) { 786 isrc = intr_lookup_source(irq); 787 if (isrc == NULL || verbose == 0) 788 db_printf("IRQ %u\n", irq); 789 else 790 db_dump_intr_event(isrc->is_event, 791 verbose == 2); 792 } else 793 db_printf("IRQ %u ???\n", irq); 794 } 795 } 796} 797#endif 798 799/* 800 * APIC probing support code. This includes code to manage enumerators. 801 */ 802 803static SLIST_HEAD(, apic_enumerator) enumerators = 804 SLIST_HEAD_INITIALIZER(enumerators); 805static struct apic_enumerator *best_enum; 806 807void 808apic_register_enumerator(struct apic_enumerator *enumerator) 809{ 810#ifdef INVARIANTS 811 struct apic_enumerator *apic_enum; 812 813 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 814 if (apic_enum == enumerator) 815 panic("%s: Duplicate register of %s", __func__, 816 enumerator->apic_name); 817 } 818#endif 819 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 820} 821 822/* 823 * Probe the APIC enumerators, enumerate CPUs, and initialize the 824 * local APIC. 825 */ 826static void 827apic_init(void *dummy __unused) 828{ 829 struct apic_enumerator *enumerator; 830 uint64_t apic_base; 831 int retval, best; 832 833 /* We only support built in local APICs. */ 834 if (!(cpu_feature & CPUID_APIC)) 835 return; 836 837 /* Don't probe if APIC mode is disabled. */ 838 if (resource_disabled("apic", 0)) 839 return; 840 841 /* First, probe all the enumerators to find the best match. */ 842 best_enum = NULL; 843 best = 0; 844 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 845 retval = enumerator->apic_probe(); 846 if (retval > 0) 847 continue; 848 if (best_enum == NULL || best < retval) { 849 best_enum = enumerator; 850 best = retval; 851 } 852 } 853 if (best_enum == NULL) { 854 if (bootverbose) 855 printf("APIC: Could not find any APICs.\n"); 856 return; 857 } 858 859 if (bootverbose) 860 printf("APIC: Using the %s enumerator.\n", 861 best_enum->apic_name); 862 863 /* 864 * To work around an errata, we disable the local APIC on some 865 * CPUs during early startup. We need to turn the local APIC back 866 * on on such CPUs now. 867 */ 868 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 869 (cpu_id & 0xff0) == 0x610) { 870 apic_base = rdmsr(MSR_APICBASE); 871 apic_base |= APICBASE_ENABLED; 872 wrmsr(MSR_APICBASE, apic_base); 873 } 874 875 /* Second, probe the CPU's in the system. */ 876 retval = best_enum->apic_probe_cpus(); 877 if (retval != 0) 878 printf("%s: Failed to probe CPUs: returned %d\n", 879 best_enum->apic_name, retval); 880 881 /* Third, initialize the local APIC. */ 882 retval = best_enum->apic_setup_local(); 883 if (retval != 0) 884 printf("%s: Failed to setup the local APIC: returned %d\n", 885 best_enum->apic_name, retval); 886#ifdef SMP 887 /* Last, setup the cpu topology now that we have probed CPUs */ 888 mp_topology(); 889#endif 890} 891SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL) 892 893/* 894 * Setup the I/O APICs. 895 */ 896static void 897apic_setup_io(void *dummy __unused) 898{ 899 int retval; 900 901 if (best_enum == NULL) 902 return; 903 retval = best_enum->apic_setup_io(); 904 if (retval != 0) 905 printf("%s: Failed to setup I/O APICs: returned %d\n", 906 best_enum->apic_name, retval); 907 908 /* 909 * Finish setting up the local APIC on the BSP once we know how to 910 * properly program the LINT pins. 911 */ 912 lapic_setup(); 913 if (bootverbose) 914 lapic_dump("BSP"); 915} 916SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 917 918#ifdef SMP 919/* 920 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 921 * private to the sys/i386 code. The public interface for the rest of the 922 * kernel is defined in mp_machdep.c. 923 */ 924int 925lapic_ipi_wait(int delay) 926{ 927 int x, incr; 928 929 /* 930 * Wait delay loops for IPI to be sent. This is highly bogus 931 * since this is sensitive to CPU clock speed. If delay is 932 * -1, we wait forever. 933 */ 934 if (delay == -1) { 935 incr = 0; 936 delay = 1; 937 } else 938 incr = 1; 939 for (x = 0; x < delay; x += incr) { 940 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 941 return (1); 942 ia32_pause(); 943 } 944 return (0); 945} 946 947void 948lapic_ipi_raw(register_t icrlo, u_int dest) 949{ 950 register_t value, eflags; 951 952 /* XXX: Need more sanity checking of icrlo? */ 953 KASSERT(lapic != NULL, ("%s called too early", __func__)); 954 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 955 ("%s: invalid dest field", __func__)); 956 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 957 ("%s: reserved bits set in ICR LO register", __func__)); 958 959 /* Set destination in ICR HI register if it is being used. */ 960 eflags = intr_disable(); 961 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 962 value = lapic->icr_hi; 963 value &= ~APIC_ID_MASK; 964 value |= dest << APIC_ID_SHIFT; 965 lapic->icr_hi = value; 966 } 967 968 /* Program the contents of the IPI and dispatch it. */ 969 value = lapic->icr_lo; 970 value &= APIC_ICRLO_RESV_MASK; 971 value |= icrlo; 972 lapic->icr_lo = value; 973 intr_restore(eflags); 974} 975 976#define BEFORE_SPIN 1000000 977#ifdef DETECT_DEADLOCK 978#define AFTER_SPIN 1000 979#endif 980 981void 982lapic_ipi_vectored(u_int vector, int dest) 983{ 984 register_t icrlo, destfield; 985 986 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 987 ("%s: invalid vector %d", __func__, vector)); 988 989 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 990 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 991 destfield = 0; 992 switch (dest) { 993 case APIC_IPI_DEST_SELF: 994 icrlo |= APIC_DEST_SELF; 995 break; 996 case APIC_IPI_DEST_ALL: 997 icrlo |= APIC_DEST_ALLISELF; 998 break; 999 case APIC_IPI_DEST_OTHERS: 1000 icrlo |= APIC_DEST_ALLESELF; 1001 break; 1002 default: 1003 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1004 ("%s: invalid destination 0x%x", __func__, dest)); 1005 destfield = dest; 1006 } 1007 1008 /* Wait for an earlier IPI to finish. */ 1009 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1010 if (panicstr != NULL) 1011 return; 1012 else 1013 panic("APIC: Previous IPI is stuck"); 1014 } 1015 1016 lapic_ipi_raw(icrlo, destfield); 1017 1018#ifdef DETECT_DEADLOCK 1019 /* Wait for IPI to be delivered. */ 1020 if (!lapic_ipi_wait(AFTER_SPIN)) { 1021#ifdef needsattention 1022 /* 1023 * XXX FIXME: 1024 * 1025 * The above function waits for the message to actually be 1026 * delivered. It breaks out after an arbitrary timeout 1027 * since the message should eventually be delivered (at 1028 * least in theory) and that if it wasn't we would catch 1029 * the failure with the check above when the next IPI is 1030 * sent. 1031 * 1032 * We could skip this wait entirely, EXCEPT it probably 1033 * protects us from other routines that assume that the 1034 * message was delivered and acted upon when this function 1035 * returns. 1036 */ 1037 printf("APIC: IPI might be stuck\n"); 1038#else /* !needsattention */ 1039 /* Wait until mesage is sent without a timeout. */ 1040 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1041 ia32_pause(); 1042#endif /* needsattention */ 1043 } 1044#endif /* DETECT_DEADLOCK */ 1045} 1046#endif /* SMP */ 1047