pcivar.h revision 88184
126159Sse/* 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2650477Speter * $FreeBSD: head/sys/dev/pci/pcivar.h 88184 2001-12-19 08:49:11Z mdodd $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 3139231Sgibbs#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#include <sys/queue.h> 3439231Sgibbs 3526159Sse/* some PCI bus constants */ 366767Sse 3726159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 3826159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 3926159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 4026159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 416100Sse 4226159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4326159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4426159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 456100Sse 4626159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 476100Sse 4826159Sse#ifdef PCI_A64 4926159Ssetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5026159Sse#else 5126159Ssetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5226159Sse#endif 536100Sse 5426159Sse/* config header information common to all header types */ 556100Sse 5626159Ssetypedef struct pcicfg { 5745720Speter struct device *dev; /* device which owns this */ 586100Sse 5926159Sse u_int16_t subvendor; /* card vendor ID */ 6026159Sse u_int16_t subdevice; /* card device ID, assigned by card vendor */ 6126159Sse u_int16_t vendor; /* chip vendor ID */ 6226159Sse u_int16_t device; /* chip device ID, assigned by chip vendor */ 636100Sse 6426159Sse u_int16_t cmdreg; /* disable/enable chip and PCI options */ 6526159Sse u_int16_t statreg; /* supported PCI features and error state */ 667233Sse 6738304Sgibbs u_int8_t baseclass; /* chip PCI class */ 6826159Sse u_int8_t subclass; /* chip PCI subclass */ 6926159Sse u_int8_t progif; /* chip PCI programming interface */ 7026159Sse u_int8_t revid; /* chip revision ID */ 716100Sse 7226159Sse u_int8_t hdrtype; /* chip config header type */ 7326159Sse u_int8_t cachelnsz; /* cache line size in 4byte units */ 7426159Sse u_int8_t intpin; /* PCI interrupt pin */ 7526159Sse u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 766100Sse 7726159Sse u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 7826159Sse u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 7926159Sse u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 806100Sse 8126159Sse u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 8226159Sse u_int8_t nummaps; /* actual number of PCI maps used */ 837233Sse 8426159Sse u_int8_t bus; /* config space bus address */ 8526159Sse u_int8_t slot; /* config space slot address */ 8626159Sse u_int8_t func; /* config space function number */ 877233Sse 8869953Smsmith u_int16_t pp_cap; /* PCI power management capabilities */ 8969953Smsmith u_int8_t pp_status; /* config space address of PCI power status reg */ 9069953Smsmith u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 9169953Smsmith u_int8_t pp_data; /* config space address of PCI power data reg */ 9269953Smsmith 9326159Sse} pcicfgregs; 946100Sse 9526159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 966100Sse 9726159Sse#ifdef PCI_A64 9826159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 9926159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 10026159Sse#else 10126159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 10226159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 10326159Sse#endif /* PCI_A64 */ 1046100Sse 10526159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 10626159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1077233Sse 10826159Ssetypedef struct { 10926159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 11026159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 11126159Sse u_int32_t membase; /* base address of memory window */ 11226159Sse u_int32_t memlimit; /* topmost address of memory window */ 11326159Sse u_int32_t iobase; /* base address of port window */ 11426159Sse u_int32_t iolimit; /* topmost address of port window */ 11526159Sse u_int16_t secstat; /* secondary bus status register */ 11626159Sse u_int16_t bridgectl; /* bridge control register */ 11726159Sse u_int8_t seclat; /* CardBus latency timer */ 11826159Sse} pcih1cfgregs; 1196100Sse 12026159Sse/* additional type 2 device config header information (CardBus bridge) */ 12126159Sse 12226159Ssetypedef struct { 12326159Sse u_int32_t membase0; /* base address of memory window */ 12426159Sse u_int32_t memlimit0; /* topmost address of memory window */ 12526159Sse u_int32_t membase1; /* base address of memory window */ 12626159Sse u_int32_t memlimit1; /* topmost address of memory window */ 12726159Sse u_int32_t iobase0; /* base address of port window */ 12826159Sse u_int32_t iolimit0; /* topmost address of port window */ 12926159Sse u_int32_t iobase1; /* base address of port window */ 13026159Sse u_int32_t iolimit1; /* topmost address of port window */ 13126159Sse u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 13226159Sse u_int16_t secstat; /* secondary bus status register */ 13326159Sse u_int16_t bridgectl; /* bridge control register */ 13426159Sse u_int8_t seclat; /* CardBus latency timer */ 13526159Sse} pcih2cfgregs; 13626159Sse 13739231Sgibbsextern u_int32_t pci_numdevs; 13839231Sgibbs 13961047Speter/* Only if the prerequisites are present */ 14061047Speter#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 14161047Speterstruct pci_devinfo { 14261047Speter STAILQ_ENTRY(pci_devinfo) pci_links; 14361047Speter struct resource_list resources; 14461047Speter pcicfgregs cfg; 14561047Speter struct pci_conf conf; 14661047Speter}; 14761047Speter#endif 14839231Sgibbs 14940004Sdfr#ifdef __alpha__ 15040004Sdfrvm_offset_t pci_cvt_to_dense (vm_offset_t); 15140004Sdfrvm_offset_t pci_cvt_to_bwx (vm_offset_t); 15240004Sdfr#endif /* __alpha__ */ 15345720Speter 15445720Speter#ifdef _SYS_BUS_H_ 15545720Speter 15645720Speter#include "pci_if.h" 15745720Speter 15852243Sdfr/* 15952243Sdfr * Define pci-specific resource flags for accessing memory via dense 16052243Sdfr * or bwx memory spaces. These flags are ignored on i386. 16152243Sdfr */ 16252243Sdfr#define PCI_RF_DENSE 0x10000 16352243Sdfr#define PCI_RF_BWX 0x20000 16452243Sdfr 16545720Speterenum pci_device_ivars { 16669953Smsmith PCI_IVAR_SUBVENDOR, 16769953Smsmith PCI_IVAR_SUBDEVICE, 16869953Smsmith PCI_IVAR_VENDOR, 16969953Smsmith PCI_IVAR_DEVICE, 17069953Smsmith PCI_IVAR_DEVID, 17169953Smsmith PCI_IVAR_CLASS, 17269953Smsmith PCI_IVAR_SUBCLASS, 17369953Smsmith PCI_IVAR_PROGIF, 17469953Smsmith PCI_IVAR_REVID, 17569953Smsmith PCI_IVAR_INTPIN, 17669953Smsmith PCI_IVAR_IRQ, 17769953Smsmith PCI_IVAR_BUS, 17869953Smsmith PCI_IVAR_SLOT, 17969953Smsmith PCI_IVAR_FUNCTION, 18045720Speter}; 18145720Speter 18245720Speter/* 18345720Speter * Simplified accessors for pci devices 18445720Speter */ 18545720Speter#define PCI_ACCESSOR(A, B, T) \ 18645720Speter \ 18745720Speterstatic __inline T pci_get_ ## A(device_t dev) \ 18845720Speter{ \ 18969953Smsmith uintptr_t v; \ 19069953Smsmith BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 19169953Smsmith return (T) v; \ 19245720Speter} \ 19345720Speter \ 19445720Speterstatic __inline void pci_set_ ## A(device_t dev, T t) \ 19545720Speter{ \ 19669953Smsmith uintptr_t v = (uintptr_t) t; \ 19769953Smsmith BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 19845720Speter} 19945720Speter 20045720SpeterPCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 20145720SpeterPCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 20245720SpeterPCI_ACCESSOR(vendor, VENDOR, u_int16_t) 20345720SpeterPCI_ACCESSOR(device, DEVICE, u_int16_t) 20445720SpeterPCI_ACCESSOR(devid, DEVID, u_int32_t) 20545720SpeterPCI_ACCESSOR(class, CLASS, u_int8_t) 20645720SpeterPCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 20745720SpeterPCI_ACCESSOR(progif, PROGIF, u_int8_t) 20845720SpeterPCI_ACCESSOR(revid, REVID, u_int8_t) 20945720SpeterPCI_ACCESSOR(intpin, INTPIN, u_int8_t) 21045720SpeterPCI_ACCESSOR(irq, IRQ, u_int8_t) 21145720SpeterPCI_ACCESSOR(bus, BUS, u_int8_t) 21245720SpeterPCI_ACCESSOR(slot, SLOT, u_int8_t) 21345720SpeterPCI_ACCESSOR(function, FUNCTION, u_int8_t) 21445720Speter 21566416Speter#undef PCI_ACCESSOR 21666416Speter 21769953Smsmith/* 21869953Smsmith * Operations on configuration space. 21969953Smsmith */ 22045720Speterstatic __inline u_int32_t 22145720Speterpci_read_config(device_t dev, int reg, int width) 22245720Speter{ 22345720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 22445720Speter} 22545720Speter 22645720Speterstatic __inline void 22745720Speterpci_write_config(device_t dev, int reg, u_int32_t val, int width) 22845720Speter{ 22945720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 23045720Speter} 23145720Speter 23247339Sgallatin/* 23347339Sgallatin * Ivars for pci bridges. 23447339Sgallatin */ 23547339Sgallatin 23647339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 23747339Sgallatinenum pcib_device_ivars { 23865176Sdfr PCIB_IVAR_BUS 23947339Sgallatin}; 24047339Sgallatin 24147339Sgallatin#define PCIB_ACCESSOR(A, B, T) \ 24247339Sgallatin \ 24347339Sgallatinstatic __inline T pcib_get_ ## A(device_t dev) \ 24447339Sgallatin{ \ 24569953Smsmith uintptr_t v; \ 24669953Smsmith BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 24769953Smsmith return (T) v; \ 24847339Sgallatin} \ 24947339Sgallatin \ 25047339Sgallatinstatic __inline void pcib_set_ ## A(device_t dev, T t) \ 25147339Sgallatin{ \ 25269953Smsmith uintptr_t v = (uintptr_t) t; \ 25369953Smsmith BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 25447339Sgallatin} 25547339Sgallatin 25665176SdfrPCIB_ACCESSOR(bus, BUS, u_int32_t) 25747339Sgallatin 25866416Speter#undef PCIB_ACCESSOR 25966416Speter 26069953Smsmith/* 26169953Smsmith * Convenience functions. 26269953Smsmith * 26369953Smsmith * These should be used in preference to manually manipulating 26469953Smsmith * configuration space. 26569953Smsmith */ 26673185Speterstatic __inline void 26773185Speterpci_enable_busmaster(device_t dev) 26873185Speter{ 26973185Speter PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 27073185Speter} 27145720Speter 27273185Speterstatic __inline void 27373185Speterpci_disable_busmaster(device_t dev) 27473185Speter{ 27573185Speter PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 27673185Speter} 27773185Speter 27873185Speterstatic __inline void 27973185Speterpci_enable_io(device_t dev, int space) 28073185Speter{ 28173185Speter PCI_ENABLE_IO(device_get_parent(dev), dev, space); 28273185Speter} 28373185Speter 28473185Speterstatic __inline void 28573185Speterpci_disable_io(device_t dev, int space) 28673185Speter{ 28773185Speter PCI_DISABLE_IO(device_get_parent(dev), dev, space); 28873185Speter} 28973185Speter 29069953Smsmith/* 29169953Smsmith * PCI power states are as defined by ACPI: 29269953Smsmith * 29369953Smsmith * D0 State in which device is on and running. It is receiving full 29469953Smsmith * power from the system and delivering full functionality to the user. 29569953Smsmith * D1 Class-specific low-power state in which device context may or may not 29669953Smsmith * be lost. Buses in D1 cannot do anything to the bus that would force 29769953Smsmith * devices on that bus to loose context. 29869953Smsmith * D2 Class-specific low-power state in which device context may or may 29969953Smsmith * not be lost. Attains greater power savings than D1. Buses in D2 30069953Smsmith * can cause devices on that bus to loose some context. Devices in D2 30169953Smsmith * must be prepared for the bus to be in D2 or higher. 30269953Smsmith * D3 State in which the device is off and not running. Device context is 30369953Smsmith * lost. Power can be removed from the device. 30469953Smsmith */ 30569953Smsmith#define PCI_POWERSTATE_D0 0 30669953Smsmith#define PCI_POWERSTATE_D1 1 30769953Smsmith#define PCI_POWERSTATE_D2 2 30869953Smsmith#define PCI_POWERSTATE_D3 3 30969953Smsmith#define PCI_POWERSTATE_UNKNOWN -1 31026159Sse 31173185Speterstatic __inline int 31273185Speterpci_set_powerstate(device_t dev, int state) 31373185Speter{ 31473185Speter return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 31573185Speter} 31658287Speter 31773185Speterstatic __inline int 31873185Speterpci_get_powerstate(device_t dev) 31973185Speter{ 32073185Speter return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 32173185Speter} 32273185Speter 32369953Smsmith#endif /* _SYS_BUS_H_ */ 32461047Speter 32569953Smsmith/* 32669953Smsmith * cdev switch for control device, initialised in generic PCI code 32769953Smsmith */ 32869953Smsmithextern struct cdevsw pcicdev; 32958287Speter 33069953Smsmith/* 33169953Smsmith * List of all PCI devices, generation count for the list. 33269953Smsmith */ 33388184SmdoddSTAILQ_HEAD(devlist, pci_devinfo); 33412453Sbde 33588184Smdoddextern struct devlist pci_devq; 33688184Smdoddextern u_int32_t pci_generation; 33788184Smdodd 33839231Sgibbs#endif /* _PCIVAR_H_ */ 339