1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40typedef uint64_t pci_addr_t; 41 42/* Interesting values for PCI power management */ 43struct pcicfg_pp { 44 uint16_t pp_cap; /* PCI power management capabilities */ 45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47 uint8_t pp_data; /* conf. space addr. of PM data reg */ 48}; 49 50struct pci_map { 51 pci_addr_t pm_value; /* Raw BAR value */ 52 pci_addr_t pm_size; 53 uint8_t pm_reg; 54 STAILQ_ENTRY(pci_map) pm_link; 55}; 56 57struct vpd_readonly { 58 char keyword[2]; 59 char *value; 60 int len; 61}; 62 63struct vpd_write { 64 char keyword[2]; 65 char *value; 66 int start; 67 int len; 68}; 69 70struct pcicfg_vpd { 71 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 72 char vpd_cached; 73 char *vpd_ident; /* string identifier */ 74 int vpd_rocnt; 75 struct vpd_readonly *vpd_ros; 76 int vpd_wcnt; 77 struct vpd_write *vpd_w; 78}; 79 80/* Interesting values for PCI MSI */ 81struct pcicfg_msi { 82 uint16_t msi_ctrl; /* Message Control */ 83 uint8_t msi_location; /* Offset of MSI capability registers. */ 84 uint8_t msi_msgnum; /* Number of messages */ 85 int msi_alloc; /* Number of allocated messages. */ 86 uint64_t msi_addr; /* Contents of address register. */ 87 uint16_t msi_data; /* Contents of data register. */ 88 u_int msi_handlers; 89}; 90 91/* Interesting values for PCI MSI-X */ 92struct msix_vector { 93 uint64_t mv_address; /* Contents of address register. */ 94 uint32_t mv_data; /* Contents of data register. */ 95 int mv_irq; 96}; 97 98struct msix_table_entry { 99 u_int mte_vector; /* 1-based index into msix_vectors array. */ 100 u_int mte_handlers; 101}; 102 103struct pcicfg_msix { 104 uint16_t msix_ctrl; /* Message Control */ 105 uint16_t msix_msgnum; /* Number of messages */ 106 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 107 uint8_t msix_table_bar; /* BAR containing vector table. */ 108 uint8_t msix_pba_bar; /* BAR containing PBA. */ 109 uint32_t msix_table_offset; 110 uint32_t msix_pba_offset; 111 int msix_alloc; /* Number of allocated vectors. */ 112 int msix_table_len; /* Length of virtual table. */ 113 struct msix_table_entry *msix_table; /* Virtual table. */ 114 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 115 struct resource *msix_table_res; /* Resource containing vector table. */ 116 struct resource *msix_pba_res; /* Resource containing PBA. */ 117}; 118 119/* Interesting values for HyperTransport */ 120struct pcicfg_ht { 121 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 122 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 123 uint16_t ht_msictrl; /* MSI mapping control */ 124 uint64_t ht_msiaddr; /* MSI mapping base address */ 125}; 126 127/* config header information common to all header types */ 128typedef struct pcicfg { 129 struct device *dev; /* device which owns this */ 130 131 STAILQ_HEAD(, pci_map) maps; /* BARs */ 132 133 uint16_t subvendor; /* card vendor ID */ 134 uint16_t subdevice; /* card device ID, assigned by card vendor */ 135 uint16_t vendor; /* chip vendor ID */ 136 uint16_t device; /* chip device ID, assigned by chip vendor */ 137 138 uint16_t cmdreg; /* disable/enable chip and PCI options */ 139 uint16_t statreg; /* supported PCI features and error state */ 140 141 uint8_t baseclass; /* chip PCI class */ 142 uint8_t subclass; /* chip PCI subclass */ 143 uint8_t progif; /* chip PCI programming interface */ 144 uint8_t revid; /* chip revision ID */ 145 146 uint8_t hdrtype; /* chip config header type */ 147 uint8_t cachelnsz; /* cache line size in 4byte units */ 148 uint8_t intpin; /* PCI interrupt pin */ 149 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 150 151 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 152 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 153 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 154 155 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 156 uint8_t nummaps; /* actual number of PCI maps used */ 157 158 uint32_t domain; /* PCI domain */ 159 uint8_t bus; /* config space bus address */ 160 uint8_t slot; /* config space slot address */ 161 uint8_t func; /* config space function number */ 162 163 struct pcicfg_pp pp; /* Power management */ 164 struct pcicfg_vpd vpd; /* Vital product data */ 165 struct pcicfg_msi msi; /* PCI MSI */ 166 struct pcicfg_msix msix; /* PCI MSI-X */ 167 struct pcicfg_ht ht; /* HyperTransport */ 168} pcicfgregs; 169 170/* additional type 1 device config header information (PCI to PCI bridge) */ 171 172#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 173#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 174#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 175#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 176 177typedef struct { 178 pci_addr_t pmembase; /* base address of prefetchable memory */ 179 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 180 uint32_t membase; /* base address of memory window */ 181 uint32_t memlimit; /* topmost address of memory window */ 182 uint32_t iobase; /* base address of port window */ 183 uint32_t iolimit; /* topmost address of port window */ 184 uint16_t secstat; /* secondary bus status register */ 185 uint16_t bridgectl; /* bridge control register */ 186 uint8_t seclat; /* CardBus latency timer */ 187} pcih1cfgregs; 188 189/* additional type 2 device config header information (CardBus bridge) */ 190 191typedef struct { 192 uint32_t membase0; /* base address of memory window */ 193 uint32_t memlimit0; /* topmost address of memory window */ 194 uint32_t membase1; /* base address of memory window */ 195 uint32_t memlimit1; /* topmost address of memory window */ 196 uint32_t iobase0; /* base address of port window */ 197 uint32_t iolimit0; /* topmost address of port window */ 198 uint32_t iobase1; /* base address of port window */ 199 uint32_t iolimit1; /* topmost address of port window */ 200 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 201 uint16_t secstat; /* secondary bus status register */ 202 uint16_t bridgectl; /* bridge control register */ 203 uint8_t seclat; /* CardBus latency timer */ 204} pcih2cfgregs; 205 206extern uint32_t pci_numdevs; 207 208/* Only if the prerequisites are present */ 209#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 210struct pci_devinfo { 211 STAILQ_ENTRY(pci_devinfo) pci_links; 212 struct resource_list resources; 213 pcicfgregs cfg; 214 struct pci_conf conf; 215}; 216#endif 217 218#ifdef _SYS_BUS_H_ 219 220#include "pci_if.h" 221 222enum pci_device_ivars { 223 PCI_IVAR_SUBVENDOR, 224 PCI_IVAR_SUBDEVICE, 225 PCI_IVAR_VENDOR, 226 PCI_IVAR_DEVICE, 227 PCI_IVAR_DEVID, 228 PCI_IVAR_CLASS, 229 PCI_IVAR_SUBCLASS, 230 PCI_IVAR_PROGIF, 231 PCI_IVAR_REVID, 232 PCI_IVAR_INTPIN, 233 PCI_IVAR_IRQ, 234 PCI_IVAR_DOMAIN, 235 PCI_IVAR_BUS, 236 PCI_IVAR_SLOT, 237 PCI_IVAR_FUNCTION, 238 PCI_IVAR_ETHADDR, 239 PCI_IVAR_CMDREG, 240 PCI_IVAR_CACHELNSZ, 241 PCI_IVAR_MINGNT, 242 PCI_IVAR_MAXLAT, 243 PCI_IVAR_LATTIMER 244}; 245 246/* 247 * Simplified accessors for pci devices 248 */ 249#define PCI_ACCESSOR(var, ivar, type) \ 250 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 251 252PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 253PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 254PCI_ACCESSOR(vendor, VENDOR, uint16_t) 255PCI_ACCESSOR(device, DEVICE, uint16_t) 256PCI_ACCESSOR(devid, DEVID, uint32_t) 257PCI_ACCESSOR(class, CLASS, uint8_t) 258PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 259PCI_ACCESSOR(progif, PROGIF, uint8_t) 260PCI_ACCESSOR(revid, REVID, uint8_t) 261PCI_ACCESSOR(intpin, INTPIN, uint8_t) 262PCI_ACCESSOR(irq, IRQ, uint8_t) 263PCI_ACCESSOR(domain, DOMAIN, uint32_t) 264PCI_ACCESSOR(bus, BUS, uint8_t) 265PCI_ACCESSOR(slot, SLOT, uint8_t) 266PCI_ACCESSOR(function, FUNCTION, uint8_t) 267PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 268PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 269PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 270PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 271PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 272PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 273 274#undef PCI_ACCESSOR 275 276/* 277 * Operations on configuration space. 278 */ 279static __inline uint32_t 280pci_read_config(device_t dev, int reg, int width) 281{ 282 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 283} 284 285static __inline void 286pci_write_config(device_t dev, int reg, uint32_t val, int width) 287{ 288 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 289} 290 291/* 292 * Ivars for pci bridges. 293 */ 294 295/*typedef enum pci_device_ivars pcib_device_ivars;*/ 296enum pcib_device_ivars { 297 PCIB_IVAR_DOMAIN, 298 PCIB_IVAR_BUS 299}; 300 301#define PCIB_ACCESSOR(var, ivar, type) \ 302 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 303 304PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 305PCIB_ACCESSOR(bus, BUS, uint32_t) 306 307#undef PCIB_ACCESSOR 308 309/* 310 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 311 * on i386 or other platforms should be mapped out in the MD pcireadconf 312 * code and not here, since the only MI invalid IRQ is 255. 313 */ 314#define PCI_INVALID_IRQ 255 315#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 316 317/* 318 * Convenience functions. 319 * 320 * These should be used in preference to manually manipulating 321 * configuration space. 322 */ 323static __inline int 324pci_enable_busmaster(device_t dev) 325{ 326 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 327} 328 329static __inline int 330pci_disable_busmaster(device_t dev) 331{ 332 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 333} 334 335static __inline int 336pci_enable_io(device_t dev, int space) 337{ 338 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 339} 340 341static __inline int 342pci_disable_io(device_t dev, int space) 343{ 344 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 345} 346 347static __inline int 348pci_get_vpd_ident(device_t dev, const char **identptr) 349{ 350 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 351} 352 353static __inline int 354pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 355{ 356 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 357} 358 359/* 360 * Check if the address range falls within the VGA defined address range(s) 361 */ 362static __inline int 363pci_is_vga_ioport_range(u_long start, u_long end) 364{ 365 366 return (((start >= 0x3b0 && end <= 0x3bb) || 367 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 368} 369 370static __inline int 371pci_is_vga_memory_range(u_long start, u_long end) 372{ 373 374 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 375} 376 377/* 378 * PCI power states are as defined by ACPI: 379 * 380 * D0 State in which device is on and running. It is receiving full 381 * power from the system and delivering full functionality to the user. 382 * D1 Class-specific low-power state in which device context may or may not 383 * be lost. Buses in D1 cannot do anything to the bus that would force 384 * devices on that bus to lose context. 385 * D2 Class-specific low-power state in which device context may or may 386 * not be lost. Attains greater power savings than D1. Buses in D2 387 * can cause devices on that bus to lose some context. Devices in D2 388 * must be prepared for the bus to be in D2 or higher. 389 * D3 State in which the device is off and not running. Device context is 390 * lost. Power can be removed from the device. 391 */ 392#define PCI_POWERSTATE_D0 0 393#define PCI_POWERSTATE_D1 1 394#define PCI_POWERSTATE_D2 2 395#define PCI_POWERSTATE_D3 3 396#define PCI_POWERSTATE_UNKNOWN -1 397 398static __inline int 399pci_set_powerstate(device_t dev, int state) 400{ 401 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 402} 403 404static __inline int 405pci_get_powerstate(device_t dev) 406{ 407 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 408} 409 410static __inline int 411pci_find_cap(device_t dev, int capability, int *capreg) 412{ 413 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 414} 415 416static __inline int 417pci_find_extcap(device_t dev, int capability, int *capreg) 418{ 419 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 420} 421 422static __inline int 423pci_alloc_msi(device_t dev, int *count) 424{ 425 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 426} 427 428static __inline int 429pci_alloc_msix(device_t dev, int *count) 430{ 431 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 432} 433 434static __inline int 435pci_remap_msix(device_t dev, int count, const u_int *vectors) 436{ 437 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 438} 439 440static __inline int 441pci_release_msi(device_t dev) 442{ 443 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 444} 445 446static __inline int 447pci_msi_count(device_t dev) 448{ 449 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 450} 451 452static __inline int 453pci_msix_count(device_t dev) 454{ 455 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 456} 457 458device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 459device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 460device_t pci_find_device(uint16_t, uint16_t); 461device_t pci_find_class(uint8_t class, uint8_t subclass); 462 463/* Can be used by drivers to manage the MSI-X table. */ 464int pci_pending_msix(device_t dev, u_int index); 465 466int pci_msi_device_blacklisted(device_t dev); 467int pci_msix_device_blacklisted(device_t dev); 468 469void pci_ht_map_msi(device_t dev, uint64_t addr); 470 471int pci_get_max_read_req(device_t dev); 472void pci_restore_state(device_t dev); 473void pci_save_state(device_t dev); 474int pci_set_max_read_req(device_t dev, int size); 475 476#endif /* _SYS_BUS_H_ */ 477 478/* 479 * cdev switch for control device, initialised in generic PCI code 480 */ 481extern struct cdevsw pcicdev; 482 483/* 484 * List of all PCI devices, generation count for the list. 485 */ 486STAILQ_HEAD(devlist, pci_devinfo); 487 488extern struct devlist pci_devq; 489extern uint32_t pci_generation; 490 491struct pci_map *pci_find_bar(device_t dev, int reg); 492int pci_bar_enabled(device_t dev, struct pci_map *pm); 493struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 494 495#define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 496#define VGA_PCI_BIOS_SHADOW_SIZE 131072 497 498int vga_pci_is_boot_display(device_t dev); 499void * vga_pci_map_bios(device_t dev, size_t *size); 500void vga_pci_unmap_bios(device_t dev, void *bios); 501 502#endif /* _PCIVAR_H_ */ 503