pcivar.h revision 88184
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 88184 2001-12-19 08:49:11Z mdodd $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36 37#define PCI_BUSMAX 255 /* highest supported bus number */ 38#define PCI_SLOTMAX 31 /* highest supported slot number */ 39#define PCI_FUNCMAX 7 /* highest supported function number */ 40#define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48#ifdef PCI_A64 49typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50#else 51typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 52#endif 53 54/* config header information common to all header types */ 55 56typedef struct pcicfg { 57 struct device *dev; /* device which owns this */ 58 59 u_int16_t subvendor; /* card vendor ID */ 60 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 61 u_int16_t vendor; /* chip vendor ID */ 62 u_int16_t device; /* chip device ID, assigned by chip vendor */ 63 64 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 65 u_int16_t statreg; /* supported PCI features and error state */ 66 67 u_int8_t baseclass; /* chip PCI class */ 68 u_int8_t subclass; /* chip PCI subclass */ 69 u_int8_t progif; /* chip PCI programming interface */ 70 u_int8_t revid; /* chip revision ID */ 71 72 u_int8_t hdrtype; /* chip config header type */ 73 u_int8_t cachelnsz; /* cache line size in 4byte units */ 74 u_int8_t intpin; /* PCI interrupt pin */ 75 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 76 77 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 78 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 79 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 80 81 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 82 u_int8_t nummaps; /* actual number of PCI maps used */ 83 84 u_int8_t bus; /* config space bus address */ 85 u_int8_t slot; /* config space slot address */ 86 u_int8_t func; /* config space function number */ 87 88 u_int16_t pp_cap; /* PCI power management capabilities */ 89 u_int8_t pp_status; /* config space address of PCI power status reg */ 90 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 91 u_int8_t pp_data; /* config space address of PCI power data reg */ 92 93} pcicfgregs; 94 95/* additional type 1 device config header information (PCI to PCI bridge) */ 96 97#ifdef PCI_A64 98#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 99#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 100#else 101#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 102#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 103#endif /* PCI_A64 */ 104 105#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 106#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 107 108typedef struct { 109 pci_addr_t pmembase; /* base address of prefetchable memory */ 110 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 111 u_int32_t membase; /* base address of memory window */ 112 u_int32_t memlimit; /* topmost address of memory window */ 113 u_int32_t iobase; /* base address of port window */ 114 u_int32_t iolimit; /* topmost address of port window */ 115 u_int16_t secstat; /* secondary bus status register */ 116 u_int16_t bridgectl; /* bridge control register */ 117 u_int8_t seclat; /* CardBus latency timer */ 118} pcih1cfgregs; 119 120/* additional type 2 device config header information (CardBus bridge) */ 121 122typedef struct { 123 u_int32_t membase0; /* base address of memory window */ 124 u_int32_t memlimit0; /* topmost address of memory window */ 125 u_int32_t membase1; /* base address of memory window */ 126 u_int32_t memlimit1; /* topmost address of memory window */ 127 u_int32_t iobase0; /* base address of port window */ 128 u_int32_t iolimit0; /* topmost address of port window */ 129 u_int32_t iobase1; /* base address of port window */ 130 u_int32_t iolimit1; /* topmost address of port window */ 131 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 132 u_int16_t secstat; /* secondary bus status register */ 133 u_int16_t bridgectl; /* bridge control register */ 134 u_int8_t seclat; /* CardBus latency timer */ 135} pcih2cfgregs; 136 137extern u_int32_t pci_numdevs; 138 139/* Only if the prerequisites are present */ 140#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 141struct pci_devinfo { 142 STAILQ_ENTRY(pci_devinfo) pci_links; 143 struct resource_list resources; 144 pcicfgregs cfg; 145 struct pci_conf conf; 146}; 147#endif 148 149#ifdef __alpha__ 150vm_offset_t pci_cvt_to_dense (vm_offset_t); 151vm_offset_t pci_cvt_to_bwx (vm_offset_t); 152#endif /* __alpha__ */ 153 154#ifdef _SYS_BUS_H_ 155 156#include "pci_if.h" 157 158/* 159 * Define pci-specific resource flags for accessing memory via dense 160 * or bwx memory spaces. These flags are ignored on i386. 161 */ 162#define PCI_RF_DENSE 0x10000 163#define PCI_RF_BWX 0x20000 164 165enum pci_device_ivars { 166 PCI_IVAR_SUBVENDOR, 167 PCI_IVAR_SUBDEVICE, 168 PCI_IVAR_VENDOR, 169 PCI_IVAR_DEVICE, 170 PCI_IVAR_DEVID, 171 PCI_IVAR_CLASS, 172 PCI_IVAR_SUBCLASS, 173 PCI_IVAR_PROGIF, 174 PCI_IVAR_REVID, 175 PCI_IVAR_INTPIN, 176 PCI_IVAR_IRQ, 177 PCI_IVAR_BUS, 178 PCI_IVAR_SLOT, 179 PCI_IVAR_FUNCTION, 180}; 181 182/* 183 * Simplified accessors for pci devices 184 */ 185#define PCI_ACCESSOR(A, B, T) \ 186 \ 187static __inline T pci_get_ ## A(device_t dev) \ 188{ \ 189 uintptr_t v; \ 190 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 191 return (T) v; \ 192} \ 193 \ 194static __inline void pci_set_ ## A(device_t dev, T t) \ 195{ \ 196 uintptr_t v = (uintptr_t) t; \ 197 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 198} 199 200PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 201PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 202PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 203PCI_ACCESSOR(device, DEVICE, u_int16_t) 204PCI_ACCESSOR(devid, DEVID, u_int32_t) 205PCI_ACCESSOR(class, CLASS, u_int8_t) 206PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 207PCI_ACCESSOR(progif, PROGIF, u_int8_t) 208PCI_ACCESSOR(revid, REVID, u_int8_t) 209PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 210PCI_ACCESSOR(irq, IRQ, u_int8_t) 211PCI_ACCESSOR(bus, BUS, u_int8_t) 212PCI_ACCESSOR(slot, SLOT, u_int8_t) 213PCI_ACCESSOR(function, FUNCTION, u_int8_t) 214 215#undef PCI_ACCESSOR 216 217/* 218 * Operations on configuration space. 219 */ 220static __inline u_int32_t 221pci_read_config(device_t dev, int reg, int width) 222{ 223 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 224} 225 226static __inline void 227pci_write_config(device_t dev, int reg, u_int32_t val, int width) 228{ 229 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 230} 231 232/* 233 * Ivars for pci bridges. 234 */ 235 236/*typedef enum pci_device_ivars pcib_device_ivars;*/ 237enum pcib_device_ivars { 238 PCIB_IVAR_BUS 239}; 240 241#define PCIB_ACCESSOR(A, B, T) \ 242 \ 243static __inline T pcib_get_ ## A(device_t dev) \ 244{ \ 245 uintptr_t v; \ 246 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 247 return (T) v; \ 248} \ 249 \ 250static __inline void pcib_set_ ## A(device_t dev, T t) \ 251{ \ 252 uintptr_t v = (uintptr_t) t; \ 253 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 254} 255 256PCIB_ACCESSOR(bus, BUS, u_int32_t) 257 258#undef PCIB_ACCESSOR 259 260/* 261 * Convenience functions. 262 * 263 * These should be used in preference to manually manipulating 264 * configuration space. 265 */ 266static __inline void 267pci_enable_busmaster(device_t dev) 268{ 269 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 270} 271 272static __inline void 273pci_disable_busmaster(device_t dev) 274{ 275 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 276} 277 278static __inline void 279pci_enable_io(device_t dev, int space) 280{ 281 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 282} 283 284static __inline void 285pci_disable_io(device_t dev, int space) 286{ 287 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 288} 289 290/* 291 * PCI power states are as defined by ACPI: 292 * 293 * D0 State in which device is on and running. It is receiving full 294 * power from the system and delivering full functionality to the user. 295 * D1 Class-specific low-power state in which device context may or may not 296 * be lost. Buses in D1 cannot do anything to the bus that would force 297 * devices on that bus to loose context. 298 * D2 Class-specific low-power state in which device context may or may 299 * not be lost. Attains greater power savings than D1. Buses in D2 300 * can cause devices on that bus to loose some context. Devices in D2 301 * must be prepared for the bus to be in D2 or higher. 302 * D3 State in which the device is off and not running. Device context is 303 * lost. Power can be removed from the device. 304 */ 305#define PCI_POWERSTATE_D0 0 306#define PCI_POWERSTATE_D1 1 307#define PCI_POWERSTATE_D2 2 308#define PCI_POWERSTATE_D3 3 309#define PCI_POWERSTATE_UNKNOWN -1 310 311static __inline int 312pci_set_powerstate(device_t dev, int state) 313{ 314 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 315} 316 317static __inline int 318pci_get_powerstate(device_t dev) 319{ 320 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 321} 322 323#endif /* _SYS_BUS_H_ */ 324 325/* 326 * cdev switch for control device, initialised in generic PCI code 327 */ 328extern struct cdevsw pcicdev; 329 330/* 331 * List of all PCI devices, generation count for the list. 332 */ 333STAILQ_HEAD(devlist, pci_devinfo); 334 335extern struct devlist pci_devq; 336extern u_int32_t pci_generation; 337 338#endif /* _PCIVAR_H_ */ 339