pcivar.h revision 65176
126159Sse/* 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2650477Speter * $FreeBSD: head/sys/dev/pci/pcivar.h 65176 2000-08-28 21:48:13Z dfr $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 3139231Sgibbs#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#include <sys/queue.h> 3439231Sgibbs 3526159Sse/* some PCI bus constants */ 366767Sse 3726159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 3826159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 3926159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 4026159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 416100Sse 4226159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4326159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4426159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 456100Sse 4626159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 476100Sse 4826159Sse#ifdef PCI_A64 4926159Ssetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5026159Sse#else 5126159Ssetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5226159Sse#endif 536100Sse 5426159Sse/* config header information common to all header types */ 556100Sse 5626159Ssetypedef struct pcicfg { 5745720Speter struct device *dev; /* device which owns this */ 5826159Sse void *hdrspec; /* pointer to header type specific data */ 596100Sse 6026159Sse u_int16_t subvendor; /* card vendor ID */ 6126159Sse u_int16_t subdevice; /* card device ID, assigned by card vendor */ 6226159Sse u_int16_t vendor; /* chip vendor ID */ 6326159Sse u_int16_t device; /* chip device ID, assigned by chip vendor */ 646100Sse 6526159Sse u_int16_t cmdreg; /* disable/enable chip and PCI options */ 6626159Sse u_int16_t statreg; /* supported PCI features and error state */ 677233Sse 6838304Sgibbs u_int8_t baseclass; /* chip PCI class */ 6926159Sse u_int8_t subclass; /* chip PCI subclass */ 7026159Sse u_int8_t progif; /* chip PCI programming interface */ 7126159Sse u_int8_t revid; /* chip revision ID */ 726100Sse 7326159Sse u_int8_t hdrtype; /* chip config header type */ 7426159Sse u_int8_t cachelnsz; /* cache line size in 4byte units */ 7526159Sse u_int8_t intpin; /* PCI interrupt pin */ 7626159Sse u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 776100Sse 7826159Sse u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 7926159Sse u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 8026159Sse u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 816100Sse 8226159Sse u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 8326159Sse u_int8_t nummaps; /* actual number of PCI maps used */ 847233Sse 8526159Sse u_int8_t bus; /* config space bus address */ 8626159Sse u_int8_t slot; /* config space slot address */ 8726159Sse u_int8_t func; /* config space function number */ 887233Sse 8926159Sse u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 9026159Sse u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 9126159Sse} pcicfgregs; 926100Sse 9326159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 946100Sse 9526159Sse#ifdef PCI_A64 9626159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 9726159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 9826159Sse#else 9926159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 10026159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 10126159Sse#endif /* PCI_A64 */ 1026100Sse 10326159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 10426159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1057233Sse 10626159Ssetypedef struct { 10726159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 10826159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 10926159Sse u_int32_t membase; /* base address of memory window */ 11026159Sse u_int32_t memlimit; /* topmost address of memory window */ 11126159Sse u_int32_t iobase; /* base address of port window */ 11226159Sse u_int32_t iolimit; /* topmost address of port window */ 11326159Sse u_int16_t secstat; /* secondary bus status register */ 11426159Sse u_int16_t bridgectl; /* bridge control register */ 11526159Sse u_int8_t seclat; /* CardBus latency timer */ 11626159Sse} pcih1cfgregs; 1176100Sse 11826159Sse/* additional type 2 device config header information (CardBus bridge) */ 11926159Sse 12026159Ssetypedef struct { 12126159Sse u_int32_t membase0; /* base address of memory window */ 12226159Sse u_int32_t memlimit0; /* topmost address of memory window */ 12326159Sse u_int32_t membase1; /* base address of memory window */ 12426159Sse u_int32_t memlimit1; /* topmost address of memory window */ 12526159Sse u_int32_t iobase0; /* base address of port window */ 12626159Sse u_int32_t iolimit0; /* topmost address of port window */ 12726159Sse u_int32_t iobase1; /* base address of port window */ 12826159Sse u_int32_t iolimit1; /* topmost address of port window */ 12926159Sse u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 13026159Sse u_int16_t secstat; /* secondary bus status register */ 13126159Sse u_int16_t bridgectl; /* bridge control register */ 13226159Sse u_int8_t seclat; /* CardBus latency timer */ 13326159Sse} pcih2cfgregs; 13426159Sse 13539231Sgibbsextern u_int32_t pci_numdevs; 13639231Sgibbs 13761047Speter/* Only if the prerequisites are present */ 13861047Speter#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 13961047Speterstruct pci_devinfo { 14061047Speter STAILQ_ENTRY(pci_devinfo) pci_links; 14161047Speter struct resource_list resources; 14261047Speter pcicfgregs cfg; 14361047Speter struct pci_conf conf; 14461047Speter}; 14561047Speter#endif 14639231Sgibbs 14726159Sse/* externally visible functions */ 14826159Sse 14954412Speterconst char *pci_ata_match(struct device *dev); 15054412Speterconst char *pci_usb_match(struct device *dev); 15157332Sdfrconst char *pci_vga_match(struct device *dev); 15261451Sdfrconst char *pci_chip_match(struct device *dev); 15326159Sse 15426159Sse/* low level PCI config register functions provided by pcibus.c */ 15526159Sse 15626159Sseint pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 15726159Ssevoid pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 15865176Sdfr 15940004Sdfr#ifdef __alpha__ 16040004Sdfrvm_offset_t pci_cvt_to_dense (vm_offset_t); 16140004Sdfrvm_offset_t pci_cvt_to_bwx (vm_offset_t); 16240004Sdfr#endif /* __alpha__ */ 16345720Speter 16447646Sroger/* low level devlist operations for the 2.2 compatibility code in pci.c */ 16547646Srogerpcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 16647646Sroger 16745720Speter#ifdef _SYS_BUS_H_ 16845720Speter 16945720Speter#include "pci_if.h" 17045720Speter 17152243Sdfr/* 17252243Sdfr * Define pci-specific resource flags for accessing memory via dense 17352243Sdfr * or bwx memory spaces. These flags are ignored on i386. 17452243Sdfr */ 17552243Sdfr#define PCI_RF_DENSE 0x10000 17652243Sdfr#define PCI_RF_BWX 0x20000 17752243Sdfr 17845720Speterenum pci_device_ivars { 17945720Speter PCI_IVAR_SUBVENDOR, 18045720Speter PCI_IVAR_SUBDEVICE, 18145720Speter PCI_IVAR_VENDOR, 18245720Speter PCI_IVAR_DEVICE, 18345720Speter PCI_IVAR_DEVID, 18445720Speter PCI_IVAR_CLASS, 18545720Speter PCI_IVAR_SUBCLASS, 18645720Speter PCI_IVAR_PROGIF, 18745720Speter PCI_IVAR_REVID, 18845720Speter PCI_IVAR_INTPIN, 18945720Speter PCI_IVAR_IRQ, 19045720Speter PCI_IVAR_BUS, 19145720Speter PCI_IVAR_SLOT, 19245720Speter PCI_IVAR_FUNCTION, 19345720Speter PCI_IVAR_SECONDARYBUS, 19445720Speter PCI_IVAR_SUBORDINATEBUS, 19545720Speter}; 19645720Speter 19745720Speter/* 19845720Speter * Simplified accessors for pci devices 19945720Speter */ 20045720Speter#define PCI_ACCESSOR(A, B, T) \ 20145720Speter \ 20245720Speterstatic __inline T pci_get_ ## A(device_t dev) \ 20345720Speter{ \ 20445720Speter uintptr_t v; \ 20545720Speter BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 20645720Speter return (T) v; \ 20745720Speter} \ 20845720Speter \ 20945720Speterstatic __inline void pci_set_ ## A(device_t dev, T t) \ 21045720Speter{ \ 21145720Speter u_long v = (u_long) t; \ 21245720Speter BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 21345720Speter} 21445720Speter 21545720SpeterPCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 21645720SpeterPCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 21745720SpeterPCI_ACCESSOR(vendor, VENDOR, u_int16_t) 21845720SpeterPCI_ACCESSOR(device, DEVICE, u_int16_t) 21945720SpeterPCI_ACCESSOR(devid, DEVID, u_int32_t) 22045720SpeterPCI_ACCESSOR(class, CLASS, u_int8_t) 22145720SpeterPCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 22245720SpeterPCI_ACCESSOR(progif, PROGIF, u_int8_t) 22345720SpeterPCI_ACCESSOR(revid, REVID, u_int8_t) 22445720SpeterPCI_ACCESSOR(intpin, INTPIN, u_int8_t) 22545720SpeterPCI_ACCESSOR(irq, IRQ, u_int8_t) 22645720SpeterPCI_ACCESSOR(bus, BUS, u_int8_t) 22745720SpeterPCI_ACCESSOR(slot, SLOT, u_int8_t) 22845720SpeterPCI_ACCESSOR(function, FUNCTION, u_int8_t) 22945720SpeterPCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 23045720SpeterPCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 23145720Speter 23245720Speterstatic __inline u_int32_t 23345720Speterpci_read_config(device_t dev, int reg, int width) 23445720Speter{ 23545720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 23645720Speter} 23745720Speter 23845720Speterstatic __inline void 23945720Speterpci_write_config(device_t dev, int reg, u_int32_t val, int width) 24045720Speter{ 24145720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 24245720Speter} 24345720Speter 24447339Sgallatin/* 24547339Sgallatin * Ivars for pci bridges. 24647339Sgallatin */ 24747339Sgallatin 24847339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 24947339Sgallatinenum pcib_device_ivars { 25065176Sdfr PCIB_IVAR_BUS 25147339Sgallatin}; 25247339Sgallatin 25347339Sgallatin#define PCIB_ACCESSOR(A, B, T) \ 25447339Sgallatin \ 25547339Sgallatinstatic __inline T pcib_get_ ## A(device_t dev) \ 25647339Sgallatin{ \ 25747339Sgallatin uintptr_t v; \ 25847339Sgallatin BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 25947339Sgallatin return (T) v; \ 26047339Sgallatin} \ 26147339Sgallatin \ 26247339Sgallatinstatic __inline void pcib_set_ ## A(device_t dev, T t) \ 26347339Sgallatin{ \ 26447339Sgallatin u_long v = (u_long) t; \ 26547339Sgallatin BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 26647339Sgallatin} 26747339Sgallatin 26865176SdfrPCIB_ACCESSOR(bus, BUS, u_int32_t) 26947339Sgallatin 27045720Speter#endif 27145720Speter 27261047Speter/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 27326159Sse 27458320Speter#if defined(_KERNEL) && !defined(KLD_MODULE) 27558287Speter#include "opt_compat_oldpci.h" 27658287Speter#endif 27758287Speter 27861047Speter#ifdef COMPAT_OLDPCI 27961047Speter 28058287Speter/* all this is going some day */ 28158287Speter 28226159Ssetypedef pcicfgregs *pcici_t; 28326159Ssetypedef unsigned pcidi_t; 28413597Ssetypedef void pci_inthand_t(void *arg); 28512453Sbde 28626159Sse#define pci_max_burst_len (3) 28726159Sse 28826159Sse/* just copied from old PCI code for now ... */ 28926159Sse 29026159Ssestruct pci_device { 29126159Sse char* pd_name; 29241766Sdillon const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 29326159Sse void (*pd_attach) (pcici_t tag, int unit); 29426159Sse u_long *pd_count; 29526159Sse int (*pd_shutdown) (int, int); 2967233Sse}; 2977233Sse 29837841Sdfr#ifdef __i386__ 29937841Sdfrtypedef u_short pci_port_t; 30037841Sdfr#else 30137841Sdfrtypedef u_int pci_port_t; 30237841Sdfr#endif 30337841Sdfr 30426159Sseu_long pci_conf_read (pcici_t tag, u_long reg); 30526159Ssevoid pci_conf_write (pcici_t tag, u_long reg, u_long data); 30637841Sdfrint pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 30726159Sseint pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 30842614Sbdeint pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 30942614Sbde intrmask_t *maskptr); 31042614Sbdeint pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 31142614Sbde intrmask_t *maskptr, u_int flags); 3127233Sseint pci_unmap_int (pcici_t tag); 3137233Sse 31447646Srogerpcici_t pci_get_parent_from_tag(pcici_t tag); 31547646Srogerint pci_get_bus_from_tag(pcici_t tag); 31647646Sroger 31746591Speterstruct module; 31846591Speterint compat_pci_handler (struct module *, int, void *); 31946023Speter#define COMPAT_PCI_DRIVER(name, pcidata) \ 32046023Speterstatic moduledata_t name##_mod = { \ 32146023Speter #name, \ 32246023Speter compat_pci_handler, \ 32346023Speter &pcidata \ 32446023Speter}; \ 32546023SpeterDECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 32661047Speter#endif /* COMPAT_OLDPCI */ 32746023Speter 32839231Sgibbs#endif /* _PCIVAR_H_ */ 329