pcivar.h revision 65176
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 65176 2000-08-28 21:48:13Z dfr $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36 37#define PCI_BUSMAX 255 /* highest supported bus number */ 38#define PCI_SLOTMAX 31 /* highest supported slot number */ 39#define PCI_FUNCMAX 7 /* highest supported function number */ 40#define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48#ifdef PCI_A64 49typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50#else 51typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 52#endif 53 54/* config header information common to all header types */ 55 56typedef struct pcicfg { 57 struct device *dev; /* device which owns this */ 58 void *hdrspec; /* pointer to header type specific data */ 59 60 u_int16_t subvendor; /* card vendor ID */ 61 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 62 u_int16_t vendor; /* chip vendor ID */ 63 u_int16_t device; /* chip device ID, assigned by chip vendor */ 64 65 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 66 u_int16_t statreg; /* supported PCI features and error state */ 67 68 u_int8_t baseclass; /* chip PCI class */ 69 u_int8_t subclass; /* chip PCI subclass */ 70 u_int8_t progif; /* chip PCI programming interface */ 71 u_int8_t revid; /* chip revision ID */ 72 73 u_int8_t hdrtype; /* chip config header type */ 74 u_int8_t cachelnsz; /* cache line size in 4byte units */ 75 u_int8_t intpin; /* PCI interrupt pin */ 76 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 77 78 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 79 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 80 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 81 82 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 83 u_int8_t nummaps; /* actual number of PCI maps used */ 84 85 u_int8_t bus; /* config space bus address */ 86 u_int8_t slot; /* config space slot address */ 87 u_int8_t func; /* config space function number */ 88 89 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 90 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 91} pcicfgregs; 92 93/* additional type 1 device config header information (PCI to PCI bridge) */ 94 95#ifdef PCI_A64 96#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 97#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 98#else 99#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 100#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 101#endif /* PCI_A64 */ 102 103#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 104#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 105 106typedef struct { 107 pci_addr_t pmembase; /* base address of prefetchable memory */ 108 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 109 u_int32_t membase; /* base address of memory window */ 110 u_int32_t memlimit; /* topmost address of memory window */ 111 u_int32_t iobase; /* base address of port window */ 112 u_int32_t iolimit; /* topmost address of port window */ 113 u_int16_t secstat; /* secondary bus status register */ 114 u_int16_t bridgectl; /* bridge control register */ 115 u_int8_t seclat; /* CardBus latency timer */ 116} pcih1cfgregs; 117 118/* additional type 2 device config header information (CardBus bridge) */ 119 120typedef struct { 121 u_int32_t membase0; /* base address of memory window */ 122 u_int32_t memlimit0; /* topmost address of memory window */ 123 u_int32_t membase1; /* base address of memory window */ 124 u_int32_t memlimit1; /* topmost address of memory window */ 125 u_int32_t iobase0; /* base address of port window */ 126 u_int32_t iolimit0; /* topmost address of port window */ 127 u_int32_t iobase1; /* base address of port window */ 128 u_int32_t iolimit1; /* topmost address of port window */ 129 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 130 u_int16_t secstat; /* secondary bus status register */ 131 u_int16_t bridgectl; /* bridge control register */ 132 u_int8_t seclat; /* CardBus latency timer */ 133} pcih2cfgregs; 134 135extern u_int32_t pci_numdevs; 136 137/* Only if the prerequisites are present */ 138#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 139struct pci_devinfo { 140 STAILQ_ENTRY(pci_devinfo) pci_links; 141 struct resource_list resources; 142 pcicfgregs cfg; 143 struct pci_conf conf; 144}; 145#endif 146 147/* externally visible functions */ 148 149const char *pci_ata_match(struct device *dev); 150const char *pci_usb_match(struct device *dev); 151const char *pci_vga_match(struct device *dev); 152const char *pci_chip_match(struct device *dev); 153 154/* low level PCI config register functions provided by pcibus.c */ 155 156int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 157void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 158 159#ifdef __alpha__ 160vm_offset_t pci_cvt_to_dense (vm_offset_t); 161vm_offset_t pci_cvt_to_bwx (vm_offset_t); 162#endif /* __alpha__ */ 163 164/* low level devlist operations for the 2.2 compatibility code in pci.c */ 165pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 166 167#ifdef _SYS_BUS_H_ 168 169#include "pci_if.h" 170 171/* 172 * Define pci-specific resource flags for accessing memory via dense 173 * or bwx memory spaces. These flags are ignored on i386. 174 */ 175#define PCI_RF_DENSE 0x10000 176#define PCI_RF_BWX 0x20000 177 178enum pci_device_ivars { 179 PCI_IVAR_SUBVENDOR, 180 PCI_IVAR_SUBDEVICE, 181 PCI_IVAR_VENDOR, 182 PCI_IVAR_DEVICE, 183 PCI_IVAR_DEVID, 184 PCI_IVAR_CLASS, 185 PCI_IVAR_SUBCLASS, 186 PCI_IVAR_PROGIF, 187 PCI_IVAR_REVID, 188 PCI_IVAR_INTPIN, 189 PCI_IVAR_IRQ, 190 PCI_IVAR_BUS, 191 PCI_IVAR_SLOT, 192 PCI_IVAR_FUNCTION, 193 PCI_IVAR_SECONDARYBUS, 194 PCI_IVAR_SUBORDINATEBUS, 195}; 196 197/* 198 * Simplified accessors for pci devices 199 */ 200#define PCI_ACCESSOR(A, B, T) \ 201 \ 202static __inline T pci_get_ ## A(device_t dev) \ 203{ \ 204 uintptr_t v; \ 205 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 206 return (T) v; \ 207} \ 208 \ 209static __inline void pci_set_ ## A(device_t dev, T t) \ 210{ \ 211 u_long v = (u_long) t; \ 212 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 213} 214 215PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 216PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 217PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 218PCI_ACCESSOR(device, DEVICE, u_int16_t) 219PCI_ACCESSOR(devid, DEVID, u_int32_t) 220PCI_ACCESSOR(class, CLASS, u_int8_t) 221PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 222PCI_ACCESSOR(progif, PROGIF, u_int8_t) 223PCI_ACCESSOR(revid, REVID, u_int8_t) 224PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 225PCI_ACCESSOR(irq, IRQ, u_int8_t) 226PCI_ACCESSOR(bus, BUS, u_int8_t) 227PCI_ACCESSOR(slot, SLOT, u_int8_t) 228PCI_ACCESSOR(function, FUNCTION, u_int8_t) 229PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 230PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 231 232static __inline u_int32_t 233pci_read_config(device_t dev, int reg, int width) 234{ 235 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 236} 237 238static __inline void 239pci_write_config(device_t dev, int reg, u_int32_t val, int width) 240{ 241 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 242} 243 244/* 245 * Ivars for pci bridges. 246 */ 247 248/*typedef enum pci_device_ivars pcib_device_ivars;*/ 249enum pcib_device_ivars { 250 PCIB_IVAR_BUS 251}; 252 253#define PCIB_ACCESSOR(A, B, T) \ 254 \ 255static __inline T pcib_get_ ## A(device_t dev) \ 256{ \ 257 uintptr_t v; \ 258 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 259 return (T) v; \ 260} \ 261 \ 262static __inline void pcib_set_ ## A(device_t dev, T t) \ 263{ \ 264 u_long v = (u_long) t; \ 265 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 266} 267 268PCIB_ACCESSOR(bus, BUS, u_int32_t) 269 270#endif 271 272/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 273 274#if defined(_KERNEL) && !defined(KLD_MODULE) 275#include "opt_compat_oldpci.h" 276#endif 277 278#ifdef COMPAT_OLDPCI 279 280/* all this is going some day */ 281 282typedef pcicfgregs *pcici_t; 283typedef unsigned pcidi_t; 284typedef void pci_inthand_t(void *arg); 285 286#define pci_max_burst_len (3) 287 288/* just copied from old PCI code for now ... */ 289 290struct pci_device { 291 char* pd_name; 292 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 293 void (*pd_attach) (pcici_t tag, int unit); 294 u_long *pd_count; 295 int (*pd_shutdown) (int, int); 296}; 297 298#ifdef __i386__ 299typedef u_short pci_port_t; 300#else 301typedef u_int pci_port_t; 302#endif 303 304u_long pci_conf_read (pcici_t tag, u_long reg); 305void pci_conf_write (pcici_t tag, u_long reg, u_long data); 306int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 307int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 308int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 309 intrmask_t *maskptr); 310int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 311 intrmask_t *maskptr, u_int flags); 312int pci_unmap_int (pcici_t tag); 313 314pcici_t pci_get_parent_from_tag(pcici_t tag); 315int pci_get_bus_from_tag(pcici_t tag); 316 317struct module; 318int compat_pci_handler (struct module *, int, void *); 319#define COMPAT_PCI_DRIVER(name, pcidata) \ 320static moduledata_t name##_mod = { \ 321 #name, \ 322 compat_pci_handler, \ 323 &pcidata \ 324}; \ 325DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 326#endif /* COMPAT_OLDPCI */ 327 328#endif /* _PCIVAR_H_ */ 329