1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Copyright (c) 2006 6 * Alfred Perlstein <alfred@FreeBSD.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD$"); 38 39/* 40 * ADMtek AN986 Pegasus and AN8511 Pegasus II USB to ethernet driver. 41 * Datasheet is available from http://www.admtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 * 47 * SMP locking by Alfred Perlstein <alfred@FreeBSD.org>. 48 * RED Inc. 49 */ 50 51/* 52 * The Pegasus chip uses four USB "endpoints" to provide 10/100 ethernet 53 * support: the control endpoint for reading/writing registers, burst 54 * read endpoint for packet reception, burst write for packet transmission 55 * and one for "interrupts." The chip uses the same RX filter scheme 56 * as the other ADMtek ethernet parts: one perfect filter entry for the 57 * the station address and a 64-bit multicast hash table. The chip supports 58 * both MII and HomePNA attachments. 59 * 60 * Since the maximum data transfer speed of USB is supposed to be 12Mbps, 61 * you're never really going to get 100Mbps speeds from this device. I 62 * think the idea is to allow the device to connect to 10 or 100Mbps 63 * networks, not necessarily to provide 100Mbps performance. Also, since 64 * the controller uses an external PHY chip, it's possible that board 65 * designers might simply choose a 10Mbps PHY. 66 * 67 * Registers are accessed using uether_do_request(). Packet 68 * transfers are done using usbd_transfer() and friends. 69 */ 70 71#include <sys/stdint.h> 72#include <sys/stddef.h> 73#include <sys/param.h> 74#include <sys/queue.h> 75#include <sys/types.h> 76#include <sys/systm.h> 77#include <sys/socket.h> 78#include <sys/kernel.h> 79#include <sys/bus.h> 80#include <sys/module.h> 81#include <sys/lock.h> 82#include <sys/mutex.h> 83#include <sys/condvar.h> 84#include <sys/sysctl.h> 85#include <sys/sx.h> 86#include <sys/unistd.h> 87#include <sys/callout.h> 88#include <sys/malloc.h> 89#include <sys/priv.h> 90 91#include <net/if.h> 92#include <net/if_var.h> 93 94#include <dev/usb/usb.h> 95#include <dev/usb/usbdi.h> 96#include <dev/usb/usbdi_util.h> 97#include "usbdevs.h" 98 99#define USB_DEBUG_VAR aue_debug 100#include <dev/usb/usb_debug.h> 101#include <dev/usb/usb_process.h> 102 103#include <dev/usb/net/usb_ethernet.h> 104#include <dev/usb/net/if_auereg.h> 105 106#ifdef USB_DEBUG 107static int aue_debug = 0; 108 109static SYSCTL_NODE(_hw_usb, OID_AUTO, aue, CTLFLAG_RW, 0, "USB aue"); 110SYSCTL_INT(_hw_usb_aue, OID_AUTO, debug, CTLFLAG_RWTUN, &aue_debug, 0, 111 "Debug level"); 112#endif 113 114/* 115 * Various supported device vendors/products. 116 */ 117static const STRUCT_USB_HOST_ID aue_devs[] = { 118#define AUE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 119 AUE_DEV(3COM, 3C460B, AUE_FLAG_PII), 120 AUE_DEV(ABOCOM, DSB650TX_PNA, 0), 121 AUE_DEV(ABOCOM, UFE1000, AUE_FLAG_LSYS), 122 AUE_DEV(ABOCOM, XX10, 0), 123 AUE_DEV(ABOCOM, XX1, AUE_FLAG_PNA | AUE_FLAG_PII), 124 AUE_DEV(ABOCOM, XX2, AUE_FLAG_PII), 125 AUE_DEV(ABOCOM, XX4, AUE_FLAG_PNA), 126 AUE_DEV(ABOCOM, XX5, AUE_FLAG_PNA), 127 AUE_DEV(ABOCOM, XX6, AUE_FLAG_PII), 128 AUE_DEV(ABOCOM, XX7, AUE_FLAG_PII), 129 AUE_DEV(ABOCOM, XX8, AUE_FLAG_PII), 130 AUE_DEV(ABOCOM, XX9, AUE_FLAG_PNA), 131 AUE_DEV(ACCTON, SS1001, AUE_FLAG_PII), 132 AUE_DEV(ACCTON, USB320_EC, 0), 133 AUE_DEV(ADMTEK, PEGASUSII_2, AUE_FLAG_PII), 134 AUE_DEV(ADMTEK, PEGASUSII_3, AUE_FLAG_PII), 135 AUE_DEV(ADMTEK, PEGASUSII_4, AUE_FLAG_PII), 136 AUE_DEV(ADMTEK, PEGASUSII, AUE_FLAG_PII), 137 AUE_DEV(ADMTEK, PEGASUS, AUE_FLAG_PNA | AUE_FLAG_DUAL_PHY), 138 AUE_DEV(AEI, FASTETHERNET, AUE_FLAG_PII), 139 AUE_DEV(ALLIEDTELESYN, ATUSB100, AUE_FLAG_PII), 140 AUE_DEV(ATEN, UC110T, AUE_FLAG_PII), 141 AUE_DEV(BELKIN, USB2LAN, AUE_FLAG_PII), 142 AUE_DEV(BILLIONTON, USB100, 0), 143 AUE_DEV(BILLIONTON, USBE100, AUE_FLAG_PII), 144 AUE_DEV(BILLIONTON, USBEL100, 0), 145 AUE_DEV(BILLIONTON, USBLP100, AUE_FLAG_PNA), 146 AUE_DEV(COREGA, FETHER_USB_TXS, AUE_FLAG_PII), 147 AUE_DEV(COREGA, FETHER_USB_TX, 0), 148 AUE_DEV(DLINK, DSB650TX1, AUE_FLAG_LSYS), 149 AUE_DEV(DLINK, DSB650TX2, AUE_FLAG_LSYS | AUE_FLAG_PII), 150 AUE_DEV(DLINK, DSB650TX3, AUE_FLAG_LSYS | AUE_FLAG_PII), 151 AUE_DEV(DLINK, DSB650TX4, AUE_FLAG_LSYS | AUE_FLAG_PII), 152 AUE_DEV(DLINK, DSB650TX_PNA, AUE_FLAG_PNA), 153 AUE_DEV(DLINK, DSB650TX, AUE_FLAG_LSYS), 154 AUE_DEV(DLINK, DSB650, AUE_FLAG_LSYS), 155 AUE_DEV(ELCON, PLAN, AUE_FLAG_PNA | AUE_FLAG_PII), 156 AUE_DEV(ELECOM, LDUSB20, AUE_FLAG_PII), 157 AUE_DEV(ELECOM, LDUSBLTX, AUE_FLAG_PII), 158 AUE_DEV(ELECOM, LDUSBTX0, 0), 159 AUE_DEV(ELECOM, LDUSBTX1, AUE_FLAG_LSYS), 160 AUE_DEV(ELECOM, LDUSBTX2, 0), 161 AUE_DEV(ELECOM, LDUSBTX3, AUE_FLAG_LSYS), 162 AUE_DEV(ELSA, USB2ETHERNET, 0), 163 AUE_DEV(GIGABYTE, GNBR402W, 0), 164 AUE_DEV(HAWKING, UF100, AUE_FLAG_PII), 165 AUE_DEV(HP, HN210E, AUE_FLAG_PII), 166 AUE_DEV(IODATA, USBETTXS, AUE_FLAG_PII), 167 AUE_DEV(IODATA, USBETTX, 0), 168 AUE_DEV(KINGSTON, KNU101TX, 0), 169 AUE_DEV(LINKSYS, USB100H1, AUE_FLAG_LSYS | AUE_FLAG_PNA), 170 AUE_DEV(LINKSYS, USB100TX, AUE_FLAG_LSYS), 171 AUE_DEV(LINKSYS, USB10TA, AUE_FLAG_LSYS), 172 AUE_DEV(LINKSYS, USB10TX1, AUE_FLAG_LSYS | AUE_FLAG_PII), 173 AUE_DEV(LINKSYS, USB10TX2, AUE_FLAG_LSYS | AUE_FLAG_PII), 174 AUE_DEV(LINKSYS, USB10T, AUE_FLAG_LSYS), 175 AUE_DEV(MELCO, LUA2TX5, AUE_FLAG_PII), 176 AUE_DEV(MELCO, LUATX1, 0), 177 AUE_DEV(MELCO, LUATX5, 0), 178 AUE_DEV(MICROSOFT, MN110, AUE_FLAG_PII), 179 AUE_DEV(NETGEAR, FA101, AUE_FLAG_PII), 180 AUE_DEV(SIEMENS, SPEEDSTREAM, AUE_FLAG_PII), 181 AUE_DEV(SIIG2, USBTOETHER, AUE_FLAG_PII), 182 AUE_DEV(SMARTBRIDGES, SMARTNIC, AUE_FLAG_PII), 183 AUE_DEV(SMC, 2202USB, 0), 184 AUE_DEV(SMC, 2206USB, AUE_FLAG_PII), 185 AUE_DEV(SOHOWARE, NUB100, 0), 186 AUE_DEV(SOHOWARE, NUB110, AUE_FLAG_PII), 187#undef AUE_DEV 188}; 189 190/* prototypes */ 191 192static device_probe_t aue_probe; 193static device_attach_t aue_attach; 194static device_detach_t aue_detach; 195static miibus_readreg_t aue_miibus_readreg; 196static miibus_writereg_t aue_miibus_writereg; 197static miibus_statchg_t aue_miibus_statchg; 198 199static usb_callback_t aue_intr_callback; 200static usb_callback_t aue_bulk_read_callback; 201static usb_callback_t aue_bulk_write_callback; 202 203static uether_fn_t aue_attach_post; 204static uether_fn_t aue_init; 205static uether_fn_t aue_stop; 206static uether_fn_t aue_start; 207static uether_fn_t aue_tick; 208static uether_fn_t aue_setmulti; 209static uether_fn_t aue_setpromisc; 210 211static uint8_t aue_csr_read_1(struct aue_softc *, uint16_t); 212static uint16_t aue_csr_read_2(struct aue_softc *, uint16_t); 213static void aue_csr_write_1(struct aue_softc *, uint16_t, uint8_t); 214static void aue_csr_write_2(struct aue_softc *, uint16_t, uint16_t); 215static uint16_t aue_eeprom_getword(struct aue_softc *, int); 216static void aue_reset(struct aue_softc *); 217static void aue_reset_pegasus_II(struct aue_softc *); 218 219static int aue_ifmedia_upd(struct ifnet *); 220static void aue_ifmedia_sts(struct ifnet *, struct ifmediareq *); 221 222static const struct usb_config aue_config[AUE_N_TRANSFER] = { 223 224 [AUE_BULK_DT_WR] = { 225 .type = UE_BULK, 226 .endpoint = UE_ADDR_ANY, 227 .direction = UE_DIR_OUT, 228 .bufsize = (MCLBYTES + 2), 229 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 230 .callback = aue_bulk_write_callback, 231 .timeout = 10000, /* 10 seconds */ 232 }, 233 234 [AUE_BULK_DT_RD] = { 235 .type = UE_BULK, 236 .endpoint = UE_ADDR_ANY, 237 .direction = UE_DIR_IN, 238 .bufsize = (MCLBYTES + 4 + ETHER_CRC_LEN), 239 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 240 .callback = aue_bulk_read_callback, 241 }, 242 243 [AUE_INTR_DT_RD] = { 244 .type = UE_INTERRUPT, 245 .endpoint = UE_ADDR_ANY, 246 .direction = UE_DIR_IN, 247 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 248 .bufsize = 0, /* use wMaxPacketSize */ 249 .callback = aue_intr_callback, 250 }, 251}; 252 253static device_method_t aue_methods[] = { 254 /* Device interface */ 255 DEVMETHOD(device_probe, aue_probe), 256 DEVMETHOD(device_attach, aue_attach), 257 DEVMETHOD(device_detach, aue_detach), 258 259 /* MII interface */ 260 DEVMETHOD(miibus_readreg, aue_miibus_readreg), 261 DEVMETHOD(miibus_writereg, aue_miibus_writereg), 262 DEVMETHOD(miibus_statchg, aue_miibus_statchg), 263 264 DEVMETHOD_END 265}; 266 267static driver_t aue_driver = { 268 .name = "aue", 269 .methods = aue_methods, 270 .size = sizeof(struct aue_softc) 271}; 272 273static devclass_t aue_devclass; 274 275DRIVER_MODULE(aue, uhub, aue_driver, aue_devclass, NULL, 0); 276DRIVER_MODULE(miibus, aue, miibus_driver, miibus_devclass, 0, 0); 277MODULE_DEPEND(aue, uether, 1, 1, 1); 278MODULE_DEPEND(aue, usb, 1, 1, 1); 279MODULE_DEPEND(aue, ether, 1, 1, 1); 280MODULE_DEPEND(aue, miibus, 1, 1, 1); 281MODULE_VERSION(aue, 1); 282USB_PNP_HOST_INFO(aue_devs); 283 284static const struct usb_ether_methods aue_ue_methods = { 285 .ue_attach_post = aue_attach_post, 286 .ue_start = aue_start, 287 .ue_init = aue_init, 288 .ue_stop = aue_stop, 289 .ue_tick = aue_tick, 290 .ue_setmulti = aue_setmulti, 291 .ue_setpromisc = aue_setpromisc, 292 .ue_mii_upd = aue_ifmedia_upd, 293 .ue_mii_sts = aue_ifmedia_sts, 294}; 295 296#define AUE_SETBIT(sc, reg, x) \ 297 aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x)) 298 299#define AUE_CLRBIT(sc, reg, x) \ 300 aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x)) 301 302static uint8_t 303aue_csr_read_1(struct aue_softc *sc, uint16_t reg) 304{ 305 struct usb_device_request req; 306 usb_error_t err; 307 uint8_t val; 308 309 req.bmRequestType = UT_READ_VENDOR_DEVICE; 310 req.bRequest = AUE_UR_READREG; 311 USETW(req.wValue, 0); 312 USETW(req.wIndex, reg); 313 USETW(req.wLength, 1); 314 315 err = uether_do_request(&sc->sc_ue, &req, &val, 1000); 316 if (err) 317 return (0); 318 return (val); 319} 320 321static uint16_t 322aue_csr_read_2(struct aue_softc *sc, uint16_t reg) 323{ 324 struct usb_device_request req; 325 usb_error_t err; 326 uint16_t val; 327 328 req.bmRequestType = UT_READ_VENDOR_DEVICE; 329 req.bRequest = AUE_UR_READREG; 330 USETW(req.wValue, 0); 331 USETW(req.wIndex, reg); 332 USETW(req.wLength, 2); 333 334 err = uether_do_request(&sc->sc_ue, &req, &val, 1000); 335 if (err) 336 return (0); 337 return (le16toh(val)); 338} 339 340static void 341aue_csr_write_1(struct aue_softc *sc, uint16_t reg, uint8_t val) 342{ 343 struct usb_device_request req; 344 345 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 346 req.bRequest = AUE_UR_WRITEREG; 347 req.wValue[0] = val; 348 req.wValue[1] = 0; 349 USETW(req.wIndex, reg); 350 USETW(req.wLength, 1); 351 352 if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { 353 /* error ignored */ 354 } 355} 356 357static void 358aue_csr_write_2(struct aue_softc *sc, uint16_t reg, uint16_t val) 359{ 360 struct usb_device_request req; 361 362 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 363 req.bRequest = AUE_UR_WRITEREG; 364 USETW(req.wValue, val); 365 USETW(req.wIndex, reg); 366 USETW(req.wLength, 2); 367 368 val = htole16(val); 369 370 if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { 371 /* error ignored */ 372 } 373} 374 375/* 376 * Read a word of data stored in the EEPROM at address 'addr.' 377 */ 378static uint16_t 379aue_eeprom_getword(struct aue_softc *sc, int addr) 380{ 381 int i; 382 383 aue_csr_write_1(sc, AUE_EE_REG, addr); 384 aue_csr_write_1(sc, AUE_EE_CTL, AUE_EECTL_READ); 385 386 for (i = 0; i != AUE_TIMEOUT; i++) { 387 if (aue_csr_read_1(sc, AUE_EE_CTL) & AUE_EECTL_DONE) 388 break; 389 if (uether_pause(&sc->sc_ue, hz / 100)) 390 break; 391 } 392 393 if (i == AUE_TIMEOUT) 394 device_printf(sc->sc_ue.ue_dev, "EEPROM read timed out\n"); 395 396 return (aue_csr_read_2(sc, AUE_EE_DATA)); 397} 398 399/* 400 * Read station address(offset 0) from the EEPROM. 401 */ 402static void 403aue_read_mac(struct aue_softc *sc, uint8_t *eaddr) 404{ 405 int i, offset; 406 uint16_t word; 407 408 for (i = 0, offset = 0; i < ETHER_ADDR_LEN / 2; i++) { 409 word = aue_eeprom_getword(sc, offset + i); 410 eaddr[i * 2] = (uint8_t)word; 411 eaddr[i * 2 + 1] = (uint8_t)(word >> 8); 412 } 413} 414 415static int 416aue_miibus_readreg(device_t dev, int phy, int reg) 417{ 418 struct aue_softc *sc = device_get_softc(dev); 419 int i, locked; 420 uint16_t val = 0; 421 422 locked = mtx_owned(&sc->sc_mtx); 423 if (!locked) 424 AUE_LOCK(sc); 425 426 /* 427 * The Am79C901 HomePNA PHY actually contains two transceivers: a 1Mbps 428 * HomePNA PHY and a 10Mbps full/half duplex ethernet PHY with NWAY 429 * autoneg. However in the ADMtek adapter, only the 1Mbps PHY is 430 * actually connected to anything, so we ignore the 10Mbps one. It 431 * happens to be configured for MII address 3, so we filter that out. 432 */ 433 if (sc->sc_flags & AUE_FLAG_DUAL_PHY) { 434 if (phy == 3) 435 goto done; 436#if 0 437 if (phy != 1) 438 goto done; 439#endif 440 } 441 aue_csr_write_1(sc, AUE_PHY_ADDR, phy); 442 aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ); 443 444 for (i = 0; i != AUE_TIMEOUT; i++) { 445 if (aue_csr_read_1(sc, AUE_PHY_CTL) & AUE_PHYCTL_DONE) 446 break; 447 if (uether_pause(&sc->sc_ue, hz / 100)) 448 break; 449 } 450 451 if (i == AUE_TIMEOUT) 452 device_printf(sc->sc_ue.ue_dev, "MII read timed out\n"); 453 454 val = aue_csr_read_2(sc, AUE_PHY_DATA); 455 456done: 457 if (!locked) 458 AUE_UNLOCK(sc); 459 return (val); 460} 461 462static int 463aue_miibus_writereg(device_t dev, int phy, int reg, int data) 464{ 465 struct aue_softc *sc = device_get_softc(dev); 466 int i; 467 int locked; 468 469 if (phy == 3) 470 return (0); 471 472 locked = mtx_owned(&sc->sc_mtx); 473 if (!locked) 474 AUE_LOCK(sc); 475 476 aue_csr_write_2(sc, AUE_PHY_DATA, data); 477 aue_csr_write_1(sc, AUE_PHY_ADDR, phy); 478 aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE); 479 480 for (i = 0; i != AUE_TIMEOUT; i++) { 481 if (aue_csr_read_1(sc, AUE_PHY_CTL) & AUE_PHYCTL_DONE) 482 break; 483 if (uether_pause(&sc->sc_ue, hz / 100)) 484 break; 485 } 486 487 if (i == AUE_TIMEOUT) 488 device_printf(sc->sc_ue.ue_dev, "MII write timed out\n"); 489 490 if (!locked) 491 AUE_UNLOCK(sc); 492 return (0); 493} 494 495static void 496aue_miibus_statchg(device_t dev) 497{ 498 struct aue_softc *sc = device_get_softc(dev); 499 struct mii_data *mii = GET_MII(sc); 500 int locked; 501 502 locked = mtx_owned(&sc->sc_mtx); 503 if (!locked) 504 AUE_LOCK(sc); 505 506 AUE_CLRBIT(sc, AUE_CTL0, AUE_CTL0_RX_ENB | AUE_CTL0_TX_ENB); 507 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 508 AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_SPEEDSEL); 509 else 510 AUE_CLRBIT(sc, AUE_CTL1, AUE_CTL1_SPEEDSEL); 511 512 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 513 AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_DUPLEX); 514 else 515 AUE_CLRBIT(sc, AUE_CTL1, AUE_CTL1_DUPLEX); 516 517 AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_RX_ENB | AUE_CTL0_TX_ENB); 518 519 /* 520 * Set the LED modes on the LinkSys adapter. 521 * This turns on the 'dual link LED' bin in the auxmode 522 * register of the Broadcom PHY. 523 */ 524 if (sc->sc_flags & AUE_FLAG_LSYS) { 525 uint16_t auxmode; 526 527 auxmode = aue_miibus_readreg(dev, 0, 0x1b); 528 aue_miibus_writereg(dev, 0, 0x1b, auxmode | 0x04); 529 } 530 if (!locked) 531 AUE_UNLOCK(sc); 532} 533 534#define AUE_BITS 6 535static void 536aue_setmulti(struct usb_ether *ue) 537{ 538 struct aue_softc *sc = uether_getsc(ue); 539 struct ifnet *ifp = uether_getifp(ue); 540 struct ifmultiaddr *ifma; 541 uint32_t h = 0; 542 uint32_t i; 543 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 544 545 AUE_LOCK_ASSERT(sc, MA_OWNED); 546 547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 548 AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_ALLMULTI); 549 return; 550 } 551 552 AUE_CLRBIT(sc, AUE_CTL0, AUE_CTL0_ALLMULTI); 553 554 /* now program new ones */ 555 if_maddr_rlock(ifp); 556 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 557 if (ifma->ifma_addr->sa_family != AF_LINK) 558 continue; 559 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 560 ifma->ifma_addr), ETHER_ADDR_LEN) & ((1 << AUE_BITS) - 1); 561 hashtbl[(h >> 3)] |= 1 << (h & 0x7); 562 } 563 if_maddr_runlock(ifp); 564 565 /* write the hashtable */ 566 for (i = 0; i != 8; i++) 567 aue_csr_write_1(sc, AUE_MAR0 + i, hashtbl[i]); 568} 569 570static void 571aue_reset_pegasus_II(struct aue_softc *sc) 572{ 573 /* Magic constants taken from Linux driver. */ 574 aue_csr_write_1(sc, AUE_REG_1D, 0); 575 aue_csr_write_1(sc, AUE_REG_7B, 2); 576#if 0 577 if ((sc->sc_flags & HAS_HOME_PNA) && mii_mode) 578 aue_csr_write_1(sc, AUE_REG_81, 6); 579 else 580#endif 581 aue_csr_write_1(sc, AUE_REG_81, 2); 582} 583 584static void 585aue_reset(struct aue_softc *sc) 586{ 587 int i; 588 589 AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_RESETMAC); 590 591 for (i = 0; i != AUE_TIMEOUT; i++) { 592 if (!(aue_csr_read_1(sc, AUE_CTL1) & AUE_CTL1_RESETMAC)) 593 break; 594 if (uether_pause(&sc->sc_ue, hz / 100)) 595 break; 596 } 597 598 if (i == AUE_TIMEOUT) 599 device_printf(sc->sc_ue.ue_dev, "reset failed\n"); 600 601 /* 602 * The PHY(s) attached to the Pegasus chip may be held 603 * in reset until we flip on the GPIO outputs. Make sure 604 * to set the GPIO pins high so that the PHY(s) will 605 * be enabled. 606 * 607 * NOTE: We used to force all of the GPIO pins low first and then 608 * enable the ones we want. This has been changed to better 609 * match the ADMtek's reference design to avoid setting the 610 * power-down configuration line of the PHY at the same time 611 * it is reset. 612 */ 613 aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); 614 aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); 615 616 if (sc->sc_flags & AUE_FLAG_LSYS) { 617 /* Grrr. LinkSys has to be different from everyone else. */ 618 aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); 619 aue_csr_write_1(sc, AUE_GPIO0, 620 AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); 621 } 622 if (sc->sc_flags & AUE_FLAG_PII) 623 aue_reset_pegasus_II(sc); 624 625 /* Wait a little while for the chip to get its brains in order: */ 626 uether_pause(&sc->sc_ue, hz / 100); 627} 628 629static void 630aue_attach_post(struct usb_ether *ue) 631{ 632 struct aue_softc *sc = uether_getsc(ue); 633 634 /* reset the adapter */ 635 aue_reset(sc); 636 637 /* get station address from the EEPROM */ 638 aue_read_mac(sc, ue->ue_eaddr); 639} 640 641/* 642 * Probe for a Pegasus chip. 643 */ 644static int 645aue_probe(device_t dev) 646{ 647 struct usb_attach_arg *uaa = device_get_ivars(dev); 648 649 if (uaa->usb_mode != USB_MODE_HOST) 650 return (ENXIO); 651 if (uaa->info.bConfigIndex != AUE_CONFIG_INDEX) 652 return (ENXIO); 653 if (uaa->info.bIfaceIndex != AUE_IFACE_IDX) 654 return (ENXIO); 655 /* 656 * Belkin USB Bluetooth dongles of the F8T012xx1 model series conflict 657 * with older Belkin USB2LAN adapters. Skip if_aue if we detect one of 658 * the devices that look like Bluetooth adapters. 659 */ 660 if (uaa->info.idVendor == USB_VENDOR_BELKIN && 661 uaa->info.idProduct == USB_PRODUCT_BELKIN_F8T012 && 662 uaa->info.bcdDevice == 0x0413) 663 return (ENXIO); 664 665 return (usbd_lookup_id_by_uaa(aue_devs, sizeof(aue_devs), uaa)); 666} 667 668/* 669 * Attach the interface. Allocate softc structures, do ifmedia 670 * setup and ethernet/BPF attach. 671 */ 672static int 673aue_attach(device_t dev) 674{ 675 struct usb_attach_arg *uaa = device_get_ivars(dev); 676 struct aue_softc *sc = device_get_softc(dev); 677 struct usb_ether *ue = &sc->sc_ue; 678 uint8_t iface_index; 679 int error; 680 681 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 682 683 if (uaa->info.bcdDevice >= 0x0201) { 684 /* XXX currently undocumented */ 685 sc->sc_flags |= AUE_FLAG_VER_2; 686 } 687 688 device_set_usb_desc(dev); 689 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 690 691 iface_index = AUE_IFACE_IDX; 692 error = usbd_transfer_setup(uaa->device, &iface_index, 693 sc->sc_xfer, aue_config, AUE_N_TRANSFER, 694 sc, &sc->sc_mtx); 695 if (error) { 696 device_printf(dev, "allocating USB transfers failed\n"); 697 goto detach; 698 } 699 700 ue->ue_sc = sc; 701 ue->ue_dev = dev; 702 ue->ue_udev = uaa->device; 703 ue->ue_mtx = &sc->sc_mtx; 704 ue->ue_methods = &aue_ue_methods; 705 706 error = uether_ifattach(ue); 707 if (error) { 708 device_printf(dev, "could not attach interface\n"); 709 goto detach; 710 } 711 return (0); /* success */ 712 713detach: 714 aue_detach(dev); 715 return (ENXIO); /* failure */ 716} 717 718static int 719aue_detach(device_t dev) 720{ 721 struct aue_softc *sc = device_get_softc(dev); 722 struct usb_ether *ue = &sc->sc_ue; 723 724 usbd_transfer_unsetup(sc->sc_xfer, AUE_N_TRANSFER); 725 uether_ifdetach(ue); 726 mtx_destroy(&sc->sc_mtx); 727 728 return (0); 729} 730 731static void 732aue_intr_callback(struct usb_xfer *xfer, usb_error_t error) 733{ 734 struct aue_softc *sc = usbd_xfer_softc(xfer); 735 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 736 struct aue_intrpkt pkt; 737 struct usb_page_cache *pc; 738 int actlen; 739 740 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 741 742 switch (USB_GET_STATE(xfer)) { 743 case USB_ST_TRANSFERRED: 744 745 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 746 actlen >= (int)sizeof(pkt)) { 747 748 pc = usbd_xfer_get_frame(xfer, 0); 749 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 750 751 if (pkt.aue_txstat0) 752 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 753 if (pkt.aue_txstat0 & (AUE_TXSTAT0_LATECOLL | 754 AUE_TXSTAT0_EXCESSCOLL)) 755 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 756 } 757 /* FALLTHROUGH */ 758 case USB_ST_SETUP: 759tr_setup: 760 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 761 usbd_transfer_submit(xfer); 762 return; 763 764 default: /* Error */ 765 if (error != USB_ERR_CANCELLED) { 766 /* try to clear stall first */ 767 usbd_xfer_set_stall(xfer); 768 goto tr_setup; 769 } 770 return; 771 } 772} 773 774static void 775aue_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 776{ 777 struct aue_softc *sc = usbd_xfer_softc(xfer); 778 struct usb_ether *ue = &sc->sc_ue; 779 struct ifnet *ifp = uether_getifp(ue); 780 struct aue_rxpkt stat; 781 struct usb_page_cache *pc; 782 int actlen; 783 784 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 785 pc = usbd_xfer_get_frame(xfer, 0); 786 787 switch (USB_GET_STATE(xfer)) { 788 case USB_ST_TRANSFERRED: 789 DPRINTFN(11, "received %d bytes\n", actlen); 790 791 if (sc->sc_flags & AUE_FLAG_VER_2) { 792 793 if (actlen == 0) { 794 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 795 goto tr_setup; 796 } 797 } else { 798 799 if (actlen <= (int)(sizeof(stat) + ETHER_CRC_LEN)) { 800 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 801 goto tr_setup; 802 } 803 usbd_copy_out(pc, actlen - sizeof(stat), &stat, 804 sizeof(stat)); 805 806 /* 807 * turn off all the non-error bits in the rx status 808 * word: 809 */ 810 stat.aue_rxstat &= AUE_RXSTAT_MASK; 811 if (stat.aue_rxstat) { 812 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 813 goto tr_setup; 814 } 815 /* No errors; receive the packet. */ 816 actlen -= (sizeof(stat) + ETHER_CRC_LEN); 817 } 818 uether_rxbuf(ue, pc, 0, actlen); 819 820 /* FALLTHROUGH */ 821 case USB_ST_SETUP: 822tr_setup: 823 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 824 usbd_transfer_submit(xfer); 825 uether_rxflush(ue); 826 return; 827 828 default: /* Error */ 829 DPRINTF("bulk read error, %s\n", 830 usbd_errstr(error)); 831 832 if (error != USB_ERR_CANCELLED) { 833 /* try to clear stall first */ 834 usbd_xfer_set_stall(xfer); 835 goto tr_setup; 836 } 837 return; 838 } 839} 840 841static void 842aue_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 843{ 844 struct aue_softc *sc = usbd_xfer_softc(xfer); 845 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 846 struct usb_page_cache *pc; 847 struct mbuf *m; 848 uint8_t buf[2]; 849 int actlen; 850 851 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 852 pc = usbd_xfer_get_frame(xfer, 0); 853 854 switch (USB_GET_STATE(xfer)) { 855 case USB_ST_TRANSFERRED: 856 DPRINTFN(11, "transfer of %d bytes complete\n", actlen); 857 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 858 859 /* FALLTHROUGH */ 860 case USB_ST_SETUP: 861tr_setup: 862 if ((sc->sc_flags & AUE_FLAG_LINK) == 0) { 863 /* 864 * don't send anything if there is no link ! 865 */ 866 return; 867 } 868 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 869 870 if (m == NULL) 871 return; 872 if (m->m_pkthdr.len > MCLBYTES) 873 m->m_pkthdr.len = MCLBYTES; 874 if (sc->sc_flags & AUE_FLAG_VER_2) { 875 876 usbd_xfer_set_frame_len(xfer, 0, m->m_pkthdr.len); 877 878 usbd_m_copy_in(pc, 0, m, 0, m->m_pkthdr.len); 879 880 } else { 881 882 usbd_xfer_set_frame_len(xfer, 0, (m->m_pkthdr.len + 2)); 883 884 /* 885 * The ADMtek documentation says that the 886 * packet length is supposed to be specified 887 * in the first two bytes of the transfer, 888 * however it actually seems to ignore this 889 * info and base the frame size on the bulk 890 * transfer length. 891 */ 892 buf[0] = (uint8_t)(m->m_pkthdr.len); 893 buf[1] = (uint8_t)(m->m_pkthdr.len >> 8); 894 895 usbd_copy_in(pc, 0, buf, 2); 896 usbd_m_copy_in(pc, 2, m, 0, m->m_pkthdr.len); 897 } 898 899 /* 900 * if there's a BPF listener, bounce a copy 901 * of this frame to him: 902 */ 903 BPF_MTAP(ifp, m); 904 905 m_freem(m); 906 907 usbd_transfer_submit(xfer); 908 return; 909 910 default: /* Error */ 911 DPRINTFN(11, "transfer error, %s\n", 912 usbd_errstr(error)); 913 914 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 915 916 if (error != USB_ERR_CANCELLED) { 917 /* try to clear stall first */ 918 usbd_xfer_set_stall(xfer); 919 goto tr_setup; 920 } 921 return; 922 } 923} 924 925static void 926aue_tick(struct usb_ether *ue) 927{ 928 struct aue_softc *sc = uether_getsc(ue); 929 struct mii_data *mii = GET_MII(sc); 930 931 AUE_LOCK_ASSERT(sc, MA_OWNED); 932 933 mii_tick(mii); 934 if ((sc->sc_flags & AUE_FLAG_LINK) == 0 935 && mii->mii_media_status & IFM_ACTIVE && 936 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 937 sc->sc_flags |= AUE_FLAG_LINK; 938 aue_start(ue); 939 } 940} 941 942static void 943aue_start(struct usb_ether *ue) 944{ 945 struct aue_softc *sc = uether_getsc(ue); 946 947 /* 948 * start the USB transfers, if not already started: 949 */ 950 usbd_transfer_start(sc->sc_xfer[AUE_INTR_DT_RD]); 951 usbd_transfer_start(sc->sc_xfer[AUE_BULK_DT_RD]); 952 usbd_transfer_start(sc->sc_xfer[AUE_BULK_DT_WR]); 953} 954 955static void 956aue_init(struct usb_ether *ue) 957{ 958 struct aue_softc *sc = uether_getsc(ue); 959 struct ifnet *ifp = uether_getifp(ue); 960 int i; 961 962 AUE_LOCK_ASSERT(sc, MA_OWNED); 963 964 /* 965 * Cancel pending I/O 966 */ 967 aue_reset(sc); 968 969 /* Set MAC address */ 970 for (i = 0; i != ETHER_ADDR_LEN; i++) 971 aue_csr_write_1(sc, AUE_PAR0 + i, IF_LLADDR(ifp)[i]); 972 973 /* update promiscuous setting */ 974 aue_setpromisc(ue); 975 976 /* Load the multicast filter. */ 977 aue_setmulti(ue); 978 979 /* Enable RX and TX */ 980 aue_csr_write_1(sc, AUE_CTL0, AUE_CTL0_RXSTAT_APPEND | AUE_CTL0_RX_ENB); 981 AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_TX_ENB); 982 AUE_SETBIT(sc, AUE_CTL2, AUE_CTL2_EP3_CLR); 983 984 usbd_xfer_set_stall(sc->sc_xfer[AUE_BULK_DT_WR]); 985 986 ifp->if_drv_flags |= IFF_DRV_RUNNING; 987 aue_start(ue); 988} 989 990static void 991aue_setpromisc(struct usb_ether *ue) 992{ 993 struct aue_softc *sc = uether_getsc(ue); 994 struct ifnet *ifp = uether_getifp(ue); 995 996 AUE_LOCK_ASSERT(sc, MA_OWNED); 997 998 /* if we want promiscuous mode, set the allframes bit: */ 999 if (ifp->if_flags & IFF_PROMISC) 1000 AUE_SETBIT(sc, AUE_CTL2, AUE_CTL2_RX_PROMISC); 1001 else 1002 AUE_CLRBIT(sc, AUE_CTL2, AUE_CTL2_RX_PROMISC); 1003} 1004 1005/* 1006 * Set media options. 1007 */ 1008static int 1009aue_ifmedia_upd(struct ifnet *ifp) 1010{ 1011 struct aue_softc *sc = ifp->if_softc; 1012 struct mii_data *mii = GET_MII(sc); 1013 struct mii_softc *miisc; 1014 int error; 1015 1016 AUE_LOCK_ASSERT(sc, MA_OWNED); 1017 1018 sc->sc_flags &= ~AUE_FLAG_LINK; 1019 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1020 PHY_RESET(miisc); 1021 error = mii_mediachg(mii); 1022 return (error); 1023} 1024 1025/* 1026 * Report current media status. 1027 */ 1028static void 1029aue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1030{ 1031 struct aue_softc *sc = ifp->if_softc; 1032 struct mii_data *mii = GET_MII(sc); 1033 1034 AUE_LOCK(sc); 1035 mii_pollstat(mii); 1036 ifmr->ifm_active = mii->mii_media_active; 1037 ifmr->ifm_status = mii->mii_media_status; 1038 AUE_UNLOCK(sc); 1039} 1040 1041/* 1042 * Stop the adapter and free any mbufs allocated to the 1043 * RX and TX lists. 1044 */ 1045static void 1046aue_stop(struct usb_ether *ue) 1047{ 1048 struct aue_softc *sc = uether_getsc(ue); 1049 struct ifnet *ifp = uether_getifp(ue); 1050 1051 AUE_LOCK_ASSERT(sc, MA_OWNED); 1052 1053 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1054 sc->sc_flags &= ~AUE_FLAG_LINK; 1055 1056 /* 1057 * stop all the transfers, if not already stopped: 1058 */ 1059 usbd_transfer_stop(sc->sc_xfer[AUE_BULK_DT_WR]); 1060 usbd_transfer_stop(sc->sc_xfer[AUE_BULK_DT_RD]); 1061 usbd_transfer_stop(sc->sc_xfer[AUE_INTR_DT_RD]); 1062 1063 aue_csr_write_1(sc, AUE_CTL0, 0); 1064 aue_csr_write_1(sc, AUE_CTL1, 0); 1065 aue_reset(sc); 1066} 1067