if_ti.c revision 87846
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 87846 2001-12-14 05:56:35Z luigi $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/sockio.h> 84#include <sys/mbuf.h> 85#include <sys/malloc.h> 86#include <sys/kernel.h> 87#include <sys/socket.h> 88#include <sys/queue.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95#include <net/if_types.h> 96#include <net/if_vlan_var.h> 97 98#include <net/bpf.h> 99 100#include <netinet/in_systm.h> 101#include <netinet/in.h> 102#include <netinet/ip.h> 103 104#include <vm/vm.h> /* for vtophys */ 105#include <vm/pmap.h> /* for vtophys */ 106#include <machine/bus_memio.h> 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <pci/pcireg.h> 113#include <pci/pcivar.h> 114 115#include <pci/if_tireg.h> 116#include <pci/ti_fw.h> 117#include <pci/ti_fw2.h> 118 119#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 120 121#if !defined(lint) 122static const char rcsid[] = 123 "$FreeBSD: head/sys/dev/ti/if_ti.c 87846 2001-12-14 05:56:35Z luigi $"; 124#endif 125 126/* 127 * Various supported device vendors/types and their names. 128 */ 129 130static struct ti_type ti_devs[] = { 131 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 132 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 133 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 134 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 135 { TC_VENDORID, TC_DEVICEID_3C985, 136 "3Com 3c985-SX Gigabit Ethernet" }, 137 { NG_VENDORID, NG_DEVICEID_GA620, 138 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 139 { NG_VENDORID, NG_DEVICEID_GA620T, 140 "Netgear GA620 1000baseT Gigabit Ethernet" }, 141 { SGI_VENDORID, SGI_DEVICEID_TIGON, 142 "Silicon Graphics Gigabit Ethernet" }, 143 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 144 "Farallon PN9000SX Gigabit Ethernet" }, 145 { 0, 0, NULL } 146}; 147 148static int ti_probe __P((device_t)); 149static int ti_attach __P((device_t)); 150static int ti_detach __P((device_t)); 151static void ti_txeof __P((struct ti_softc *)); 152static void ti_rxeof __P((struct ti_softc *)); 153 154static void ti_stats_update __P((struct ti_softc *)); 155static int ti_encap __P((struct ti_softc *, struct mbuf *, 156 u_int32_t *)); 157 158static void ti_intr __P((void *)); 159static void ti_start __P((struct ifnet *)); 160static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 161static void ti_init __P((void *)); 162static void ti_init2 __P((struct ti_softc *)); 163static void ti_stop __P((struct ti_softc *)); 164static void ti_watchdog __P((struct ifnet *)); 165static void ti_shutdown __P((device_t)); 166static int ti_ifmedia_upd __P((struct ifnet *)); 167static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 168 169static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 170static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 171 int, u_int8_t *)); 172static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 173 174static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 175static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 176static void ti_setmulti __P((struct ti_softc *)); 177 178static void ti_mem __P((struct ti_softc *, u_int32_t, 179 u_int32_t, caddr_t)); 180static void ti_loadfw __P((struct ti_softc *)); 181static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 182static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 183 caddr_t, int)); 184static void ti_handle_events __P((struct ti_softc *)); 185static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 186static void *ti_jalloc __P((struct ti_softc *)); 187static void ti_jfree __P((caddr_t, void *)); 188static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 189static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 190static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 191static int ti_init_rx_ring_std __P((struct ti_softc *)); 192static void ti_free_rx_ring_std __P((struct ti_softc *)); 193static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 194static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 195static int ti_init_rx_ring_mini __P((struct ti_softc *)); 196static void ti_free_rx_ring_mini __P((struct ti_softc *)); 197static void ti_free_tx_ring __P((struct ti_softc *)); 198static int ti_init_tx_ring __P((struct ti_softc *)); 199 200static int ti_64bitslot_war __P((struct ti_softc *)); 201static int ti_chipinit __P((struct ti_softc *)); 202static int ti_gibinit __P((struct ti_softc *)); 203 204static device_method_t ti_methods[] = { 205 /* Device interface */ 206 DEVMETHOD(device_probe, ti_probe), 207 DEVMETHOD(device_attach, ti_attach), 208 DEVMETHOD(device_detach, ti_detach), 209 DEVMETHOD(device_shutdown, ti_shutdown), 210 { 0, 0 } 211}; 212 213static driver_t ti_driver = { 214 "ti", 215 ti_methods, 216 sizeof(struct ti_softc) 217}; 218 219static devclass_t ti_devclass; 220 221DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 222 223/* 224 * Send an instruction or address to the EEPROM, check for ACK. 225 */ 226static u_int32_t ti_eeprom_putbyte(sc, byte) 227 struct ti_softc *sc; 228 int byte; 229{ 230 register int i, ack = 0; 231 232 /* 233 * Make sure we're in TX mode. 234 */ 235 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 236 237 /* 238 * Feed in each bit and stobe the clock. 239 */ 240 for (i = 0x80; i; i >>= 1) { 241 if (byte & i) { 242 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 243 } else { 244 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 245 } 246 DELAY(1); 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 DELAY(1); 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 250 } 251 252 /* 253 * Turn off TX mode. 254 */ 255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 256 257 /* 258 * Check for ack. 259 */ 260 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 261 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 262 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 263 264 return(ack); 265} 266 267/* 268 * Read a byte of data stored in the EEPROM at address 'addr.' 269 * We have to send two address bytes since the EEPROM can hold 270 * more than 256 bytes of data. 271 */ 272static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 273 struct ti_softc *sc; 274 int addr; 275 u_int8_t *dest; 276{ 277 register int i; 278 u_int8_t byte = 0; 279 280 EEPROM_START; 281 282 /* 283 * Send write control code to EEPROM. 284 */ 285 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 286 printf("ti%d: failed to send write command, status: %x\n", 287 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 288 return(1); 289 } 290 291 /* 292 * Send first byte of address of byte we want to read. 293 */ 294 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 295 printf("ti%d: failed to send address, status: %x\n", 296 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return(1); 298 } 299 /* 300 * Send second byte address of byte we want to read. 301 */ 302 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 303 printf("ti%d: failed to send address, status: %x\n", 304 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 305 return(1); 306 } 307 308 EEPROM_STOP; 309 EEPROM_START; 310 /* 311 * Send read control code to EEPROM. 312 */ 313 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 314 printf("ti%d: failed to send read command, status: %x\n", 315 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 316 return(1); 317 } 318 319 /* 320 * Start reading bits from EEPROM. 321 */ 322 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 323 for (i = 0x80; i; i >>= 1) { 324 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 325 DELAY(1); 326 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 327 byte |= i; 328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 329 DELAY(1); 330 } 331 332 EEPROM_STOP; 333 334 /* 335 * No ACK generated for read, so just return byte. 336 */ 337 338 *dest = byte; 339 340 return(0); 341} 342 343/* 344 * Read a sequence of bytes from the EEPROM. 345 */ 346static int ti_read_eeprom(sc, dest, off, cnt) 347 struct ti_softc *sc; 348 caddr_t dest; 349 int off; 350 int cnt; 351{ 352 int err = 0, i; 353 u_int8_t byte = 0; 354 355 for (i = 0; i < cnt; i++) { 356 err = ti_eeprom_getbyte(sc, off + i, &byte); 357 if (err) 358 break; 359 *(dest + i) = byte; 360 } 361 362 return(err ? 1 : 0); 363} 364 365/* 366 * NIC memory access function. Can be used to either clear a section 367 * of NIC local memory or (if buf is non-NULL) copy data into it. 368 */ 369static void ti_mem(sc, addr, len, buf) 370 struct ti_softc *sc; 371 u_int32_t addr, len; 372 caddr_t buf; 373{ 374 int segptr, segsize, cnt; 375 caddr_t ti_winbase, ptr; 376 377 segptr = addr; 378 cnt = len; 379 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 380 ptr = buf; 381 382 while(cnt) { 383 if (cnt < TI_WINLEN) 384 segsize = cnt; 385 else 386 segsize = TI_WINLEN - (segptr % TI_WINLEN); 387 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 388 if (buf == NULL) 389 bzero((char *)ti_winbase + (segptr & 390 (TI_WINLEN - 1)), segsize); 391 else { 392 bcopy((char *)ptr, (char *)ti_winbase + 393 (segptr & (TI_WINLEN - 1)), segsize); 394 ptr += segsize; 395 } 396 segptr += segsize; 397 cnt -= segsize; 398 } 399 400 return; 401} 402 403/* 404 * Load firmware image into the NIC. Check that the firmware revision 405 * is acceptable and see if we want the firmware for the Tigon 1 or 406 * Tigon 2. 407 */ 408static void ti_loadfw(sc) 409 struct ti_softc *sc; 410{ 411 switch(sc->ti_hwrev) { 412 case TI_HWREV_TIGON: 413 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 414 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 415 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 416 printf("ti%d: firmware revision mismatch; want " 417 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 418 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 419 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 420 tigonFwReleaseMinor, tigonFwReleaseFix); 421 return; 422 } 423 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 424 (caddr_t)tigonFwText); 425 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 426 (caddr_t)tigonFwData); 427 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 428 (caddr_t)tigonFwRodata); 429 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 430 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 431 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 432 break; 433 case TI_HWREV_TIGON_II: 434 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 435 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 436 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 437 printf("ti%d: firmware revision mismatch; want " 438 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 439 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 440 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 441 tigon2FwReleaseMinor, tigon2FwReleaseFix); 442 return; 443 } 444 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 445 (caddr_t)tigon2FwText); 446 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 447 (caddr_t)tigon2FwData); 448 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 449 (caddr_t)tigon2FwRodata); 450 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 451 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 452 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 453 break; 454 default: 455 printf("ti%d: can't load firmware: unknown hardware rev\n", 456 sc->ti_unit); 457 break; 458 } 459 460 return; 461} 462 463/* 464 * Send the NIC a command via the command ring. 465 */ 466static void ti_cmd(sc, cmd) 467 struct ti_softc *sc; 468 struct ti_cmd_desc *cmd; 469{ 470 u_int32_t index; 471 472 if (sc->ti_rdata->ti_cmd_ring == NULL) 473 return; 474 475 index = sc->ti_cmd_saved_prodidx; 476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 477 TI_INC(index, TI_CMD_RING_CNT); 478 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 479 sc->ti_cmd_saved_prodidx = index; 480 481 return; 482} 483 484/* 485 * Send the NIC an extended command. The 'len' parameter specifies the 486 * number of command slots to include after the initial command. 487 */ 488static void ti_cmd_ext(sc, cmd, arg, len) 489 struct ti_softc *sc; 490 struct ti_cmd_desc *cmd; 491 caddr_t arg; 492 int len; 493{ 494 u_int32_t index; 495 register int i; 496 497 if (sc->ti_rdata->ti_cmd_ring == NULL) 498 return; 499 500 index = sc->ti_cmd_saved_prodidx; 501 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 502 TI_INC(index, TI_CMD_RING_CNT); 503 for (i = 0; i < len; i++) { 504 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 505 *(u_int32_t *)(&arg[i * 4])); 506 TI_INC(index, TI_CMD_RING_CNT); 507 } 508 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 509 sc->ti_cmd_saved_prodidx = index; 510 511 return; 512} 513 514/* 515 * Handle events that have triggered interrupts. 516 */ 517static void ti_handle_events(sc) 518 struct ti_softc *sc; 519{ 520 struct ti_event_desc *e; 521 522 if (sc->ti_rdata->ti_event_ring == NULL) 523 return; 524 525 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 526 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 527 switch(e->ti_event) { 528 case TI_EV_LINKSTAT_CHANGED: 529 sc->ti_linkstat = e->ti_code; 530 if (e->ti_code == TI_EV_CODE_LINK_UP) 531 printf("ti%d: 10/100 link up\n", sc->ti_unit); 532 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 533 printf("ti%d: gigabit link up\n", sc->ti_unit); 534 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 535 printf("ti%d: link down\n", sc->ti_unit); 536 break; 537 case TI_EV_ERROR: 538 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 539 printf("ti%d: invalid command\n", sc->ti_unit); 540 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 541 printf("ti%d: unknown command\n", sc->ti_unit); 542 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 543 printf("ti%d: bad config data\n", sc->ti_unit); 544 break; 545 case TI_EV_FIRMWARE_UP: 546 ti_init2(sc); 547 break; 548 case TI_EV_STATS_UPDATED: 549 ti_stats_update(sc); 550 break; 551 case TI_EV_RESET_JUMBO_RING: 552 case TI_EV_MCAST_UPDATED: 553 /* Who cares. */ 554 break; 555 default: 556 printf("ti%d: unknown event: %d\n", 557 sc->ti_unit, e->ti_event); 558 break; 559 } 560 /* Advance the consumer index. */ 561 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 562 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 563 } 564 565 return; 566} 567 568/* 569 * Memory management for the jumbo receive ring is a pain in the 570 * butt. We need to allocate at least 9018 bytes of space per frame, 571 * _and_ it has to be contiguous (unless you use the extended 572 * jumbo descriptor format). Using malloc() all the time won't 573 * work: malloc() allocates memory in powers of two, which means we 574 * would end up wasting a considerable amount of space by allocating 575 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 576 * to do our own memory management. 577 * 578 * The driver needs to allocate a contiguous chunk of memory at boot 579 * time. We then chop this up ourselves into 9K pieces and use them 580 * as external mbuf storage. 581 * 582 * One issue here is how much memory to allocate. The jumbo ring has 583 * 256 slots in it, but at 9K per slot than can consume over 2MB of 584 * RAM. This is a bit much, especially considering we also need 585 * RAM for the standard ring and mini ring (on the Tigon 2). To 586 * save space, we only actually allocate enough memory for 64 slots 587 * by default, which works out to between 500 and 600K. This can 588 * be tuned by changing a #define in if_tireg.h. 589 */ 590 591static int ti_alloc_jumbo_mem(sc) 592 struct ti_softc *sc; 593{ 594 caddr_t ptr; 595 register int i; 596 struct ti_jpool_entry *entry; 597 598 /* Grab a big chunk o' storage. */ 599 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 600 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 601 602 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 603 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 604 return(ENOBUFS); 605 } 606 607 SLIST_INIT(&sc->ti_jfree_listhead); 608 SLIST_INIT(&sc->ti_jinuse_listhead); 609 610 /* 611 * Now divide it up into 9K pieces and save the addresses 612 * in an array. 613 */ 614 ptr = sc->ti_cdata.ti_jumbo_buf; 615 for (i = 0; i < TI_JSLOTS; i++) { 616 sc->ti_cdata.ti_jslots[i] = ptr; 617 ptr += TI_JLEN; 618 entry = malloc(sizeof(struct ti_jpool_entry), 619 M_DEVBUF, M_NOWAIT); 620 if (entry == NULL) { 621 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 622 M_DEVBUF); 623 sc->ti_cdata.ti_jumbo_buf = NULL; 624 printf("ti%d: no memory for jumbo " 625 "buffer queue!\n", sc->ti_unit); 626 return(ENOBUFS); 627 } 628 entry->slot = i; 629 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 630 } 631 632 return(0); 633} 634 635/* 636 * Allocate a jumbo buffer. 637 */ 638static void *ti_jalloc(sc) 639 struct ti_softc *sc; 640{ 641 struct ti_jpool_entry *entry; 642 643 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 644 645 if (entry == NULL) { 646 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 647 return(NULL); 648 } 649 650 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 651 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 652 return(sc->ti_cdata.ti_jslots[entry->slot]); 653} 654 655/* 656 * Release a jumbo buffer. 657 */ 658static void ti_jfree(buf, args) 659 caddr_t buf; 660 void *args; 661{ 662 struct ti_softc *sc; 663 int i; 664 struct ti_jpool_entry *entry; 665 666 /* Extract the softc struct pointer. */ 667 sc = (struct ti_softc *)args; 668 669 if (sc == NULL) 670 panic("ti_jfree: didn't get softc pointer!"); 671 672 /* calculate the slot this buffer belongs to */ 673 i = ((vm_offset_t)buf 674 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 675 676 if ((i < 0) || (i >= TI_JSLOTS)) 677 panic("ti_jfree: asked to free buffer that we don't manage!"); 678 679 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 680 if (entry == NULL) 681 panic("ti_jfree: buffer not in use!"); 682 entry->slot = i; 683 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 684 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 685 686 return; 687} 688 689 690/* 691 * Intialize a standard receive ring descriptor. 692 */ 693static int ti_newbuf_std(sc, i, m) 694 struct ti_softc *sc; 695 int i; 696 struct mbuf *m; 697{ 698 struct mbuf *m_new = NULL; 699 struct ti_rx_desc *r; 700 701 if (m == NULL) { 702 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 703 if (m_new == NULL) 704 return(ENOBUFS); 705 706 MCLGET(m_new, M_DONTWAIT); 707 if (!(m_new->m_flags & M_EXT)) { 708 m_freem(m_new); 709 return(ENOBUFS); 710 } 711 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 712 } else { 713 m_new = m; 714 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 715 m_new->m_data = m_new->m_ext.ext_buf; 716 } 717 718 m_adj(m_new, ETHER_ALIGN); 719 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 720 r = &sc->ti_rdata->ti_rx_std_ring[i]; 721 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 722 r->ti_type = TI_BDTYPE_RECV_BD; 723 r->ti_flags = 0; 724 if (sc->arpcom.ac_if.if_hwassist) 725 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 726 r->ti_len = m_new->m_len; 727 r->ti_idx = i; 728 729 return(0); 730} 731 732/* 733 * Intialize a mini receive ring descriptor. This only applies to 734 * the Tigon 2. 735 */ 736static int ti_newbuf_mini(sc, i, m) 737 struct ti_softc *sc; 738 int i; 739 struct mbuf *m; 740{ 741 struct mbuf *m_new = NULL; 742 struct ti_rx_desc *r; 743 744 if (m == NULL) { 745 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 746 if (m_new == NULL) { 747 printf("ti%d: mbuf allocation failed " 748 "-- packet dropped!\n", sc->ti_unit); 749 return(ENOBUFS); 750 } 751 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 752 } else { 753 m_new = m; 754 m_new->m_data = m_new->m_pktdat; 755 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 756 } 757 758 m_adj(m_new, ETHER_ALIGN); 759 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 760 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 761 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 762 r->ti_type = TI_BDTYPE_RECV_BD; 763 r->ti_flags = TI_BDFLAG_MINI_RING; 764 if (sc->arpcom.ac_if.if_hwassist) 765 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 766 r->ti_len = m_new->m_len; 767 r->ti_idx = i; 768 769 return(0); 770} 771 772/* 773 * Initialize a jumbo receive ring descriptor. This allocates 774 * a jumbo buffer from the pool managed internally by the driver. 775 */ 776static int ti_newbuf_jumbo(sc, i, m) 777 struct ti_softc *sc; 778 int i; 779 struct mbuf *m; 780{ 781 struct mbuf *m_new = NULL; 782 struct ti_rx_desc *r; 783 784 if (m == NULL) { 785 caddr_t *buf = NULL; 786 787 /* Allocate the mbuf. */ 788 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 789 if (m_new == NULL) { 790 printf("ti%d: mbuf allocation failed " 791 "-- packet dropped!\n", sc->ti_unit); 792 return(ENOBUFS); 793 } 794 795 /* Allocate the jumbo buffer */ 796 buf = ti_jalloc(sc); 797 if (buf == NULL) { 798 m_freem(m_new); 799 printf("ti%d: jumbo allocation failed " 800 "-- packet dropped!\n", sc->ti_unit); 801 return(ENOBUFS); 802 } 803 804 /* Attach the buffer to the mbuf. */ 805 m_new->m_data = (void *) buf; 806 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 807 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 808 (struct ti_softc *)sc, 0, EXT_NET_DRV); 809 } else { 810 m_new = m; 811 m_new->m_data = m_new->m_ext.ext_buf; 812 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 813 } 814 815 m_adj(m_new, ETHER_ALIGN); 816 /* Set up the descriptor. */ 817 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 818 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 819 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 820 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 821 r->ti_flags = TI_BDFLAG_JUMBO_RING; 822 if (sc->arpcom.ac_if.if_hwassist) 823 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 824 r->ti_len = m_new->m_len; 825 r->ti_idx = i; 826 827 return(0); 828} 829 830/* 831 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 832 * that's 1MB or memory, which is a lot. For now, we fill only the first 833 * 256 ring entries and hope that our CPU is fast enough to keep up with 834 * the NIC. 835 */ 836static int ti_init_rx_ring_std(sc) 837 struct ti_softc *sc; 838{ 839 register int i; 840 struct ti_cmd_desc cmd; 841 842 for (i = 0; i < TI_SSLOTS; i++) { 843 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 844 return(ENOBUFS); 845 }; 846 847 TI_UPDATE_STDPROD(sc, i - 1); 848 sc->ti_std = i - 1; 849 850 return(0); 851} 852 853static void ti_free_rx_ring_std(sc) 854 struct ti_softc *sc; 855{ 856 register int i; 857 858 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 859 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 860 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 861 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 862 } 863 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 864 sizeof(struct ti_rx_desc)); 865 } 866 867 return; 868} 869 870static int ti_init_rx_ring_jumbo(sc) 871 struct ti_softc *sc; 872{ 873 register int i; 874 struct ti_cmd_desc cmd; 875 876 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 877 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 878 return(ENOBUFS); 879 }; 880 881 TI_UPDATE_JUMBOPROD(sc, i - 1); 882 sc->ti_jumbo = i - 1; 883 884 return(0); 885} 886 887static void ti_free_rx_ring_jumbo(sc) 888 struct ti_softc *sc; 889{ 890 register int i; 891 892 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 893 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 894 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 895 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 896 } 897 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 898 sizeof(struct ti_rx_desc)); 899 } 900 901 return; 902} 903 904static int ti_init_rx_ring_mini(sc) 905 struct ti_softc *sc; 906{ 907 register int i; 908 909 for (i = 0; i < TI_MSLOTS; i++) { 910 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 911 return(ENOBUFS); 912 }; 913 914 TI_UPDATE_MINIPROD(sc, i - 1); 915 sc->ti_mini = i - 1; 916 917 return(0); 918} 919 920static void ti_free_rx_ring_mini(sc) 921 struct ti_softc *sc; 922{ 923 register int i; 924 925 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 926 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 927 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 928 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 929 } 930 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 931 sizeof(struct ti_rx_desc)); 932 } 933 934 return; 935} 936 937static void ti_free_tx_ring(sc) 938 struct ti_softc *sc; 939{ 940 register int i; 941 942 if (sc->ti_rdata->ti_tx_ring == NULL) 943 return; 944 945 for (i = 0; i < TI_TX_RING_CNT; i++) { 946 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 947 m_freem(sc->ti_cdata.ti_tx_chain[i]); 948 sc->ti_cdata.ti_tx_chain[i] = NULL; 949 } 950 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 951 sizeof(struct ti_tx_desc)); 952 } 953 954 return; 955} 956 957static int ti_init_tx_ring(sc) 958 struct ti_softc *sc; 959{ 960 sc->ti_txcnt = 0; 961 sc->ti_tx_saved_considx = 0; 962 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 963 return(0); 964} 965 966/* 967 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 968 * but we have to support the old way too so that Tigon 1 cards will 969 * work. 970 */ 971void ti_add_mcast(sc, addr) 972 struct ti_softc *sc; 973 struct ether_addr *addr; 974{ 975 struct ti_cmd_desc cmd; 976 u_int16_t *m; 977 u_int32_t ext[2] = {0, 0}; 978 979 m = (u_int16_t *)&addr->octet[0]; 980 981 switch(sc->ti_hwrev) { 982 case TI_HWREV_TIGON: 983 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 984 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 985 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 986 break; 987 case TI_HWREV_TIGON_II: 988 ext[0] = htons(m[0]); 989 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 990 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 991 break; 992 default: 993 printf("ti%d: unknown hwrev\n", sc->ti_unit); 994 break; 995 } 996 997 return; 998} 999 1000void ti_del_mcast(sc, addr) 1001 struct ti_softc *sc; 1002 struct ether_addr *addr; 1003{ 1004 struct ti_cmd_desc cmd; 1005 u_int16_t *m; 1006 u_int32_t ext[2] = {0, 0}; 1007 1008 m = (u_int16_t *)&addr->octet[0]; 1009 1010 switch(sc->ti_hwrev) { 1011 case TI_HWREV_TIGON: 1012 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1013 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1014 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1015 break; 1016 case TI_HWREV_TIGON_II: 1017 ext[0] = htons(m[0]); 1018 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1019 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1020 break; 1021 default: 1022 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1023 break; 1024 } 1025 1026 return; 1027} 1028 1029/* 1030 * Configure the Tigon's multicast address filter. 1031 * 1032 * The actual multicast table management is a bit of a pain, thanks to 1033 * slight brain damage on the part of both Alteon and us. With our 1034 * multicast code, we are only alerted when the multicast address table 1035 * changes and at that point we only have the current list of addresses: 1036 * we only know the current state, not the previous state, so we don't 1037 * actually know what addresses were removed or added. The firmware has 1038 * state, but we can't get our grubby mits on it, and there is no 'delete 1039 * all multicast addresses' command. Hence, we have to maintain our own 1040 * state so we know what addresses have been programmed into the NIC at 1041 * any given time. 1042 */ 1043static void ti_setmulti(sc) 1044 struct ti_softc *sc; 1045{ 1046 struct ifnet *ifp; 1047 struct ifmultiaddr *ifma; 1048 struct ti_cmd_desc cmd; 1049 struct ti_mc_entry *mc; 1050 u_int32_t intrs; 1051 1052 ifp = &sc->arpcom.ac_if; 1053 1054 if (ifp->if_flags & IFF_ALLMULTI) { 1055 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1056 return; 1057 } else { 1058 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1059 } 1060 1061 /* Disable interrupts. */ 1062 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1063 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1064 1065 /* First, zot all the existing filters. */ 1066 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1067 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1068 ti_del_mcast(sc, &mc->mc_addr); 1069 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1070 free(mc, M_DEVBUF); 1071 } 1072 1073 /* Now program new ones. */ 1074 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1075 if (ifma->ifma_addr->sa_family != AF_LINK) 1076 continue; 1077 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1078 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1079 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1080 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1081 ti_add_mcast(sc, &mc->mc_addr); 1082 } 1083 1084 /* Re-enable interrupts. */ 1085 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1086 1087 return; 1088} 1089 1090/* 1091 * Check to see if the BIOS has configured us for a 64 bit slot when 1092 * we aren't actually in one. If we detect this condition, we can work 1093 * around it on the Tigon 2 by setting a bit in the PCI state register, 1094 * but for the Tigon 1 we must give up and abort the interface attach. 1095 */ 1096static int ti_64bitslot_war(sc) 1097 struct ti_softc *sc; 1098{ 1099 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1100 CSR_WRITE_4(sc, 0x600, 0); 1101 CSR_WRITE_4(sc, 0x604, 0); 1102 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1103 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1104 if (sc->ti_hwrev == TI_HWREV_TIGON) 1105 return(EINVAL); 1106 else { 1107 TI_SETBIT(sc, TI_PCI_STATE, 1108 TI_PCISTATE_32BIT_BUS); 1109 return(0); 1110 } 1111 } 1112 } 1113 1114 return(0); 1115} 1116 1117/* 1118 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1119 * self-test results. 1120 */ 1121static int ti_chipinit(sc) 1122 struct ti_softc *sc; 1123{ 1124 u_int32_t cacheline; 1125 u_int32_t pci_writemax = 0; 1126 1127 /* Initialize link to down state. */ 1128 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1129 1130 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1131 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1132 else 1133 sc->arpcom.ac_if.if_hwassist = 0; 1134 1135 /* Set endianness before we access any non-PCI registers. */ 1136#if BYTE_ORDER == BIG_ENDIAN 1137 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1138 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1139#else 1140 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1141 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1142#endif 1143 1144 /* Check the ROM failed bit to see if self-tests passed. */ 1145 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1146 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1147 return(ENODEV); 1148 } 1149 1150 /* Halt the CPU. */ 1151 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1152 1153 /* Figure out the hardware revision. */ 1154 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1155 case TI_REV_TIGON_I: 1156 sc->ti_hwrev = TI_HWREV_TIGON; 1157 break; 1158 case TI_REV_TIGON_II: 1159 sc->ti_hwrev = TI_HWREV_TIGON_II; 1160 break; 1161 default: 1162 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1163 return(ENODEV); 1164 } 1165 1166 /* Do special setup for Tigon 2. */ 1167 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1168 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1169 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1170 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1171 } 1172 1173 /* Set up the PCI state register. */ 1174 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1175 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1176 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1177 } 1178 1179 /* Clear the read/write max DMA parameters. */ 1180 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1181 TI_PCISTATE_READ_MAXDMA)); 1182 1183 /* Get cache line size. */ 1184 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1185 1186 /* 1187 * If the system has set enabled the PCI memory write 1188 * and invalidate command in the command register, set 1189 * the write max parameter accordingly. This is necessary 1190 * to use MWI with the Tigon 2. 1191 */ 1192 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1193 switch(cacheline) { 1194 case 1: 1195 case 4: 1196 case 8: 1197 case 16: 1198 case 32: 1199 case 64: 1200 break; 1201 default: 1202 /* Disable PCI memory write and invalidate. */ 1203 if (bootverbose) 1204 printf("ti%d: cache line size %d not " 1205 "supported; disabling PCI MWI\n", 1206 sc->ti_unit, cacheline); 1207 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1208 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1209 break; 1210 } 1211 } 1212 1213#ifdef __brokenalpha__ 1214 /* 1215 * From the Alteon sample driver: 1216 * Must insure that we do not cross an 8K (bytes) boundary 1217 * for DMA reads. Our highest limit is 1K bytes. This is a 1218 * restriction on some ALPHA platforms with early revision 1219 * 21174 PCI chipsets, such as the AlphaPC 164lx 1220 */ 1221 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1222#else 1223 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1224#endif 1225 1226 /* This sets the min dma param all the way up (0xff). */ 1227 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1228 1229 /* Configure DMA variables. */ 1230#if BYTE_ORDER == BIG_ENDIAN 1231 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1232 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1233 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1234 TI_OPMODE_DONT_FRAG_JUMBO); 1235#else 1236 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1237 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1238 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1239#endif 1240 1241 /* 1242 * Only allow 1 DMA channel to be active at a time. 1243 * I don't think this is a good idea, but without it 1244 * the firmware racks up lots of nicDmaReadRingFull 1245 * errors. This is not compatible with hardware checksums. 1246 */ 1247 if (sc->arpcom.ac_if.if_hwassist == 0) 1248 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1249 1250 /* Recommended settings from Tigon manual. */ 1251 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1252 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1253 1254 if (ti_64bitslot_war(sc)) { 1255 printf("ti%d: bios thinks we're in a 64 bit slot, " 1256 "but we aren't", sc->ti_unit); 1257 return(EINVAL); 1258 } 1259 1260 return(0); 1261} 1262 1263/* 1264 * Initialize the general information block and firmware, and 1265 * start the CPU(s) running. 1266 */ 1267static int ti_gibinit(sc) 1268 struct ti_softc *sc; 1269{ 1270 struct ti_rcb *rcb; 1271 int i; 1272 struct ifnet *ifp; 1273 1274 ifp = &sc->arpcom.ac_if; 1275 1276 /* Disable interrupts for now. */ 1277 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1278 1279 /* Tell the chip where to find the general information block. */ 1280 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1281 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1282 1283 /* Load the firmware into SRAM. */ 1284 ti_loadfw(sc); 1285 1286 /* Set up the contents of the general info and ring control blocks. */ 1287 1288 /* Set up the event ring and producer pointer. */ 1289 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1290 1291 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1292 rcb->ti_flags = 0; 1293 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1294 vtophys(&sc->ti_ev_prodidx); 1295 sc->ti_ev_prodidx.ti_idx = 0; 1296 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1297 sc->ti_ev_saved_considx = 0; 1298 1299 /* Set up the command ring and producer mailbox. */ 1300 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1301 1302 sc->ti_rdata->ti_cmd_ring = 1303 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1304 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1305 rcb->ti_flags = 0; 1306 rcb->ti_max_len = 0; 1307 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1308 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1309 } 1310 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1311 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1312 sc->ti_cmd_saved_prodidx = 0; 1313 1314 /* 1315 * Assign the address of the stats refresh buffer. 1316 * We re-use the current stats buffer for this to 1317 * conserve memory. 1318 */ 1319 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1320 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1321 1322 /* Set up the standard receive ring. */ 1323 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1324 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1325 rcb->ti_max_len = TI_FRAMELEN; 1326 rcb->ti_flags = 0; 1327 if (sc->arpcom.ac_if.if_hwassist) 1328 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1329 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1330 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1331 1332 /* Set up the jumbo receive ring. */ 1333 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1334 TI_HOSTADDR(rcb->ti_hostaddr) = 1335 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1336 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1337 rcb->ti_flags = 0; 1338 if (sc->arpcom.ac_if.if_hwassist) 1339 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1340 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1341 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1342 1343 /* 1344 * Set up the mini ring. Only activated on the 1345 * Tigon 2 but the slot in the config block is 1346 * still there on the Tigon 1. 1347 */ 1348 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1349 TI_HOSTADDR(rcb->ti_hostaddr) = 1350 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1351 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1352 if (sc->ti_hwrev == TI_HWREV_TIGON) 1353 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1354 else 1355 rcb->ti_flags = 0; 1356 if (sc->arpcom.ac_if.if_hwassist) 1357 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1358 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1359 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1360 1361 /* 1362 * Set up the receive return ring. 1363 */ 1364 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1365 TI_HOSTADDR(rcb->ti_hostaddr) = 1366 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1367 rcb->ti_flags = 0; 1368 rcb->ti_max_len = TI_RETURN_RING_CNT; 1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1370 vtophys(&sc->ti_return_prodidx); 1371 1372 /* 1373 * Set up the tx ring. Note: for the Tigon 2, we have the option 1374 * of putting the transmit ring in the host's address space and 1375 * letting the chip DMA it instead of leaving the ring in the NIC's 1376 * memory and accessing it through the shared memory region. We 1377 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1378 * so we have to revert to the shared memory scheme if we detect 1379 * a Tigon 1 chip. 1380 */ 1381 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1382 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1383 sc->ti_rdata->ti_tx_ring_nic = 1384 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1385 } 1386 bzero((char *)sc->ti_rdata->ti_tx_ring, 1387 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1388 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1389 if (sc->ti_hwrev == TI_HWREV_TIGON) 1390 rcb->ti_flags = 0; 1391 else 1392 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1393 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1394 if (sc->arpcom.ac_if.if_hwassist) 1395 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1396 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1397 rcb->ti_max_len = TI_TX_RING_CNT; 1398 if (sc->ti_hwrev == TI_HWREV_TIGON) 1399 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1400 else 1401 TI_HOSTADDR(rcb->ti_hostaddr) = 1402 vtophys(&sc->ti_rdata->ti_tx_ring); 1403 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1404 vtophys(&sc->ti_tx_considx); 1405 1406 /* Set up tuneables */ 1407 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1408 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1409 (sc->ti_rx_coal_ticks / 10)); 1410 else 1411 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1412 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1413 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1414 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1415 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1416 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1417 1418 /* Turn interrupts on. */ 1419 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1420 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1421 1422 /* Start CPU. */ 1423 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1424 1425 return(0); 1426} 1427 1428/* 1429 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1430 * against our list and return its name if we find a match. 1431 */ 1432static int ti_probe(dev) 1433 device_t dev; 1434{ 1435 struct ti_type *t; 1436 1437 t = ti_devs; 1438 1439 while(t->ti_name != NULL) { 1440 if ((pci_get_vendor(dev) == t->ti_vid) && 1441 (pci_get_device(dev) == t->ti_did)) { 1442 device_set_desc(dev, t->ti_name); 1443 return(0); 1444 } 1445 t++; 1446 } 1447 1448 return(ENXIO); 1449} 1450 1451static int ti_attach(dev) 1452 device_t dev; 1453{ 1454 u_int32_t command; 1455 struct ifnet *ifp; 1456 struct ti_softc *sc; 1457 int unit, error = 0, rid; 1458 1459 sc = device_get_softc(dev); 1460 unit = device_get_unit(dev); 1461 bzero(sc, sizeof(struct ti_softc)); 1462 1463 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1464 TI_LOCK(sc); 1465 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 1466 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 1467 1468 /* 1469 * Map control/status registers. 1470 */ 1471 pci_enable_busmaster(dev); 1472 pci_enable_io(dev, SYS_RES_MEMORY); 1473 command = pci_read_config(dev, PCIR_COMMAND, 4); 1474 1475 if (!(command & PCIM_CMD_MEMEN)) { 1476 printf("ti%d: failed to enable memory mapping!\n", unit); 1477 error = ENXIO; 1478 goto fail; 1479 } 1480 1481 rid = TI_PCI_LOMEM; 1482 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1483 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1484 1485 if (sc->ti_res == NULL) { 1486 printf ("ti%d: couldn't map memory\n", unit); 1487 error = ENXIO; 1488 goto fail; 1489 } 1490 1491 sc->ti_btag = rman_get_bustag(sc->ti_res); 1492 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1493 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1494 1495 /* Allocate interrupt */ 1496 rid = 0; 1497 1498 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1499 RF_SHAREABLE | RF_ACTIVE); 1500 1501 if (sc->ti_irq == NULL) { 1502 printf("ti%d: couldn't map interrupt\n", unit); 1503 error = ENXIO; 1504 goto fail; 1505 } 1506 1507 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1508 ti_intr, sc, &sc->ti_intrhand); 1509 1510 if (error) { 1511 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1512 bus_release_resource(dev, SYS_RES_MEMORY, 1513 TI_PCI_LOMEM, sc->ti_res); 1514 printf("ti%d: couldn't set up irq\n", unit); 1515 goto fail; 1516 } 1517 1518 sc->ti_unit = unit; 1519 1520 if (ti_chipinit(sc)) { 1521 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1522 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1523 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1524 bus_release_resource(dev, SYS_RES_MEMORY, 1525 TI_PCI_LOMEM, sc->ti_res); 1526 error = ENXIO; 1527 goto fail; 1528 } 1529 1530 /* Zero out the NIC's on-board SRAM. */ 1531 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1532 1533 /* Init again -- zeroing memory may have clobbered some registers. */ 1534 if (ti_chipinit(sc)) { 1535 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1536 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1537 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1538 bus_release_resource(dev, SYS_RES_MEMORY, 1539 TI_PCI_LOMEM, sc->ti_res); 1540 error = ENXIO; 1541 goto fail; 1542 } 1543 1544 /* 1545 * Get station address from the EEPROM. Note: the manual states 1546 * that the MAC address is at offset 0x8c, however the data is 1547 * stored as two longwords (since that's how it's loaded into 1548 * the NIC). This means the MAC address is actually preceded 1549 * by two zero bytes. We need to skip over those. 1550 */ 1551 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1552 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1553 printf("ti%d: failed to read station address\n", unit); 1554 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1555 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1556 bus_release_resource(dev, SYS_RES_MEMORY, 1557 TI_PCI_LOMEM, sc->ti_res); 1558 error = ENXIO; 1559 goto fail; 1560 } 1561 1562 /* 1563 * A Tigon chip was detected. Inform the world. 1564 */ 1565 printf("ti%d: Ethernet address: %6D\n", unit, 1566 sc->arpcom.ac_enaddr, ":"); 1567 1568 /* Allocate the general information block and ring buffers. */ 1569 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1570 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1571 1572 if (sc->ti_rdata == NULL) { 1573 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1574 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1575 bus_release_resource(dev, SYS_RES_MEMORY, 1576 TI_PCI_LOMEM, sc->ti_res); 1577 error = ENXIO; 1578 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1579 goto fail; 1580 } 1581 1582 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1583 1584 /* Try to allocate memory for jumbo buffers. */ 1585 if (ti_alloc_jumbo_mem(sc)) { 1586 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1587 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1589 bus_release_resource(dev, SYS_RES_MEMORY, 1590 TI_PCI_LOMEM, sc->ti_res); 1591 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1592 M_DEVBUF); 1593 error = ENXIO; 1594 goto fail; 1595 } 1596 1597 /* 1598 * We really need a better way to tell a 1000baseTX card 1599 * from a 1000baseSX one, since in theory there could be 1600 * OEMed 1000baseTX cards from lame vendors who aren't 1601 * clever enough to change the PCI ID. For the moment 1602 * though, the AceNIC is the only copper card available. 1603 */ 1604 if (pci_get_vendor(dev) == ALT_VENDORID && 1605 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1606 sc->ti_copper = 1; 1607 /* Ok, it's not the only copper card available. */ 1608 if (pci_get_vendor(dev) == NG_VENDORID && 1609 pci_get_device(dev) == NG_DEVICEID_GA620T) 1610 sc->ti_copper = 1; 1611 1612 /* Set default tuneable values. */ 1613 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1614 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1615 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1616 sc->ti_rx_max_coal_bds = 64; 1617 sc->ti_tx_max_coal_bds = 128; 1618 sc->ti_tx_buf_ratio = 21; 1619 1620 /* Set up ifnet structure */ 1621 ifp = &sc->arpcom.ac_if; 1622 ifp->if_softc = sc; 1623 ifp->if_unit = sc->ti_unit; 1624 ifp->if_name = "ti"; 1625 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1626 ifp->if_ioctl = ti_ioctl; 1627 ifp->if_output = ether_output; 1628 ifp->if_start = ti_start; 1629 ifp->if_watchdog = ti_watchdog; 1630 ifp->if_init = ti_init; 1631 ifp->if_mtu = ETHERMTU; 1632 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1633 1634 /* Set up ifmedia support. */ 1635 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1636 if (sc->ti_copper) { 1637 /* 1638 * Copper cards allow manual 10/100 mode selection, 1639 * but not manual 1000baseTX mode selection. Why? 1640 * Becuase currently there's no way to specify the 1641 * master/slave setting through the firmware interface, 1642 * so Alteon decided to just bag it and handle it 1643 * via autonegotiation. 1644 */ 1645 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1646 ifmedia_add(&sc->ifmedia, 1647 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1648 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1649 ifmedia_add(&sc->ifmedia, 1650 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1651 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1652 ifmedia_add(&sc->ifmedia, 1653 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1654 } else { 1655 /* Fiber cards don't support 10/100 modes. */ 1656 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1657 ifmedia_add(&sc->ifmedia, 1658 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1659 } 1660 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1661 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1662 1663 /* 1664 * Call MI attach routine. 1665 */ 1666 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1667 TI_UNLOCK(sc); 1668 return(0); 1669 1670fail: 1671 TI_UNLOCK(sc); 1672 mtx_destroy(&sc->ti_mtx); 1673 return(error); 1674} 1675 1676static int ti_detach(dev) 1677 device_t dev; 1678{ 1679 struct ti_softc *sc; 1680 struct ifnet *ifp; 1681 1682 1683 sc = device_get_softc(dev); 1684 TI_LOCK(sc); 1685 ifp = &sc->arpcom.ac_if; 1686 1687 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1688 ti_stop(sc); 1689 1690 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1691 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1692 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1693 1694 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1695 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1696 ifmedia_removeall(&sc->ifmedia); 1697 1698 TI_UNLOCK(sc); 1699 mtx_destroy(&sc->ti_mtx); 1700 1701 return(0); 1702} 1703 1704/* 1705 * Frame reception handling. This is called if there's a frame 1706 * on the receive return list. 1707 * 1708 * Note: we have to be able to handle three possibilities here: 1709 * 1) the frame is from the mini receive ring (can only happen) 1710 * on Tigon 2 boards) 1711 * 2) the frame is from the jumbo recieve ring 1712 * 3) the frame is from the standard receive ring 1713 */ 1714 1715static void ti_rxeof(sc) 1716 struct ti_softc *sc; 1717{ 1718 struct ifnet *ifp; 1719 struct ti_cmd_desc cmd; 1720 1721 ifp = &sc->arpcom.ac_if; 1722 1723 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1724 struct ti_rx_desc *cur_rx; 1725 u_int32_t rxidx; 1726 struct ether_header *eh; 1727 struct mbuf *m = NULL; 1728 u_int16_t vlan_tag = 0; 1729 int have_tag = 0; 1730 1731 cur_rx = 1732 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1733 rxidx = cur_rx->ti_idx; 1734 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1735 1736 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1737 have_tag = 1; 1738 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1739 } 1740 1741 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1742 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1743 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1744 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1745 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1746 ifp->if_ierrors++; 1747 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1748 continue; 1749 } 1750 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1751 ifp->if_ierrors++; 1752 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1753 continue; 1754 } 1755 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1756 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1757 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1758 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1759 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1760 ifp->if_ierrors++; 1761 ti_newbuf_mini(sc, sc->ti_mini, m); 1762 continue; 1763 } 1764 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1765 ifp->if_ierrors++; 1766 ti_newbuf_mini(sc, sc->ti_mini, m); 1767 continue; 1768 } 1769 } else { 1770 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1771 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1772 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1773 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1774 ifp->if_ierrors++; 1775 ti_newbuf_std(sc, sc->ti_std, m); 1776 continue; 1777 } 1778 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1779 ifp->if_ierrors++; 1780 ti_newbuf_std(sc, sc->ti_std, m); 1781 continue; 1782 } 1783 } 1784 1785 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1786 ifp->if_ipackets++; 1787 eh = mtod(m, struct ether_header *); 1788 m->m_pkthdr.rcvif = ifp; 1789 1790 /* Remove header from mbuf and pass it on. */ 1791 m_adj(m, sizeof(struct ether_header)); 1792 1793 if (ifp->if_hwassist) { 1794 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1795 CSUM_DATA_VALID; 1796 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1797 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1798 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1799 } 1800 1801 /* 1802 * If we received a packet with a vlan tag, pass it 1803 * to vlan_input() instead of ether_input(). 1804 */ 1805 if (have_tag) { 1806 VLAN_INPUT_TAG(eh, m, vlan_tag); 1807 have_tag = vlan_tag = 0; 1808 continue; 1809 } 1810 ether_input(ifp, eh, m); 1811 } 1812 1813 /* Only necessary on the Tigon 1. */ 1814 if (sc->ti_hwrev == TI_HWREV_TIGON) 1815 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1816 sc->ti_rx_saved_considx); 1817 1818 TI_UPDATE_STDPROD(sc, sc->ti_std); 1819 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1820 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1821 1822 return; 1823} 1824 1825static void ti_txeof(sc) 1826 struct ti_softc *sc; 1827{ 1828 struct ti_tx_desc *cur_tx = NULL; 1829 struct ifnet *ifp; 1830 1831 ifp = &sc->arpcom.ac_if; 1832 1833 /* 1834 * Go through our tx ring and free mbufs for those 1835 * frames that have been sent. 1836 */ 1837 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1838 u_int32_t idx = 0; 1839 1840 idx = sc->ti_tx_saved_considx; 1841 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1842 if (idx > 383) 1843 CSR_WRITE_4(sc, TI_WINBASE, 1844 TI_TX_RING_BASE + 6144); 1845 else if (idx > 255) 1846 CSR_WRITE_4(sc, TI_WINBASE, 1847 TI_TX_RING_BASE + 4096); 1848 else if (idx > 127) 1849 CSR_WRITE_4(sc, TI_WINBASE, 1850 TI_TX_RING_BASE + 2048); 1851 else 1852 CSR_WRITE_4(sc, TI_WINBASE, 1853 TI_TX_RING_BASE); 1854 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1855 } else 1856 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1857 if (cur_tx->ti_flags & TI_BDFLAG_END) 1858 ifp->if_opackets++; 1859 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1860 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1861 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1862 } 1863 sc->ti_txcnt--; 1864 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1865 ifp->if_timer = 0; 1866 } 1867 1868 if (cur_tx != NULL) 1869 ifp->if_flags &= ~IFF_OACTIVE; 1870 1871 return; 1872} 1873 1874static void ti_intr(xsc) 1875 void *xsc; 1876{ 1877 struct ti_softc *sc; 1878 struct ifnet *ifp; 1879 1880 sc = xsc; 1881 TI_LOCK(sc); 1882 ifp = &sc->arpcom.ac_if; 1883 1884#ifdef notdef 1885 /* Avoid this for now -- checking this register is expensive. */ 1886 /* Make sure this is really our interrupt. */ 1887 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 1888 TI_UNLOCK(sc); 1889 return; 1890 } 1891#endif 1892 1893 /* Ack interrupt and stop others from occuring. */ 1894 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1895 1896 if (ifp->if_flags & IFF_RUNNING) { 1897 /* Check RX return ring producer/consumer */ 1898 ti_rxeof(sc); 1899 1900 /* Check TX ring producer/consumer */ 1901 ti_txeof(sc); 1902 } 1903 1904 ti_handle_events(sc); 1905 1906 /* Re-enable interrupts. */ 1907 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1908 1909 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1910 ti_start(ifp); 1911 1912 TI_UNLOCK(sc); 1913 1914 return; 1915} 1916 1917static void ti_stats_update(sc) 1918 struct ti_softc *sc; 1919{ 1920 struct ifnet *ifp; 1921 1922 ifp = &sc->arpcom.ac_if; 1923 1924 ifp->if_collisions += 1925 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1926 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1927 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1928 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1929 ifp->if_collisions; 1930 1931 return; 1932} 1933 1934/* 1935 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1936 * pointers to descriptors. 1937 */ 1938static int ti_encap(sc, m_head, txidx) 1939 struct ti_softc *sc; 1940 struct mbuf *m_head; 1941 u_int32_t *txidx; 1942{ 1943 struct ti_tx_desc *f = NULL; 1944 struct mbuf *m; 1945 u_int32_t frag, cur, cnt = 0; 1946 u_int16_t csum_flags = 0; 1947 struct ifvlan *ifv = NULL; 1948 1949 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1950 m_head->m_pkthdr.rcvif != NULL && 1951 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1952 ifv = m_head->m_pkthdr.rcvif->if_softc; 1953 1954 m = m_head; 1955 cur = frag = *txidx; 1956 1957 if (m_head->m_pkthdr.csum_flags) { 1958 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1959 csum_flags |= TI_BDFLAG_IP_CKSUM; 1960 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1961 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1962 if (m_head->m_flags & M_LASTFRAG) 1963 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1964 else if (m_head->m_flags & M_FRAG) 1965 csum_flags |= TI_BDFLAG_IP_FRAG; 1966 } 1967 /* 1968 * Start packing the mbufs in this chain into 1969 * the fragment pointers. Stop when we run out 1970 * of fragments or hit the end of the mbuf chain. 1971 */ 1972 for (m = m_head; m != NULL; m = m->m_next) { 1973 if (m->m_len != 0) { 1974 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1975 if (frag > 383) 1976 CSR_WRITE_4(sc, TI_WINBASE, 1977 TI_TX_RING_BASE + 6144); 1978 else if (frag > 255) 1979 CSR_WRITE_4(sc, TI_WINBASE, 1980 TI_TX_RING_BASE + 4096); 1981 else if (frag > 127) 1982 CSR_WRITE_4(sc, TI_WINBASE, 1983 TI_TX_RING_BASE + 2048); 1984 else 1985 CSR_WRITE_4(sc, TI_WINBASE, 1986 TI_TX_RING_BASE); 1987 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1988 } else 1989 f = &sc->ti_rdata->ti_tx_ring[frag]; 1990 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1991 break; 1992 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1993 f->ti_len = m->m_len; 1994 f->ti_flags = csum_flags; 1995 1996 if (ifv != NULL) { 1997 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1998 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 1999 } else { 2000 f->ti_vlan_tag = 0; 2001 } 2002 2003 /* 2004 * Sanity check: avoid coming within 16 descriptors 2005 * of the end of the ring. 2006 */ 2007 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2008 return(ENOBUFS); 2009 cur = frag; 2010 TI_INC(frag, TI_TX_RING_CNT); 2011 cnt++; 2012 } 2013 } 2014 2015 if (m != NULL) 2016 return(ENOBUFS); 2017 2018 if (frag == sc->ti_tx_saved_considx) 2019 return(ENOBUFS); 2020 2021 if (sc->ti_hwrev == TI_HWREV_TIGON) 2022 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2023 TI_BDFLAG_END; 2024 else 2025 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2026 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2027 sc->ti_txcnt += cnt; 2028 2029 *txidx = frag; 2030 2031 return(0); 2032} 2033 2034/* 2035 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2036 * to the mbuf data regions directly in the transmit descriptors. 2037 */ 2038static void ti_start(ifp) 2039 struct ifnet *ifp; 2040{ 2041 struct ti_softc *sc; 2042 struct mbuf *m_head = NULL; 2043 u_int32_t prodidx = 0; 2044 2045 sc = ifp->if_softc; 2046 TI_LOCK(sc); 2047 2048 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2049 2050 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2051 IF_DEQUEUE(&ifp->if_snd, m_head); 2052 if (m_head == NULL) 2053 break; 2054 2055 /* 2056 * XXX 2057 * safety overkill. If this is a fragmented packet chain 2058 * with delayed TCP/UDP checksums, then only encapsulate 2059 * it if we have enough descriptors to handle the entire 2060 * chain at once. 2061 * (paranoia -- may not actually be needed) 2062 */ 2063 if (m_head->m_flags & M_FIRSTFRAG && 2064 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2065 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2066 m_head->m_pkthdr.csum_data + 16) { 2067 IF_PREPEND(&ifp->if_snd, m_head); 2068 ifp->if_flags |= IFF_OACTIVE; 2069 break; 2070 } 2071 } 2072 2073 /* 2074 * Pack the data into the transmit ring. If we 2075 * don't have room, set the OACTIVE flag and wait 2076 * for the NIC to drain the ring. 2077 */ 2078 if (ti_encap(sc, m_head, &prodidx)) { 2079 IF_PREPEND(&ifp->if_snd, m_head); 2080 ifp->if_flags |= IFF_OACTIVE; 2081 break; 2082 } 2083 2084 /* 2085 * If there's a BPF listener, bounce a copy of this frame 2086 * to him. 2087 */ 2088 if (ifp->if_bpf) 2089 bpf_mtap(ifp, m_head); 2090 } 2091 2092 /* Transmit */ 2093 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2094 2095 /* 2096 * Set a timeout in case the chip goes out to lunch. 2097 */ 2098 ifp->if_timer = 5; 2099 TI_UNLOCK(sc); 2100 2101 return; 2102} 2103 2104static void ti_init(xsc) 2105 void *xsc; 2106{ 2107 struct ti_softc *sc = xsc; 2108 2109 /* Cancel pending I/O and flush buffers. */ 2110 ti_stop(sc); 2111 2112 TI_LOCK(sc); 2113 /* Init the gen info block, ring control blocks and firmware. */ 2114 if (ti_gibinit(sc)) { 2115 printf("ti%d: initialization failure\n", sc->ti_unit); 2116 TI_UNLOCK(sc); 2117 return; 2118 } 2119 2120 TI_UNLOCK(sc); 2121 2122 return; 2123} 2124 2125static void ti_init2(sc) 2126 struct ti_softc *sc; 2127{ 2128 struct ti_cmd_desc cmd; 2129 struct ifnet *ifp; 2130 u_int16_t *m; 2131 struct ifmedia *ifm; 2132 int tmp; 2133 2134 ifp = &sc->arpcom.ac_if; 2135 2136 /* Specify MTU and interface index. */ 2137 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2138 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2139 ETHER_HDR_LEN + ETHER_CRC_LEN); 2140 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2141 2142 /* Load our MAC address. */ 2143 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2144 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2145 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2146 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2147 2148 /* Enable or disable promiscuous mode as needed. */ 2149 if (ifp->if_flags & IFF_PROMISC) { 2150 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2151 } else { 2152 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2153 } 2154 2155 /* Program multicast filter. */ 2156 ti_setmulti(sc); 2157 2158 /* 2159 * If this is a Tigon 1, we should tell the 2160 * firmware to use software packet filtering. 2161 */ 2162 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2163 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2164 } 2165 2166 /* Init RX ring. */ 2167 ti_init_rx_ring_std(sc); 2168 2169 /* Init jumbo RX ring. */ 2170 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2171 ti_init_rx_ring_jumbo(sc); 2172 2173 /* 2174 * If this is a Tigon 2, we can also configure the 2175 * mini ring. 2176 */ 2177 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2178 ti_init_rx_ring_mini(sc); 2179 2180 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2181 sc->ti_rx_saved_considx = 0; 2182 2183 /* Init TX ring. */ 2184 ti_init_tx_ring(sc); 2185 2186 /* Tell firmware we're alive. */ 2187 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2188 2189 /* Enable host interrupts. */ 2190 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2191 2192 ifp->if_flags |= IFF_RUNNING; 2193 ifp->if_flags &= ~IFF_OACTIVE; 2194 2195 /* 2196 * Make sure to set media properly. We have to do this 2197 * here since we have to issue commands in order to set 2198 * the link negotiation and we can't issue commands until 2199 * the firmware is running. 2200 */ 2201 ifm = &sc->ifmedia; 2202 tmp = ifm->ifm_media; 2203 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2204 ti_ifmedia_upd(ifp); 2205 ifm->ifm_media = tmp; 2206 2207 return; 2208} 2209 2210/* 2211 * Set media options. 2212 */ 2213static int ti_ifmedia_upd(ifp) 2214 struct ifnet *ifp; 2215{ 2216 struct ti_softc *sc; 2217 struct ifmedia *ifm; 2218 struct ti_cmd_desc cmd; 2219 2220 sc = ifp->if_softc; 2221 ifm = &sc->ifmedia; 2222 2223 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2224 return(EINVAL); 2225 2226 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2227 case IFM_AUTO: 2228 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2229 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2230 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2231 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2232 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2233 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2234 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2235 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2236 break; 2237 case IFM_1000_SX: 2238 case IFM_1000_TX: 2239 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2240 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2241 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2242 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2243 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2244 } 2245 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2246 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2247 break; 2248 case IFM_100_FX: 2249 case IFM_10_FL: 2250 case IFM_100_TX: 2251 case IFM_10_T: 2252 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2253 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2254 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2255 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2256 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2257 } else { 2258 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2259 } 2260 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2261 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2262 } else { 2263 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2264 } 2265 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2266 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2267 break; 2268 } 2269 2270 return(0); 2271} 2272 2273/* 2274 * Report current media status. 2275 */ 2276static void ti_ifmedia_sts(ifp, ifmr) 2277 struct ifnet *ifp; 2278 struct ifmediareq *ifmr; 2279{ 2280 struct ti_softc *sc; 2281 u_int32_t media = 0; 2282 2283 sc = ifp->if_softc; 2284 2285 ifmr->ifm_status = IFM_AVALID; 2286 ifmr->ifm_active = IFM_ETHER; 2287 2288 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2289 return; 2290 2291 ifmr->ifm_status |= IFM_ACTIVE; 2292 2293 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2294 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2295 if (sc->ti_copper) 2296 ifmr->ifm_active |= IFM_1000_TX; 2297 else 2298 ifmr->ifm_active |= IFM_1000_SX; 2299 if (media & TI_GLNK_FULL_DUPLEX) 2300 ifmr->ifm_active |= IFM_FDX; 2301 else 2302 ifmr->ifm_active |= IFM_HDX; 2303 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2304 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2305 if (sc->ti_copper) { 2306 if (media & TI_LNK_100MB) 2307 ifmr->ifm_active |= IFM_100_TX; 2308 if (media & TI_LNK_10MB) 2309 ifmr->ifm_active |= IFM_10_T; 2310 } else { 2311 if (media & TI_LNK_100MB) 2312 ifmr->ifm_active |= IFM_100_FX; 2313 if (media & TI_LNK_10MB) 2314 ifmr->ifm_active |= IFM_10_FL; 2315 } 2316 if (media & TI_LNK_FULL_DUPLEX) 2317 ifmr->ifm_active |= IFM_FDX; 2318 if (media & TI_LNK_HALF_DUPLEX) 2319 ifmr->ifm_active |= IFM_HDX; 2320 } 2321 2322 return; 2323} 2324 2325static int ti_ioctl(ifp, command, data) 2326 struct ifnet *ifp; 2327 u_long command; 2328 caddr_t data; 2329{ 2330 struct ti_softc *sc = ifp->if_softc; 2331 struct ifreq *ifr = (struct ifreq *) data; 2332 int mask, error = 0; 2333 struct ti_cmd_desc cmd; 2334 2335 TI_LOCK(sc); 2336 2337 switch(command) { 2338 case SIOCSIFADDR: 2339 case SIOCGIFADDR: 2340 error = ether_ioctl(ifp, command, data); 2341 break; 2342 case SIOCSIFMTU: 2343 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2344 error = EINVAL; 2345 else { 2346 ifp->if_mtu = ifr->ifr_mtu; 2347 ti_init(sc); 2348 } 2349 break; 2350 case SIOCSIFFLAGS: 2351 if (ifp->if_flags & IFF_UP) { 2352 /* 2353 * If only the state of the PROMISC flag changed, 2354 * then just use the 'set promisc mode' command 2355 * instead of reinitializing the entire NIC. Doing 2356 * a full re-init means reloading the firmware and 2357 * waiting for it to start up, which may take a 2358 * second or two. 2359 */ 2360 if (ifp->if_flags & IFF_RUNNING && 2361 ifp->if_flags & IFF_PROMISC && 2362 !(sc->ti_if_flags & IFF_PROMISC)) { 2363 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2364 TI_CMD_CODE_PROMISC_ENB, 0); 2365 } else if (ifp->if_flags & IFF_RUNNING && 2366 !(ifp->if_flags & IFF_PROMISC) && 2367 sc->ti_if_flags & IFF_PROMISC) { 2368 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2369 TI_CMD_CODE_PROMISC_DIS, 0); 2370 } else 2371 ti_init(sc); 2372 } else { 2373 if (ifp->if_flags & IFF_RUNNING) { 2374 ti_stop(sc); 2375 } 2376 } 2377 sc->ti_if_flags = ifp->if_flags; 2378 error = 0; 2379 break; 2380 case SIOCADDMULTI: 2381 case SIOCDELMULTI: 2382 if (ifp->if_flags & IFF_RUNNING) { 2383 ti_setmulti(sc); 2384 error = 0; 2385 } 2386 break; 2387 case SIOCSIFMEDIA: 2388 case SIOCGIFMEDIA: 2389 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2390 break; 2391 case SIOCSIFCAP: 2392 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2393 if (mask & IFCAP_HWCSUM) { 2394 if (IFCAP_HWCSUM & ifp->if_capenable) 2395 ifp->if_capenable &= ~IFCAP_HWCSUM; 2396 else 2397 ifp->if_capenable |= IFCAP_HWCSUM; 2398 if (ifp->if_flags & IFF_RUNNING) 2399 ti_init(sc); 2400 } 2401 error = 0; 2402 break; 2403 default: 2404 error = EINVAL; 2405 break; 2406 } 2407 2408 TI_UNLOCK(sc); 2409 2410 return(error); 2411} 2412 2413static void ti_watchdog(ifp) 2414 struct ifnet *ifp; 2415{ 2416 struct ti_softc *sc; 2417 2418 sc = ifp->if_softc; 2419 TI_LOCK(sc); 2420 2421 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2422 ti_stop(sc); 2423 ti_init(sc); 2424 2425 ifp->if_oerrors++; 2426 TI_UNLOCK(sc); 2427 2428 return; 2429} 2430 2431/* 2432 * Stop the adapter and free any mbufs allocated to the 2433 * RX and TX lists. 2434 */ 2435static void ti_stop(sc) 2436 struct ti_softc *sc; 2437{ 2438 struct ifnet *ifp; 2439 struct ti_cmd_desc cmd; 2440 2441 TI_LOCK(sc); 2442 2443 ifp = &sc->arpcom.ac_if; 2444 2445 /* Disable host interrupts. */ 2446 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2447 /* 2448 * Tell firmware we're shutting down. 2449 */ 2450 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2451 2452 /* Halt and reinitialize. */ 2453 ti_chipinit(sc); 2454 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2455 ti_chipinit(sc); 2456 2457 /* Free the RX lists. */ 2458 ti_free_rx_ring_std(sc); 2459 2460 /* Free jumbo RX list. */ 2461 ti_free_rx_ring_jumbo(sc); 2462 2463 /* Free mini RX list. */ 2464 ti_free_rx_ring_mini(sc); 2465 2466 /* Free TX buffers. */ 2467 ti_free_tx_ring(sc); 2468 2469 sc->ti_ev_prodidx.ti_idx = 0; 2470 sc->ti_return_prodidx.ti_idx = 0; 2471 sc->ti_tx_considx.ti_idx = 0; 2472 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2473 2474 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2475 TI_UNLOCK(sc); 2476 2477 return; 2478} 2479 2480/* 2481 * Stop all chip I/O so that the kernel's probe routines don't 2482 * get confused by errant DMAs when rebooting. 2483 */ 2484static void ti_shutdown(dev) 2485 device_t dev; 2486{ 2487 struct ti_softc *sc; 2488 2489 sc = device_get_softc(dev); 2490 TI_LOCK(sc); 2491 ti_chipinit(sc); 2492 TI_UNLOCK(sc); 2493 2494 return; 2495} 2496