if_ti.c revision 63090
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 63090 2000-07-13 22:54:34Z archie $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "vlan.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90#include <sys/queue.h> 91 92#include <net/if.h> 93#include <net/if_arp.h> 94#include <net/ethernet.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97 98#include <net/bpf.h> 99 100#if NVLAN > 0 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103#endif 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/clock.h> /* for DELAY */ 112#include <machine/bus_memio.h> 113#include <machine/bus.h> 114#include <machine/resource.h> 115#include <sys/bus.h> 116#include <sys/rman.h> 117 118#include <pci/pcireg.h> 119#include <pci/pcivar.h> 120 121#include <pci/if_tireg.h> 122#include <pci/ti_fw.h> 123#include <pci/ti_fw2.h> 124 125#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 126 127#if !defined(lint) 128static const char rcsid[] = 129 "$FreeBSD: head/sys/dev/ti/if_ti.c 63090 2000-07-13 22:54:34Z archie $"; 130#endif 131 132/* 133 * Various supported device vendors/types and their names. 134 */ 135 136static struct ti_type ti_devs[] = { 137 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 138 "Alteon AceNIC Gigabit Ethernet" }, 139 { TC_VENDORID, TC_DEVICEID_3C985, 140 "3Com 3c985-SX Gigabit Ethernet" }, 141 { NG_VENDORID, NG_DEVICEID_GA620, 142 "Netgear GA620 Gigabit Ethernet" }, 143 { SGI_VENDORID, SGI_DEVICEID_TIGON, 144 "Silicon Graphics Gigabit Ethernet" }, 145 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 146 "Farallon PN9000SX Gigabit Ethernet" }, 147 { 0, 0, NULL } 148}; 149 150static int ti_probe __P((device_t)); 151static int ti_attach __P((device_t)); 152static int ti_detach __P((device_t)); 153static void ti_txeof __P((struct ti_softc *)); 154static void ti_rxeof __P((struct ti_softc *)); 155 156static void ti_stats_update __P((struct ti_softc *)); 157static int ti_encap __P((struct ti_softc *, struct mbuf *, 158 u_int32_t *)); 159 160static void ti_intr __P((void *)); 161static void ti_start __P((struct ifnet *)); 162static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 163static void ti_init __P((void *)); 164static void ti_init2 __P((struct ti_softc *)); 165static void ti_stop __P((struct ti_softc *)); 166static void ti_watchdog __P((struct ifnet *)); 167static void ti_shutdown __P((device_t)); 168static int ti_ifmedia_upd __P((struct ifnet *)); 169static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 170 171static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 172static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 173 int, u_int8_t *)); 174static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 175 176static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 177static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 178static void ti_setmulti __P((struct ti_softc *)); 179 180static void ti_mem __P((struct ti_softc *, u_int32_t, 181 u_int32_t, caddr_t)); 182static void ti_loadfw __P((struct ti_softc *)); 183static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 184static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 185 caddr_t, int)); 186static void ti_handle_events __P((struct ti_softc *)); 187static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 188static void *ti_jalloc __P((struct ti_softc *)); 189static void ti_jfree __P((caddr_t, u_int)); 190static void ti_jref __P((caddr_t, u_int)); 191static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 192static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 193static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 194static int ti_init_rx_ring_std __P((struct ti_softc *)); 195static void ti_free_rx_ring_std __P((struct ti_softc *)); 196static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 197static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 198static int ti_init_rx_ring_mini __P((struct ti_softc *)); 199static void ti_free_rx_ring_mini __P((struct ti_softc *)); 200static void ti_free_tx_ring __P((struct ti_softc *)); 201static int ti_init_tx_ring __P((struct ti_softc *)); 202 203static int ti_64bitslot_war __P((struct ti_softc *)); 204static int ti_chipinit __P((struct ti_softc *)); 205static int ti_gibinit __P((struct ti_softc *)); 206 207static device_method_t ti_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, ti_probe), 210 DEVMETHOD(device_attach, ti_attach), 211 DEVMETHOD(device_detach, ti_detach), 212 DEVMETHOD(device_shutdown, ti_shutdown), 213 { 0, 0 } 214}; 215 216static driver_t ti_driver = { 217 "ti", 218 ti_methods, 219 sizeof(struct ti_softc) 220}; 221 222static devclass_t ti_devclass; 223 224DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 225 226/* 227 * Send an instruction or address to the EEPROM, check for ACK. 228 */ 229static u_int32_t ti_eeprom_putbyte(sc, byte) 230 struct ti_softc *sc; 231 int byte; 232{ 233 register int i, ack = 0; 234 235 /* 236 * Make sure we're in TX mode. 237 */ 238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Feed in each bit and stobe the clock. 242 */ 243 for (i = 0x80; i; i >>= 1) { 244 if (byte & i) { 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 246 } else { 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } 249 DELAY(1); 250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 251 DELAY(1); 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 } 254 255 /* 256 * Turn off TX mode. 257 */ 258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 259 260 /* 261 * Check for ack. 262 */ 263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 265 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 267 return(ack); 268} 269 270/* 271 * Read a byte of data stored in the EEPROM at address 'addr.' 272 * We have to send two address bytes since the EEPROM can hold 273 * more than 256 bytes of data. 274 */ 275static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 276 struct ti_softc *sc; 277 int addr; 278 u_int8_t *dest; 279{ 280 register int i; 281 u_int8_t byte = 0; 282 283 EEPROM_START; 284 285 /* 286 * Send write control code to EEPROM. 287 */ 288 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 289 printf("ti%d: failed to send write command, status: %x\n", 290 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 291 return(1); 292 } 293 294 /* 295 * Send first byte of address of byte we want to read. 296 */ 297 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 298 printf("ti%d: failed to send address, status: %x\n", 299 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return(1); 301 } 302 /* 303 * Send second byte address of byte we want to read. 304 */ 305 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 306 printf("ti%d: failed to send address, status: %x\n", 307 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 308 return(1); 309 } 310 311 EEPROM_STOP; 312 EEPROM_START; 313 /* 314 * Send read control code to EEPROM. 315 */ 316 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 317 printf("ti%d: failed to send read command, status: %x\n", 318 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 319 return(1); 320 } 321 322 /* 323 * Start reading bits from EEPROM. 324 */ 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 326 for (i = 0x80; i; i >>= 1) { 327 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 328 DELAY(1); 329 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 330 byte |= i; 331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 332 DELAY(1); 333 } 334 335 EEPROM_STOP; 336 337 /* 338 * No ACK generated for read, so just return byte. 339 */ 340 341 *dest = byte; 342 343 return(0); 344} 345 346/* 347 * Read a sequence of bytes from the EEPROM. 348 */ 349static int ti_read_eeprom(sc, dest, off, cnt) 350 struct ti_softc *sc; 351 caddr_t dest; 352 int off; 353 int cnt; 354{ 355 int err = 0, i; 356 u_int8_t byte = 0; 357 358 for (i = 0; i < cnt; i++) { 359 err = ti_eeprom_getbyte(sc, off + i, &byte); 360 if (err) 361 break; 362 *(dest + i) = byte; 363 } 364 365 return(err ? 1 : 0); 366} 367 368/* 369 * NIC memory access function. Can be used to either clear a section 370 * of NIC local memory or (if buf is non-NULL) copy data into it. 371 */ 372static void ti_mem(sc, addr, len, buf) 373 struct ti_softc *sc; 374 u_int32_t addr, len; 375 caddr_t buf; 376{ 377 int segptr, segsize, cnt; 378 caddr_t ti_winbase, ptr; 379 380 segptr = addr; 381 cnt = len; 382 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 383 ptr = buf; 384 385 while(cnt) { 386 if (cnt < TI_WINLEN) 387 segsize = cnt; 388 else 389 segsize = TI_WINLEN - (segptr % TI_WINLEN); 390 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 391 if (buf == NULL) 392 bzero((char *)ti_winbase + (segptr & 393 (TI_WINLEN - 1)), segsize); 394 else { 395 bcopy((char *)ptr, (char *)ti_winbase + 396 (segptr & (TI_WINLEN - 1)), segsize); 397 ptr += segsize; 398 } 399 segptr += segsize; 400 cnt -= segsize; 401 } 402 403 return; 404} 405 406/* 407 * Load firmware image into the NIC. Check that the firmware revision 408 * is acceptable and see if we want the firmware for the Tigon 1 or 409 * Tigon 2. 410 */ 411static void ti_loadfw(sc) 412 struct ti_softc *sc; 413{ 414 switch(sc->ti_hwrev) { 415 case TI_HWREV_TIGON: 416 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 417 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 418 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 419 printf("ti%d: firmware revision mismatch; want " 420 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 422 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 423 tigonFwReleaseMinor, tigonFwReleaseFix); 424 return; 425 } 426 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 427 (caddr_t)tigonFwText); 428 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 429 (caddr_t)tigonFwData); 430 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 431 (caddr_t)tigonFwRodata); 432 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 433 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 434 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 435 break; 436 case TI_HWREV_TIGON_II: 437 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 438 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 439 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 440 printf("ti%d: firmware revision mismatch; want " 441 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 442 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 443 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 444 tigon2FwReleaseMinor, tigon2FwReleaseFix); 445 return; 446 } 447 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 448 (caddr_t)tigon2FwText); 449 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 450 (caddr_t)tigon2FwData); 451 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 452 (caddr_t)tigon2FwRodata); 453 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 454 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 455 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 456 break; 457 default: 458 printf("ti%d: can't load firmware: unknown hardware rev\n", 459 sc->ti_unit); 460 break; 461 } 462 463 return; 464} 465 466/* 467 * Send the NIC a command via the command ring. 468 */ 469static void ti_cmd(sc, cmd) 470 struct ti_softc *sc; 471 struct ti_cmd_desc *cmd; 472{ 473 u_int32_t index; 474 475 if (sc->ti_rdata->ti_cmd_ring == NULL) 476 return; 477 478 index = sc->ti_cmd_saved_prodidx; 479 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 480 TI_INC(index, TI_CMD_RING_CNT); 481 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 482 sc->ti_cmd_saved_prodidx = index; 483 484 return; 485} 486 487/* 488 * Send the NIC an extended command. The 'len' parameter specifies the 489 * number of command slots to include after the initial command. 490 */ 491static void ti_cmd_ext(sc, cmd, arg, len) 492 struct ti_softc *sc; 493 struct ti_cmd_desc *cmd; 494 caddr_t arg; 495 int len; 496{ 497 u_int32_t index; 498 register int i; 499 500 if (sc->ti_rdata->ti_cmd_ring == NULL) 501 return; 502 503 index = sc->ti_cmd_saved_prodidx; 504 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 505 TI_INC(index, TI_CMD_RING_CNT); 506 for (i = 0; i < len; i++) { 507 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 508 *(u_int32_t *)(&arg[i * 4])); 509 TI_INC(index, TI_CMD_RING_CNT); 510 } 511 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 512 sc->ti_cmd_saved_prodidx = index; 513 514 return; 515} 516 517/* 518 * Handle events that have triggered interrupts. 519 */ 520static void ti_handle_events(sc) 521 struct ti_softc *sc; 522{ 523 struct ti_event_desc *e; 524 525 if (sc->ti_rdata->ti_event_ring == NULL) 526 return; 527 528 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 529 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 530 switch(e->ti_event) { 531 case TI_EV_LINKSTAT_CHANGED: 532 sc->ti_linkstat = e->ti_code; 533 if (e->ti_code == TI_EV_CODE_LINK_UP) 534 printf("ti%d: 10/100 link up\n", sc->ti_unit); 535 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 536 printf("ti%d: gigabit link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 538 printf("ti%d: link down\n", sc->ti_unit); 539 break; 540 case TI_EV_ERROR: 541 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 542 printf("ti%d: invalid command\n", sc->ti_unit); 543 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 544 printf("ti%d: unknown command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 546 printf("ti%d: bad config data\n", sc->ti_unit); 547 break; 548 case TI_EV_FIRMWARE_UP: 549 ti_init2(sc); 550 break; 551 case TI_EV_STATS_UPDATED: 552 ti_stats_update(sc); 553 break; 554 case TI_EV_RESET_JUMBO_RING: 555 case TI_EV_MCAST_UPDATED: 556 /* Who cares. */ 557 break; 558 default: 559 printf("ti%d: unknown event: %d\n", 560 sc->ti_unit, e->ti_event); 561 break; 562 } 563 /* Advance the consumer index. */ 564 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 565 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 566 } 567 568 return; 569} 570 571/* 572 * Memory management for the jumbo receive ring is a pain in the 573 * butt. We need to allocate at least 9018 bytes of space per frame, 574 * _and_ it has to be contiguous (unless you use the extended 575 * jumbo descriptor format). Using malloc() all the time won't 576 * work: malloc() allocates memory in powers of two, which means we 577 * would end up wasting a considerable amount of space by allocating 578 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 579 * to do our own memory management. 580 * 581 * The driver needs to allocate a contiguous chunk of memory at boot 582 * time. We then chop this up ourselves into 9K pieces and use them 583 * as external mbuf storage. 584 * 585 * One issue here is how much memory to allocate. The jumbo ring has 586 * 256 slots in it, but at 9K per slot than can consume over 2MB of 587 * RAM. This is a bit much, especially considering we also need 588 * RAM for the standard ring and mini ring (on the Tigon 2). To 589 * save space, we only actually allocate enough memory for 64 slots 590 * by default, which works out to between 500 and 600K. This can 591 * be tuned by changing a #define in if_tireg.h. 592 */ 593 594static int ti_alloc_jumbo_mem(sc) 595 struct ti_softc *sc; 596{ 597 caddr_t ptr; 598 register int i; 599 struct ti_jpool_entry *entry; 600 601 /* Grab a big chunk o' storage. */ 602 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 603 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 604 605 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 606 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 607 return(ENOBUFS); 608 } 609 610 SLIST_INIT(&sc->ti_jfree_listhead); 611 SLIST_INIT(&sc->ti_jinuse_listhead); 612 613 /* 614 * Now divide it up into 9K pieces and save the addresses 615 * in an array. Note that we play an evil trick here by using 616 * the first few bytes in the buffer to hold the the address 617 * of the softc structure for this interface. This is because 618 * ti_jfree() needs it, but it is called by the mbuf management 619 * code which will not pass it to us explicitly. 620 */ 621 ptr = sc->ti_cdata.ti_jumbo_buf; 622 for (i = 0; i < TI_JSLOTS; i++) { 623 u_int64_t **aptr; 624 aptr = (u_int64_t **)ptr; 625 aptr[0] = (u_int64_t *)sc; 626 ptr += sizeof(u_int64_t); 627 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 628 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 629 ptr += (TI_JLEN - sizeof(u_int64_t)); 630 entry = malloc(sizeof(struct ti_jpool_entry), 631 M_DEVBUF, M_NOWAIT); 632 if (entry == NULL) { 633 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 634 M_DEVBUF); 635 sc->ti_cdata.ti_jumbo_buf = NULL; 636 printf("ti%d: no memory for jumbo " 637 "buffer queue!\n", sc->ti_unit); 638 return(ENOBUFS); 639 } 640 entry->slot = i; 641 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 642 } 643 644 return(0); 645} 646 647/* 648 * Allocate a jumbo buffer. 649 */ 650static void *ti_jalloc(sc) 651 struct ti_softc *sc; 652{ 653 struct ti_jpool_entry *entry; 654 655 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 656 657 if (entry == NULL) { 658 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 659 return(NULL); 660 } 661 662 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 663 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 664 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 665 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 666} 667 668/* 669 * Adjust usage count on a jumbo buffer. In general this doesn't 670 * get used much because our jumbo buffers don't get passed around 671 * too much, but it's implemented for correctness. 672 */ 673static void ti_jref(buf, size) 674 caddr_t buf; 675 u_int size; 676{ 677 struct ti_softc *sc; 678 u_int64_t **aptr; 679 register int i; 680 681 /* Extract the softc struct pointer. */ 682 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 683 sc = (struct ti_softc *)(aptr[0]); 684 685 if (sc == NULL) 686 panic("ti_jref: can't find softc pointer!"); 687 688 if (size != TI_JUMBO_FRAMELEN) 689 panic("ti_jref: adjusting refcount of buf of wrong size!"); 690 691 /* calculate the slot this buffer belongs to */ 692 693 i = ((vm_offset_t)aptr 694 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 695 696 if ((i < 0) || (i >= TI_JSLOTS)) 697 panic("ti_jref: asked to reference buffer " 698 "that we don't manage!"); 699 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 700 panic("ti_jref: buffer already free!"); 701 else 702 sc->ti_cdata.ti_jslots[i].ti_inuse++; 703 704 return; 705} 706 707/* 708 * Release a jumbo buffer. 709 */ 710static void ti_jfree(buf, size) 711 caddr_t buf; 712 u_int size; 713{ 714 struct ti_softc *sc; 715 u_int64_t **aptr; 716 int i; 717 struct ti_jpool_entry *entry; 718 719 /* Extract the softc struct pointer. */ 720 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 721 sc = (struct ti_softc *)(aptr[0]); 722 723 if (sc == NULL) 724 panic("ti_jfree: can't find softc pointer!"); 725 726 if (size != TI_JUMBO_FRAMELEN) 727 panic("ti_jfree: freeing buffer of wrong size!"); 728 729 /* calculate the slot this buffer belongs to */ 730 731 i = ((vm_offset_t)aptr 732 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 733 734 if ((i < 0) || (i >= TI_JSLOTS)) 735 panic("ti_jfree: asked to free buffer that we don't manage!"); 736 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 737 panic("ti_jfree: buffer already free!"); 738 else { 739 sc->ti_cdata.ti_jslots[i].ti_inuse--; 740 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 741 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 742 if (entry == NULL) 743 panic("ti_jfree: buffer not in use!"); 744 entry->slot = i; 745 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 746 jpool_entries); 747 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 748 entry, jpool_entries); 749 } 750 } 751 752 return; 753} 754 755 756/* 757 * Intialize a standard receive ring descriptor. 758 */ 759static int ti_newbuf_std(sc, i, m) 760 struct ti_softc *sc; 761 int i; 762 struct mbuf *m; 763{ 764 struct mbuf *m_new = NULL; 765 struct ti_rx_desc *r; 766 767 if (m == NULL) { 768 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 769 if (m_new == NULL) { 770 printf("ti%d: mbuf allocation failed " 771 "-- packet dropped!\n", sc->ti_unit); 772 return(ENOBUFS); 773 } 774 775 MCLGET(m_new, M_DONTWAIT); 776 if (!(m_new->m_flags & M_EXT)) { 777 printf("ti%d: cluster allocation failed " 778 "-- packet dropped!\n", sc->ti_unit); 779 m_freem(m_new); 780 return(ENOBUFS); 781 } 782 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 783 } else { 784 m_new = m; 785 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 786 m_new->m_data = m_new->m_ext.ext_buf; 787 } 788 789 m_adj(m_new, ETHER_ALIGN); 790 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 791 r = &sc->ti_rdata->ti_rx_std_ring[i]; 792 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 793 r->ti_type = TI_BDTYPE_RECV_BD; 794 r->ti_flags = 0; 795 if (sc->arpcom.ac_if.if_hwassist) 796 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 797 r->ti_len = m_new->m_len; 798 r->ti_idx = i; 799 800 return(0); 801} 802 803/* 804 * Intialize a mini receive ring descriptor. This only applies to 805 * the Tigon 2. 806 */ 807static int ti_newbuf_mini(sc, i, m) 808 struct ti_softc *sc; 809 int i; 810 struct mbuf *m; 811{ 812 struct mbuf *m_new = NULL; 813 struct ti_rx_desc *r; 814 815 if (m == NULL) { 816 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 817 if (m_new == NULL) { 818 printf("ti%d: mbuf allocation failed " 819 "-- packet dropped!\n", sc->ti_unit); 820 return(ENOBUFS); 821 } 822 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 823 } else { 824 m_new = m; 825 m_new->m_data = m_new->m_pktdat; 826 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 827 } 828 829 m_adj(m_new, ETHER_ALIGN); 830 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 831 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 832 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 833 r->ti_type = TI_BDTYPE_RECV_BD; 834 r->ti_flags = TI_BDFLAG_MINI_RING; 835 if (sc->arpcom.ac_if.if_hwassist) 836 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 837 r->ti_len = m_new->m_len; 838 r->ti_idx = i; 839 840 return(0); 841} 842 843/* 844 * Initialize a jumbo receive ring descriptor. This allocates 845 * a jumbo buffer from the pool managed internally by the driver. 846 */ 847static int ti_newbuf_jumbo(sc, i, m) 848 struct ti_softc *sc; 849 int i; 850 struct mbuf *m; 851{ 852 struct mbuf *m_new = NULL; 853 struct ti_rx_desc *r; 854 855 if (m == NULL) { 856 caddr_t *buf = NULL; 857 858 /* Allocate the mbuf. */ 859 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 860 if (m_new == NULL) { 861 printf("ti%d: mbuf allocation failed " 862 "-- packet dropped!\n", sc->ti_unit); 863 return(ENOBUFS); 864 } 865 866 /* Allocate the jumbo buffer */ 867 buf = ti_jalloc(sc); 868 if (buf == NULL) { 869 m_freem(m_new); 870 printf("ti%d: jumbo allocation failed " 871 "-- packet dropped!\n", sc->ti_unit); 872 return(ENOBUFS); 873 } 874 875 /* Attach the buffer to the mbuf. */ 876 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 877 m_new->m_flags |= M_EXT; 878 m_new->m_len = m_new->m_pkthdr.len = 879 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 880 m_new->m_ext.ext_free = ti_jfree; 881 m_new->m_ext.ext_ref = ti_jref; 882 } else { 883 m_new = m; 884 m_new->m_data = m_new->m_ext.ext_buf; 885 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 886 } 887 888 m_adj(m_new, ETHER_ALIGN); 889 /* Set up the descriptor. */ 890 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 891 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 892 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 893 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 894 r->ti_flags = TI_BDFLAG_JUMBO_RING; 895 if (sc->arpcom.ac_if.if_hwassist) 896 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 897 r->ti_len = m_new->m_len; 898 r->ti_idx = i; 899 900 return(0); 901} 902 903/* 904 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 905 * that's 1MB or memory, which is a lot. For now, we fill only the first 906 * 256 ring entries and hope that our CPU is fast enough to keep up with 907 * the NIC. 908 */ 909static int ti_init_rx_ring_std(sc) 910 struct ti_softc *sc; 911{ 912 register int i; 913 struct ti_cmd_desc cmd; 914 915 for (i = 0; i < TI_SSLOTS; i++) { 916 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 917 return(ENOBUFS); 918 }; 919 920 TI_UPDATE_STDPROD(sc, i - 1); 921 sc->ti_std = i - 1; 922 923 return(0); 924} 925 926static void ti_free_rx_ring_std(sc) 927 struct ti_softc *sc; 928{ 929 register int i; 930 931 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 932 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 933 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 934 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 935 } 936 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 937 sizeof(struct ti_rx_desc)); 938 } 939 940 return; 941} 942 943static int ti_init_rx_ring_jumbo(sc) 944 struct ti_softc *sc; 945{ 946 register int i; 947 struct ti_cmd_desc cmd; 948 949 for (i = 0; i < (TI_JSLOTS - 20); i++) { 950 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 951 return(ENOBUFS); 952 }; 953 954 TI_UPDATE_JUMBOPROD(sc, i - 1); 955 sc->ti_jumbo = i - 1; 956 957 return(0); 958} 959 960static void ti_free_rx_ring_jumbo(sc) 961 struct ti_softc *sc; 962{ 963 register int i; 964 965 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 966 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 967 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 968 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 969 } 970 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 971 sizeof(struct ti_rx_desc)); 972 } 973 974 return; 975} 976 977static int ti_init_rx_ring_mini(sc) 978 struct ti_softc *sc; 979{ 980 register int i; 981 982 for (i = 0; i < TI_MSLOTS; i++) { 983 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 984 return(ENOBUFS); 985 }; 986 987 TI_UPDATE_MINIPROD(sc, i - 1); 988 sc->ti_mini = i - 1; 989 990 return(0); 991} 992 993static void ti_free_rx_ring_mini(sc) 994 struct ti_softc *sc; 995{ 996 register int i; 997 998 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 999 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1000 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1001 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1002 } 1003 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1004 sizeof(struct ti_rx_desc)); 1005 } 1006 1007 return; 1008} 1009 1010static void ti_free_tx_ring(sc) 1011 struct ti_softc *sc; 1012{ 1013 register int i; 1014 1015 if (sc->ti_rdata->ti_tx_ring == NULL) 1016 return; 1017 1018 for (i = 0; i < TI_TX_RING_CNT; i++) { 1019 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1020 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1021 sc->ti_cdata.ti_tx_chain[i] = NULL; 1022 } 1023 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1024 sizeof(struct ti_tx_desc)); 1025 } 1026 1027 return; 1028} 1029 1030static int ti_init_tx_ring(sc) 1031 struct ti_softc *sc; 1032{ 1033 sc->ti_txcnt = 0; 1034 sc->ti_tx_saved_considx = 0; 1035 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1036 return(0); 1037} 1038 1039/* 1040 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1041 * but we have to support the old way too so that Tigon 1 cards will 1042 * work. 1043 */ 1044void ti_add_mcast(sc, addr) 1045 struct ti_softc *sc; 1046 struct ether_addr *addr; 1047{ 1048 struct ti_cmd_desc cmd; 1049 u_int16_t *m; 1050 u_int32_t ext[2] = {0, 0}; 1051 1052 m = (u_int16_t *)&addr->octet[0]; 1053 1054 switch(sc->ti_hwrev) { 1055 case TI_HWREV_TIGON: 1056 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1057 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1058 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1059 break; 1060 case TI_HWREV_TIGON_II: 1061 ext[0] = htons(m[0]); 1062 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1063 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1064 break; 1065 default: 1066 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1067 break; 1068 } 1069 1070 return; 1071} 1072 1073void ti_del_mcast(sc, addr) 1074 struct ti_softc *sc; 1075 struct ether_addr *addr; 1076{ 1077 struct ti_cmd_desc cmd; 1078 u_int16_t *m; 1079 u_int32_t ext[2] = {0, 0}; 1080 1081 m = (u_int16_t *)&addr->octet[0]; 1082 1083 switch(sc->ti_hwrev) { 1084 case TI_HWREV_TIGON: 1085 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1086 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1087 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1088 break; 1089 case TI_HWREV_TIGON_II: 1090 ext[0] = htons(m[0]); 1091 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1092 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1093 break; 1094 default: 1095 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1096 break; 1097 } 1098 1099 return; 1100} 1101 1102/* 1103 * Configure the Tigon's multicast address filter. 1104 * 1105 * The actual multicast table management is a bit of a pain, thanks to 1106 * slight brain damage on the part of both Alteon and us. With our 1107 * multicast code, we are only alerted when the multicast address table 1108 * changes and at that point we only have the current list of addresses: 1109 * we only know the current state, not the previous state, so we don't 1110 * actually know what addresses were removed or added. The firmware has 1111 * state, but we can't get our grubby mits on it, and there is no 'delete 1112 * all multicast addresses' command. Hence, we have to maintain our own 1113 * state so we know what addresses have been programmed into the NIC at 1114 * any given time. 1115 */ 1116static void ti_setmulti(sc) 1117 struct ti_softc *sc; 1118{ 1119 struct ifnet *ifp; 1120 struct ifmultiaddr *ifma; 1121 struct ti_cmd_desc cmd; 1122 struct ti_mc_entry *mc; 1123 u_int32_t intrs; 1124 1125 ifp = &sc->arpcom.ac_if; 1126 1127 if (ifp->if_flags & IFF_ALLMULTI) { 1128 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1129 return; 1130 } else { 1131 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1132 } 1133 1134 /* Disable interrupts. */ 1135 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1136 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1137 1138 /* First, zot all the existing filters. */ 1139 while (sc->ti_mc_listhead.slh_first != NULL) { 1140 mc = sc->ti_mc_listhead.slh_first; 1141 ti_del_mcast(sc, &mc->mc_addr); 1142 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1143 free(mc, M_DEVBUF); 1144 } 1145 1146 /* Now program new ones. */ 1147 for (ifma = ifp->if_multiaddrs.lh_first; 1148 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1149 if (ifma->ifma_addr->sa_family != AF_LINK) 1150 continue; 1151 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1152 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1153 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1154 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1155 ti_add_mcast(sc, &mc->mc_addr); 1156 } 1157 1158 /* Re-enable interrupts. */ 1159 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1160 1161 return; 1162} 1163 1164/* 1165 * Check to see if the BIOS has configured us for a 64 bit slot when 1166 * we aren't actually in one. If we detect this condition, we can work 1167 * around it on the Tigon 2 by setting a bit in the PCI state register, 1168 * but for the Tigon 1 we must give up and abort the interface attach. 1169 */ 1170static int ti_64bitslot_war(sc) 1171 struct ti_softc *sc; 1172{ 1173 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1174 CSR_WRITE_4(sc, 0x600, 0); 1175 CSR_WRITE_4(sc, 0x604, 0); 1176 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1177 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1178 if (sc->ti_hwrev == TI_HWREV_TIGON) 1179 return(EINVAL); 1180 else { 1181 TI_SETBIT(sc, TI_PCI_STATE, 1182 TI_PCISTATE_32BIT_BUS); 1183 return(0); 1184 } 1185 } 1186 } 1187 1188 return(0); 1189} 1190 1191/* 1192 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1193 * self-test results. 1194 */ 1195static int ti_chipinit(sc) 1196 struct ti_softc *sc; 1197{ 1198 u_int32_t cacheline; 1199 u_int32_t pci_writemax = 0; 1200 1201 /* Initialize link to down state. */ 1202 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1203 1204 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1205 1206 /* Set endianness before we access any non-PCI registers. */ 1207#if BYTE_ORDER == BIG_ENDIAN 1208 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1209 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1210#else 1211 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1212 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1213#endif 1214 1215 /* Check the ROM failed bit to see if self-tests passed. */ 1216 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1217 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1218 return(ENODEV); 1219 } 1220 1221 /* Halt the CPU. */ 1222 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1223 1224 /* Figure out the hardware revision. */ 1225 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1226 case TI_REV_TIGON_I: 1227 sc->ti_hwrev = TI_HWREV_TIGON; 1228 break; 1229 case TI_REV_TIGON_II: 1230 sc->ti_hwrev = TI_HWREV_TIGON_II; 1231 break; 1232 default: 1233 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1234 return(ENODEV); 1235 } 1236 1237 /* Do special setup for Tigon 2. */ 1238 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1239 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1241 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1242 } 1243 1244 /* Set up the PCI state register. */ 1245 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1246 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1247 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1248 } 1249 1250 /* Clear the read/write max DMA parameters. */ 1251 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1252 TI_PCISTATE_READ_MAXDMA)); 1253 1254 /* Get cache line size. */ 1255 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1256 1257 /* 1258 * If the system has set enabled the PCI memory write 1259 * and invalidate command in the command register, set 1260 * the write max parameter accordingly. This is necessary 1261 * to use MWI with the Tigon 2. 1262 */ 1263 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1264 switch(cacheline) { 1265 case 1: 1266 case 4: 1267 case 8: 1268 case 16: 1269 case 32: 1270 case 64: 1271 break; 1272 default: 1273 /* Disable PCI memory write and invalidate. */ 1274 if (bootverbose) 1275 printf("ti%d: cache line size %d not " 1276 "supported; disabling PCI MWI\n", 1277 sc->ti_unit, cacheline); 1278 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1279 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1280 break; 1281 } 1282 } 1283 1284#ifdef __brokenalpha__ 1285 /* 1286 * From the Alteon sample driver: 1287 * Must insure that we do not cross an 8K (bytes) boundary 1288 * for DMA reads. Our highest limit is 1K bytes. This is a 1289 * restriction on some ALPHA platforms with early revision 1290 * 21174 PCI chipsets, such as the AlphaPC 164lx 1291 */ 1292 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1293#else 1294 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1295#endif 1296 1297 /* This sets the min dma param all the way up (0xff). */ 1298 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1299 1300 /* Configure DMA variables. */ 1301#if BYTE_ORDER == BIG_ENDIAN 1302 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1303 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1304 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1305 TI_OPMODE_DONT_FRAG_JUMBO); 1306#else 1307 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1308 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1309 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1310#endif 1311 1312 /* 1313 * Only allow 1 DMA channel to be active at a time. 1314 * I don't think this is a good idea, but without it 1315 * the firmware racks up lots of nicDmaReadRingFull 1316 * errors. This is not compatible with hardware checksums. 1317 */ 1318 if (sc->arpcom.ac_if.if_hwassist == 0) 1319 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1320 1321 /* Recommended settings from Tigon manual. */ 1322 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1323 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1324 1325 if (ti_64bitslot_war(sc)) { 1326 printf("ti%d: bios thinks we're in a 64 bit slot, " 1327 "but we aren't", sc->ti_unit); 1328 return(EINVAL); 1329 } 1330 1331 return(0); 1332} 1333 1334/* 1335 * Initialize the general information block and firmware, and 1336 * start the CPU(s) running. 1337 */ 1338static int ti_gibinit(sc) 1339 struct ti_softc *sc; 1340{ 1341 struct ti_rcb *rcb; 1342 int i; 1343 struct ifnet *ifp; 1344 1345 ifp = &sc->arpcom.ac_if; 1346 1347 /* Disable interrupts for now. */ 1348 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1349 1350 /* Tell the chip where to find the general information block. */ 1351 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1352 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1353 1354 /* Load the firmware into SRAM. */ 1355 ti_loadfw(sc); 1356 1357 /* Set up the contents of the general info and ring control blocks. */ 1358 1359 /* Set up the event ring and producer pointer. */ 1360 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1361 1362 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1363 rcb->ti_flags = 0; 1364 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1365 vtophys(&sc->ti_ev_prodidx); 1366 sc->ti_ev_prodidx.ti_idx = 0; 1367 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1368 sc->ti_ev_saved_considx = 0; 1369 1370 /* Set up the command ring and producer mailbox. */ 1371 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1372 1373 sc->ti_rdata->ti_cmd_ring = 1374 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1375 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1376 rcb->ti_flags = 0; 1377 rcb->ti_max_len = 0; 1378 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1379 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1380 } 1381 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1382 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1383 sc->ti_cmd_saved_prodidx = 0; 1384 1385 /* 1386 * Assign the address of the stats refresh buffer. 1387 * We re-use the current stats buffer for this to 1388 * conserve memory. 1389 */ 1390 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1391 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1392 1393 /* Set up the standard receive ring. */ 1394 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1395 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1396 rcb->ti_max_len = TI_FRAMELEN; 1397 rcb->ti_flags = 0; 1398 if (sc->arpcom.ac_if.if_hwassist) 1399 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1400 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1401#if NVLAN > 0 1402 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1403#endif 1404 1405 /* Set up the jumbo receive ring. */ 1406 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1407 TI_HOSTADDR(rcb->ti_hostaddr) = 1408 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1409 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1410 rcb->ti_flags = 0; 1411 if (sc->arpcom.ac_if.if_hwassist) 1412 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1413 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1414#if NVLAN > 0 1415 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1416#endif 1417 1418 /* 1419 * Set up the mini ring. Only activated on the 1420 * Tigon 2 but the slot in the config block is 1421 * still there on the Tigon 1. 1422 */ 1423 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1424 TI_HOSTADDR(rcb->ti_hostaddr) = 1425 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1426 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1427 if (sc->ti_hwrev == TI_HWREV_TIGON) 1428 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1429 else 1430 rcb->ti_flags = 0; 1431 if (sc->arpcom.ac_if.if_hwassist) 1432 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1433 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1434#if NVLAN > 0 1435 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1436#endif 1437 1438 /* 1439 * Set up the receive return ring. 1440 */ 1441 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1442 TI_HOSTADDR(rcb->ti_hostaddr) = 1443 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1444 rcb->ti_flags = 0; 1445 rcb->ti_max_len = TI_RETURN_RING_CNT; 1446 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1447 vtophys(&sc->ti_return_prodidx); 1448 1449 /* 1450 * Set up the tx ring. Note: for the Tigon 2, we have the option 1451 * of putting the transmit ring in the host's address space and 1452 * letting the chip DMA it instead of leaving the ring in the NIC's 1453 * memory and accessing it through the shared memory region. We 1454 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1455 * so we have to revert to the shared memory scheme if we detect 1456 * a Tigon 1 chip. 1457 */ 1458 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1459 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1460 sc->ti_rdata->ti_tx_ring_nic = 1461 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1462 } 1463 bzero((char *)sc->ti_rdata->ti_tx_ring, 1464 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1465 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1466 if (sc->ti_hwrev == TI_HWREV_TIGON) 1467 rcb->ti_flags = 0; 1468 else 1469 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1470#if NVLAN > 0 1471 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1472#endif 1473 if (sc->arpcom.ac_if.if_hwassist) 1474 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1475 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1476 rcb->ti_max_len = TI_TX_RING_CNT; 1477 if (sc->ti_hwrev == TI_HWREV_TIGON) 1478 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1479 else 1480 TI_HOSTADDR(rcb->ti_hostaddr) = 1481 vtophys(&sc->ti_rdata->ti_tx_ring); 1482 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1483 vtophys(&sc->ti_tx_considx); 1484 1485 /* Set up tuneables */ 1486 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1487 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1488 (sc->ti_rx_coal_ticks / 10)); 1489 else 1490 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1491 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1492 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1493 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1494 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1495 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1496 1497 /* Turn interrupts on. */ 1498 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1499 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1500 1501 /* Start CPU. */ 1502 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1503 1504 return(0); 1505} 1506 1507/* 1508 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1509 * against our list and return its name if we find a match. 1510 */ 1511static int ti_probe(dev) 1512 device_t dev; 1513{ 1514 struct ti_type *t; 1515 1516 t = ti_devs; 1517 1518 while(t->ti_name != NULL) { 1519 if ((pci_get_vendor(dev) == t->ti_vid) && 1520 (pci_get_device(dev) == t->ti_did)) { 1521 device_set_desc(dev, t->ti_name); 1522 return(0); 1523 } 1524 t++; 1525 } 1526 1527 return(ENXIO); 1528} 1529 1530static int ti_attach(dev) 1531 device_t dev; 1532{ 1533 int s; 1534 u_int32_t command; 1535 struct ifnet *ifp; 1536 struct ti_softc *sc; 1537 int unit, error = 0, rid; 1538 1539 s = splimp(); 1540 1541 sc = device_get_softc(dev); 1542 unit = device_get_unit(dev); 1543 bzero(sc, sizeof(struct ti_softc)); 1544 1545 /* 1546 * Map control/status registers. 1547 */ 1548 command = pci_read_config(dev, PCIR_COMMAND, 4); 1549 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1550 pci_write_config(dev, PCIR_COMMAND, command, 4); 1551 command = pci_read_config(dev, PCIR_COMMAND, 4); 1552 1553 if (!(command & PCIM_CMD_MEMEN)) { 1554 printf("ti%d: failed to enable memory mapping!\n", unit); 1555 error = ENXIO; 1556 goto fail; 1557 } 1558 1559 rid = TI_PCI_LOMEM; 1560 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1561 0, ~0, 1, RF_ACTIVE); 1562 1563 if (sc->ti_res == NULL) { 1564 printf ("ti%d: couldn't map memory\n", unit); 1565 error = ENXIO; 1566 goto fail; 1567 } 1568 1569 sc->ti_btag = rman_get_bustag(sc->ti_res); 1570 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1571 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1572 1573 /* 1574 * XXX FIXME: rman_get_virtual() on the alpha is currently 1575 * broken and returns a physical address instead of a kernel 1576 * virtual address. Consequently, we need to do a little 1577 * extra mangling of the vhandle on the alpha. This should 1578 * eventually be fixed! The whole idea here is to get rid 1579 * of platform dependencies. 1580 */ 1581#ifdef __alpha__ 1582 if (pci_cvt_to_bwx(sc->ti_vhandle)) 1583 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 1584 else 1585 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 1586 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 1587#endif 1588 1589 /* Allocate interrupt */ 1590 rid = 0; 1591 1592 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1593 RF_SHAREABLE | RF_ACTIVE); 1594 1595 if (sc->ti_irq == NULL) { 1596 printf("ti%d: couldn't map interrupt\n", unit); 1597 error = ENXIO; 1598 goto fail; 1599 } 1600 1601 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1602 ti_intr, sc, &sc->ti_intrhand); 1603 1604 if (error) { 1605 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1606 bus_release_resource(dev, SYS_RES_MEMORY, 1607 TI_PCI_LOMEM, sc->ti_res); 1608 printf("ti%d: couldn't set up irq\n", unit); 1609 goto fail; 1610 } 1611 1612 sc->ti_unit = unit; 1613 1614 if (ti_chipinit(sc)) { 1615 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1616 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1618 bus_release_resource(dev, SYS_RES_MEMORY, 1619 TI_PCI_LOMEM, sc->ti_res); 1620 error = ENXIO; 1621 goto fail; 1622 } 1623 1624 /* Zero out the NIC's on-board SRAM. */ 1625 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1626 1627 /* Init again -- zeroing memory may have clobbered some registers. */ 1628 if (ti_chipinit(sc)) { 1629 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1630 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1632 bus_release_resource(dev, SYS_RES_MEMORY, 1633 TI_PCI_LOMEM, sc->ti_res); 1634 error = ENXIO; 1635 goto fail; 1636 } 1637 1638 /* 1639 * Get station address from the EEPROM. Note: the manual states 1640 * that the MAC address is at offset 0x8c, however the data is 1641 * stored as two longwords (since that's how it's loaded into 1642 * the NIC). This means the MAC address is actually preceeded 1643 * by two zero bytes. We need to skip over those. 1644 */ 1645 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1646 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1647 printf("ti%d: failed to read station address\n", unit); 1648 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1649 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1650 bus_release_resource(dev, SYS_RES_MEMORY, 1651 TI_PCI_LOMEM, sc->ti_res); 1652 error = ENXIO; 1653 goto fail; 1654 } 1655 1656 /* 1657 * A Tigon chip was detected. Inform the world. 1658 */ 1659 printf("ti%d: Ethernet address: %6D\n", unit, 1660 sc->arpcom.ac_enaddr, ":"); 1661 1662 /* Allocate the general information block and ring buffers. */ 1663 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1664 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1665 1666 if (sc->ti_rdata == NULL) { 1667 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1668 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1669 bus_release_resource(dev, SYS_RES_MEMORY, 1670 TI_PCI_LOMEM, sc->ti_res); 1671 error = ENXIO; 1672 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1673 goto fail; 1674 } 1675 1676 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1677 1678 /* Try to allocate memory for jumbo buffers. */ 1679 if (ti_alloc_jumbo_mem(sc)) { 1680 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1681 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1682 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1683 bus_release_resource(dev, SYS_RES_MEMORY, 1684 TI_PCI_LOMEM, sc->ti_res); 1685 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1686 M_DEVBUF); 1687 error = ENXIO; 1688 goto fail; 1689 } 1690 1691 /* Set default tuneable values. */ 1692 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1693 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1694 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1695 sc->ti_rx_max_coal_bds = 64; 1696 sc->ti_tx_max_coal_bds = 128; 1697 sc->ti_tx_buf_ratio = 21; 1698 1699 /* Set up ifnet structure */ 1700 ifp = &sc->arpcom.ac_if; 1701 ifp->if_softc = sc; 1702 ifp->if_unit = sc->ti_unit; 1703 ifp->if_name = "ti"; 1704 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1705 ifp->if_ioctl = ti_ioctl; 1706 ifp->if_output = ether_output; 1707 ifp->if_start = ti_start; 1708 ifp->if_watchdog = ti_watchdog; 1709 ifp->if_init = ti_init; 1710 ifp->if_mtu = ETHERMTU; 1711 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1712 1713 /* Set up ifmedia support. */ 1714 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1715 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1716 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1717 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1719 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1720 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1721 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1722 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1723 1724 /* 1725 * Call MI attach routine. 1726 */ 1727 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1728 1729fail: 1730 splx(s); 1731 1732 return(error); 1733} 1734 1735static int ti_detach(dev) 1736 device_t dev; 1737{ 1738 struct ti_softc *sc; 1739 struct ifnet *ifp; 1740 int s; 1741 1742 s = splimp(); 1743 1744 sc = device_get_softc(dev); 1745 ifp = &sc->arpcom.ac_if; 1746 1747 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1748 ti_stop(sc); 1749 1750 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1751 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1752 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1753 1754 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1755 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1756 ifmedia_removeall(&sc->ifmedia); 1757 1758 splx(s); 1759 1760 return(0); 1761} 1762 1763/* 1764 * Frame reception handling. This is called if there's a frame 1765 * on the receive return list. 1766 * 1767 * Note: we have to be able to handle three possibilities here: 1768 * 1) the frame is from the mini receive ring (can only happen) 1769 * on Tigon 2 boards) 1770 * 2) the frame is from the jumbo recieve ring 1771 * 3) the frame is from the standard receive ring 1772 */ 1773 1774static void ti_rxeof(sc) 1775 struct ti_softc *sc; 1776{ 1777 struct ifnet *ifp; 1778 struct ti_cmd_desc cmd; 1779 1780 ifp = &sc->arpcom.ac_if; 1781 1782 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1783 struct ti_rx_desc *cur_rx; 1784 u_int32_t rxidx; 1785 struct ether_header *eh; 1786 struct mbuf *m = NULL; 1787#if NVLAN > 0 1788 u_int16_t vlan_tag = 0; 1789 int have_tag = 0; 1790#endif 1791 1792 cur_rx = 1793 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1794 rxidx = cur_rx->ti_idx; 1795 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1796 1797#if NVLAN > 0 1798 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1799 have_tag = 1; 1800 vlan_tag = cur_rx->ti_vlan_tag; 1801 } 1802#endif 1803 1804 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1805 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1806 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1807 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1808 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1809 ifp->if_ierrors++; 1810 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1811 continue; 1812 } 1813 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1814 ifp->if_ierrors++; 1815 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1816 continue; 1817 } 1818 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1819 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1820 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1821 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1822 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1823 ifp->if_ierrors++; 1824 ti_newbuf_mini(sc, sc->ti_mini, m); 1825 continue; 1826 } 1827 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1828 ifp->if_ierrors++; 1829 ti_newbuf_mini(sc, sc->ti_mini, m); 1830 continue; 1831 } 1832 } else { 1833 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1834 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1835 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1836 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1837 ifp->if_ierrors++; 1838 ti_newbuf_std(sc, sc->ti_std, m); 1839 continue; 1840 } 1841 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1842 ifp->if_ierrors++; 1843 ti_newbuf_std(sc, sc->ti_std, m); 1844 continue; 1845 } 1846 } 1847 1848 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1849 ifp->if_ipackets++; 1850 eh = mtod(m, struct ether_header *); 1851 m->m_pkthdr.rcvif = ifp; 1852 1853 /* Remove header from mbuf and pass it on. */ 1854 m_adj(m, sizeof(struct ether_header)); 1855 1856 if (ifp->if_hwassist) { 1857 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1858 CSUM_DATA_VALID; 1859 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1860 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1861 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1862 } 1863 1864#if NVLAN > 0 1865 /* 1866 * If we received a packet with a vlan tag, pass it 1867 * to vlan_input() instead of ether_input(). 1868 */ 1869 if (have_tag) { 1870 vlan_input_tag(eh, m, vlan_tag); 1871 have_tag = vlan_tag = 0; 1872 continue; 1873 } 1874#endif 1875 ether_input(ifp, eh, m); 1876 } 1877 1878 /* Only necessary on the Tigon 1. */ 1879 if (sc->ti_hwrev == TI_HWREV_TIGON) 1880 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1881 sc->ti_rx_saved_considx); 1882 1883 TI_UPDATE_STDPROD(sc, sc->ti_std); 1884 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1885 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1886 1887 return; 1888} 1889 1890static void ti_txeof(sc) 1891 struct ti_softc *sc; 1892{ 1893 struct ti_tx_desc *cur_tx = NULL; 1894 struct ifnet *ifp; 1895 1896 ifp = &sc->arpcom.ac_if; 1897 1898 /* 1899 * Go through our tx ring and free mbufs for those 1900 * frames that have been sent. 1901 */ 1902 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1903 u_int32_t idx = 0; 1904 1905 idx = sc->ti_tx_saved_considx; 1906 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1907 if (idx > 383) 1908 CSR_WRITE_4(sc, TI_WINBASE, 1909 TI_TX_RING_BASE + 6144); 1910 else if (idx > 255) 1911 CSR_WRITE_4(sc, TI_WINBASE, 1912 TI_TX_RING_BASE + 4096); 1913 else if (idx > 127) 1914 CSR_WRITE_4(sc, TI_WINBASE, 1915 TI_TX_RING_BASE + 2048); 1916 else 1917 CSR_WRITE_4(sc, TI_WINBASE, 1918 TI_TX_RING_BASE); 1919 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1920 } else 1921 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1922 if (cur_tx->ti_flags & TI_BDFLAG_END) 1923 ifp->if_opackets++; 1924 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1925 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1926 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1927 } 1928 sc->ti_txcnt--; 1929 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1930 ifp->if_timer = 0; 1931 } 1932 1933 if (cur_tx != NULL) 1934 ifp->if_flags &= ~IFF_OACTIVE; 1935 1936 return; 1937} 1938 1939static void ti_intr(xsc) 1940 void *xsc; 1941{ 1942 struct ti_softc *sc; 1943 struct ifnet *ifp; 1944 1945 sc = xsc; 1946 ifp = &sc->arpcom.ac_if; 1947 1948#ifdef notdef 1949 /* Avoid this for now -- checking this register is expensive. */ 1950 /* Make sure this is really our interrupt. */ 1951 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1952 return; 1953#endif 1954 1955 /* Ack interrupt and stop others from occuring. */ 1956 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1957 1958 if (ifp->if_flags & IFF_RUNNING) { 1959 /* Check RX return ring producer/consumer */ 1960 ti_rxeof(sc); 1961 1962 /* Check TX ring producer/consumer */ 1963 ti_txeof(sc); 1964 } 1965 1966 ti_handle_events(sc); 1967 1968 /* Re-enable interrupts. */ 1969 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1970 1971 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1972 ti_start(ifp); 1973 1974 return; 1975} 1976 1977static void ti_stats_update(sc) 1978 struct ti_softc *sc; 1979{ 1980 struct ifnet *ifp; 1981 1982 ifp = &sc->arpcom.ac_if; 1983 1984 ifp->if_collisions += 1985 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1986 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1987 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1988 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1989 ifp->if_collisions; 1990 1991 return; 1992} 1993 1994/* 1995 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1996 * pointers to descriptors. 1997 */ 1998static int ti_encap(sc, m_head, txidx) 1999 struct ti_softc *sc; 2000 struct mbuf *m_head; 2001 u_int32_t *txidx; 2002{ 2003 struct ti_tx_desc *f = NULL; 2004 struct mbuf *m; 2005 u_int32_t frag, cur, cnt = 0; 2006 u_int16_t csum_flags = 0; 2007#if NVLAN > 0 2008 struct ifvlan *ifv = NULL; 2009 2010 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2011 m_head->m_pkthdr.rcvif != NULL && 2012 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2013 ifv = m_head->m_pkthdr.rcvif->if_softc; 2014#endif 2015 2016 m = m_head; 2017 cur = frag = *txidx; 2018 2019 if (m_head->m_pkthdr.csum_flags) { 2020 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2021 csum_flags |= TI_BDFLAG_IP_CKSUM; 2022 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2023 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2024 if (m_head->m_flags & M_LASTFRAG) 2025 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2026 else if (m_head->m_flags & M_FRAG) 2027 csum_flags |= TI_BDFLAG_IP_FRAG; 2028 } 2029 /* 2030 * Start packing the mbufs in this chain into 2031 * the fragment pointers. Stop when we run out 2032 * of fragments or hit the end of the mbuf chain. 2033 */ 2034 for (m = m_head; m != NULL; m = m->m_next) { 2035 if (m->m_len != 0) { 2036 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2037 if (frag > 383) 2038 CSR_WRITE_4(sc, TI_WINBASE, 2039 TI_TX_RING_BASE + 6144); 2040 else if (frag > 255) 2041 CSR_WRITE_4(sc, TI_WINBASE, 2042 TI_TX_RING_BASE + 4096); 2043 else if (frag > 127) 2044 CSR_WRITE_4(sc, TI_WINBASE, 2045 TI_TX_RING_BASE + 2048); 2046 else 2047 CSR_WRITE_4(sc, TI_WINBASE, 2048 TI_TX_RING_BASE); 2049 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2050 } else 2051 f = &sc->ti_rdata->ti_tx_ring[frag]; 2052 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2053 break; 2054 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2055 f->ti_len = m->m_len; 2056 f->ti_flags = csum_flags; 2057#if NVLAN > 0 2058 if (ifv != NULL) { 2059 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2060 f->ti_vlan_tag = ifv->ifv_tag; 2061 } else { 2062 f->ti_vlan_tag = 0; 2063 } 2064#endif 2065 /* 2066 * Sanity check: avoid coming within 16 descriptors 2067 * of the end of the ring. 2068 */ 2069 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2070 return(ENOBUFS); 2071 cur = frag; 2072 TI_INC(frag, TI_TX_RING_CNT); 2073 cnt++; 2074 } 2075 } 2076 2077 if (m != NULL) 2078 return(ENOBUFS); 2079 2080 if (frag == sc->ti_tx_saved_considx) 2081 return(ENOBUFS); 2082 2083 if (sc->ti_hwrev == TI_HWREV_TIGON) 2084 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2085 TI_BDFLAG_END; 2086 else 2087 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2088 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2089 sc->ti_txcnt += cnt; 2090 2091 *txidx = frag; 2092 2093 return(0); 2094} 2095 2096/* 2097 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2098 * to the mbuf data regions directly in the transmit descriptors. 2099 */ 2100static void ti_start(ifp) 2101 struct ifnet *ifp; 2102{ 2103 struct ti_softc *sc; 2104 struct mbuf *m_head = NULL; 2105 u_int32_t prodidx = 0; 2106 2107 sc = ifp->if_softc; 2108 2109 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2110 2111 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2112 IF_DEQUEUE(&ifp->if_snd, m_head); 2113 if (m_head == NULL) 2114 break; 2115 2116 /* 2117 * XXX 2118 * safety overkill. If this is a fragmented packet chain 2119 * with delayed TCP/UDP checksums, then only encapsulate 2120 * it if we have enough descriptors to handle the entire 2121 * chain at once. 2122 * (paranoia -- may not actually be needed) 2123 */ 2124 if (m_head->m_flags & M_FIRSTFRAG && 2125 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2126 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2127 m_head->m_pkthdr.csum_data + 16) { 2128 IF_PREPEND(&ifp->if_snd, m_head); 2129 ifp->if_flags |= IFF_OACTIVE; 2130 break; 2131 } 2132 } 2133 2134 /* 2135 * Pack the data into the transmit ring. If we 2136 * don't have room, set the OACTIVE flag and wait 2137 * for the NIC to drain the ring. 2138 */ 2139 if (ti_encap(sc, m_head, &prodidx)) { 2140 IF_PREPEND(&ifp->if_snd, m_head); 2141 ifp->if_flags |= IFF_OACTIVE; 2142 break; 2143 } 2144 2145 /* 2146 * If there's a BPF listener, bounce a copy of this frame 2147 * to him. 2148 */ 2149 if (ifp->if_bpf) 2150 bpf_mtap(ifp, m_head); 2151 } 2152 2153 /* Transmit */ 2154 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2155 2156 /* 2157 * Set a timeout in case the chip goes out to lunch. 2158 */ 2159 ifp->if_timer = 5; 2160 2161 return; 2162} 2163 2164static void ti_init(xsc) 2165 void *xsc; 2166{ 2167 struct ti_softc *sc = xsc; 2168 int s; 2169 2170 s = splimp(); 2171 2172 /* Cancel pending I/O and flush buffers. */ 2173 ti_stop(sc); 2174 2175 /* Init the gen info block, ring control blocks and firmware. */ 2176 if (ti_gibinit(sc)) { 2177 printf("ti%d: initialization failure\n", sc->ti_unit); 2178 splx(s); 2179 return; 2180 } 2181 2182 splx(s); 2183 2184 return; 2185} 2186 2187static void ti_init2(sc) 2188 struct ti_softc *sc; 2189{ 2190 struct ti_cmd_desc cmd; 2191 struct ifnet *ifp; 2192 u_int16_t *m; 2193 struct ifmedia *ifm; 2194 int tmp; 2195 2196 ifp = &sc->arpcom.ac_if; 2197 2198 /* Specify MTU and interface index. */ 2199 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2200 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2201 ETHER_HDR_LEN + ETHER_CRC_LEN); 2202 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2203 2204 /* Load our MAC address. */ 2205 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2206 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2207 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2208 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2209 2210 /* Enable or disable promiscuous mode as needed. */ 2211 if (ifp->if_flags & IFF_PROMISC) { 2212 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2213 } else { 2214 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2215 } 2216 2217 /* Program multicast filter. */ 2218 ti_setmulti(sc); 2219 2220 /* 2221 * If this is a Tigon 1, we should tell the 2222 * firmware to use software packet filtering. 2223 */ 2224 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2225 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2226 } 2227 2228 /* Init RX ring. */ 2229 ti_init_rx_ring_std(sc); 2230 2231 /* Init jumbo RX ring. */ 2232 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2233 ti_init_rx_ring_jumbo(sc); 2234 2235 /* 2236 * If this is a Tigon 2, we can also configure the 2237 * mini ring. 2238 */ 2239 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2240 ti_init_rx_ring_mini(sc); 2241 2242 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2243 sc->ti_rx_saved_considx = 0; 2244 2245 /* Init TX ring. */ 2246 ti_init_tx_ring(sc); 2247 2248 /* Tell firmware we're alive. */ 2249 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2250 2251 /* Enable host interrupts. */ 2252 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2253 2254 ifp->if_flags |= IFF_RUNNING; 2255 ifp->if_flags &= ~IFF_OACTIVE; 2256 2257 /* 2258 * Make sure to set media properly. We have to do this 2259 * here since we have to issue commands in order to set 2260 * the link negotiation and we can't issue commands until 2261 * the firmware is running. 2262 */ 2263 ifm = &sc->ifmedia; 2264 tmp = ifm->ifm_media; 2265 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2266 ti_ifmedia_upd(ifp); 2267 ifm->ifm_media = tmp; 2268 2269 return; 2270} 2271 2272/* 2273 * Set media options. 2274 */ 2275static int ti_ifmedia_upd(ifp) 2276 struct ifnet *ifp; 2277{ 2278 struct ti_softc *sc; 2279 struct ifmedia *ifm; 2280 struct ti_cmd_desc cmd; 2281 2282 sc = ifp->if_softc; 2283 ifm = &sc->ifmedia; 2284 2285 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2286 return(EINVAL); 2287 2288 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2289 case IFM_AUTO: 2290 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2291 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2292 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2293 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2294 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2295 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2296 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2297 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2298 break; 2299 case IFM_1000_SX: 2300 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2301 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2302 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2303 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2304 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2305 break; 2306 case IFM_100_FX: 2307 case IFM_10_FL: 2308 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2309 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2310 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2311 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2312 } else { 2313 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2314 } 2315 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2316 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2317 } else { 2318 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2319 } 2320 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2321 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2322 break; 2323 } 2324 2325 return(0); 2326} 2327 2328/* 2329 * Report current media status. 2330 */ 2331static void ti_ifmedia_sts(ifp, ifmr) 2332 struct ifnet *ifp; 2333 struct ifmediareq *ifmr; 2334{ 2335 struct ti_softc *sc; 2336 2337 sc = ifp->if_softc; 2338 2339 ifmr->ifm_status = IFM_AVALID; 2340 ifmr->ifm_active = IFM_ETHER; 2341 2342 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2343 return; 2344 2345 ifmr->ifm_status |= IFM_ACTIVE; 2346 2347 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2348 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2349 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2350 u_int32_t media; 2351 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2352 if (media & TI_LNK_100MB) 2353 ifmr->ifm_active |= IFM_100_FX; 2354 if (media & TI_LNK_10MB) 2355 ifmr->ifm_active |= IFM_10_FL; 2356 if (media & TI_LNK_FULL_DUPLEX) 2357 ifmr->ifm_active |= IFM_FDX; 2358 if (media & TI_LNK_HALF_DUPLEX) 2359 ifmr->ifm_active |= IFM_HDX; 2360 } 2361 2362 return; 2363} 2364 2365static int ti_ioctl(ifp, command, data) 2366 struct ifnet *ifp; 2367 u_long command; 2368 caddr_t data; 2369{ 2370 struct ti_softc *sc = ifp->if_softc; 2371 struct ifreq *ifr = (struct ifreq *) data; 2372 int s, error = 0; 2373 struct ti_cmd_desc cmd; 2374 2375 s = splimp(); 2376 2377 switch(command) { 2378 case SIOCSIFADDR: 2379 case SIOCGIFADDR: 2380 error = ether_ioctl(ifp, command, data); 2381 break; 2382 case SIOCSIFMTU: 2383 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2384 error = EINVAL; 2385 else { 2386 ifp->if_mtu = ifr->ifr_mtu; 2387 ti_init(sc); 2388 } 2389 break; 2390 case SIOCSIFFLAGS: 2391 if (ifp->if_flags & IFF_UP) { 2392 /* 2393 * If only the state of the PROMISC flag changed, 2394 * then just use the 'set promisc mode' command 2395 * instead of reinitializing the entire NIC. Doing 2396 * a full re-init means reloading the firmware and 2397 * waiting for it to start up, which may take a 2398 * second or two. 2399 */ 2400 if (ifp->if_flags & IFF_RUNNING && 2401 ifp->if_flags & IFF_PROMISC && 2402 !(sc->ti_if_flags & IFF_PROMISC)) { 2403 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2404 TI_CMD_CODE_PROMISC_ENB, 0); 2405 } else if (ifp->if_flags & IFF_RUNNING && 2406 !(ifp->if_flags & IFF_PROMISC) && 2407 sc->ti_if_flags & IFF_PROMISC) { 2408 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2409 TI_CMD_CODE_PROMISC_DIS, 0); 2410 } else 2411 ti_init(sc); 2412 } else { 2413 if (ifp->if_flags & IFF_RUNNING) { 2414 ti_stop(sc); 2415 } 2416 } 2417 sc->ti_if_flags = ifp->if_flags; 2418 error = 0; 2419 break; 2420 case SIOCADDMULTI: 2421 case SIOCDELMULTI: 2422 if (ifp->if_flags & IFF_RUNNING) { 2423 ti_setmulti(sc); 2424 error = 0; 2425 } 2426 break; 2427 case SIOCSIFMEDIA: 2428 case SIOCGIFMEDIA: 2429 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2430 break; 2431 default: 2432 error = EINVAL; 2433 break; 2434 } 2435 2436 (void)splx(s); 2437 2438 return(error); 2439} 2440 2441static void ti_watchdog(ifp) 2442 struct ifnet *ifp; 2443{ 2444 struct ti_softc *sc; 2445 2446 sc = ifp->if_softc; 2447 2448 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2449 ti_stop(sc); 2450 ti_init(sc); 2451 2452 ifp->if_oerrors++; 2453 2454 return; 2455} 2456 2457/* 2458 * Stop the adapter and free any mbufs allocated to the 2459 * RX and TX lists. 2460 */ 2461static void ti_stop(sc) 2462 struct ti_softc *sc; 2463{ 2464 struct ifnet *ifp; 2465 struct ti_cmd_desc cmd; 2466 2467 ifp = &sc->arpcom.ac_if; 2468 2469 /* Disable host interrupts. */ 2470 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2471 /* 2472 * Tell firmware we're shutting down. 2473 */ 2474 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2475 2476 /* Halt and reinitialize. */ 2477 ti_chipinit(sc); 2478 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2479 ti_chipinit(sc); 2480 2481 /* Free the RX lists. */ 2482 ti_free_rx_ring_std(sc); 2483 2484 /* Free jumbo RX list. */ 2485 ti_free_rx_ring_jumbo(sc); 2486 2487 /* Free mini RX list. */ 2488 ti_free_rx_ring_mini(sc); 2489 2490 /* Free TX buffers. */ 2491 ti_free_tx_ring(sc); 2492 2493 sc->ti_ev_prodidx.ti_idx = 0; 2494 sc->ti_return_prodidx.ti_idx = 0; 2495 sc->ti_tx_considx.ti_idx = 0; 2496 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2497 2498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2499 2500 return; 2501} 2502 2503/* 2504 * Stop all chip I/O so that the kernel's probe routines don't 2505 * get confused by errant DMAs when rebooting. 2506 */ 2507static void ti_shutdown(dev) 2508 device_t dev; 2509{ 2510 struct ti_softc *sc; 2511 2512 sc = device_get_softc(dev); 2513 2514 ti_chipinit(sc); 2515 2516 return; 2517} 2518