if_ti.c revision 49078
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_ti.c,v 1.12 1999/07/23 18:46:24 wpaul Exp $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "bpf.h" 82#include "vlan.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/socket.h> 91#include <sys/queue.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#if NBPF > 0 100#include <net/bpf.h> 101#endif 102 103#if NVLAN > 0 104#include <net/if_types.h> 105#include <net/if_vlan_var.h> 106#endif 107 108#include <netinet/in_systm.h> 109#include <netinet/in.h> 110#include <netinet/ip.h> 111 112#include <vm/vm.h> /* for vtophys */ 113#include <vm/pmap.h> /* for vtophys */ 114#include <machine/clock.h> /* for DELAY */ 115#include <machine/bus_memio.h> 116#include <machine/bus.h> 117#include <machine/resource.h> 118#include <sys/bus.h> 119#include <sys/rman.h> 120 121#include <pci/pcireg.h> 122#include <pci/pcivar.h> 123 124#include <pci/if_tireg.h> 125#include <pci/ti_fw.h> 126#include <pci/ti_fw2.h> 127 128#ifdef M_HWCKSUM 129/*#define TI_CSUM_OFFLOAD*/ 130#endif 131 132#if !defined(lint) 133static const char rcsid[] = 134 "$Id: if_ti.c,v 1.12 1999/07/23 18:46:24 wpaul Exp $"; 135#endif 136 137/* 138 * Various supported device vendors/types and their names. 139 */ 140 141static struct ti_type ti_devs[] = { 142 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 143 "Alteon AceNIC Gigabit Ethernet" }, 144 { TC_VENDORID, TC_DEVICEID_3C985, 145 "3Com 3c985-SX Gigabit Ethernet" }, 146 { NG_VENDORID, NG_DEVICEID_GA620, 147 "Netgear GA620 Gigabit Ethernet" }, 148 { SGI_VENDORID, SGI_DEVICEID_TIGON, 149 "Silicon Graphics Gigabit Ethernet" }, 150 { 0, 0, NULL } 151}; 152 153static int ti_probe __P((device_t)); 154static int ti_attach __P((device_t)); 155static int ti_detach __P((device_t)); 156static void ti_txeof __P((struct ti_softc *)); 157static void ti_rxeof __P((struct ti_softc *)); 158 159static void ti_stats_update __P((struct ti_softc *)); 160static int ti_encap __P((struct ti_softc *, struct mbuf *, 161 u_int32_t *)); 162 163static void ti_intr __P((void *)); 164static void ti_start __P((struct ifnet *)); 165static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 166static void ti_init __P((void *)); 167static void ti_init2 __P((struct ti_softc *)); 168static void ti_stop __P((struct ti_softc *)); 169static void ti_watchdog __P((struct ifnet *)); 170static void ti_shutdown __P((device_t)); 171static int ti_ifmedia_upd __P((struct ifnet *)); 172static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 175static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 176 int, u_int8_t *)); 177static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 178 179static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 180static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 181static void ti_setmulti __P((struct ti_softc *)); 182 183static void ti_mem __P((struct ti_softc *, u_int32_t, 184 u_int32_t, caddr_t)); 185static void ti_loadfw __P((struct ti_softc *)); 186static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 187static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int)); 189static void ti_handle_events __P((struct ti_softc *)); 190static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 191static void *ti_jalloc __P((struct ti_softc *)); 192static void ti_jfree __P((caddr_t, u_int)); 193static void ti_jref __P((caddr_t, u_int)); 194static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 195static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 196static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 197static int ti_init_rx_ring_std __P((struct ti_softc *)); 198static void ti_free_rx_ring_std __P((struct ti_softc *)); 199static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 200static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 201static int ti_init_rx_ring_mini __P((struct ti_softc *)); 202static void ti_free_rx_ring_mini __P((struct ti_softc *)); 203static void ti_free_tx_ring __P((struct ti_softc *)); 204static int ti_init_tx_ring __P((struct ti_softc *)); 205 206static int ti_64bitslot_war __P((struct ti_softc *)); 207static int ti_chipinit __P((struct ti_softc *)); 208static int ti_gibinit __P((struct ti_softc *)); 209 210static device_method_t ti_methods[] = { 211 /* Device interface */ 212 DEVMETHOD(device_probe, ti_probe), 213 DEVMETHOD(device_attach, ti_attach), 214 DEVMETHOD(device_detach, ti_detach), 215 DEVMETHOD(device_shutdown, ti_shutdown), 216 { 0, 0 } 217}; 218 219static driver_t ti_driver = { 220 "ti", 221 ti_methods, 222 sizeof(struct ti_softc) 223}; 224 225static devclass_t ti_devclass; 226 227DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 228 229/* 230 * Send an instruction or address to the EEPROM, check for ACK. 231 */ 232static u_int32_t ti_eeprom_putbyte(sc, byte) 233 struct ti_softc *sc; 234 int byte; 235{ 236 register int i, ack = 0; 237 238 /* 239 * Make sure we're in TX mode. 240 */ 241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 242 243 /* 244 * Feed in each bit and stobe the clock. 245 */ 246 for (i = 0x80; i; i >>= 1) { 247 if (byte & i) { 248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 249 } else { 250 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 251 } 252 DELAY(1); 253 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 254 DELAY(1); 255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 256 } 257 258 /* 259 * Turn off TX mode. 260 */ 261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 262 263 /* 264 * Check for ack. 265 */ 266 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 267 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 268 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 269 270 return(ack); 271} 272 273/* 274 * Read a byte of data stored in the EEPROM at address 'addr.' 275 * We have to send two address bytes since the EEPROM can hold 276 * more than 256 bytes of data. 277 */ 278static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 279 struct ti_softc *sc; 280 int addr; 281 u_int8_t *dest; 282{ 283 register int i; 284 u_int8_t byte = 0; 285 286 EEPROM_START; 287 288 /* 289 * Send write control code to EEPROM. 290 */ 291 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 292 printf("ti%d: failed to send write command, status: %x\n", 293 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return(1); 295 } 296 297 /* 298 * Send first byte of address of byte we want to read. 299 */ 300 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 301 printf("ti%d: failed to send address, status: %x\n", 302 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 /* 306 * Send second byte address of byte we want to read. 307 */ 308 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 309 printf("ti%d: failed to send address, status: %x\n", 310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 311 return(1); 312 } 313 314 EEPROM_STOP; 315 EEPROM_START; 316 /* 317 * Send read control code to EEPROM. 318 */ 319 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 320 printf("ti%d: failed to send read command, status: %x\n", 321 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 322 return(1); 323 } 324 325 /* 326 * Start reading bits from EEPROM. 327 */ 328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 329 for (i = 0x80; i; i >>= 1) { 330 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 331 DELAY(1); 332 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 333 byte |= i; 334 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 335 DELAY(1); 336 } 337 338 EEPROM_STOP; 339 340 /* 341 * No ACK generated for read, so just return byte. 342 */ 343 344 *dest = byte; 345 346 return(0); 347} 348 349/* 350 * Read a sequence of bytes from the EEPROM. 351 */ 352static int ti_read_eeprom(sc, dest, off, cnt) 353 struct ti_softc *sc; 354 caddr_t dest; 355 int off; 356 int cnt; 357{ 358 int err = 0, i; 359 u_int8_t byte = 0; 360 361 for (i = 0; i < cnt; i++) { 362 err = ti_eeprom_getbyte(sc, off + i, &byte); 363 if (err) 364 break; 365 *(dest + i) = byte; 366 } 367 368 return(err ? 1 : 0); 369} 370 371/* 372 * NIC memory access function. Can be used to either clear a section 373 * of NIC local memory or (if buf is non-NULL) copy data into it. 374 */ 375static void ti_mem(sc, addr, len, buf) 376 struct ti_softc *sc; 377 u_int32_t addr, len; 378 caddr_t buf; 379{ 380 int segptr, segsize, cnt; 381 caddr_t ti_winbase, ptr; 382 383 segptr = addr; 384 cnt = len; 385 ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW); 386 ptr = buf; 387 388 while(cnt) { 389 if (cnt < TI_WINLEN) 390 segsize = cnt; 391 else 392 segsize = TI_WINLEN - (segptr % TI_WINLEN); 393 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 394 if (buf == NULL) 395 bzero((char *)ti_winbase + (segptr & 396 (TI_WINLEN - 1)), segsize); 397 else { 398 bcopy((char *)ptr, (char *)ti_winbase + 399 (segptr & (TI_WINLEN - 1)), segsize); 400 ptr += segsize; 401 } 402 segptr += segsize; 403 cnt -= segsize; 404 } 405 406 return; 407} 408 409/* 410 * Load firmware image into the NIC. Check that the firmware revision 411 * is acceptable and see if we want the firmware for the Tigon 1 or 412 * Tigon 2. 413 */ 414static void ti_loadfw(sc) 415 struct ti_softc *sc; 416{ 417 switch(sc->ti_hwrev) { 418 case TI_HWREV_TIGON: 419 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 420 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 421 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 422 printf("ti%d: firmware revision mismatch; want " 423 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 424 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 425 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 426 tigonFwReleaseMinor, tigonFwReleaseFix); 427 return; 428 } 429 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 430 (caddr_t)tigonFwText); 431 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 432 (caddr_t)tigonFwData); 433 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 434 (caddr_t)tigonFwRodata); 435 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 436 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 437 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 438 break; 439 case TI_HWREV_TIGON_II: 440 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 441 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 442 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 443 printf("ti%d: firmware revision mismatch; want " 444 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 445 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 446 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 447 tigon2FwReleaseMinor, tigon2FwReleaseFix); 448 return; 449 } 450 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 451 (caddr_t)tigon2FwText); 452 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 453 (caddr_t)tigon2FwData); 454 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 455 (caddr_t)tigon2FwRodata); 456 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 457 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 458 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 459 break; 460 default: 461 printf("ti%d: can't load firmware: unknown hardware rev\n", 462 sc->ti_unit); 463 break; 464 } 465 466 return; 467} 468 469/* 470 * Send the NIC a command via the command ring. 471 */ 472static void ti_cmd(sc, cmd) 473 struct ti_softc *sc; 474 struct ti_cmd_desc *cmd; 475{ 476 u_int32_t index; 477 478 if (sc->ti_rdata->ti_cmd_ring == NULL) 479 return; 480 481 index = sc->ti_cmd_saved_prodidx; 482 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 483 TI_INC(index, TI_CMD_RING_CNT); 484 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 485 sc->ti_cmd_saved_prodidx = index; 486 487 return; 488} 489 490/* 491 * Send the NIC an extended command. The 'len' parameter specifies the 492 * number of command slots to include after the initial command. 493 */ 494static void ti_cmd_ext(sc, cmd, arg, len) 495 struct ti_softc *sc; 496 struct ti_cmd_desc *cmd; 497 caddr_t arg; 498 int len; 499{ 500 u_int32_t index; 501 register int i; 502 503 if (sc->ti_rdata->ti_cmd_ring == NULL) 504 return; 505 506 index = sc->ti_cmd_saved_prodidx; 507 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 508 TI_INC(index, TI_CMD_RING_CNT); 509 for (i = 0; i < len; i++) { 510 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 511 *(u_int32_t *)(&arg[i * 4])); 512 TI_INC(index, TI_CMD_RING_CNT); 513 } 514 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 515 sc->ti_cmd_saved_prodidx = index; 516 517 return; 518} 519 520/* 521 * Handle events that have triggered interrupts. 522 */ 523static void ti_handle_events(sc) 524 struct ti_softc *sc; 525{ 526 struct ti_event_desc *e; 527 528 if (sc->ti_rdata->ti_event_ring == NULL) 529 return; 530 531 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 532 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 533 switch(e->ti_event) { 534 case TI_EV_LINKSTAT_CHANGED: 535 sc->ti_linkstat = e->ti_code; 536 if (e->ti_code == TI_EV_CODE_LINK_UP) 537 printf("ti%d: 10/100 link up\n", sc->ti_unit); 538 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 539 printf("ti%d: gigabit link up\n", sc->ti_unit); 540 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 541 printf("ti%d: link down\n", sc->ti_unit); 542 break; 543 case TI_EV_ERROR: 544 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 545 printf("ti%d: invalid command\n", sc->ti_unit); 546 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 547 printf("ti%d: unknown command\n", sc->ti_unit); 548 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 549 printf("ti%d: bad config data\n", sc->ti_unit); 550 break; 551 case TI_EV_FIRMWARE_UP: 552 ti_init2(sc); 553 break; 554 case TI_EV_STATS_UPDATED: 555 ti_stats_update(sc); 556 break; 557 case TI_EV_RESET_JUMBO_RING: 558 case TI_EV_MCAST_UPDATED: 559 /* Who cares. */ 560 break; 561 default: 562 printf("ti%d: unknown event: %d\n", 563 sc->ti_unit, e->ti_event); 564 break; 565 } 566 /* Advance the consumer index. */ 567 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 568 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 569 } 570 571 return; 572} 573 574/* 575 * Memory management for the jumbo receive ring is a pain in the 576 * butt. We need to allocate at least 9018 bytes of space per frame, 577 * _and_ it has to be contiguous (unless you use the extended 578 * jumbo descriptor format). Using malloc() all the time won't 579 * work: malloc() allocates memory in powers of two, which means we 580 * would end up wasting a considerable amount of space by allocating 581 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 582 * to do our own memory management. 583 * 584 * The driver needs to allocate a contiguous chunk of memory at boot 585 * time. We then chop this up ourselves into 9K pieces and use them 586 * as external mbuf storage. 587 * 588 * One issue here is how much memory to allocate. The jumbo ring has 589 * 256 slots in it, but at 9K per slot than can consume over 2MB of 590 * RAM. This is a bit much, especially considering we also need 591 * RAM for the standard ring and mini ring (on the Tigon 2). To 592 * save space, we only actually allocate enough memory for 64 slots 593 * by default, which works out to between 500 and 600K. This can 594 * be tuned by changing a #define in if_tireg.h. 595 */ 596 597static int ti_alloc_jumbo_mem(sc) 598 struct ti_softc *sc; 599{ 600 caddr_t ptr; 601 register int i; 602 struct ti_jpool_entry *entry; 603 604 /* Grab a big chunk o' storage. */ 605 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 606 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 607 608 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 609 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 610 return(ENOBUFS); 611 } 612 613 SLIST_INIT(&sc->ti_jfree_listhead); 614 SLIST_INIT(&sc->ti_jinuse_listhead); 615 616 /* 617 * Now divide it up into 9K pieces and save the addresses 618 * in an array. Note that we play an evil trick here by using 619 * the first few bytes in the buffer to hold the the address 620 * of the softc structure for this interface. This is because 621 * ti_jfree() needs it, but it is called by the mbuf management 622 * code which will not pass it to us explicitly. 623 */ 624 ptr = sc->ti_cdata.ti_jumbo_buf; 625 for (i = 0; i < TI_JSLOTS; i++) { 626 u_int64_t **aptr; 627 aptr = (u_int64_t **)ptr; 628 aptr[0] = (u_int64_t *)sc; 629 ptr += sizeof(u_int64_t); 630 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 631 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 632 ptr += (TI_JLEN - sizeof(u_int64_t)); 633 entry = malloc(sizeof(struct ti_jpool_entry), 634 M_DEVBUF, M_NOWAIT); 635 if (entry == NULL) { 636 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 637 sc->ti_cdata.ti_jumbo_buf = NULL; 638 printf("ti%d: no memory for jumbo " 639 "buffer queue!\n", sc->ti_unit); 640 return(ENOBUFS); 641 } 642 entry->slot = i; 643 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 644 } 645 646 return(0); 647} 648 649/* 650 * Allocate a jumbo buffer. 651 */ 652static void *ti_jalloc(sc) 653 struct ti_softc *sc; 654{ 655 struct ti_jpool_entry *entry; 656 657 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 658 659 if (entry == NULL) { 660 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 661 return(NULL); 662 } 663 664 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 665 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 666 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 667 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 668} 669 670/* 671 * Adjust usage count on a jumbo buffer. In general this doesn't 672 * get used much because our jumbo buffers don't get passed around 673 * too much, but it's implemented for correctness. 674 */ 675static void ti_jref(buf, size) 676 caddr_t buf; 677 u_int size; 678{ 679 struct ti_softc *sc; 680 u_int64_t **aptr; 681 register int i; 682 683 /* Extract the softc struct pointer. */ 684 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 685 sc = (struct ti_softc *)(aptr[0]); 686 687 if (sc == NULL) 688 panic("ti_jref: can't find softc pointer!"); 689 690 if (size != TI_JUMBO_FRAMELEN) 691 panic("ti_jref: adjusting refcount of buf of wrong size!"); 692 693 /* calculate the slot this buffer belongs to */ 694 695 i = ((vm_offset_t)aptr 696 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 697 698 if ((i < 0) || (i >= TI_JSLOTS)) 699 panic("ti_jref: asked to reference buffer " 700 "that we don't manage!"); 701 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 702 panic("ti_jref: buffer already free!"); 703 else 704 sc->ti_cdata.ti_jslots[i].ti_inuse++; 705 706 return; 707} 708 709/* 710 * Release a jumbo buffer. 711 */ 712static void ti_jfree(buf, size) 713 caddr_t buf; 714 u_int size; 715{ 716 struct ti_softc *sc; 717 u_int64_t **aptr; 718 int i; 719 struct ti_jpool_entry *entry; 720 721 /* Extract the softc struct pointer. */ 722 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 723 sc = (struct ti_softc *)(aptr[0]); 724 725 if (sc == NULL) 726 panic("ti_jfree: can't find softc pointer!"); 727 728 if (size != TI_JUMBO_FRAMELEN) 729 panic("ti_jfree: freeing buffer of wrong size!"); 730 731 /* calculate the slot this buffer belongs to */ 732 733 i = ((vm_offset_t)aptr 734 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 735 736 if ((i < 0) || (i >= TI_JSLOTS)) 737 panic("ti_jfree: asked to free buffer that we don't manage!"); 738 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 739 panic("ti_jfree: buffer already free!"); 740 else { 741 sc->ti_cdata.ti_jslots[i].ti_inuse--; 742 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 743 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 744 if (entry == NULL) 745 panic("ti_jfree: buffer not in use!"); 746 entry->slot = i; 747 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 748 jpool_entries); 749 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 750 entry, jpool_entries); 751 } 752 } 753 754 return; 755} 756 757 758/* 759 * Intialize a standard receive ring descriptor. 760 */ 761static int ti_newbuf_std(sc, i, m) 762 struct ti_softc *sc; 763 int i; 764 struct mbuf *m; 765{ 766 struct mbuf *m_new = NULL; 767 struct ti_rx_desc *r; 768 769 if (m == NULL) { 770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 771 if (m_new == NULL) { 772 printf("ti%d: mbuf allocation failed " 773 "-- packet dropped!\n", sc->ti_unit); 774 return(ENOBUFS); 775 } 776 777 MCLGET(m_new, M_DONTWAIT); 778 if (!(m_new->m_flags & M_EXT)) { 779 printf("ti%d: cluster allocation failed " 780 "-- packet dropped!\n", sc->ti_unit); 781 m_freem(m_new); 782 return(ENOBUFS); 783 } 784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 785 } else { 786 m_new = m; 787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 788 m_new->m_data = m_new->m_ext.ext_buf; 789 } 790 791 m_adj(m_new, ETHER_ALIGN); 792 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 793 r = &sc->ti_rdata->ti_rx_std_ring[i]; 794 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 795 r->ti_type = TI_BDTYPE_RECV_BD; 796#ifdef TI_CSUM_OFFLOAD 797 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 798#else 799 r->ti_flags = 0; 800#endif 801 r->ti_len = m_new->m_len; 802 r->ti_idx = i; 803 804 return(0); 805} 806 807/* 808 * Intialize a mini receive ring descriptor. This only applies to 809 * the Tigon 2. 810 */ 811static int ti_newbuf_mini(sc, i, m) 812 struct ti_softc *sc; 813 int i; 814 struct mbuf *m; 815{ 816 struct mbuf *m_new = NULL; 817 struct ti_rx_desc *r; 818 819 if (m == NULL) { 820 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 821 if (m_new == NULL) { 822 printf("ti%d: mbuf allocation failed " 823 "-- packet dropped!\n", sc->ti_unit); 824 return(ENOBUFS); 825 } 826 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 827 } else { 828 m_new = m; 829 m_new->m_data = m_new->m_pktdat; 830 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 831 } 832 833 m_adj(m_new, ETHER_ALIGN); 834 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 837 r->ti_type = TI_BDTYPE_RECV_BD; 838 r->ti_flags = TI_BDFLAG_MINI_RING; 839#ifdef TI_CSUM_OFFLOAD 840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 841#endif 842 r->ti_len = m_new->m_len; 843 r->ti_idx = i; 844 845 return(0); 846} 847 848/* 849 * Initialize a jumbo receive ring descriptor. This allocates 850 * a jumbo buffer from the pool managed internally by the driver. 851 */ 852static int ti_newbuf_jumbo(sc, i, m) 853 struct ti_softc *sc; 854 int i; 855 struct mbuf *m; 856{ 857 struct mbuf *m_new = NULL; 858 struct ti_rx_desc *r; 859 860 if (m == NULL) { 861 caddr_t *buf = NULL; 862 863 /* Allocate the mbuf. */ 864 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 865 if (m_new == NULL) { 866 printf("ti%d: mbuf allocation failed " 867 "-- packet dropped!\n", sc->ti_unit); 868 return(ENOBUFS); 869 } 870 871 /* Allocate the jumbo buffer */ 872 buf = ti_jalloc(sc); 873 if (buf == NULL) { 874 m_freem(m_new); 875 printf("ti%d: jumbo allocation failed " 876 "-- packet dropped!\n", sc->ti_unit); 877 return(ENOBUFS); 878 } 879 880 /* Attach the buffer to the mbuf. */ 881 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 882 m_new->m_flags |= M_EXT; 883 m_new->m_len = m_new->m_pkthdr.len = 884 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 885 m_new->m_ext.ext_free = ti_jfree; 886 m_new->m_ext.ext_ref = ti_jref; 887 } else { 888 m_new = m; 889 m_new->m_data = m_new->m_ext.ext_buf; 890 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 891 } 892 893 m_adj(m, ETHER_ALIGN); 894 /* Set up the descriptor. */ 895 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 896 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 897 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 898 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 899 r->ti_flags = TI_BDFLAG_JUMBO_RING; 900#ifdef TI_CSUM_OFFLOAD 901 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 902#endif 903 r->ti_len = m_new->m_len; 904 r->ti_idx = i; 905 906 return(0); 907} 908 909/* 910 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 911 * that's 1MB or memory, which is a lot. For now, we fill only the first 912 * 256 ring entries and hope that our CPU is fast enough to keep up with 913 * the NIC. 914 */ 915static int ti_init_rx_ring_std(sc) 916 struct ti_softc *sc; 917{ 918 register int i; 919 struct ti_cmd_desc cmd; 920 921 for (i = 0; i < TI_SSLOTS; i++) { 922 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 923 return(ENOBUFS); 924 }; 925 926 TI_UPDATE_STDPROD(sc, i - 1); 927 sc->ti_std = i - 1; 928 929 return(0); 930} 931 932static void ti_free_rx_ring_std(sc) 933 struct ti_softc *sc; 934{ 935 register int i; 936 937 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 938 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 939 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 940 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 941 } 942 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 943 sizeof(struct ti_rx_desc)); 944 } 945 946 return; 947} 948 949static int ti_init_rx_ring_jumbo(sc) 950 struct ti_softc *sc; 951{ 952 register int i; 953 struct ti_cmd_desc cmd; 954 955 for (i = 0; i < (TI_JSLOTS - 20); i++) { 956 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 957 return(ENOBUFS); 958 }; 959 960 TI_UPDATE_JUMBOPROD(sc, i - 1); 961 sc->ti_jumbo = i - 1; 962 963 return(0); 964} 965 966static void ti_free_rx_ring_jumbo(sc) 967 struct ti_softc *sc; 968{ 969 register int i; 970 971 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 972 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 973 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 974 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 975 } 976 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 977 sizeof(struct ti_rx_desc)); 978 } 979 980 return; 981} 982 983static int ti_init_rx_ring_mini(sc) 984 struct ti_softc *sc; 985{ 986 register int i; 987 988 for (i = 0; i < TI_MSLOTS; i++) { 989 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 990 return(ENOBUFS); 991 }; 992 993 TI_UPDATE_MINIPROD(sc, i - 1); 994 sc->ti_mini = i - 1; 995 996 return(0); 997} 998 999static void ti_free_rx_ring_mini(sc) 1000 struct ti_softc *sc; 1001{ 1002 register int i; 1003 1004 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1005 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1006 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1007 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1008 } 1009 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1010 sizeof(struct ti_rx_desc)); 1011 } 1012 1013 return; 1014} 1015 1016static void ti_free_tx_ring(sc) 1017 struct ti_softc *sc; 1018{ 1019 register int i; 1020 1021 if (sc->ti_rdata->ti_tx_ring == NULL) 1022 return; 1023 1024 for (i = 0; i < TI_TX_RING_CNT; i++) { 1025 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1026 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1027 sc->ti_cdata.ti_tx_chain[i] = NULL; 1028 } 1029 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1030 sizeof(struct ti_tx_desc)); 1031 } 1032 1033 return; 1034} 1035 1036static int ti_init_tx_ring(sc) 1037 struct ti_softc *sc; 1038{ 1039 sc->ti_txcnt = 0; 1040 sc->ti_tx_saved_considx = 0; 1041 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1042 return(0); 1043} 1044 1045/* 1046 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1047 * but we have to support the old way too so that Tigon 1 cards will 1048 * work. 1049 */ 1050void ti_add_mcast(sc, addr) 1051 struct ti_softc *sc; 1052 struct ether_addr *addr; 1053{ 1054 struct ti_cmd_desc cmd; 1055 u_int16_t *m; 1056 u_int32_t ext[2] = {0, 0}; 1057 1058 m = (u_int16_t *)&addr->octet[0]; 1059 1060 switch(sc->ti_hwrev) { 1061 case TI_HWREV_TIGON: 1062 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1063 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1064 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1065 break; 1066 case TI_HWREV_TIGON_II: 1067 ext[0] = htons(m[0]); 1068 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1069 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1070 break; 1071 default: 1072 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1073 break; 1074 } 1075 1076 return; 1077} 1078 1079void ti_del_mcast(sc, addr) 1080 struct ti_softc *sc; 1081 struct ether_addr *addr; 1082{ 1083 struct ti_cmd_desc cmd; 1084 u_int16_t *m; 1085 u_int32_t ext[2] = {0, 0}; 1086 1087 m = (u_int16_t *)&addr->octet[0]; 1088 1089 switch(sc->ti_hwrev) { 1090 case TI_HWREV_TIGON: 1091 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1092 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1093 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1094 break; 1095 case TI_HWREV_TIGON_II: 1096 ext[0] = htons(m[0]); 1097 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1098 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1099 break; 1100 default: 1101 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1102 break; 1103 } 1104 1105 return; 1106} 1107 1108/* 1109 * Configure the Tigon's multicast address filter. 1110 * 1111 * The actual multicast table management is a bit of a pain, thanks to 1112 * slight brain damage on the part of both Alteon and us. With our 1113 * multicast code, we are only alerted when the multicast address table 1114 * changes and at that point we only have the current list of addresses: 1115 * we only know the current state, not the previous state, so we don't 1116 * actually know what addresses were removed or added. The firmware has 1117 * state, but we can't get our grubby mits on it, and there is no 'delete 1118 * all multicast addresses' command. Hence, we have to maintain our own 1119 * state so we know what addresses have been programmed into the NIC at 1120 * any given time. 1121 */ 1122static void ti_setmulti(sc) 1123 struct ti_softc *sc; 1124{ 1125 struct ifnet *ifp; 1126 struct ifmultiaddr *ifma; 1127 struct ti_cmd_desc cmd; 1128 struct ti_mc_entry *mc; 1129 u_int32_t intrs; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 if (ifp->if_flags & IFF_ALLMULTI) { 1134 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1135 return; 1136 } else { 1137 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1138 } 1139 1140 /* Disable interrupts. */ 1141 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1142 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1143 1144 /* First, zot all the existing filters. */ 1145 while (sc->ti_mc_listhead.slh_first != NULL) { 1146 mc = sc->ti_mc_listhead.slh_first; 1147 ti_del_mcast(sc, &mc->mc_addr); 1148 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1149 free(mc, M_DEVBUF); 1150 } 1151 1152 /* Now program new ones. */ 1153 for (ifma = ifp->if_multiaddrs.lh_first; 1154 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1155 if (ifma->ifma_addr->sa_family != AF_LINK) 1156 continue; 1157 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1158 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1159 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1160 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1161 ti_add_mcast(sc, &mc->mc_addr); 1162 } 1163 1164 /* Re-enable interrupts. */ 1165 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1166 1167 return; 1168} 1169 1170/* 1171 * Check to see if the BIOS has configured us for a 64 bit slot when 1172 * we aren't actually in one. If we detect this condition, we can work 1173 * around it on the Tigon 2 by setting a bit in the PCI state register, 1174 * but for the Tigon 1 we must give up and abort the interface attach. 1175 */ 1176static int ti_64bitslot_war(sc) 1177 struct ti_softc *sc; 1178{ 1179 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1180 CSR_WRITE_4(sc, 0x600, 0); 1181 CSR_WRITE_4(sc, 0x604, 0); 1182 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1183 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1184 if (sc->ti_hwrev == TI_HWREV_TIGON) 1185 return(EINVAL); 1186 else { 1187 TI_SETBIT(sc, TI_PCI_STATE, 1188 TI_PCISTATE_32BIT_BUS); 1189 return(0); 1190 } 1191 } 1192 } 1193 1194 return(0); 1195} 1196 1197/* 1198 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1199 * self-test results. 1200 */ 1201static int ti_chipinit(sc) 1202 struct ti_softc *sc; 1203{ 1204 u_int32_t cacheline; 1205 u_int32_t pci_writemax = 0; 1206 1207 /* Initialize link to down state. */ 1208 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1209 1210 /* Set endianness before we access any non-PCI registers. */ 1211#if BYTE_ORDER == BIG_ENDIAN 1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1213 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1214#else 1215 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1216 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1217#endif 1218 1219 /* Check the ROM failed bit to see if self-tests passed. */ 1220 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1221 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1222 return(ENODEV); 1223 } 1224 1225 /* Halt the CPU. */ 1226 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1227 1228 /* Figure out the hardware revision. */ 1229 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1230 case TI_REV_TIGON_I: 1231 sc->ti_hwrev = TI_HWREV_TIGON; 1232 break; 1233 case TI_REV_TIGON_II: 1234 sc->ti_hwrev = TI_HWREV_TIGON_II; 1235 break; 1236 default: 1237 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1238 return(ENODEV); 1239 } 1240 1241 /* Do special setup for Tigon 2. */ 1242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1243 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1245 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1246 } 1247 1248 /* Set up the PCI state register. */ 1249 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1251 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1252 } 1253 1254 /* Clear the read/write max DMA parameters. */ 1255 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1256 TI_PCISTATE_READ_MAXDMA)); 1257 1258 /* Get cache line size. */ 1259 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1260 1261 /* 1262 * If the system has set enabled the PCI memory write 1263 * and invalidate command in the command register, set 1264 * the write max parameter accordingly. This is necessary 1265 * to use MWI with the Tigon 2. 1266 */ 1267 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1268 switch(cacheline) { 1269 case 1: 1270 case 4: 1271 case 8: 1272 case 16: 1273 case 32: 1274 case 64: 1275 break; 1276 default: 1277 /* Disable PCI memory write and invalidate. */ 1278 if (bootverbose) 1279 printf("ti%d: cache line size %d not " 1280 "supported; disabling PCI MWI\n", 1281 sc->ti_unit, cacheline); 1282 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1283 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1284 break; 1285 } 1286 } 1287 1288#ifdef __brokenalpha__ 1289 /* 1290 * From the Alteon sample driver: 1291 * Must insure that we do not cross an 8K (bytes) boundary 1292 * for DMA reads. Our highest limit is 1K bytes. This is a 1293 * restriction on some ALPHA platforms with early revision 1294 * 21174 PCI chipsets, such as the AlphaPC 164lx 1295 */ 1296 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1297#else 1298 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1299#endif 1300 1301 /* This sets the min dma param all the way up (0xff). */ 1302 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1303 1304 /* Configure DMA variables. */ 1305#if BYTE_ORDER == BIG_ENDIAN 1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1307 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1308 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1309 TI_OPMODE_DONT_FRAG_JUMBO); 1310#else 1311 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1312 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1313 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1314#endif 1315 1316 /* 1317 * Only allow 1 DMA channel to be active at a time. 1318 * I don't think this is a good idea, but without it 1319 * the firmware racks up lots of nicDmaReadRingFull 1320 * errors. 1321 */ 1322#ifndef TI_CSUM_OFFLOAD 1323 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1324#endif 1325 1326 /* Recommended settings from Tigon manual. */ 1327 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1328 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1329 1330 if (ti_64bitslot_war(sc)) { 1331 printf("ti%d: bios thinks we're in a 64 bit slot, " 1332 "but we aren't", sc->ti_unit); 1333 return(EINVAL); 1334 } 1335 1336 return(0); 1337} 1338 1339/* 1340 * Initialize the general information block and firmware, and 1341 * start the CPU(s) running. 1342 */ 1343static int ti_gibinit(sc) 1344 struct ti_softc *sc; 1345{ 1346 struct ti_rcb *rcb; 1347 int i; 1348 struct ifnet *ifp; 1349 1350 ifp = &sc->arpcom.ac_if; 1351 1352 /* Disable interrupts for now. */ 1353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1354 1355 /* Tell the chip where to find the general information block. */ 1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1358 1359 /* Load the firmware into SRAM. */ 1360 ti_loadfw(sc); 1361 1362 /* Set up the contents of the general info and ring control blocks. */ 1363 1364 /* Set up the event ring and producer pointer. */ 1365 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1366 1367 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1368 rcb->ti_flags = 0; 1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1370 vtophys(&sc->ti_ev_prodidx); 1371 sc->ti_ev_prodidx.ti_idx = 0; 1372 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1373 sc->ti_ev_saved_considx = 0; 1374 1375 /* Set up the command ring and producer mailbox. */ 1376 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1377 1378 sc->ti_rdata->ti_cmd_ring = 1379 (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING); 1380 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1381 rcb->ti_flags = 0; 1382 rcb->ti_max_len = 0; 1383 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1384 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1385 } 1386 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1387 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1388 sc->ti_cmd_saved_prodidx = 0; 1389 1390 /* 1391 * Assign the address of the stats refresh buffer. 1392 * We re-use the current stats buffer for this to 1393 * conserve memory. 1394 */ 1395 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1396 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1397 1398 /* Set up the standard receive ring. */ 1399 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1400 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1401 rcb->ti_max_len = TI_FRAMELEN; 1402 rcb->ti_flags = 0; 1403#ifdef TI_CSUM_OFFLOAD 1404 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1405#endif 1406#if NVLAN > 0 1407 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1408#endif 1409 1410 /* Set up the jumbo receive ring. */ 1411 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1412 TI_HOSTADDR(rcb->ti_hostaddr) = 1413 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1414 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1415 rcb->ti_flags = 0; 1416#ifdef TI_CSUM_OFFLOAD 1417 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1418#endif 1419#if NVLAN > 0 1420 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1421#endif 1422 1423 /* 1424 * Set up the mini ring. Only activated on the 1425 * Tigon 2 but the slot in the config block is 1426 * still there on the Tigon 1. 1427 */ 1428 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1429 TI_HOSTADDR(rcb->ti_hostaddr) = 1430 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1431 rcb->ti_max_len = MHLEN; 1432 if (sc->ti_hwrev == TI_HWREV_TIGON) 1433 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1434 else 1435 rcb->ti_flags = 0; 1436#ifdef TI_CSUM_OFFLOAD 1437 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1438#endif 1439#if NVLAN > 0 1440 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1441#endif 1442 1443 /* 1444 * Set up the receive return ring. 1445 */ 1446 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1447 TI_HOSTADDR(rcb->ti_hostaddr) = 1448 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1449 rcb->ti_flags = 0; 1450 rcb->ti_max_len = TI_RETURN_RING_CNT; 1451 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1452 vtophys(&sc->ti_return_prodidx); 1453 1454 /* 1455 * Set up the tx ring. Note: for the Tigon 2, we have the option 1456 * of putting the transmit ring in the host's address space and 1457 * letting the chip DMA it instead of leaving the ring in the NIC's 1458 * memory and accessing it through the shared memory region. We 1459 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1460 * so we have to revert to the shared memory scheme if we detect 1461 * a Tigon 1 chip. 1462 */ 1463 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1464 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1465 sc->ti_rdata->ti_tx_ring_nic = 1466 (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW); 1467 } 1468 bzero((char *)sc->ti_rdata->ti_tx_ring, 1469 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1470 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1471 if (sc->ti_hwrev == TI_HWREV_TIGON) 1472 rcb->ti_flags = 0; 1473 else 1474 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1475#if NVLAN > 0 1476 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1477#endif 1478 rcb->ti_max_len = TI_TX_RING_CNT; 1479 if (sc->ti_hwrev == TI_HWREV_TIGON) 1480 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1481 else 1482 TI_HOSTADDR(rcb->ti_hostaddr) = 1483 vtophys(&sc->ti_rdata->ti_tx_ring); 1484 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1485 vtophys(&sc->ti_tx_considx); 1486 1487 /* Set up tuneables */ 1488 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1489 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1490 (sc->ti_rx_coal_ticks / 10)); 1491 else 1492 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1493 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1494 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1495 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1496 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1497 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1498 1499 /* Turn interrupts on. */ 1500 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1501 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1502 1503 /* Start CPU. */ 1504 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1505 1506 return(0); 1507} 1508 1509/* 1510 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1511 * against our list and return its name if we find a match. 1512 */ 1513static int ti_probe(dev) 1514 device_t dev; 1515{ 1516 struct ti_type *t; 1517 1518 t = ti_devs; 1519 1520 while(t->ti_name != NULL) { 1521 if ((pci_get_vendor(dev) == t->ti_vid) && 1522 (pci_get_device(dev) == t->ti_did)) { 1523 device_set_desc(dev, t->ti_name); 1524 return(0); 1525 } 1526 t++; 1527 } 1528 1529 return(ENXIO); 1530} 1531 1532static int ti_attach(dev) 1533 device_t dev; 1534{ 1535 int s; 1536 u_int32_t command; 1537 struct ifnet *ifp; 1538 struct ti_softc *sc; 1539 int unit, error = 0, rid; 1540 1541 s = splimp(); 1542 1543 sc = device_get_softc(dev); 1544 unit = device_get_unit(dev); 1545 bzero(sc, sizeof(struct ti_softc)); 1546 1547 /* 1548 * Map control/status registers. 1549 */ 1550 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1551 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1552 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1553 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1554 1555 if (!(command & PCIM_CMD_MEMEN)) { 1556 printf("ti%d: failed to enable memory mapping!\n", unit); 1557 error = ENXIO; 1558 goto fail; 1559 } 1560 1561 rid = TI_PCI_LOMEM; 1562 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1563 0, ~0, 1, RF_ACTIVE); 1564 1565 if (sc->ti_res == NULL) { 1566 printf ("ti%d: couldn't map memory\n", unit); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 1571 sc->ti_btag = rman_get_bustag(sc->ti_res); 1572 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1573 1574 /* Allocate interrupt */ 1575 rid = 0; 1576 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1577 RF_SHAREABLE | RF_ACTIVE); 1578 1579 if (sc->ti_irq == NULL) { 1580 printf("ti%d: couldn't map interrupt\n", unit); 1581 error = ENXIO; 1582 goto fail; 1583 } 1584 1585 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1586 ti_intr, sc, &sc->ti_intrhand); 1587 1588 if (error) { 1589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1590 bus_release_resource(dev, SYS_RES_MEMORY, 1591 TI_PCI_LOMEM, sc->ti_res); 1592 printf("ti%d: couldn't set up irq\n", unit); 1593 goto fail; 1594 } 1595 1596 sc->ti_unit = unit; 1597 1598 if (ti_chipinit(sc)) { 1599 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1600 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1601 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1602 bus_release_resource(dev, SYS_RES_MEMORY, 1603 TI_PCI_LOMEM, sc->ti_res); 1604 error = ENXIO; 1605 goto fail; 1606 } 1607 1608 /* Zero out the NIC's on-board SRAM. */ 1609 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1610 1611 /* Init again -- zeroing memory may have clobbered some registers. */ 1612 if (ti_chipinit(sc)) { 1613 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1614 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1615 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1616 bus_release_resource(dev, SYS_RES_MEMORY, 1617 TI_PCI_LOMEM, sc->ti_res); 1618 error = ENXIO; 1619 goto fail; 1620 } 1621 1622 /* 1623 * Get station address from the EEPROM. Note: the manual states 1624 * that the MAC address is at offset 0x8c, however the data is 1625 * stored as two longwords (since that's how it's loaded into 1626 * the NIC). This means the MAC address is actually preceeded 1627 * by two zero bytes. We need to skip over those. 1628 */ 1629 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1630 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1631 printf("ti%d: failed to read station address\n", unit); 1632 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1633 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1634 bus_release_resource(dev, SYS_RES_MEMORY, 1635 TI_PCI_LOMEM, sc->ti_res); 1636 error = ENXIO; 1637 goto fail; 1638 } 1639 1640 /* 1641 * A Tigon chip was detected. Inform the world. 1642 */ 1643 printf("ti%d: Ethernet address: %6D\n", unit, 1644 sc->arpcom.ac_enaddr, ":"); 1645 1646 /* Allocate the general information block and ring buffers. */ 1647 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1648 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1649 1650 if (sc->ti_rdata == NULL) { 1651 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1652 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1653 bus_release_resource(dev, SYS_RES_MEMORY, 1654 TI_PCI_LOMEM, sc->ti_res); 1655 error = ENXIO; 1656 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1657 goto fail; 1658 } 1659 1660 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1661 1662 /* Try to allocate memory for jumbo buffers. */ 1663 if (ti_alloc_jumbo_mem(sc)) { 1664 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1665 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1666 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1667 bus_release_resource(dev, SYS_RES_MEMORY, 1668 TI_PCI_LOMEM, sc->ti_res); 1669 free(sc->ti_rdata, M_DEVBUF); 1670 error = ENXIO; 1671 goto fail; 1672 } 1673 1674 /* Set default tuneable values. */ 1675 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1676 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1677 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1678 sc->ti_rx_max_coal_bds = 64; 1679 sc->ti_tx_max_coal_bds = 128; 1680 sc->ti_tx_buf_ratio = 21; 1681 1682 /* Set up ifnet structure */ 1683 ifp = &sc->arpcom.ac_if; 1684 ifp->if_softc = sc; 1685 ifp->if_unit = sc->ti_unit; 1686 ifp->if_name = "ti"; 1687 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1688 ifp->if_ioctl = ti_ioctl; 1689 ifp->if_output = ether_output; 1690 ifp->if_start = ti_start; 1691 ifp->if_watchdog = ti_watchdog; 1692 ifp->if_init = ti_init; 1693 ifp->if_mtu = ETHERMTU; 1694 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1695 1696 /* Set up ifmedia support. */ 1697 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1698 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1699 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1700 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1701 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1702 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1703 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1704 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1705 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1706 1707 /* 1708 * Call MI attach routines. 1709 */ 1710 if_attach(ifp); 1711 ether_ifattach(ifp); 1712 1713#if NBPF > 0 1714 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1715#endif 1716 1717fail: 1718 splx(s); 1719 1720 return(error); 1721} 1722 1723static int ti_detach(dev) 1724 device_t dev; 1725{ 1726 struct ti_softc *sc; 1727 struct ifnet *ifp; 1728 int s; 1729 1730 s = splimp(); 1731 1732 sc = device_get_softc(dev); 1733 ifp = &sc->arpcom.ac_if; 1734 1735 if_detach(ifp); 1736 ti_stop(sc); 1737 1738 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1739 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1740 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1741 1742 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 1743 free(sc->ti_rdata, M_DEVBUF); 1744 ifmedia_removeall(&sc->ifmedia); 1745 1746 splx(s); 1747 1748 return(0); 1749} 1750 1751/* 1752 * Frame reception handling. This is called if there's a frame 1753 * on the receive return list. 1754 * 1755 * Note: we have to be able to handle three possibilities here: 1756 * 1) the frame is from the mini receive ring (can only happen) 1757 * on Tigon 2 boards) 1758 * 2) the frame is from the jumbo recieve ring 1759 * 3) the frame is from the standard receive ring 1760 */ 1761 1762static void ti_rxeof(sc) 1763 struct ti_softc *sc; 1764{ 1765 struct ifnet *ifp; 1766 struct ti_cmd_desc cmd; 1767 1768 ifp = &sc->arpcom.ac_if; 1769 1770 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1771 struct ti_rx_desc *cur_rx; 1772 u_int32_t rxidx; 1773 struct ether_header *eh; 1774 struct mbuf *m = NULL; 1775#if NVLAN > 0 1776 u_int16_t vlan_tag = 0; 1777 int have_tag = 0; 1778#endif 1779#ifdef TI_CSUM_OFFLOAD 1780 struct ip *ip; 1781#endif 1782 1783 cur_rx = 1784 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1785 rxidx = cur_rx->ti_idx; 1786 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1787 1788#if NVLAN > 0 1789 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1790 have_tag = 1; 1791 vlan_tag = cur_rx->ti_vlan_tag; 1792 } 1793#endif 1794 1795 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1796 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1797 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1798 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1799 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1800 ifp->if_ierrors++; 1801 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1802 continue; 1803 } 1804 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1805 ifp->if_ierrors++; 1806 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1807 continue; 1808 } 1809 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1810 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1811 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1812 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1813 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1814 ifp->if_ierrors++; 1815 ti_newbuf_mini(sc, sc->ti_mini, m); 1816 continue; 1817 } 1818 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1819 ifp->if_ierrors++; 1820 ti_newbuf_mini(sc, sc->ti_mini, m); 1821 continue; 1822 } 1823 } else { 1824 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1825 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1826 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1827 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1828 ifp->if_ierrors++; 1829 ti_newbuf_std(sc, sc->ti_std, m); 1830 continue; 1831 } 1832 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1833 ifp->if_ierrors++; 1834 ti_newbuf_std(sc, sc->ti_std, m); 1835 continue; 1836 } 1837 } 1838 1839 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1840 ifp->if_ipackets++; 1841 eh = mtod(m, struct ether_header *); 1842 m->m_pkthdr.rcvif = ifp; 1843 1844#if NBPF > 0 1845 /* 1846 * Handle BPF listeners. Let the BPF user see the packet, but 1847 * don't pass it up to the ether_input() layer unless it's 1848 * a broadcast packet, multicast packet, matches our ethernet 1849 * address or the interface is in promiscuous mode. 1850 */ 1851 if (ifp->if_bpf) { 1852 bpf_mtap(ifp, m); 1853 if (ifp->if_flags & IFF_PROMISC && 1854 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1855 ETHER_ADDR_LEN) && 1856 (eh->ether_dhost[0] & 1) == 0)) { 1857 m_freem(m); 1858 continue; 1859 } 1860 } 1861#endif 1862 1863 /* Remove header from mbuf and pass it on. */ 1864 m_adj(m, sizeof(struct ether_header)); 1865 1866#ifdef TI_CSUM_OFFLOAD 1867 ip = mtod(m, struct ip *); 1868 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1869 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1870 m->m_flags |= M_HWCKSUM; 1871#endif 1872 1873#if NVLAN > 0 1874 /* 1875 * If we received a packet with a vlan tag, pass it 1876 * to vlan_input() instead of ether_input(). 1877 */ 1878 if (have_tag) { 1879 vlan_input_tag(eh, m, vlan_tag); 1880 have_tag = vlan_tag = 0; 1881 continue; 1882 } 1883#endif 1884 ether_input(ifp, eh, m); 1885 } 1886 1887 /* Only necessary on the Tigon 1. */ 1888 if (sc->ti_hwrev == TI_HWREV_TIGON) 1889 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1890 sc->ti_rx_saved_considx); 1891 1892 TI_UPDATE_STDPROD(sc, sc->ti_std); 1893 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1894 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1895 1896 return; 1897} 1898 1899static void ti_txeof(sc) 1900 struct ti_softc *sc; 1901{ 1902 struct ti_tx_desc *cur_tx = NULL; 1903 struct ifnet *ifp; 1904 1905 ifp = &sc->arpcom.ac_if; 1906 1907 /* 1908 * Go through our tx ring and free mbufs for those 1909 * frames that have been sent. 1910 */ 1911 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1912 u_int32_t idx = 0; 1913 1914 idx = sc->ti_tx_saved_considx; 1915 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1916 if (idx > 383) 1917 CSR_WRITE_4(sc, TI_WINBASE, 1918 TI_TX_RING_BASE + 6144); 1919 else if (idx > 255) 1920 CSR_WRITE_4(sc, TI_WINBASE, 1921 TI_TX_RING_BASE + 4096); 1922 else if (idx > 127) 1923 CSR_WRITE_4(sc, TI_WINBASE, 1924 TI_TX_RING_BASE + 2048); 1925 else 1926 CSR_WRITE_4(sc, TI_WINBASE, 1927 TI_TX_RING_BASE); 1928 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1929 } else 1930 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1931 if (cur_tx->ti_flags & TI_BDFLAG_END) 1932 ifp->if_opackets++; 1933 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1934 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1935 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1936 } 1937 sc->ti_txcnt--; 1938 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1939 ifp->if_timer = 0; 1940 } 1941 1942 if (cur_tx != NULL) 1943 ifp->if_flags &= ~IFF_OACTIVE; 1944 1945 return; 1946} 1947 1948static void ti_intr(xsc) 1949 void *xsc; 1950{ 1951 struct ti_softc *sc; 1952 struct ifnet *ifp; 1953 1954 sc = xsc; 1955 ifp = &sc->arpcom.ac_if; 1956 1957#ifdef notdef 1958 /* Avoid this for now -- checking this register is expensive. */ 1959 /* Make sure this is really our interrupt. */ 1960 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1961 return; 1962#endif 1963 1964 /* Ack interrupt and stop others from occuring. */ 1965 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1966 1967 if (ifp->if_flags & IFF_RUNNING) { 1968 /* Check RX return ring producer/consumer */ 1969 ti_rxeof(sc); 1970 1971 /* Check TX ring producer/consumer */ 1972 ti_txeof(sc); 1973 } 1974 1975 ti_handle_events(sc); 1976 1977 /* Re-enable interrupts. */ 1978 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1979 1980 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1981 ti_start(ifp); 1982 1983 return; 1984} 1985 1986static void ti_stats_update(sc) 1987 struct ti_softc *sc; 1988{ 1989 struct ifnet *ifp; 1990 1991 ifp = &sc->arpcom.ac_if; 1992 1993 ifp->if_collisions += 1994 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1995 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1996 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1997 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1998 ifp->if_collisions; 1999 2000 return; 2001} 2002 2003/* 2004 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2005 * pointers to descriptors. 2006 */ 2007static int ti_encap(sc, m_head, txidx) 2008 struct ti_softc *sc; 2009 struct mbuf *m_head; 2010 u_int32_t *txidx; 2011{ 2012 struct ti_tx_desc *f = NULL; 2013 struct mbuf *m; 2014 u_int32_t frag, cur, cnt = 0; 2015#if NVLAN > 0 2016 struct ifvlan *ifv = NULL; 2017 2018 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2019 m_head->m_pkthdr.rcvif != NULL && 2020 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2021 ifv = m_head->m_pkthdr.rcvif->if_softc; 2022#endif 2023 2024 m = m_head; 2025 cur = frag = *txidx; 2026 2027 /* 2028 * Start packing the mbufs in this chain into 2029 * the fragment pointers. Stop when we run out 2030 * of fragments or hit the end of the mbuf chain. 2031 */ 2032 for (m = m_head; m != NULL; m = m->m_next) { 2033 if (m->m_len != 0) { 2034 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2035 if (frag > 383) 2036 CSR_WRITE_4(sc, TI_WINBASE, 2037 TI_TX_RING_BASE + 6144); 2038 else if (frag > 255) 2039 CSR_WRITE_4(sc, TI_WINBASE, 2040 TI_TX_RING_BASE + 4096); 2041 else if (frag > 127) 2042 CSR_WRITE_4(sc, TI_WINBASE, 2043 TI_TX_RING_BASE + 2048); 2044 else 2045 CSR_WRITE_4(sc, TI_WINBASE, 2046 TI_TX_RING_BASE); 2047 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2048 } else 2049 f = &sc->ti_rdata->ti_tx_ring[frag]; 2050 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2051 break; 2052 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2053 f->ti_len = m->m_len; 2054 f->ti_flags = 0; 2055#if NVLAN > 0 2056 if (ifv != NULL) { 2057 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2058 f->ti_vlan_tag = ifv->ifv_tag; 2059 } else { 2060 f->ti_vlan_tag = 0; 2061 } 2062#endif 2063 /* 2064 * Sanity check: avoid coming within 16 descriptors 2065 * of the end of the ring. 2066 */ 2067 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2068 return(ENOBUFS); 2069 cur = frag; 2070 TI_INC(frag, TI_TX_RING_CNT); 2071 cnt++; 2072 } 2073 } 2074 2075 if (m != NULL) 2076 return(ENOBUFS); 2077 2078 if (frag == sc->ti_tx_saved_considx) 2079 return(ENOBUFS); 2080 2081 if (sc->ti_hwrev == TI_HWREV_TIGON) 2082 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2083 TI_BDFLAG_END; 2084 else 2085 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2086 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2087 sc->ti_txcnt += cnt; 2088 2089 *txidx = frag; 2090 2091 return(0); 2092} 2093 2094/* 2095 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2096 * to the mbuf data regions directly in the transmit descriptors. 2097 */ 2098static void ti_start(ifp) 2099 struct ifnet *ifp; 2100{ 2101 struct ti_softc *sc; 2102 struct mbuf *m_head = NULL; 2103 u_int32_t prodidx = 0; 2104 2105 sc = ifp->if_softc; 2106 2107 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2108 2109 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2110 IF_DEQUEUE(&ifp->if_snd, m_head); 2111 if (m_head == NULL) 2112 break; 2113 2114 /* 2115 * Pack the data into the transmit ring. If we 2116 * don't have room, set the OACTIVE flag and wait 2117 * for the NIC to drain the ring. 2118 */ 2119 if (ti_encap(sc, m_head, &prodidx)) { 2120 IF_PREPEND(&ifp->if_snd, m_head); 2121 ifp->if_flags |= IFF_OACTIVE; 2122 break; 2123 } 2124 2125 /* 2126 * If there's a BPF listener, bounce a copy of this frame 2127 * to him. 2128 */ 2129#if NBPF > 0 2130 if (ifp->if_bpf) 2131 bpf_mtap(ifp, m_head); 2132#endif 2133 } 2134 2135 /* Transmit */ 2136 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2137 2138 /* 2139 * Set a timeout in case the chip goes out to lunch. 2140 */ 2141 ifp->if_timer = 5; 2142 2143 return; 2144} 2145 2146static void ti_init(xsc) 2147 void *xsc; 2148{ 2149 struct ti_softc *sc = xsc; 2150 int s; 2151 2152 s = splimp(); 2153 2154 /* Cancel pending I/O and flush buffers. */ 2155 ti_stop(sc); 2156 2157 /* Init the gen info block, ring control blocks and firmware. */ 2158 if (ti_gibinit(sc)) { 2159 printf("ti%d: initialization failure\n", sc->ti_unit); 2160 splx(s); 2161 return; 2162 } 2163 2164 splx(s); 2165 2166 return; 2167} 2168 2169static void ti_init2(sc) 2170 struct ti_softc *sc; 2171{ 2172 struct ti_cmd_desc cmd; 2173 struct ifnet *ifp; 2174 u_int16_t *m; 2175 struct ifmedia *ifm; 2176 int tmp; 2177 2178 ifp = &sc->arpcom.ac_if; 2179 2180 /* Specify MTU and interface index. */ 2181 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2182 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2183 ETHER_HDR_LEN + ETHER_CRC_LEN); 2184 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2185 2186 /* Load our MAC address. */ 2187 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2188 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2189 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2190 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2191 2192 /* Enable or disable promiscuous mode as needed. */ 2193 if (ifp->if_flags & IFF_PROMISC) { 2194 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2195 } else { 2196 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2197 } 2198 2199 /* Program multicast filter. */ 2200 ti_setmulti(sc); 2201 2202 /* 2203 * If this is a Tigon 1, we should tell the 2204 * firmware to use software packet filtering. 2205 */ 2206 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2207 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2208 } 2209 2210 /* Init RX ring. */ 2211 ti_init_rx_ring_std(sc); 2212 2213 /* Init jumbo RX ring. */ 2214 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2215 ti_init_rx_ring_jumbo(sc); 2216 2217 /* 2218 * If this is a Tigon 2, we can also configure the 2219 * mini ring. 2220 */ 2221 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2222 ti_init_rx_ring_mini(sc); 2223 2224 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2225 sc->ti_rx_saved_considx = 0; 2226 2227 /* Init TX ring. */ 2228 ti_init_tx_ring(sc); 2229 2230 /* Tell firmware we're alive. */ 2231 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2232 2233 /* Enable host interrupts. */ 2234 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2235 2236 ifp->if_flags |= IFF_RUNNING; 2237 ifp->if_flags &= ~IFF_OACTIVE; 2238 2239 /* 2240 * Make sure to set media properly. We have to do this 2241 * here since we have to issue commands in order to set 2242 * the link negotiation and we can't issue commands until 2243 * the firmware is running. 2244 */ 2245 ifm = &sc->ifmedia; 2246 tmp = ifm->ifm_media; 2247 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2248 ti_ifmedia_upd(ifp); 2249 ifm->ifm_media = tmp; 2250 2251 return; 2252} 2253 2254/* 2255 * Set media options. 2256 */ 2257static int ti_ifmedia_upd(ifp) 2258 struct ifnet *ifp; 2259{ 2260 struct ti_softc *sc; 2261 struct ifmedia *ifm; 2262 struct ti_cmd_desc cmd; 2263 2264 sc = ifp->if_softc; 2265 ifm = &sc->ifmedia; 2266 2267 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2268 return(EINVAL); 2269 2270 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2271 case IFM_AUTO: 2272 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2273 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2274 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2275 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2276 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2277 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2278 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2279 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2280 break; 2281 case IFM_1000_SX: 2282 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2283 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2284 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2285 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2286 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2287 break; 2288 case IFM_100_FX: 2289 case IFM_10_FL: 2290 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2291 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2292 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2293 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2294 } else { 2295 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2296 } 2297 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2298 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2299 } else { 2300 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2301 } 2302 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2303 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2304 break; 2305 } 2306 2307 return(0); 2308} 2309 2310/* 2311 * Report current media status. 2312 */ 2313static void ti_ifmedia_sts(ifp, ifmr) 2314 struct ifnet *ifp; 2315 struct ifmediareq *ifmr; 2316{ 2317 struct ti_softc *sc; 2318 2319 sc = ifp->if_softc; 2320 2321 ifmr->ifm_status = IFM_AVALID; 2322 ifmr->ifm_active = IFM_ETHER; 2323 2324 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2325 return; 2326 2327 ifmr->ifm_status |= IFM_ACTIVE; 2328 2329 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2330 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2331 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2332 u_int32_t media; 2333 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2334 if (media & TI_LNK_100MB) 2335 ifmr->ifm_active |= IFM_100_FX; 2336 if (media & TI_LNK_10MB) 2337 ifmr->ifm_active |= IFM_10_FL; 2338 if (media & TI_LNK_FULL_DUPLEX) 2339 ifmr->ifm_active |= IFM_FDX; 2340 if (media & TI_LNK_HALF_DUPLEX) 2341 ifmr->ifm_active |= IFM_HDX; 2342 } 2343 2344 return; 2345} 2346 2347static int ti_ioctl(ifp, command, data) 2348 struct ifnet *ifp; 2349 u_long command; 2350 caddr_t data; 2351{ 2352 struct ti_softc *sc = ifp->if_softc; 2353 struct ifreq *ifr = (struct ifreq *) data; 2354 int s, error = 0; 2355 struct ti_cmd_desc cmd; 2356 2357 s = splimp(); 2358 2359 switch(command) { 2360 case SIOCSIFADDR: 2361 case SIOCGIFADDR: 2362 error = ether_ioctl(ifp, command, data); 2363 break; 2364 case SIOCSIFMTU: 2365 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2366 error = EINVAL; 2367 else { 2368 ifp->if_mtu = ifr->ifr_mtu; 2369 ti_init(sc); 2370 } 2371 break; 2372 case SIOCSIFFLAGS: 2373 if (ifp->if_flags & IFF_UP) { 2374 /* 2375 * If only the state of the PROMISC flag changed, 2376 * then just use the 'set promisc mode' command 2377 * instead of reinitializing the entire NIC. Doing 2378 * a full re-init means reloading the firmware and 2379 * waiting for it to start up, which may take a 2380 * second or two. 2381 */ 2382 if (ifp->if_flags & IFF_RUNNING && 2383 ifp->if_flags & IFF_PROMISC && 2384 !(sc->ti_if_flags & IFF_PROMISC)) { 2385 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2386 TI_CMD_CODE_PROMISC_ENB, 0); 2387 } else if (ifp->if_flags & IFF_RUNNING && 2388 !(ifp->if_flags & IFF_PROMISC) && 2389 sc->ti_if_flags & IFF_PROMISC) { 2390 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2391 TI_CMD_CODE_PROMISC_DIS, 0); 2392 } else 2393 ti_init(sc); 2394 } else { 2395 if (ifp->if_flags & IFF_RUNNING) { 2396 ti_stop(sc); 2397 } 2398 } 2399 sc->ti_if_flags = ifp->if_flags; 2400 error = 0; 2401 break; 2402 case SIOCADDMULTI: 2403 case SIOCDELMULTI: 2404 if (ifp->if_flags & IFF_RUNNING) { 2405 ti_setmulti(sc); 2406 error = 0; 2407 } 2408 break; 2409 case SIOCSIFMEDIA: 2410 case SIOCGIFMEDIA: 2411 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2412 break; 2413 default: 2414 error = EINVAL; 2415 break; 2416 } 2417 2418 (void)splx(s); 2419 2420 return(error); 2421} 2422 2423static void ti_watchdog(ifp) 2424 struct ifnet *ifp; 2425{ 2426 struct ti_softc *sc; 2427 2428 sc = ifp->if_softc; 2429 2430 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2431 ti_stop(sc); 2432 ti_init(sc); 2433 2434 ifp->if_oerrors++; 2435 2436 return; 2437} 2438 2439/* 2440 * Stop the adapter and free any mbufs allocated to the 2441 * RX and TX lists. 2442 */ 2443static void ti_stop(sc) 2444 struct ti_softc *sc; 2445{ 2446 struct ifnet *ifp; 2447 struct ti_cmd_desc cmd; 2448 2449 ifp = &sc->arpcom.ac_if; 2450 2451 /* Disable host interrupts. */ 2452 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2453 /* 2454 * Tell firmware we're shutting down. 2455 */ 2456 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2457 2458 /* Halt and reinitialize. */ 2459 ti_chipinit(sc); 2460 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2461 ti_chipinit(sc); 2462 2463 /* Free the RX lists. */ 2464 ti_free_rx_ring_std(sc); 2465 2466 /* Free jumbo RX list. */ 2467 ti_free_rx_ring_jumbo(sc); 2468 2469 /* Free mini RX list. */ 2470 ti_free_rx_ring_mini(sc); 2471 2472 /* Free TX buffers. */ 2473 ti_free_tx_ring(sc); 2474 2475 sc->ti_ev_prodidx.ti_idx = 0; 2476 sc->ti_return_prodidx.ti_idx = 0; 2477 sc->ti_tx_considx.ti_idx = 0; 2478 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2479 2480 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2481 2482 return; 2483} 2484 2485/* 2486 * Stop all chip I/O so that the kernel's probe routines don't 2487 * get confused by errant DMAs when rebooting. 2488 */ 2489static void ti_shutdown(dev) 2490 device_t dev; 2491{ 2492 struct ti_softc *sc; 2493 2494 sc = device_get_softc(dev); 2495 2496 ti_chipinit(sc); 2497 2498 return; 2499} 2500