if_ti.c revision 49011
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_ti.c,v 1.114 1999/07/05 19:20:31 wpaul Exp $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "bpf.h" 82#include "vlan.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/socket.h> 91#include <sys/queue.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#if NBPF > 0 100#include <net/bpf.h> 101#endif 102 103#if NVLAN > 0 104#include <net/if_types.h> 105#include <net/if_vlan_var.h> 106#endif 107 108#include <netinet/in_systm.h> 109#include <netinet/in.h> 110#include <netinet/ip.h> 111 112#include <vm/vm.h> /* for vtophys */ 113#include <vm/pmap.h> /* for vtophys */ 114#include <machine/clock.h> /* for DELAY */ 115#include <machine/bus_memio.h> 116#include <machine/bus.h> 117#include <machine/resource.h> 118#include <sys/bus.h> 119#include <sys/rman.h> 120 121#include <pci/pcireg.h> 122#include <pci/pcivar.h> 123 124#include <pci/if_tireg.h> 125#include <pci/ti_fw.h> 126#include <pci/ti_fw2.h> 127 128#ifdef M_HWCKSUM 129/*#define TI_CSUM_OFFLOAD*/ 130#endif 131 132#if !defined(lint) 133static const char rcsid[] = 134 "$Id: if_ti.c,v 1.114 1999/07/05 19:20:31 wpaul Exp $"; 135#endif 136 137/* 138 * Various supported device vendors/types and their names. 139 */ 140 141static struct ti_type ti_devs[] = { 142 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 143 "Alteon AceNIC Gigabit Ethernet" }, 144 { TC_VENDORID, TC_DEVICEID_3C985, 145 "3Com 3c985-SX Gigabit Ethernet" }, 146 { NG_VENDORID, NG_DEVICEID_GA620, 147 "Netgear GA620 Gigabit Ethernet" }, 148 { SGI_VENDORID, SGI_DEVICEID_TIGON, 149 "Silicon Graphics Gigabit Ethernet" }, 150 { 0, 0, NULL } 151}; 152 153static int ti_probe __P((device_t)); 154static int ti_attach __P((device_t)); 155static int ti_detach __P((device_t)); 156static void ti_txeof __P((struct ti_softc *)); 157static void ti_rxeof __P((struct ti_softc *)); 158 159static void ti_stats_update __P((struct ti_softc *)); 160static int ti_encap __P((struct ti_softc *, struct mbuf *, 161 u_int32_t *)); 162 163static void ti_intr __P((void *)); 164static void ti_start __P((struct ifnet *)); 165static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 166static void ti_init __P((void *)); 167static void ti_init2 __P((struct ti_softc *)); 168static void ti_stop __P((struct ti_softc *)); 169static void ti_watchdog __P((struct ifnet *)); 170static void ti_shutdown __P((device_t)); 171static int ti_ifmedia_upd __P((struct ifnet *)); 172static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 175static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 176 int, u_int8_t *)); 177static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 178 179static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 180static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 181static void ti_setmulti __P((struct ti_softc *)); 182 183static void ti_mem __P((struct ti_softc *, u_int32_t, 184 u_int32_t, caddr_t)); 185static void ti_loadfw __P((struct ti_softc *)); 186static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 187static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int)); 189static void ti_handle_events __P((struct ti_softc *)); 190static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 191static void *ti_jalloc __P((struct ti_softc *)); 192static void ti_jfree __P((caddr_t, u_int)); 193static void ti_jref __P((caddr_t, u_int)); 194static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 195static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 196static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 197static int ti_init_rx_ring_std __P((struct ti_softc *)); 198static void ti_free_rx_ring_std __P((struct ti_softc *)); 199static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 200static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 201static int ti_init_rx_ring_mini __P((struct ti_softc *)); 202static void ti_free_rx_ring_mini __P((struct ti_softc *)); 203static void ti_free_tx_ring __P((struct ti_softc *)); 204static int ti_init_tx_ring __P((struct ti_softc *)); 205 206static int ti_64bitslot_war __P((struct ti_softc *)); 207static int ti_chipinit __P((struct ti_softc *)); 208static int ti_gibinit __P((struct ti_softc *)); 209 210static device_method_t ti_methods[] = { 211 /* Device interface */ 212 DEVMETHOD(device_probe, ti_probe), 213 DEVMETHOD(device_attach, ti_attach), 214 DEVMETHOD(device_detach, ti_detach), 215 DEVMETHOD(device_shutdown, ti_shutdown), 216 { 0, 0 } 217}; 218 219static driver_t ti_driver = { 220 "ti", 221 ti_methods, 222 sizeof(struct ti_softc) 223}; 224 225static devclass_t ti_devclass; 226 227DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 228 229/* 230 * Send an instruction or address to the EEPROM, check for ACK. 231 */ 232static u_int32_t ti_eeprom_putbyte(sc, byte) 233 struct ti_softc *sc; 234 int byte; 235{ 236 register int i, ack = 0; 237 238 /* 239 * Make sure we're in TX mode. 240 */ 241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 242 243 /* 244 * Feed in each bit and stobe the clock. 245 */ 246 for (i = 0x80; i; i >>= 1) { 247 if (byte & i) { 248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 249 } else { 250 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 251 } 252 DELAY(1); 253 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 254 DELAY(1); 255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 256 } 257 258 /* 259 * Turn off TX mode. 260 */ 261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 262 263 /* 264 * Check for ack. 265 */ 266 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 267 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 268 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 269 270 return(ack); 271} 272 273/* 274 * Read a byte of data stored in the EEPROM at address 'addr.' 275 * We have to send two address bytes since the EEPROM can hold 276 * more than 256 bytes of data. 277 */ 278static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 279 struct ti_softc *sc; 280 int addr; 281 u_int8_t *dest; 282{ 283 register int i; 284 u_int8_t byte = 0; 285 286 EEPROM_START; 287 288 /* 289 * Send write control code to EEPROM. 290 */ 291 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 292 printf("ti%d: failed to send write command, status: %x\n", 293 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return(1); 295 } 296 297 /* 298 * Send first byte of address of byte we want to read. 299 */ 300 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 301 printf("ti%d: failed to send address, status: %x\n", 302 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 /* 306 * Send second byte address of byte we want to read. 307 */ 308 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 309 printf("ti%d: failed to send address, status: %x\n", 310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 311 return(1); 312 } 313 314 EEPROM_STOP; 315 EEPROM_START; 316 /* 317 * Send read control code to EEPROM. 318 */ 319 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 320 printf("ti%d: failed to send read command, status: %x\n", 321 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 322 return(1); 323 } 324 325 /* 326 * Start reading bits from EEPROM. 327 */ 328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 329 for (i = 0x80; i; i >>= 1) { 330 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 331 DELAY(1); 332 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 333 byte |= i; 334 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 335 DELAY(1); 336 } 337 338 EEPROM_STOP; 339 340 /* 341 * No ACK generated for read, so just return byte. 342 */ 343 344 *dest = byte; 345 346 return(0); 347} 348 349/* 350 * Read a sequence of bytes from the EEPROM. 351 */ 352static int ti_read_eeprom(sc, dest, off, cnt) 353 struct ti_softc *sc; 354 caddr_t dest; 355 int off; 356 int cnt; 357{ 358 int err = 0, i; 359 u_int8_t byte = 0; 360 361 for (i = 0; i < cnt; i++) { 362 err = ti_eeprom_getbyte(sc, off + i, &byte); 363 if (err) 364 break; 365 *(dest + i) = byte; 366 } 367 368 return(err ? 1 : 0); 369} 370 371/* 372 * NIC memory access function. Can be used to either clear a section 373 * of NIC local memory or (if buf is non-NULL) copy data into it. 374 */ 375static void ti_mem(sc, addr, len, buf) 376 struct ti_softc *sc; 377 u_int32_t addr, len; 378 caddr_t buf; 379{ 380 int segptr, segsize, cnt; 381 caddr_t ti_winbase, ptr; 382 383 segptr = addr; 384 cnt = len; 385#ifdef __i386__ 386 ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW); 387#endif 388#ifdef __alpha__ 389 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 390#endif 391 ptr = buf; 392 393 while(cnt) { 394 if (cnt < TI_WINLEN) 395 segsize = cnt; 396 else 397 segsize = TI_WINLEN - (segptr % TI_WINLEN); 398 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 399 if (buf == NULL) 400 bzero((char *)ti_winbase + (segptr & 401 (TI_WINLEN - 1)), segsize); 402 else { 403 bcopy((char *)ptr, (char *)ti_winbase + 404 (segptr & (TI_WINLEN - 1)), segsize); 405 ptr += segsize; 406 } 407 segptr += segsize; 408 cnt -= segsize; 409 } 410 411 return; 412} 413 414/* 415 * Load firmware image into the NIC. Check that the firmware revision 416 * is acceptable and see if we want the firmware for the Tigon 1 or 417 * Tigon 2. 418 */ 419static void ti_loadfw(sc) 420 struct ti_softc *sc; 421{ 422 switch(sc->ti_hwrev) { 423 case TI_HWREV_TIGON: 424 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 425 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 426 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 427 printf("ti%d: firmware revision mismatch; want " 428 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 429 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 430 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 431 tigonFwReleaseMinor, tigonFwReleaseFix); 432 return; 433 } 434 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 435 (caddr_t)tigonFwText); 436 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 437 (caddr_t)tigonFwData); 438 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 439 (caddr_t)tigonFwRodata); 440 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 441 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 442 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 443 break; 444 case TI_HWREV_TIGON_II: 445 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 446 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 447 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 448 printf("ti%d: firmware revision mismatch; want " 449 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 450 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 451 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 452 tigon2FwReleaseMinor, tigon2FwReleaseFix); 453 return; 454 } 455 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 456 (caddr_t)tigon2FwText); 457 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 458 (caddr_t)tigon2FwData); 459 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 460 (caddr_t)tigon2FwRodata); 461 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 462 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 463 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 464 break; 465 default: 466 printf("ti%d: can't load firmware: unknown hardware rev\n", 467 sc->ti_unit); 468 break; 469 } 470 471 return; 472} 473 474/* 475 * Send the NIC a command via the command ring. 476 */ 477static void ti_cmd(sc, cmd) 478 struct ti_softc *sc; 479 struct ti_cmd_desc *cmd; 480{ 481 u_int32_t index; 482 483 if (sc->ti_rdata->ti_cmd_ring == NULL) 484 return; 485 486 index = sc->ti_cmd_saved_prodidx; 487 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 488 TI_INC(index, TI_CMD_RING_CNT); 489 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 490 sc->ti_cmd_saved_prodidx = index; 491 492 return; 493} 494 495/* 496 * Send the NIC an extended command. The 'len' parameter specifies the 497 * number of command slots to include after the initial command. 498 */ 499static void ti_cmd_ext(sc, cmd, arg, len) 500 struct ti_softc *sc; 501 struct ti_cmd_desc *cmd; 502 caddr_t arg; 503 int len; 504{ 505 u_int32_t index; 506 register int i; 507 508 if (sc->ti_rdata->ti_cmd_ring == NULL) 509 return; 510 511 index = sc->ti_cmd_saved_prodidx; 512 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 513 TI_INC(index, TI_CMD_RING_CNT); 514 for (i = 0; i < len; i++) { 515 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 516 *(u_int32_t *)(&arg[i * 4])); 517 TI_INC(index, TI_CMD_RING_CNT); 518 } 519 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 520 sc->ti_cmd_saved_prodidx = index; 521 522 return; 523} 524 525/* 526 * Handle events that have triggered interrupts. 527 */ 528static void ti_handle_events(sc) 529 struct ti_softc *sc; 530{ 531 struct ti_event_desc *e; 532 533 if (sc->ti_rdata->ti_event_ring == NULL) 534 return; 535 536 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 537 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 538 switch(e->ti_event) { 539 case TI_EV_LINKSTAT_CHANGED: 540 sc->ti_linkstat = e->ti_code; 541 if (e->ti_code == TI_EV_CODE_LINK_UP) 542 printf("ti%d: 10/100 link up\n", sc->ti_unit); 543 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 544 printf("ti%d: gigabit link up\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 546 printf("ti%d: link down\n", sc->ti_unit); 547 break; 548 case TI_EV_ERROR: 549 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 550 printf("ti%d: invalid command\n", sc->ti_unit); 551 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 552 printf("ti%d: unknown command\n", sc->ti_unit); 553 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 554 printf("ti%d: bad config data\n", sc->ti_unit); 555 break; 556 case TI_EV_FIRMWARE_UP: 557 ti_init2(sc); 558 break; 559 case TI_EV_STATS_UPDATED: 560 ti_stats_update(sc); 561 break; 562 case TI_EV_RESET_JUMBO_RING: 563 case TI_EV_MCAST_UPDATED: 564 /* Who cares. */ 565 break; 566 default: 567 printf("ti%d: unknown event: %d\n", 568 sc->ti_unit, e->ti_event); 569 break; 570 } 571 /* Advance the consumer index. */ 572 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 573 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 574 } 575 576 return; 577} 578 579/* 580 * Memory management for the jumbo receive ring is a pain in the 581 * butt. We need to allocate at least 9018 bytes of space per frame, 582 * _and_ it has to be contiguous (unless you use the extended 583 * jumbo descriptor format). Using malloc() all the time won't 584 * work: malloc() allocates memory in powers of two, which means we 585 * would end up wasting a considerable amount of space by allocating 586 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 587 * to do our own memory management. 588 * 589 * The driver needs to allocate a contiguous chunk of memory at boot 590 * time. We then chop this up ourselves into 9K pieces and use them 591 * as external mbuf storage. 592 * 593 * One issue here is how much memory to allocate. The jumbo ring has 594 * 256 slots in it, but at 9K per slot than can consume over 2MB of 595 * RAM. This is a bit much, especially considering we also need 596 * RAM for the standard ring and mini ring (on the Tigon 2). To 597 * save space, we only actually allocate enough memory for 64 slots 598 * by default, which works out to between 500 and 600K. This can 599 * be tuned by changing a #define in if_tireg.h. 600 */ 601 602static int ti_alloc_jumbo_mem(sc) 603 struct ti_softc *sc; 604{ 605 caddr_t ptr; 606 register int i; 607 struct ti_jpool_entry *entry; 608 609 /* Grab a big chunk o' storage. */ 610 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 611 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 612 613 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 614 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 615 return(ENOBUFS); 616 } 617 618 SLIST_INIT(&sc->ti_jfree_listhead); 619 SLIST_INIT(&sc->ti_jinuse_listhead); 620 621 /* 622 * Now divide it up into 9K pieces and save the addresses 623 * in an array. Note that we play an evil trick here by using 624 * the first few bytes in the buffer to hold the the address 625 * of the softc structure for this interface. This is because 626 * ti_jfree() needs it, but it is called by the mbuf management 627 * code which will not pass it to us explicitly. 628 */ 629 ptr = sc->ti_cdata.ti_jumbo_buf; 630 for (i = 0; i < TI_JSLOTS; i++) { 631 u_int64_t **aptr; 632 aptr = (u_int64_t **)ptr; 633 aptr[0] = (u_int64_t *)sc; 634 ptr += sizeof(u_int64_t); 635 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 636 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 637 ptr += (TI_JLEN - sizeof(u_int64_t)); 638 entry = malloc(sizeof(struct ti_jpool_entry), 639 M_DEVBUF, M_NOWAIT); 640 if (entry == NULL) { 641 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 642 sc->ti_cdata.ti_jumbo_buf = NULL; 643 printf("ti%d: no memory for jumbo " 644 "buffer queue!\n", sc->ti_unit); 645 return(ENOBUFS); 646 } 647 entry->slot = i; 648 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 649 } 650 651 return(0); 652} 653 654/* 655 * Allocate a jumbo buffer. 656 */ 657static void *ti_jalloc(sc) 658 struct ti_softc *sc; 659{ 660 struct ti_jpool_entry *entry; 661 662 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 663 664 if (entry == NULL) { 665 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 666 return(NULL); 667 } 668 669 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 670 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 671 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 672 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 673} 674 675/* 676 * Adjust usage count on a jumbo buffer. In general this doesn't 677 * get used much because our jumbo buffers don't get passed around 678 * too much, but it's implemented for correctness. 679 */ 680static void ti_jref(buf, size) 681 caddr_t buf; 682 u_int size; 683{ 684 struct ti_softc *sc; 685 u_int64_t **aptr; 686 register int i; 687 688 /* Extract the softc struct pointer. */ 689 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 690 sc = (struct ti_softc *)(aptr[0]); 691 692 if (sc == NULL) 693 panic("ti_jref: can't find softc pointer!"); 694 695 if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 696 panic("ti_jref: adjusting refcount of buf of wrong size!"); 697 698 /* calculate the slot this buffer belongs to */ 699 700 i = ((vm_offset_t)aptr 701 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 702 703 if ((i < 0) || (i >= TI_JSLOTS)) 704 panic("ti_jref: asked to reference buffer " 705 "that we don't manage!"); 706 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 707 panic("ti_jref: buffer already free!"); 708 else 709 sc->ti_cdata.ti_jslots[i].ti_inuse++; 710 711 return; 712} 713 714/* 715 * Release a jumbo buffer. 716 */ 717static void ti_jfree(buf, size) 718 caddr_t buf; 719 u_int size; 720{ 721 struct ti_softc *sc; 722 u_int64_t **aptr; 723 int i; 724 struct ti_jpool_entry *entry; 725 726 /* Extract the softc struct pointer. */ 727 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 728 sc = (struct ti_softc *)(aptr[0]); 729 730 if (sc == NULL) 731 panic("ti_jfree: can't find softc pointer!"); 732 733 if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 734 panic("ti_jfree: freeing buffer of wrong size!"); 735 736 /* calculate the slot this buffer belongs to */ 737 738 i = ((vm_offset_t)aptr 739 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 740 741 if ((i < 0) || (i >= TI_JSLOTS)) 742 panic("ti_jfree: asked to free buffer that we don't manage!"); 743 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 744 panic("ti_jfree: buffer already free!"); 745 else { 746 sc->ti_cdata.ti_jslots[i].ti_inuse--; 747 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 748 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 749 if (entry == NULL) 750 panic("ti_jfree: buffer not in use!"); 751 entry->slot = i; 752 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 753 jpool_entries); 754 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 755 entry, jpool_entries); 756 } 757 } 758 759 return; 760} 761 762 763/* 764 * Intialize a standard receive ring descriptor. 765 */ 766static int ti_newbuf_std(sc, i, m) 767 struct ti_softc *sc; 768 int i; 769 struct mbuf *m; 770{ 771 struct mbuf *m_new = NULL; 772 struct ti_rx_desc *r; 773 774 if (m != NULL) { 775 m_new = m; 776 } else { 777 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 778 if (m_new == NULL) { 779 printf("ti%d: mbuf allocation failed " 780 "-- packet dropped!\n", sc->ti_unit); 781 return(ENOBUFS); 782 } 783 784 MCLGET(m_new, M_DONTWAIT); 785 if (!(m_new->m_flags & M_EXT)) { 786 printf("ti%d: cluster allocation failed " 787 "-- packet dropped!\n", sc->ti_unit); 788 m_freem(m_new); 789 return(ENOBUFS); 790 } 791 } 792 793 m_adj(m_new, ETHER_ALIGN); 794 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 795 r = &sc->ti_rdata->ti_rx_std_ring[i]; 796 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 797 r->ti_type = TI_BDTYPE_RECV_BD; 798#ifdef TI_CSUM_OFFLOAD 799 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 800#else 801 r->ti_flags = 0; 802#endif 803 r->ti_len = MCLBYTES - ETHER_ALIGN; 804 r->ti_idx = i; 805 806 return(0); 807} 808 809/* 810 * Intialize a mini receive ring descriptor. This only applies to 811 * the Tigon 2. 812 */ 813static int ti_newbuf_mini(sc, i, m) 814 struct ti_softc *sc; 815 int i; 816 struct mbuf *m; 817{ 818 struct mbuf *m_new = NULL; 819 struct ti_rx_desc *r; 820 821 if (m != NULL) { 822 m_new = m; 823 } else { 824 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 825 if (m_new == NULL) { 826 printf("ti%d: mbuf allocation failed " 827 "-- packet dropped!\n", sc->ti_unit); 828 return(ENOBUFS); 829 } 830 } 831 m_adj(m_new, ETHER_ALIGN); 832 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 833 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 834 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 835 r->ti_type = TI_BDTYPE_RECV_BD; 836 r->ti_flags = TI_BDFLAG_MINI_RING; 837#ifdef TI_CSUM_OFFLOAD 838 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 839#endif 840 r->ti_len = MHLEN - ETHER_ALIGN; 841 r->ti_idx = i; 842 843 return(0); 844} 845 846/* 847 * Initialize a jumbo receive ring descriptor. This allocates 848 * a jumbo buffer from the pool managed internally by the driver. 849 */ 850static int ti_newbuf_jumbo(sc, i, m) 851 struct ti_softc *sc; 852 int i; 853 struct mbuf *m; 854{ 855 struct mbuf *m_new = NULL; 856 struct ti_rx_desc *r; 857 858 if (m != NULL) { 859 m_new = m; 860 } else { 861 caddr_t *buf = NULL; 862 863 /* Allocate the mbuf. */ 864 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 865 if (m_new == NULL) { 866 printf("ti%d: mbuf allocation failed " 867 "-- packet dropped!\n", sc->ti_unit); 868 return(ENOBUFS); 869 } 870 871 /* Allocate the jumbo buffer */ 872 buf = ti_jalloc(sc); 873 if (buf == NULL) { 874 m_freem(m_new); 875 printf("ti%d: jumbo allocation failed " 876 "-- packet dropped!\n", sc->ti_unit); 877 return(ENOBUFS); 878 } 879 880 /* Attach the buffer to the mbuf. */ 881 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 882 m_new->m_data += ETHER_ALIGN; 883 m_new->m_flags |= M_EXT; 884 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 885 m_new->m_ext.ext_free = ti_jfree; 886 m_new->m_ext.ext_ref = ti_jref; 887 } 888 889 /* Set up the descriptor. */ 890 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 891 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 892 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 893 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 894 r->ti_flags = TI_BDFLAG_JUMBO_RING; 895#ifdef TI_CSUM_OFFLOAD 896 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 897#endif 898 r->ti_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 899 r->ti_idx = i; 900 901 return(0); 902} 903 904/* 905 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 906 * that's 1MB or memory, which is a lot. For now, we fill only the first 907 * 256 ring entries and hope that our CPU is fast enough to keep up with 908 * the NIC. 909 */ 910static int ti_init_rx_ring_std(sc) 911 struct ti_softc *sc; 912{ 913 register int i; 914 struct ti_cmd_desc cmd; 915 916 for (i = 0; i < TI_SSLOTS; i++) { 917 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 918 return(ENOBUFS); 919 }; 920 921 TI_UPDATE_STDPROD(sc, i - 1); 922 sc->ti_std = i - 1; 923 924 return(0); 925} 926 927static void ti_free_rx_ring_std(sc) 928 struct ti_softc *sc; 929{ 930 register int i; 931 932 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 933 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 934 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 935 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 936 } 937 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 938 sizeof(struct ti_rx_desc)); 939 } 940 941 return; 942} 943 944static int ti_init_rx_ring_jumbo(sc) 945 struct ti_softc *sc; 946{ 947 register int i; 948 struct ti_cmd_desc cmd; 949 950 for (i = 0; i < (TI_JSLOTS - 20); i++) { 951 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 952 return(ENOBUFS); 953 }; 954 955 TI_UPDATE_JUMBOPROD(sc, i - 1); 956 sc->ti_jumbo = i - 1; 957 958 return(0); 959} 960 961static void ti_free_rx_ring_jumbo(sc) 962 struct ti_softc *sc; 963{ 964 register int i; 965 966 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 967 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 968 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 969 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 970 } 971 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 972 sizeof(struct ti_rx_desc)); 973 } 974 975 return; 976} 977 978static int ti_init_rx_ring_mini(sc) 979 struct ti_softc *sc; 980{ 981 register int i; 982 983 for (i = 0; i < TI_MSLOTS; i++) { 984 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 985 return(ENOBUFS); 986 }; 987 988 TI_UPDATE_MINIPROD(sc, i - 1); 989 sc->ti_mini = i - 1; 990 991 return(0); 992} 993 994static void ti_free_rx_ring_mini(sc) 995 struct ti_softc *sc; 996{ 997 register int i; 998 999 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1000 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1001 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1002 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1003 } 1004 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1005 sizeof(struct ti_rx_desc)); 1006 } 1007 1008 return; 1009} 1010 1011static void ti_free_tx_ring(sc) 1012 struct ti_softc *sc; 1013{ 1014 register int i; 1015 1016 if (sc->ti_rdata->ti_tx_ring == NULL) 1017 return; 1018 1019 for (i = 0; i < TI_TX_RING_CNT; i++) { 1020 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1021 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1022 sc->ti_cdata.ti_tx_chain[i] = NULL; 1023 } 1024 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1025 sizeof(struct ti_tx_desc)); 1026 } 1027 1028 return; 1029} 1030 1031static int ti_init_tx_ring(sc) 1032 struct ti_softc *sc; 1033{ 1034 sc->ti_txcnt = 0; 1035 sc->ti_tx_saved_considx = 0; 1036 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1037 return(0); 1038} 1039 1040/* 1041 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1042 * but we have to support the old way too so that Tigon 1 cards will 1043 * work. 1044 */ 1045void ti_add_mcast(sc, addr) 1046 struct ti_softc *sc; 1047 struct ether_addr *addr; 1048{ 1049 struct ti_cmd_desc cmd; 1050 u_int16_t *m; 1051 u_int32_t ext[2] = {0, 0}; 1052 1053 m = (u_int16_t *)&addr->octet[0]; 1054 1055 switch(sc->ti_hwrev) { 1056 case TI_HWREV_TIGON: 1057 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1058 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1059 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1060 break; 1061 case TI_HWREV_TIGON_II: 1062 ext[0] = htons(m[0]); 1063 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1064 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1065 break; 1066 default: 1067 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1068 break; 1069 } 1070 1071 return; 1072} 1073 1074void ti_del_mcast(sc, addr) 1075 struct ti_softc *sc; 1076 struct ether_addr *addr; 1077{ 1078 struct ti_cmd_desc cmd; 1079 u_int16_t *m; 1080 u_int32_t ext[2] = {0, 0}; 1081 1082 m = (u_int16_t *)&addr->octet[0]; 1083 1084 switch(sc->ti_hwrev) { 1085 case TI_HWREV_TIGON: 1086 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1087 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1088 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1089 break; 1090 case TI_HWREV_TIGON_II: 1091 ext[0] = htons(m[0]); 1092 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1093 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1094 break; 1095 default: 1096 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1097 break; 1098 } 1099 1100 return; 1101} 1102 1103/* 1104 * Configure the Tigon's multicast address filter. 1105 * 1106 * The actual multicast table management is a bit of a pain, thanks to 1107 * slight brain damage on the part of both Alteon and us. With our 1108 * multicast code, we are only alerted when the multicast address table 1109 * changes and at that point we only have the current list of addresses: 1110 * we only know the current state, not the previous state, so we don't 1111 * actually know what addresses were removed or added. The firmware has 1112 * state, but we can't get our grubby mits on it, and there is no 'delete 1113 * all multicast addresses' command. Hence, we have to maintain our own 1114 * state so we know what addresses have been programmed into the NIC at 1115 * any given time. 1116 */ 1117static void ti_setmulti(sc) 1118 struct ti_softc *sc; 1119{ 1120 struct ifnet *ifp; 1121 struct ifmultiaddr *ifma; 1122 struct ti_cmd_desc cmd; 1123 struct ti_mc_entry *mc; 1124 u_int32_t intrs; 1125 1126 ifp = &sc->arpcom.ac_if; 1127 1128 if (ifp->if_flags & IFF_ALLMULTI) { 1129 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1130 return; 1131 } else { 1132 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1133 } 1134 1135 /* Disable interrupts. */ 1136 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1137 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1138 1139 /* First, zot all the existing filters. */ 1140 while (sc->ti_mc_listhead.slh_first != NULL) { 1141 mc = sc->ti_mc_listhead.slh_first; 1142 ti_del_mcast(sc, &mc->mc_addr); 1143 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1144 free(mc, M_DEVBUF); 1145 } 1146 1147 /* Now program new ones. */ 1148 for (ifma = ifp->if_multiaddrs.lh_first; 1149 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1150 if (ifma->ifma_addr->sa_family != AF_LINK) 1151 continue; 1152 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1153 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1154 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1155 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1156 ti_add_mcast(sc, &mc->mc_addr); 1157 } 1158 1159 /* Re-enable interrupts. */ 1160 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1161 1162 return; 1163} 1164 1165/* 1166 * Check to see if the BIOS has configured us for a 64 bit slot when 1167 * we aren't actually in one. If we detect this condition, we can work 1168 * around it on the Tigon 2 by setting a bit in the PCI state register, 1169 * but for the Tigon 1 we must give up and abort the interface attach. 1170 */ 1171static int ti_64bitslot_war(sc) 1172 struct ti_softc *sc; 1173{ 1174 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1175 CSR_WRITE_4(sc, 0x600, 0); 1176 CSR_WRITE_4(sc, 0x604, 0); 1177 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1178 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1179 if (sc->ti_hwrev == TI_HWREV_TIGON) 1180 return(EINVAL); 1181 else { 1182 TI_SETBIT(sc, TI_PCI_STATE, 1183 TI_PCISTATE_32BIT_BUS); 1184 return(0); 1185 } 1186 } 1187 } 1188 1189 return(0); 1190} 1191 1192/* 1193 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1194 * self-test results. 1195 */ 1196static int ti_chipinit(sc) 1197 struct ti_softc *sc; 1198{ 1199 u_int32_t cacheline; 1200 u_int32_t pci_writemax = 0; 1201 1202 /* Initialize link to down state. */ 1203 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1204 1205 /* Set endianness before we access any non-PCI registers. */ 1206#if BYTE_ORDER == BIG_ENDIAN 1207 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1208 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1209#else 1210 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1211 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1212#endif 1213 1214 /* Check the ROM failed bit to see if self-tests passed. */ 1215 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1216 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1217 return(ENODEV); 1218 } 1219 1220 /* Halt the CPU. */ 1221 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1222 1223 /* Figure out the hardware revision. */ 1224 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1225 case TI_REV_TIGON_I: 1226 sc->ti_hwrev = TI_HWREV_TIGON; 1227 break; 1228 case TI_REV_TIGON_II: 1229 sc->ti_hwrev = TI_HWREV_TIGON_II; 1230 break; 1231 default: 1232 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1233 return(ENODEV); 1234 } 1235 1236 /* Do special setup for Tigon 2. */ 1237 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1238 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1240 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1241 } 1242 1243 /* Set up the PCI state register. */ 1244 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1245 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1246 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1247 } 1248 1249 /* Clear the read/write max DMA parameters. */ 1250 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1251 TI_PCISTATE_READ_MAXDMA)); 1252 1253 /* Get cache line size. */ 1254 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1255 1256 /* 1257 * If the system has set enabled the PCI memory write 1258 * and invalidate command in the command register, set 1259 * the write max parameter accordingly. This is necessary 1260 * to use MWI with the Tigon 2. 1261 */ 1262 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1263 switch(cacheline) { 1264 case 1: 1265 case 4: 1266 case 8: 1267 case 16: 1268 case 32: 1269 case 64: 1270 break; 1271 default: 1272 /* Disable PCI memory write and invalidate. */ 1273 if (bootverbose) 1274 printf("ti%d: cache line size %d not " 1275 "supported; disabling PCI MWI\n", 1276 sc->ti_unit, cacheline); 1277 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1278 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1279 break; 1280 } 1281 } 1282 1283#ifdef __brokenalpha__ 1284 /* 1285 * From the Alteon sample driver: 1286 * Must insure that we do not cross an 8K (bytes) boundary 1287 * for DMA reads. Our highest limit is 1K bytes. This is a 1288 * restriction on some ALPHA platforms with early revision 1289 * 21174 PCI chipsets, such as the AlphaPC 164lx 1290 */ 1291 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1292#else 1293 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1294#endif 1295 1296 /* This sets the min dma param all the way up (0xff). */ 1297 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1298 1299 /* Configure DMA variables. */ 1300#if BYTE_ORDER == BIG_ENDIAN 1301 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1302 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1303 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1304 TI_OPMODE_DONT_FRAG_JUMBO); 1305#else 1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1307 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1308 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1309#endif 1310 1311 /* 1312 * Only allow 1 DMA channel to be active at a time. 1313 * I don't think this is a good idea, but without it 1314 * the firmware racks up lots of nicDmaReadRingFull 1315 * errors. 1316 */ 1317#ifndef TI_CSUM_OFFLOAD 1318 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1319#endif 1320 1321 /* Recommended settings from Tigon manual. */ 1322 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1323 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1324 1325 if (ti_64bitslot_war(sc)) { 1326 printf("ti%d: bios thinks we're in a 64 bit slot, " 1327 "but we aren't", sc->ti_unit); 1328 return(EINVAL); 1329 } 1330 1331 return(0); 1332} 1333 1334/* 1335 * Initialize the general information block and firmware, and 1336 * start the CPU(s) running. 1337 */ 1338static int ti_gibinit(sc) 1339 struct ti_softc *sc; 1340{ 1341 struct ti_rcb *rcb; 1342 int i; 1343 struct ifnet *ifp; 1344 1345 ifp = &sc->arpcom.ac_if; 1346 1347 /* Disable interrupts for now. */ 1348 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1349 1350 /* Tell the chip where to find the general information block. */ 1351 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1352 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1353 1354 /* Load the firmware into SRAM. */ 1355 ti_loadfw(sc); 1356 1357 /* Set up the contents of the general info and ring control blocks. */ 1358 1359 /* Set up the event ring and producer pointer. */ 1360 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1361 1362 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1363 rcb->ti_flags = 0; 1364 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1365 vtophys(&sc->ti_ev_prodidx); 1366 sc->ti_ev_prodidx.ti_idx = 0; 1367 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1368 sc->ti_ev_saved_considx = 0; 1369 1370 /* Set up the command ring and producer mailbox. */ 1371 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1372 1373#ifdef __i386__ 1374 sc->ti_rdata->ti_cmd_ring = 1375 (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING); 1376#endif 1377#ifdef __alpha__ 1378 sc->ti_rdata->ti_cmd_ring = 1379 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1380#endif 1381 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1382 rcb->ti_flags = 0; 1383 rcb->ti_max_len = 0; 1384 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1385 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1386 } 1387 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1388 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1389 sc->ti_cmd_saved_prodidx = 0; 1390 1391 /* 1392 * Assign the address of the stats refresh buffer. 1393 * We re-use the current stats buffer for this to 1394 * conserve memory. 1395 */ 1396 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1397 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1398 1399 /* Set up the standard receive ring. */ 1400 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1401 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1402 rcb->ti_max_len = TI_FRAMELEN; 1403 rcb->ti_flags = 0; 1404#ifdef TI_CSUM_OFFLOAD 1405 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1406#endif 1407#if NVLAN > 0 1408 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1409#endif 1410 1411 /* Set up the jumbo receive ring. */ 1412 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1413 TI_HOSTADDR(rcb->ti_hostaddr) = 1414 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1415 rcb->ti_max_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 1416 rcb->ti_flags = 0; 1417#ifdef TI_CSUM_OFFLOAD 1418 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1419#endif 1420#if NVLAN > 0 1421 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1422#endif 1423 1424 /* 1425 * Set up the mini ring. Only activated on the 1426 * Tigon 2 but the slot in the config block is 1427 * still there on the Tigon 1. 1428 */ 1429 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1430 TI_HOSTADDR(rcb->ti_hostaddr) = 1431 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1432 rcb->ti_max_len = MHLEN; 1433 if (sc->ti_hwrev == TI_HWREV_TIGON) 1434 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1435 else 1436 rcb->ti_flags = 0; 1437#ifdef TI_CSUM_OFFLOAD 1438 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1439#endif 1440#if NVLAN > 0 1441 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1442#endif 1443 1444 /* 1445 * Set up the receive return ring. 1446 */ 1447 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1448 TI_HOSTADDR(rcb->ti_hostaddr) = 1449 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1450 rcb->ti_flags = 0; 1451 rcb->ti_max_len = TI_RETURN_RING_CNT; 1452 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1453 vtophys(&sc->ti_return_prodidx); 1454 1455 /* 1456 * Set up the tx ring. Note: for the Tigon 2, we have the option 1457 * of putting the transmit ring in the host's address space and 1458 * letting the chip DMA it instead of leaving the ring in the NIC's 1459 * memory and accessing it through the shared memory region. We 1460 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1461 * so we have to revert to the shared memory scheme if we detect 1462 * a Tigon 1 chip. 1463 */ 1464 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1465 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1466#ifdef __i386__ 1467 sc->ti_rdata->ti_tx_ring_nic = 1468 (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW); 1469#endif 1470#ifdef __alpha__ 1471 sc->ti_rdata->ti_tx_ring_nic = 1472 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1473#endif 1474 } 1475 bzero((char *)sc->ti_rdata->ti_tx_ring, 1476 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1477 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1478 if (sc->ti_hwrev == TI_HWREV_TIGON) 1479 rcb->ti_flags = 0; 1480 else 1481 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1482#if NVLAN > 0 1483 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1484#endif 1485 rcb->ti_max_len = TI_TX_RING_CNT; 1486 if (sc->ti_hwrev == TI_HWREV_TIGON) 1487 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1488 else 1489 TI_HOSTADDR(rcb->ti_hostaddr) = 1490 vtophys(&sc->ti_rdata->ti_tx_ring); 1491 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1492 vtophys(&sc->ti_tx_considx); 1493 1494 /* Set up tuneables */ 1495 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1496 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1497 (sc->ti_rx_coal_ticks / 10)); 1498 else 1499 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1500 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1501 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1502 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1503 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1504 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1505 1506 /* Turn interrupts on. */ 1507 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1508 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1509 1510 /* Start CPU. */ 1511 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1512 1513 return(0); 1514} 1515 1516/* 1517 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1518 * against our list and return its name if we find a match. 1519 */ 1520static int ti_probe(dev) 1521 device_t dev; 1522{ 1523 struct ti_type *t; 1524 1525 t = ti_devs; 1526 1527 while(t->ti_name != NULL) { 1528 if ((pci_get_vendor(dev) == t->ti_vid) && 1529 (pci_get_device(dev) == t->ti_did)) { 1530 device_set_desc(dev, t->ti_name); 1531 return(0); 1532 } 1533 t++; 1534 } 1535 1536 return(ENXIO); 1537} 1538 1539static int ti_attach(dev) 1540 device_t dev; 1541{ 1542 int s; 1543 u_int32_t command; 1544 struct ifnet *ifp; 1545 struct ti_softc *sc; 1546 int unit, error = 0, rid; 1547 1548 s = splimp(); 1549 1550 sc = device_get_softc(dev); 1551 unit = device_get_unit(dev); 1552 bzero(sc, sizeof(struct ti_softc)); 1553 1554 /* 1555 * Map control/status registers. 1556 */ 1557 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1558 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1559 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1560 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1561 1562 if (!(command & PCIM_CMD_MEMEN)) { 1563 printf("ti%d: failed to enable memory mapping!\n", unit); 1564 error = ENXIO; 1565 goto fail; 1566 } 1567 1568 rid = TI_PCI_LOMEM; 1569 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1570 0, ~0, 1, RF_ACTIVE); 1571 1572 if (sc->ti_res == NULL) { 1573 printf ("ti%d: couldn't map memory\n", unit); 1574 error = ENXIO; 1575 goto fail; 1576 } 1577 1578 /* Allocate interrupt */ 1579 rid = 0; 1580 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1581 RF_SHAREABLE | RF_ACTIVE); 1582 1583 if (sc->ti_irq == NULL) { 1584 printf("ti%d: couldn't map interrupt\n", unit); 1585 error = ENXIO; 1586 goto fail; 1587 } 1588 1589 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1590 ti_intr, sc, &sc->ti_intrhand); 1591 1592 if (error) { 1593 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1594 bus_release_resource(dev, SYS_RES_MEMORY, 1595 TI_PCI_LOMEM, sc->ti_res); 1596 printf("ti%d: couldn't set up irq\n", unit); 1597 goto fail; 1598 } 1599 1600 sc->ti_unit = unit; 1601 1602 if (ti_chipinit(sc)) { 1603 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1604 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1605 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1606 bus_release_resource(dev, SYS_RES_MEMORY, 1607 TI_PCI_LOMEM, sc->ti_res); 1608 error = ENXIO; 1609 goto fail; 1610 } 1611 1612 /* Zero out the NIC's on-board SRAM. */ 1613 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1614 1615 /* Init again -- zeroing memory may have clobbered some registers. */ 1616 if (ti_chipinit(sc)) { 1617 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1618 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1619 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1620 bus_release_resource(dev, SYS_RES_MEMORY, 1621 TI_PCI_LOMEM, sc->ti_res); 1622 error = ENXIO; 1623 goto fail; 1624 } 1625 1626 /* 1627 * Get station address from the EEPROM. Note: the manual states 1628 * that the MAC address is at offset 0x8c, however the data is 1629 * stored as two longwords (since that's how it's loaded into 1630 * the NIC). This means the MAC address is actually preceeded 1631 * by two zero bytes. We need to skip over those. 1632 */ 1633 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1634 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1635 printf("ti%d: failed to read station address\n", unit); 1636 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1637 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1638 bus_release_resource(dev, SYS_RES_MEMORY, 1639 TI_PCI_LOMEM, sc->ti_res); 1640 error = ENXIO; 1641 goto fail; 1642 } 1643 1644 /* 1645 * A Tigon chip was detected. Inform the world. 1646 */ 1647 printf("ti%d: Ethernet address: %6D\n", unit, 1648 sc->arpcom.ac_enaddr, ":"); 1649 1650 /* Allocate the general information block and ring buffers. */ 1651 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1652 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1653 1654 if (sc->ti_rdata == NULL) { 1655 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1656 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1657 bus_release_resource(dev, SYS_RES_MEMORY, 1658 TI_PCI_LOMEM, sc->ti_res); 1659 error = ENXIO; 1660 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1661 goto fail; 1662 } 1663 1664 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1665 1666 /* Try to allocate memory for jumbo buffers. */ 1667 if (ti_alloc_jumbo_mem(sc)) { 1668 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1669 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1670 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1671 bus_release_resource(dev, SYS_RES_MEMORY, 1672 TI_PCI_LOMEM, sc->ti_res); 1673 free(sc->ti_rdata, M_DEVBUF); 1674 error = ENXIO; 1675 goto fail; 1676 } 1677 1678 /* Set default tuneable values. */ 1679 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1680 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1681 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1682 sc->ti_rx_max_coal_bds = 64; 1683 sc->ti_tx_max_coal_bds = 128; 1684 sc->ti_tx_buf_ratio = 21; 1685 1686 /* Set up ifnet structure */ 1687 ifp = &sc->arpcom.ac_if; 1688 ifp->if_softc = sc; 1689 ifp->if_unit = sc->ti_unit; 1690 ifp->if_name = "ti"; 1691 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1692 ifp->if_ioctl = ti_ioctl; 1693 ifp->if_output = ether_output; 1694 ifp->if_start = ti_start; 1695 ifp->if_watchdog = ti_watchdog; 1696 ifp->if_init = ti_init; 1697 ifp->if_mtu = ETHERMTU; 1698 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1699 1700 /* Set up ifmedia support. */ 1701 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1702 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1703 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1704 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1705 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1706 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1707 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1708 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1709 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1710 1711 /* 1712 * Call MI attach routines. 1713 */ 1714 if_attach(ifp); 1715 ether_ifattach(ifp); 1716 1717#if NBPF > 0 1718 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1719#endif 1720 1721fail: 1722 splx(s); 1723 1724 return(error); 1725} 1726 1727static int ti_detach(dev) 1728 device_t dev; 1729{ 1730 struct ti_softc *sc; 1731 struct ifnet *ifp; 1732 int s; 1733 1734 s = splimp(); 1735 1736 sc = device_get_softc(dev); 1737 ifp = &sc->arpcom.ac_if; 1738 1739 if_detach(ifp); 1740 ti_stop(sc); 1741 1742 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1743 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1744 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1745 1746 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 1747 free(sc->ti_rdata, M_DEVBUF); 1748 ifmedia_removeall(&sc->ifmedia); 1749 1750 splx(s); 1751 1752 return(0); 1753} 1754 1755/* 1756 * Frame reception handling. This is called if there's a frame 1757 * on the receive return list. 1758 * 1759 * Note: we have to be able to handle three possibilities here: 1760 * 1) the frame is from the mini receive ring (can only happen) 1761 * on Tigon 2 boards) 1762 * 2) the frame is from the jumbo recieve ring 1763 * 3) the frame is from the standard receive ring 1764 */ 1765 1766static void ti_rxeof(sc) 1767 struct ti_softc *sc; 1768{ 1769 struct ifnet *ifp; 1770 struct ti_cmd_desc cmd; 1771 1772 ifp = &sc->arpcom.ac_if; 1773 1774 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1775 struct ti_rx_desc *cur_rx; 1776 u_int32_t rxidx; 1777 struct ether_header *eh; 1778 struct mbuf *m = NULL; 1779#if NVLAN > 0 1780 u_int16_t vlan_tag = 0; 1781 int have_tag = 0; 1782#endif 1783#ifdef TI_CSUM_OFFLOAD 1784 struct ip *ip; 1785#endif 1786 1787 cur_rx = 1788 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1789 rxidx = cur_rx->ti_idx; 1790 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1791 1792#if NVLAN > 0 1793 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1794 have_tag = 1; 1795 vlan_tag = cur_rx->ti_vlan_tag; 1796 } 1797#endif 1798 1799 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1800 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1801 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1802 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1803 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1804 ifp->if_ierrors++; 1805 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1806 continue; 1807 } 1808 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1809 ifp->if_ierrors++; 1810 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1811 continue; 1812 } 1813 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1814 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1815 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1816 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1817 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1818 ifp->if_ierrors++; 1819 ti_newbuf_mini(sc, sc->ti_mini, m); 1820 continue; 1821 } 1822 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1823 ifp->if_ierrors++; 1824 ti_newbuf_mini(sc, sc->ti_mini, m); 1825 continue; 1826 } 1827 } else { 1828 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1829 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1830 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1831 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1832 ifp->if_ierrors++; 1833 ti_newbuf_std(sc, sc->ti_std, m); 1834 continue; 1835 } 1836 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1837 ifp->if_ierrors++; 1838 ti_newbuf_std(sc, sc->ti_std, m); 1839 continue; 1840 } 1841 } 1842 1843 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1844 ifp->if_ipackets++; 1845 eh = mtod(m, struct ether_header *); 1846 m->m_pkthdr.rcvif = ifp; 1847 1848#if NBPF > 0 1849 /* 1850 * Handle BPF listeners. Let the BPF user see the packet, but 1851 * don't pass it up to the ether_input() layer unless it's 1852 * a broadcast packet, multicast packet, matches our ethernet 1853 * address or the interface is in promiscuous mode. 1854 */ 1855 if (ifp->if_bpf) { 1856 bpf_mtap(ifp, m); 1857 if (ifp->if_flags & IFF_PROMISC && 1858 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1859 ETHER_ADDR_LEN) && 1860 (eh->ether_dhost[0] & 1) == 0)) { 1861 m_freem(m); 1862 continue; 1863 } 1864 } 1865#endif 1866 1867 /* Remove header from mbuf and pass it on. */ 1868 m_adj(m, sizeof(struct ether_header)); 1869 1870#ifdef TI_CSUM_OFFLOAD 1871 ip = mtod(m, struct ip *); 1872 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1873 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1874 m->m_flags |= M_HWCKSUM; 1875#endif 1876 1877#if NVLAN > 0 1878 /* 1879 * If we received a packet with a vlan tag, pass it 1880 * to vlan_input() instead of ether_input(). 1881 */ 1882 if (have_tag) { 1883 vlan_input_tag(eh, m, vlan_tag); 1884 have_tag = vlan_tag = 0; 1885 continue; 1886 } 1887#endif 1888 ether_input(ifp, eh, m); 1889 } 1890 1891 /* Only necessary on the Tigon 1. */ 1892 if (sc->ti_hwrev == TI_HWREV_TIGON) 1893 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1894 sc->ti_rx_saved_considx); 1895 1896 TI_UPDATE_STDPROD(sc, sc->ti_std); 1897 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1898 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1899 1900 return; 1901} 1902 1903static void ti_txeof(sc) 1904 struct ti_softc *sc; 1905{ 1906 struct ti_tx_desc *cur_tx = NULL; 1907 struct ifnet *ifp; 1908 1909 ifp = &sc->arpcom.ac_if; 1910 1911 /* 1912 * Go through our tx ring and free mbufs for those 1913 * frames that have been sent. 1914 */ 1915 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1916 u_int32_t idx = 0; 1917 1918 idx = sc->ti_tx_saved_considx; 1919 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1920 if (idx > 383) 1921 CSR_WRITE_4(sc, TI_WINBASE, 1922 TI_TX_RING_BASE + 6144); 1923 else if (idx > 255) 1924 CSR_WRITE_4(sc, TI_WINBASE, 1925 TI_TX_RING_BASE + 4096); 1926 else if (idx > 127) 1927 CSR_WRITE_4(sc, TI_WINBASE, 1928 TI_TX_RING_BASE + 2048); 1929 else 1930 CSR_WRITE_4(sc, TI_WINBASE, 1931 TI_TX_RING_BASE); 1932 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1933 } else 1934 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1935 if (cur_tx->ti_flags & TI_BDFLAG_END) 1936 ifp->if_opackets++; 1937 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1938 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1939 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1940 } 1941 sc->ti_txcnt--; 1942 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1943 ifp->if_timer = 0; 1944 } 1945 1946 if (cur_tx != NULL) 1947 ifp->if_flags &= ~IFF_OACTIVE; 1948 1949 return; 1950} 1951 1952static void ti_intr(xsc) 1953 void *xsc; 1954{ 1955 struct ti_softc *sc; 1956 struct ifnet *ifp; 1957 1958 sc = xsc; 1959 ifp = &sc->arpcom.ac_if; 1960 1961#ifdef notdef 1962 /* Avoid this for now -- checking this register is expensive. */ 1963 /* Make sure this is really our interrupt. */ 1964 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1965 return; 1966#endif 1967 1968 /* Ack interrupt and stop others from occuring. */ 1969 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1970 1971 if (ifp->if_flags & IFF_RUNNING) { 1972 /* Check RX return ring producer/consumer */ 1973 ti_rxeof(sc); 1974 1975 /* Check TX ring producer/consumer */ 1976 ti_txeof(sc); 1977 } 1978 1979 ti_handle_events(sc); 1980 1981 /* Re-enable interrupts. */ 1982 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1983 1984 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1985 ti_start(ifp); 1986 1987 return; 1988} 1989 1990static void ti_stats_update(sc) 1991 struct ti_softc *sc; 1992{ 1993 struct ifnet *ifp; 1994 1995 ifp = &sc->arpcom.ac_if; 1996 1997 ifp->if_collisions += 1998 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1999 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2000 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2001 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2002 ifp->if_collisions; 2003 2004 return; 2005} 2006 2007/* 2008 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2009 * pointers to descriptors. 2010 */ 2011static int ti_encap(sc, m_head, txidx) 2012 struct ti_softc *sc; 2013 struct mbuf *m_head; 2014 u_int32_t *txidx; 2015{ 2016 struct ti_tx_desc *f = NULL; 2017 struct mbuf *m; 2018 u_int32_t frag, cur, cnt = 0; 2019#if NVLAN > 0 2020 struct ifvlan *ifv = NULL; 2021 2022 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2023 m_head->m_pkthdr.rcvif != NULL && 2024 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2025 ifv = m_head->m_pkthdr.rcvif->if_softc; 2026#endif 2027 2028 m = m_head; 2029 cur = frag = *txidx; 2030 2031 /* 2032 * Start packing the mbufs in this chain into 2033 * the fragment pointers. Stop when we run out 2034 * of fragments or hit the end of the mbuf chain. 2035 */ 2036 for (m = m_head; m != NULL; m = m->m_next) { 2037 if (m->m_len != 0) { 2038 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2039 if (frag > 383) 2040 CSR_WRITE_4(sc, TI_WINBASE, 2041 TI_TX_RING_BASE + 6144); 2042 else if (frag > 255) 2043 CSR_WRITE_4(sc, TI_WINBASE, 2044 TI_TX_RING_BASE + 4096); 2045 else if (frag > 127) 2046 CSR_WRITE_4(sc, TI_WINBASE, 2047 TI_TX_RING_BASE + 2048); 2048 else 2049 CSR_WRITE_4(sc, TI_WINBASE, 2050 TI_TX_RING_BASE); 2051 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2052 } else 2053 f = &sc->ti_rdata->ti_tx_ring[frag]; 2054 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2055 break; 2056 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2057 f->ti_len = m->m_len; 2058 f->ti_flags = 0; 2059#if NVLAN > 0 2060 if (ifv != NULL) { 2061 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2062 f->ti_vlan_tag = ifv->ifv_tag; 2063 } else { 2064 f->ti_vlan_tag = 0; 2065 } 2066#endif 2067 /* 2068 * Sanity check: avoid coming within 16 descriptors 2069 * of the end of the ring. 2070 */ 2071 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2072 return(ENOBUFS); 2073 cur = frag; 2074 TI_INC(frag, TI_TX_RING_CNT); 2075 cnt++; 2076 } 2077 } 2078 2079 if (m != NULL) 2080 return(ENOBUFS); 2081 2082 if (frag == sc->ti_tx_saved_considx) 2083 return(ENOBUFS); 2084 2085 if (sc->ti_hwrev == TI_HWREV_TIGON) 2086 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2087 TI_BDFLAG_END; 2088 else 2089 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2090 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2091 sc->ti_txcnt += cnt; 2092 2093 *txidx = frag; 2094 2095 return(0); 2096} 2097 2098/* 2099 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2100 * to the mbuf data regions directly in the transmit descriptors. 2101 */ 2102static void ti_start(ifp) 2103 struct ifnet *ifp; 2104{ 2105 struct ti_softc *sc; 2106 struct mbuf *m_head = NULL; 2107 u_int32_t prodidx = 0; 2108 2109 sc = ifp->if_softc; 2110 2111 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2112 2113 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2114 IF_DEQUEUE(&ifp->if_snd, m_head); 2115 if (m_head == NULL) 2116 break; 2117 2118 /* 2119 * Pack the data into the transmit ring. If we 2120 * don't have room, set the OACTIVE flag and wait 2121 * for the NIC to drain the ring. 2122 */ 2123 if (ti_encap(sc, m_head, &prodidx)) { 2124 IF_PREPEND(&ifp->if_snd, m_head); 2125 ifp->if_flags |= IFF_OACTIVE; 2126 break; 2127 } 2128 2129 /* 2130 * If there's a BPF listener, bounce a copy of this frame 2131 * to him. 2132 */ 2133#if NBPF > 0 2134 if (ifp->if_bpf) 2135 bpf_mtap(ifp, m_head); 2136#endif 2137 } 2138 2139 /* Transmit */ 2140 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2141 2142 /* 2143 * Set a timeout in case the chip goes out to lunch. 2144 */ 2145 ifp->if_timer = 5; 2146 2147 return; 2148} 2149 2150static void ti_init(xsc) 2151 void *xsc; 2152{ 2153 struct ti_softc *sc = xsc; 2154 int s; 2155 2156 s = splimp(); 2157 2158 /* Cancel pending I/O and flush buffers. */ 2159 ti_stop(sc); 2160 2161 /* Init the gen info block, ring control blocks and firmware. */ 2162 if (ti_gibinit(sc)) { 2163 printf("ti%d: initialization failure\n", sc->ti_unit); 2164 splx(s); 2165 return; 2166 } 2167 2168 splx(s); 2169 2170 return; 2171} 2172 2173static void ti_init2(sc) 2174 struct ti_softc *sc; 2175{ 2176 struct ti_cmd_desc cmd; 2177 struct ifnet *ifp; 2178 u_int16_t *m; 2179 struct ifmedia *ifm; 2180 int tmp; 2181 2182 ifp = &sc->arpcom.ac_if; 2183 2184 /* Specify MTU and interface index. */ 2185 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2186 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2187 ETHER_HDR_LEN + ETHER_CRC_LEN); 2188 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2189 2190 /* Load our MAC address. */ 2191 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2192 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2193 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2194 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2195 2196 /* Enable or disable promiscuous mode as needed. */ 2197 if (ifp->if_flags & IFF_PROMISC) { 2198 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2199 } else { 2200 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2201 } 2202 2203 /* Program multicast filter. */ 2204 ti_setmulti(sc); 2205 2206 /* 2207 * If this is a Tigon 1, we should tell the 2208 * firmware to use software packet filtering. 2209 */ 2210 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2211 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2212 } 2213 2214 /* Init RX ring. */ 2215 ti_init_rx_ring_std(sc); 2216 2217 /* Init jumbo RX ring. */ 2218 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2219 ti_init_rx_ring_jumbo(sc); 2220 2221 /* 2222 * If this is a Tigon 2, we can also configure the 2223 * mini ring. 2224 */ 2225 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2226 ti_init_rx_ring_mini(sc); 2227 2228 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2229 sc->ti_rx_saved_considx = 0; 2230 2231 /* Init TX ring. */ 2232 ti_init_tx_ring(sc); 2233 2234 /* Tell firmware we're alive. */ 2235 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2236 2237 /* Enable host interrupts. */ 2238 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2239 2240 ifp->if_flags |= IFF_RUNNING; 2241 ifp->if_flags &= ~IFF_OACTIVE; 2242 2243 /* 2244 * Make sure to set media properly. We have to do this 2245 * here since we have to issue commands in order to set 2246 * the link negotiation and we can't issue commands until 2247 * the firmware is running. 2248 */ 2249 ifm = &sc->ifmedia; 2250 tmp = ifm->ifm_media; 2251 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2252 ti_ifmedia_upd(ifp); 2253 ifm->ifm_media = tmp; 2254 2255 return; 2256} 2257 2258/* 2259 * Set media options. 2260 */ 2261static int ti_ifmedia_upd(ifp) 2262 struct ifnet *ifp; 2263{ 2264 struct ti_softc *sc; 2265 struct ifmedia *ifm; 2266 struct ti_cmd_desc cmd; 2267 2268 sc = ifp->if_softc; 2269 ifm = &sc->ifmedia; 2270 2271 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2272 return(EINVAL); 2273 2274 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2275 case IFM_AUTO: 2276 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2277 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2278 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2279 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2280 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2281 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2282 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2283 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2284 break; 2285 case IFM_1000_SX: 2286 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2287 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2288 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2289 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2290 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2291 break; 2292 case IFM_100_FX: 2293 case IFM_10_FL: 2294 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2295 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2296 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2297 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2298 } else { 2299 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2300 } 2301 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2302 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2303 } else { 2304 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2305 } 2306 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2307 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2308 break; 2309 } 2310 2311 return(0); 2312} 2313 2314/* 2315 * Report current media status. 2316 */ 2317static void ti_ifmedia_sts(ifp, ifmr) 2318 struct ifnet *ifp; 2319 struct ifmediareq *ifmr; 2320{ 2321 struct ti_softc *sc; 2322 2323 sc = ifp->if_softc; 2324 2325 ifmr->ifm_status = IFM_AVALID; 2326 ifmr->ifm_active = IFM_ETHER; 2327 2328 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2329 return; 2330 2331 ifmr->ifm_status |= IFM_ACTIVE; 2332 2333 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2334 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2335 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2336 u_int32_t media; 2337 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2338 if (media & TI_LNK_100MB) 2339 ifmr->ifm_active |= IFM_100_FX; 2340 if (media & TI_LNK_10MB) 2341 ifmr->ifm_active |= IFM_10_FL; 2342 if (media & TI_LNK_FULL_DUPLEX) 2343 ifmr->ifm_active |= IFM_FDX; 2344 if (media & TI_LNK_HALF_DUPLEX) 2345 ifmr->ifm_active |= IFM_HDX; 2346 } 2347 2348 return; 2349} 2350 2351static int ti_ioctl(ifp, command, data) 2352 struct ifnet *ifp; 2353 u_long command; 2354 caddr_t data; 2355{ 2356 struct ti_softc *sc = ifp->if_softc; 2357 struct ifreq *ifr = (struct ifreq *) data; 2358 int s, error = 0; 2359 struct ti_cmd_desc cmd; 2360 2361 s = splimp(); 2362 2363 switch(command) { 2364 case SIOCSIFADDR: 2365 case SIOCGIFADDR: 2366 error = ether_ioctl(ifp, command, data); 2367 break; 2368 case SIOCSIFMTU: 2369 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2370 error = EINVAL; 2371 else { 2372 ifp->if_mtu = ifr->ifr_mtu; 2373 ti_init(sc); 2374 } 2375 break; 2376 case SIOCSIFFLAGS: 2377 if (ifp->if_flags & IFF_UP) { 2378 /* 2379 * If only the state of the PROMISC flag changed, 2380 * then just use the 'set promisc mode' command 2381 * instead of reinitializing the entire NIC. Doing 2382 * a full re-init means reloading the firmware and 2383 * waiting for it to start up, which may take a 2384 * second or two. 2385 */ 2386 if (ifp->if_flags & IFF_RUNNING && 2387 ifp->if_flags & IFF_PROMISC && 2388 !(sc->ti_if_flags & IFF_PROMISC)) { 2389 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2390 TI_CMD_CODE_PROMISC_ENB, 0); 2391 } else if (ifp->if_flags & IFF_RUNNING && 2392 !(ifp->if_flags & IFF_PROMISC) && 2393 sc->ti_if_flags & IFF_PROMISC) { 2394 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2395 TI_CMD_CODE_PROMISC_DIS, 0); 2396 } else 2397 ti_init(sc); 2398 } else { 2399 if (ifp->if_flags & IFF_RUNNING) { 2400 ti_stop(sc); 2401 } 2402 } 2403 sc->ti_if_flags = ifp->if_flags; 2404 error = 0; 2405 break; 2406 case SIOCADDMULTI: 2407 case SIOCDELMULTI: 2408 if (ifp->if_flags & IFF_RUNNING) { 2409 ti_setmulti(sc); 2410 error = 0; 2411 } 2412 break; 2413 case SIOCSIFMEDIA: 2414 case SIOCGIFMEDIA: 2415 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2416 break; 2417 default: 2418 error = EINVAL; 2419 break; 2420 } 2421 2422 (void)splx(s); 2423 2424 return(error); 2425} 2426 2427static void ti_watchdog(ifp) 2428 struct ifnet *ifp; 2429{ 2430 struct ti_softc *sc; 2431 2432 sc = ifp->if_softc; 2433 2434 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2435 ti_stop(sc); 2436 ti_init(sc); 2437 2438 ifp->if_oerrors++; 2439 2440 return; 2441} 2442 2443/* 2444 * Stop the adapter and free any mbufs allocated to the 2445 * RX and TX lists. 2446 */ 2447static void ti_stop(sc) 2448 struct ti_softc *sc; 2449{ 2450 struct ifnet *ifp; 2451 struct ti_cmd_desc cmd; 2452 2453 ifp = &sc->arpcom.ac_if; 2454 2455 /* Disable host interrupts. */ 2456 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2457 /* 2458 * Tell firmware we're shutting down. 2459 */ 2460 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2461 2462 /* Halt and reinitialize. */ 2463 ti_chipinit(sc); 2464 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2465 ti_chipinit(sc); 2466 2467 /* Free the RX lists. */ 2468 ti_free_rx_ring_std(sc); 2469 2470 /* Free jumbo RX list. */ 2471 ti_free_rx_ring_jumbo(sc); 2472 2473 /* Free mini RX list. */ 2474 ti_free_rx_ring_mini(sc); 2475 2476 /* Free TX buffers. */ 2477 ti_free_tx_ring(sc); 2478 2479 sc->ti_ev_prodidx.ti_idx = 0; 2480 sc->ti_return_prodidx.ti_idx = 0; 2481 sc->ti_tx_considx.ti_idx = 0; 2482 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2483 2484 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2485 2486 return; 2487} 2488 2489/* 2490 * Stop all chip I/O so that the kernel's probe routines don't 2491 * get confused by errant DMAs when rebooting. 2492 */ 2493static void ti_shutdown(dev) 2494 device_t dev; 2495{ 2496 struct ti_softc *sc; 2497 2498 sc = device_get_softc(dev); 2499 2500 ti_chipinit(sc); 2501 2502 return; 2503} 2504