if_ti.c revision 242425
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 242425 2012-11-01 05:39:21Z yongari $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#ifdef TI_SF_BUF_JUMBO 116#include <vm/vm.h> 117#include <vm/vm_page.h> 118#endif 119 120#include <dev/pci/pcireg.h> 121#include <dev/pci/pcivar.h> 122 123#include <sys/tiio.h> 124#include <dev/ti/if_tireg.h> 125#include <dev/ti/ti_fw.h> 126#include <dev/ti/ti_fw2.h> 127 128#include <sys/sysctl.h> 129 130#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 131/* 132 * We can only turn on header splitting if we're using extended receive 133 * BDs. 134 */ 135#if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 136#error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 137#endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 138 139typedef enum { 140 TI_SWAP_HTON, 141 TI_SWAP_NTOH 142} ti_swap_type; 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static const struct ti_type const ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf **); 188 189static void ti_intr(void *); 190static void ti_start(struct ifnet *); 191static void ti_start_locked(struct ifnet *); 192static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193static void ti_init(void *); 194static void ti_init_locked(void *); 195static void ti_init2(struct ti_softc *); 196static void ti_stop(struct ti_softc *); 197static void ti_watchdog(void *); 198static int ti_shutdown(device_t); 199static int ti_ifmedia_upd(struct ifnet *); 200static int ti_ifmedia_upd_locked(struct ti_softc *); 201static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 202 203static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 204static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 205static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 206 207static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 208static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 209static void ti_setmulti(struct ti_softc *); 210 211static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 212static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 213static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 214static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 215 int); 216static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 217 int, int, int); 218static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219static void ti_loadfw(struct ti_softc *); 220static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222static void ti_handle_events(struct ti_softc *); 223static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 224static int ti_dma_alloc(struct ti_softc *); 225static void ti_dma_free(struct ti_softc *); 226static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 227 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 228static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 229 bus_dmamap_t *); 230static int ti_newbuf_std(struct ti_softc *, int); 231static int ti_newbuf_mini(struct ti_softc *, int); 232static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 233static int ti_init_rx_ring_std(struct ti_softc *); 234static void ti_free_rx_ring_std(struct ti_softc *); 235static int ti_init_rx_ring_jumbo(struct ti_softc *); 236static void ti_free_rx_ring_jumbo(struct ti_softc *); 237static int ti_init_rx_ring_mini(struct ti_softc *); 238static void ti_free_rx_ring_mini(struct ti_softc *); 239static void ti_free_tx_ring(struct ti_softc *); 240static int ti_init_tx_ring(struct ti_softc *); 241static void ti_discard_std(struct ti_softc *, int); 242#ifndef TI_SF_BUF_JUMBO 243static void ti_discard_jumbo(struct ti_softc *, int); 244#endif 245static void ti_discard_mini(struct ti_softc *, int); 246 247static int ti_64bitslot_war(struct ti_softc *); 248static int ti_chipinit(struct ti_softc *); 249static int ti_gibinit(struct ti_softc *); 250 251#ifdef TI_JUMBO_HDRSPLIT 252static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 253 int idx); 254#endif /* TI_JUMBO_HDRSPLIT */ 255 256static void ti_sysctl_node(struct ti_softc *); 257 258static device_method_t ti_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, ti_probe), 261 DEVMETHOD(device_attach, ti_attach), 262 DEVMETHOD(device_detach, ti_detach), 263 DEVMETHOD(device_shutdown, ti_shutdown), 264 { 0, 0 } 265}; 266 267static driver_t ti_driver = { 268 "ti", 269 ti_methods, 270 sizeof(struct ti_softc) 271}; 272 273static devclass_t ti_devclass; 274 275DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 276MODULE_DEPEND(ti, pci, 1, 1, 1); 277MODULE_DEPEND(ti, ether, 1, 1, 1); 278 279/* 280 * Send an instruction or address to the EEPROM, check for ACK. 281 */ 282static uint32_t 283ti_eeprom_putbyte(struct ti_softc *sc, int byte) 284{ 285 int i, ack = 0; 286 287 /* 288 * Make sure we're in TX mode. 289 */ 290 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 291 292 /* 293 * Feed in each bit and stobe the clock. 294 */ 295 for (i = 0x80; i; i >>= 1) { 296 if (byte & i) { 297 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 298 } else { 299 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 300 } 301 DELAY(1); 302 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 303 DELAY(1); 304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 305 } 306 307 /* 308 * Turn off TX mode. 309 */ 310 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 311 312 /* 313 * Check for ack. 314 */ 315 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 316 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 318 319 return (ack); 320} 321 322/* 323 * Read a byte of data stored in the EEPROM at address 'addr.' 324 * We have to send two address bytes since the EEPROM can hold 325 * more than 256 bytes of data. 326 */ 327static uint8_t 328ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 329{ 330 int i; 331 uint8_t byte = 0; 332 333 EEPROM_START; 334 335 /* 336 * Send write control code to EEPROM. 337 */ 338 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 339 device_printf(sc->ti_dev, 340 "failed to send write command, status: %x\n", 341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 342 return (1); 343 } 344 345 /* 346 * Send first byte of address of byte we want to read. 347 */ 348 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 349 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 /* 354 * Send second byte address of byte we want to read. 355 */ 356 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 357 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 358 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 359 return (1); 360 } 361 362 EEPROM_STOP; 363 EEPROM_START; 364 /* 365 * Send read control code to EEPROM. 366 */ 367 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 368 device_printf(sc->ti_dev, 369 "failed to send read command, status: %x\n", 370 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 371 return (1); 372 } 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 378 for (i = 0x80; i; i >>= 1) { 379 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 380 DELAY(1); 381 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 382 byte |= i; 383 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 384 DELAY(1); 385 } 386 387 EEPROM_STOP; 388 389 /* 390 * No ACK generated for read, so just return byte. 391 */ 392 393 *dest = byte; 394 395 return (0); 396} 397 398/* 399 * Read a sequence of bytes from the EEPROM. 400 */ 401static int 402ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 403{ 404 int err = 0, i; 405 uint8_t byte = 0; 406 407 for (i = 0; i < cnt; i++) { 408 err = ti_eeprom_getbyte(sc, off + i, &byte); 409 if (err) 410 break; 411 *(dest + i) = byte; 412 } 413 414 return (err ? 1 : 0); 415} 416 417/* 418 * NIC memory read function. 419 * Can be used to copy data from NIC local memory. 420 */ 421static void 422ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 423{ 424 int segptr, segsize, cnt; 425 char *ptr; 426 427 segptr = addr; 428 cnt = len; 429 ptr = buf; 430 431 while (cnt) { 432 if (cnt < TI_WINLEN) 433 segsize = cnt; 434 else 435 segsize = TI_WINLEN - (segptr % TI_WINLEN); 436 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 437 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 438 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 439 segsize / 4); 440 ptr += segsize; 441 segptr += segsize; 442 cnt -= segsize; 443 } 444} 445 446 447/* 448 * NIC memory write function. 449 * Can be used to copy data into NIC local memory. 450 */ 451static void 452ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 453{ 454 int segptr, segsize, cnt; 455 char *ptr; 456 457 segptr = addr; 458 cnt = len; 459 ptr = buf; 460 461 while (cnt) { 462 if (cnt < TI_WINLEN) 463 segsize = cnt; 464 else 465 segsize = TI_WINLEN - (segptr % TI_WINLEN); 466 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 467 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 468 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 469 segsize / 4); 470 ptr += segsize; 471 segptr += segsize; 472 cnt -= segsize; 473 } 474} 475 476/* 477 * NIC memory read function. 478 * Can be used to clear a section of NIC local memory. 479 */ 480static void 481ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 482{ 483 int segptr, segsize, cnt; 484 485 segptr = addr; 486 cnt = len; 487 488 while (cnt) { 489 if (cnt < TI_WINLEN) 490 segsize = cnt; 491 else 492 segsize = TI_WINLEN - (segptr % TI_WINLEN); 493 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 494 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 495 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 496 segptr += segsize; 497 cnt -= segsize; 498 } 499} 500 501static int 502ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 503 caddr_t buf, int useraddr, int readdata) 504{ 505 int segptr, segsize, cnt; 506 caddr_t ptr; 507 uint32_t origwin; 508 int resid, segresid; 509 int first_pass; 510 511 TI_LOCK_ASSERT(sc); 512 513 /* 514 * At the moment, we don't handle non-aligned cases, we just bail. 515 * If this proves to be a problem, it will be fixed. 516 */ 517 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 518 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 519 "word-aligned\n", __func__, tigon_addr); 520 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 521 "yet supported\n", __func__); 522 return (EINVAL); 523 } 524 525 segptr = tigon_addr & ~0x3; 526 segresid = tigon_addr - segptr; 527 528 /* 529 * This is the non-aligned amount left over that we'll need to 530 * copy. 531 */ 532 resid = len & 0x3; 533 534 /* Add in the left over amount at the front of the buffer */ 535 resid += segresid; 536 537 cnt = len & ~0x3; 538 /* 539 * If resid + segresid is >= 4, add multiples of 4 to the count and 540 * decrease the residual by that much. 541 */ 542 cnt += resid & ~0x3; 543 resid -= resid & ~0x3; 544 545 ptr = buf; 546 547 first_pass = 1; 548 549 /* 550 * Save the old window base value. 551 */ 552 origwin = CSR_READ_4(sc, TI_WINBASE); 553 554 while (cnt) { 555 bus_size_t ti_offset; 556 557 if (cnt < TI_WINLEN) 558 segsize = cnt; 559 else 560 segsize = TI_WINLEN - (segptr % TI_WINLEN); 561 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 562 563 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 564 565 if (readdata) { 566 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 567 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 568 if (useraddr) { 569 /* 570 * Yeah, this is a little on the kludgy 571 * side, but at least this code is only 572 * used for debugging. 573 */ 574 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 575 segsize, TI_SWAP_NTOH); 576 577 TI_UNLOCK(sc); 578 if (first_pass) { 579 copyout(&sc->ti_membuf2[segresid], ptr, 580 segsize - segresid); 581 first_pass = 0; 582 } else 583 copyout(sc->ti_membuf2, ptr, segsize); 584 TI_LOCK(sc); 585 } else { 586 if (first_pass) { 587 588 ti_bcopy_swap(sc->ti_membuf, 589 sc->ti_membuf2, segsize, 590 TI_SWAP_NTOH); 591 TI_UNLOCK(sc); 592 bcopy(&sc->ti_membuf2[segresid], ptr, 593 segsize - segresid); 594 TI_LOCK(sc); 595 first_pass = 0; 596 } else 597 ti_bcopy_swap(sc->ti_membuf, ptr, 598 segsize, TI_SWAP_NTOH); 599 } 600 601 } else { 602 if (useraddr) { 603 TI_UNLOCK(sc); 604 copyin(ptr, sc->ti_membuf2, segsize); 605 TI_LOCK(sc); 606 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 607 segsize, TI_SWAP_HTON); 608 } else 609 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 610 TI_SWAP_HTON); 611 612 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 613 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 614 } 615 segptr += segsize; 616 ptr += segsize; 617 cnt -= segsize; 618 } 619 620 /* 621 * Handle leftover, non-word-aligned bytes. 622 */ 623 if (resid != 0) { 624 uint32_t tmpval, tmpval2; 625 bus_size_t ti_offset; 626 627 /* 628 * Set the segment pointer. 629 */ 630 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 631 632 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 633 634 /* 635 * First, grab whatever is in our source/destination. 636 * We'll obviously need this for reads, but also for 637 * writes, since we'll be doing read/modify/write. 638 */ 639 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 640 ti_offset, &tmpval, 1); 641 642 /* 643 * Next, translate this from little-endian to big-endian 644 * (at least on i386 boxes). 645 */ 646 tmpval2 = ntohl(tmpval); 647 648 if (readdata) { 649 /* 650 * If we're reading, just copy the leftover number 651 * of bytes from the host byte order buffer to 652 * the user's buffer. 653 */ 654 if (useraddr) { 655 TI_UNLOCK(sc); 656 copyout(&tmpval2, ptr, resid); 657 TI_LOCK(sc); 658 } else 659 bcopy(&tmpval2, ptr, resid); 660 } else { 661 /* 662 * If we're writing, first copy the bytes to be 663 * written into the network byte order buffer, 664 * leaving the rest of the buffer with whatever was 665 * originally in there. Then, swap the bytes 666 * around into host order and write them out. 667 * 668 * XXX KDM the read side of this has been verified 669 * to work, but the write side of it has not been 670 * verified. So user beware. 671 */ 672 if (useraddr) { 673 TI_UNLOCK(sc); 674 copyin(ptr, &tmpval2, resid); 675 TI_LOCK(sc); 676 } else 677 bcopy(ptr, &tmpval2, resid); 678 679 tmpval = htonl(tmpval2); 680 681 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 682 ti_offset, &tmpval, 1); 683 } 684 } 685 686 CSR_WRITE_4(sc, TI_WINBASE, origwin); 687 688 return (0); 689} 690 691static int 692ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 693 caddr_t buf, int useraddr, int readdata, int cpu) 694{ 695 uint32_t segptr; 696 int cnt; 697 uint32_t tmpval, tmpval2; 698 caddr_t ptr; 699 700 TI_LOCK_ASSERT(sc); 701 702 /* 703 * At the moment, we don't handle non-aligned cases, we just bail. 704 * If this proves to be a problem, it will be fixed. 705 */ 706 if (tigon_addr & 0x3) { 707 device_printf(sc->ti_dev, "%s: tigon address %#x " 708 "isn't word-aligned\n", __func__, tigon_addr); 709 return (EINVAL); 710 } 711 712 if (len & 0x3) { 713 device_printf(sc->ti_dev, "%s: transfer length %d " 714 "isn't word-aligned\n", __func__, len); 715 return (EINVAL); 716 } 717 718 segptr = tigon_addr; 719 cnt = len; 720 ptr = buf; 721 722 while (cnt) { 723 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 724 725 if (readdata) { 726 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 727 728 tmpval = ntohl(tmpval2); 729 730 /* 731 * Note: I've used this debugging interface 732 * extensively with Alteon's 12.3.15 firmware, 733 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 734 * 735 * When you compile the firmware without 736 * optimization, which is necessary sometimes in 737 * order to properly step through it, you sometimes 738 * read out a bogus value of 0xc0017c instead of 739 * whatever was supposed to be in that scratchpad 740 * location. That value is on the stack somewhere, 741 * but I've never been able to figure out what was 742 * causing the problem. 743 * 744 * The address seems to pop up in random places, 745 * often not in the same place on two subsequent 746 * reads. 747 * 748 * In any case, the underlying data doesn't seem 749 * to be affected, just the value read out. 750 * 751 * KDM, 3/7/2000 752 */ 753 754 if (tmpval2 == 0xc0017c) 755 device_printf(sc->ti_dev, "found 0xc0017c at " 756 "%#x (tmpval2)\n", segptr); 757 758 if (tmpval == 0xc0017c) 759 device_printf(sc->ti_dev, "found 0xc0017c at " 760 "%#x (tmpval)\n", segptr); 761 762 if (useraddr) 763 copyout(&tmpval, ptr, 4); 764 else 765 bcopy(&tmpval, ptr, 4); 766 } else { 767 if (useraddr) 768 copyin(ptr, &tmpval2, 4); 769 else 770 bcopy(ptr, &tmpval2, 4); 771 772 tmpval = htonl(tmpval2); 773 774 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 775 } 776 777 cnt -= 4; 778 segptr += 4; 779 ptr += 4; 780 } 781 782 return (0); 783} 784 785static int 786ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 787{ 788 const uint8_t *tmpsrc; 789 uint8_t *tmpdst; 790 size_t tmplen; 791 792 if (len & 0x3) { 793 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 794 return (-1); 795 } 796 797 tmpsrc = src; 798 tmpdst = dst; 799 tmplen = len; 800 801 while (tmplen) { 802 if (swap_type == TI_SWAP_NTOH) 803 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 804 else 805 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 806 tmpsrc += 4; 807 tmpdst += 4; 808 tmplen -= 4; 809 } 810 811 return (0); 812} 813 814/* 815 * Load firmware image into the NIC. Check that the firmware revision 816 * is acceptable and see if we want the firmware for the Tigon 1 or 817 * Tigon 2. 818 */ 819static void 820ti_loadfw(struct ti_softc *sc) 821{ 822 823 TI_LOCK_ASSERT(sc); 824 825 switch (sc->ti_hwrev) { 826 case TI_HWREV_TIGON: 827 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 828 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 829 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 830 device_printf(sc->ti_dev, "firmware revision mismatch; " 831 "want %d.%d.%d, got %d.%d.%d\n", 832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 833 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 834 tigonFwReleaseMinor, tigonFwReleaseFix); 835 return; 836 } 837 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 838 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 839 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 840 tigonFwRodata); 841 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 842 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 844 break; 845 case TI_HWREV_TIGON_II: 846 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 847 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 848 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 849 device_printf(sc->ti_dev, "firmware revision mismatch; " 850 "want %d.%d.%d, got %d.%d.%d\n", 851 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 852 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 853 tigon2FwReleaseMinor, tigon2FwReleaseFix); 854 return; 855 } 856 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 857 tigon2FwText); 858 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 859 tigon2FwData); 860 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 861 tigon2FwRodata); 862 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 863 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 864 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 865 break; 866 default: 867 device_printf(sc->ti_dev, 868 "can't load firmware: unknown hardware rev\n"); 869 break; 870 } 871} 872 873/* 874 * Send the NIC a command via the command ring. 875 */ 876static void 877ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 878{ 879 int index; 880 881 index = sc->ti_cmd_saved_prodidx; 882 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 883 TI_INC(index, TI_CMD_RING_CNT); 884 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 885 sc->ti_cmd_saved_prodidx = index; 886} 887 888/* 889 * Send the NIC an extended command. The 'len' parameter specifies the 890 * number of command slots to include after the initial command. 891 */ 892static void 893ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 894{ 895 int index; 896 int i; 897 898 index = sc->ti_cmd_saved_prodidx; 899 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 900 TI_INC(index, TI_CMD_RING_CNT); 901 for (i = 0; i < len; i++) { 902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 903 *(uint32_t *)(&arg[i * 4])); 904 TI_INC(index, TI_CMD_RING_CNT); 905 } 906 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 907 sc->ti_cmd_saved_prodidx = index; 908} 909 910/* 911 * Handle events that have triggered interrupts. 912 */ 913static void 914ti_handle_events(struct ti_softc *sc) 915{ 916 struct ti_event_desc *e; 917 918 if (sc->ti_rdata.ti_event_ring == NULL) 919 return; 920 921 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 922 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 924 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 925 switch (TI_EVENT_EVENT(e)) { 926 case TI_EV_LINKSTAT_CHANGED: 927 sc->ti_linkstat = TI_EVENT_CODE(e); 928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 930 sc->ti_ifp->if_baudrate = IF_Mbps(100); 931 if (bootverbose) 932 device_printf(sc->ti_dev, 933 "10/100 link up\n"); 934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 937 if (bootverbose) 938 device_printf(sc->ti_dev, 939 "gigabit link up\n"); 940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 941 if_link_state_change(sc->ti_ifp, 942 LINK_STATE_DOWN); 943 sc->ti_ifp->if_baudrate = 0; 944 if (bootverbose) 945 device_printf(sc->ti_dev, 946 "link down\n"); 947 } 948 break; 949 case TI_EV_ERROR: 950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 951 device_printf(sc->ti_dev, "invalid command\n"); 952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 953 device_printf(sc->ti_dev, "unknown command\n"); 954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 955 device_printf(sc->ti_dev, "bad config data\n"); 956 break; 957 case TI_EV_FIRMWARE_UP: 958 ti_init2(sc); 959 break; 960 case TI_EV_STATS_UPDATED: 961 ti_stats_update(sc); 962 break; 963 case TI_EV_RESET_JUMBO_RING: 964 case TI_EV_MCAST_UPDATED: 965 /* Who cares. */ 966 break; 967 default: 968 device_printf(sc->ti_dev, "unknown event: %d\n", 969 TI_EVENT_EVENT(e)); 970 break; 971 } 972 /* Advance the consumer index. */ 973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 975 } 976 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 977 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 978} 979 980struct ti_dmamap_arg { 981 bus_addr_t ti_busaddr; 982}; 983 984static void 985ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 986{ 987 struct ti_dmamap_arg *ctx; 988 989 if (error) 990 return; 991 992 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 993 994 ctx = arg; 995 ctx->ti_busaddr = segs->ds_addr; 996} 997 998static int 999ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 1000 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1001 const char *msg) 1002{ 1003 struct ti_dmamap_arg ctx; 1004 int error; 1005 1006 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1007 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1008 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1009 if (error != 0) { 1010 device_printf(sc->ti_dev, 1011 "could not create %s dma tag\n", msg); 1012 return (error); 1013 } 1014 /* Allocate DMA'able memory for ring. */ 1015 error = bus_dmamem_alloc(*tag, (void **)ring, 1016 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1017 if (error != 0) { 1018 device_printf(sc->ti_dev, 1019 "could not allocate DMA'able memory for %s\n", msg); 1020 return (error); 1021 } 1022 /* Load the address of the ring. */ 1023 ctx.ti_busaddr = 0; 1024 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1025 &ctx, BUS_DMA_NOWAIT); 1026 if (error != 0) { 1027 device_printf(sc->ti_dev, 1028 "could not load DMA'able memory for %s\n", msg); 1029 return (error); 1030 } 1031 *paddr = ctx.ti_busaddr; 1032 return (0); 1033} 1034 1035static void 1036ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1037 bus_dmamap_t *map) 1038{ 1039 1040 if (*map != NULL) 1041 bus_dmamap_unload(*tag, *map); 1042 if (*map != NULL && *ring != NULL) { 1043 bus_dmamem_free(*tag, *ring, *map); 1044 *ring = NULL; 1045 *map = NULL; 1046 } 1047 if (*tag) { 1048 bus_dma_tag_destroy(*tag); 1049 *tag = NULL; 1050 } 1051} 1052 1053static int 1054ti_dma_alloc(struct ti_softc *sc) 1055{ 1056 bus_addr_t lowaddr; 1057 int i, error; 1058 1059 lowaddr = BUS_SPACE_MAXADDR; 1060 if (sc->ti_dac == 0) 1061 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1062 1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1064 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1065 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1066 &sc->ti_cdata.ti_parent_tag); 1067 if (error != 0) { 1068 device_printf(sc->ti_dev, 1069 "could not allocate parent dma tag\n"); 1070 return (ENOMEM); 1071 } 1072 1073 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1074 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1075 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1076 if (error) 1077 return (error); 1078 1079 /* Producer/consumer status */ 1080 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1081 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1082 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1083 "event ring"); 1084 if (error) 1085 return (error); 1086 1087 /* Event ring */ 1088 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1089 &sc->ti_cdata.ti_event_ring_tag, 1090 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1091 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1092 "event ring"); 1093 if (error) 1094 return (error); 1095 1096 /* Command ring lives in shared memory so no need to create DMA area. */ 1097 1098 /* Standard RX ring */ 1099 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1100 &sc->ti_cdata.ti_rx_std_ring_tag, 1101 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1102 &sc->ti_cdata.ti_rx_std_ring_map, 1103 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1104 if (error) 1105 return (error); 1106 1107 /* Jumbo RX ring */ 1108 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1109 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1110 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1111 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1112 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1113 if (error) 1114 return (error); 1115 1116 /* RX return ring */ 1117 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1118 &sc->ti_cdata.ti_rx_return_ring_tag, 1119 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1120 &sc->ti_cdata.ti_rx_return_ring_map, 1121 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1122 if (error) 1123 return (error); 1124 1125 /* Create DMA tag for standard RX mbufs. */ 1126 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1128 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1129 if (error) { 1130 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1131 return (error); 1132 } 1133 1134 /* Create DMA tag for jumbo RX mbufs. */ 1135#ifdef TI_SF_BUF_JUMBO 1136 /* 1137 * The VM system will take care of providing aligned pages. Alignment 1138 * is set to 1 here so that busdma resources won't be wasted. 1139 */ 1140 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1141 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1142 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1143#else 1144 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1146 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1147#endif 1148 if (error) { 1149 device_printf(sc->ti_dev, 1150 "could not allocate jumbo RX dma tag\n"); 1151 return (error); 1152 } 1153 1154 /* Create DMA tag for TX mbufs. */ 1155 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1156 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1157 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1158 &sc->ti_cdata.ti_tx_tag); 1159 if (error) { 1160 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1161 return (ENOMEM); 1162 } 1163 1164 /* Create DMA maps for RX buffers. */ 1165 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1166 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1167 &sc->ti_cdata.ti_rx_std_maps[i]); 1168 if (error) { 1169 device_printf(sc->ti_dev, 1170 "could not create DMA map for RX\n"); 1171 return (error); 1172 } 1173 } 1174 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1175 &sc->ti_cdata.ti_rx_std_sparemap); 1176 if (error) { 1177 device_printf(sc->ti_dev, 1178 "could not create spare DMA map for RX\n"); 1179 return (error); 1180 } 1181 1182 /* Create DMA maps for jumbo RX buffers. */ 1183 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1184 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1185 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1186 if (error) { 1187 device_printf(sc->ti_dev, 1188 "could not create DMA map for jumbo RX\n"); 1189 return (error); 1190 } 1191 } 1192 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1193 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1194 if (error) { 1195 device_printf(sc->ti_dev, 1196 "could not create spare DMA map for jumbo RX\n"); 1197 return (error); 1198 } 1199 1200 /* Create DMA maps for TX buffers. */ 1201 for (i = 0; i < TI_TX_RING_CNT; i++) { 1202 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1203 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1204 if (error) { 1205 device_printf(sc->ti_dev, 1206 "could not create DMA map for TX\n"); 1207 return (ENOMEM); 1208 } 1209 } 1210 1211 /* Mini ring and TX ring is not available on Tigon 1. */ 1212 if (sc->ti_hwrev == TI_HWREV_TIGON) 1213 return (0); 1214 1215 /* TX ring */ 1216 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1217 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1218 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1219 "TX ring"); 1220 if (error) 1221 return (error); 1222 1223 /* Mini RX ring */ 1224 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1225 &sc->ti_cdata.ti_rx_mini_ring_tag, 1226 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1227 &sc->ti_cdata.ti_rx_mini_ring_map, 1228 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1229 if (error) 1230 return (error); 1231 1232 /* Create DMA tag for mini RX mbufs. */ 1233 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1235 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1236 if (error) { 1237 device_printf(sc->ti_dev, 1238 "could not allocate mini RX dma tag\n"); 1239 return (error); 1240 } 1241 1242 /* Create DMA maps for mini RX buffers. */ 1243 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1244 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1245 &sc->ti_cdata.ti_rx_mini_maps[i]); 1246 if (error) { 1247 device_printf(sc->ti_dev, 1248 "could not create DMA map for mini RX\n"); 1249 return (error); 1250 } 1251 } 1252 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1253 &sc->ti_cdata.ti_rx_mini_sparemap); 1254 if (error) { 1255 device_printf(sc->ti_dev, 1256 "could not create spare DMA map for mini RX\n"); 1257 return (error); 1258 } 1259 1260 return (0); 1261} 1262 1263static void 1264ti_dma_free(struct ti_softc *sc) 1265{ 1266 int i; 1267 1268 /* Destroy DMA maps for RX buffers. */ 1269 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1270 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1271 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1272 sc->ti_cdata.ti_rx_std_maps[i]); 1273 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1274 } 1275 } 1276 if (sc->ti_cdata.ti_rx_std_sparemap) { 1277 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1278 sc->ti_cdata.ti_rx_std_sparemap); 1279 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1280 } 1281 if (sc->ti_cdata.ti_rx_std_tag) { 1282 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1283 sc->ti_cdata.ti_rx_std_tag = NULL; 1284 } 1285 1286 /* Destroy DMA maps for jumbo RX buffers. */ 1287 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1288 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1289 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1290 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1291 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1292 } 1293 } 1294 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1295 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1296 sc->ti_cdata.ti_rx_jumbo_sparemap); 1297 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1298 } 1299 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1300 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1301 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1302 } 1303 1304 /* Destroy DMA maps for mini RX buffers. */ 1305 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1306 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1307 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1308 sc->ti_cdata.ti_rx_mini_maps[i]); 1309 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1310 } 1311 } 1312 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1313 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1314 sc->ti_cdata.ti_rx_mini_sparemap); 1315 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1316 } 1317 if (sc->ti_cdata.ti_rx_mini_tag) { 1318 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1319 sc->ti_cdata.ti_rx_mini_tag = NULL; 1320 } 1321 1322 /* Destroy DMA maps for TX buffers. */ 1323 for (i = 0; i < TI_TX_RING_CNT; i++) { 1324 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1325 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1326 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1327 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1328 } 1329 } 1330 if (sc->ti_cdata.ti_tx_tag) { 1331 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1332 sc->ti_cdata.ti_tx_tag = NULL; 1333 } 1334 1335 /* Destroy standard RX ring. */ 1336 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1337 (void *)&sc->ti_rdata.ti_rx_std_ring, 1338 &sc->ti_cdata.ti_rx_std_ring_map); 1339 /* Destroy jumbo RX ring. */ 1340 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1341 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1342 &sc->ti_cdata.ti_rx_jumbo_ring_map); 1343 /* Destroy mini RX ring. */ 1344 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1345 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1346 &sc->ti_cdata.ti_rx_mini_ring_map); 1347 /* Destroy RX return ring. */ 1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1349 (void *)&sc->ti_rdata.ti_rx_return_ring, 1350 &sc->ti_cdata.ti_rx_return_ring_map); 1351 /* Destroy TX ring. */ 1352 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1353 (void *)&sc->ti_rdata.ti_tx_ring, &sc->ti_cdata.ti_tx_ring_map); 1354 /* Destroy status block. */ 1355 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1356 (void *)&sc->ti_rdata.ti_status, &sc->ti_cdata.ti_status_map); 1357 /* Destroy event ring. */ 1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1359 (void *)&sc->ti_rdata.ti_event_ring, 1360 &sc->ti_cdata.ti_event_ring_map); 1361 /* Destroy GIB */ 1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1363 (void *)&sc->ti_rdata.ti_info, &sc->ti_cdata.ti_gib_map); 1364 1365 /* Destroy the parent tag. */ 1366 if (sc->ti_cdata.ti_parent_tag) { 1367 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1368 sc->ti_cdata.ti_parent_tag = NULL; 1369 } 1370} 1371 1372/* 1373 * Intialize a standard receive ring descriptor. 1374 */ 1375static int 1376ti_newbuf_std(struct ti_softc *sc, int i) 1377{ 1378 bus_dmamap_t map; 1379 bus_dma_segment_t segs[1]; 1380 struct mbuf *m; 1381 struct ti_rx_desc *r; 1382 int error, nsegs; 1383 1384 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1385 if (m == NULL) 1386 return (ENOBUFS); 1387 m->m_len = m->m_pkthdr.len = MCLBYTES; 1388 m_adj(m, ETHER_ALIGN); 1389 1390 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1391 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1392 if (error != 0) { 1393 m_freem(m); 1394 return (error); 1395 } 1396 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1397 1398 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1399 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1400 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1402 sc->ti_cdata.ti_rx_std_maps[i]); 1403 } 1404 1405 map = sc->ti_cdata.ti_rx_std_maps[i]; 1406 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1407 sc->ti_cdata.ti_rx_std_sparemap = map; 1408 sc->ti_cdata.ti_rx_std_chain[i] = m; 1409 1410 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1411 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1412 r->ti_len = segs[0].ds_len; 1413 r->ti_type = TI_BDTYPE_RECV_BD; 1414 r->ti_flags = 0; 1415 r->ti_vlan_tag = 0; 1416 r->ti_tcp_udp_cksum = 0; 1417 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1418 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1419 r->ti_idx = i; 1420 1421 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1422 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1423 return (0); 1424} 1425 1426/* 1427 * Intialize a mini receive ring descriptor. This only applies to 1428 * the Tigon 2. 1429 */ 1430static int 1431ti_newbuf_mini(struct ti_softc *sc, int i) 1432{ 1433 bus_dmamap_t map; 1434 bus_dma_segment_t segs[1]; 1435 struct mbuf *m; 1436 struct ti_rx_desc *r; 1437 int error, nsegs; 1438 1439 MGETHDR(m, M_DONTWAIT, MT_DATA); 1440 if (m == NULL) 1441 return (ENOBUFS); 1442 m->m_len = m->m_pkthdr.len = MHLEN; 1443 m_adj(m, ETHER_ALIGN); 1444 1445 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1446 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1447 if (error != 0) { 1448 m_freem(m); 1449 return (error); 1450 } 1451 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1452 1453 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1454 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1455 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1456 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1457 sc->ti_cdata.ti_rx_mini_maps[i]); 1458 } 1459 1460 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1461 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1462 sc->ti_cdata.ti_rx_mini_sparemap = map; 1463 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1464 1465 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1466 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1467 r->ti_len = segs[0].ds_len; 1468 r->ti_type = TI_BDTYPE_RECV_BD; 1469 r->ti_flags = TI_BDFLAG_MINI_RING; 1470 r->ti_vlan_tag = 0; 1471 r->ti_tcp_udp_cksum = 0; 1472 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1473 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1474 r->ti_idx = i; 1475 1476 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1477 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1478 return (0); 1479} 1480 1481#ifndef TI_SF_BUF_JUMBO 1482 1483/* 1484 * Initialize a jumbo receive ring descriptor. This allocates 1485 * a jumbo buffer from the pool managed internally by the driver. 1486 */ 1487static int 1488ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1489{ 1490 bus_dmamap_t map; 1491 bus_dma_segment_t segs[1]; 1492 struct mbuf *m; 1493 struct ti_rx_desc *r; 1494 int error, nsegs; 1495 1496 (void)dummy; 1497 1498 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1499 if (m == NULL) 1500 return (ENOBUFS); 1501 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1502 m_adj(m, ETHER_ALIGN); 1503 1504 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1505 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1506 if (error != 0) { 1507 m_freem(m); 1508 return (error); 1509 } 1510 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1511 1512 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1513 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1514 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1515 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1516 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1517 } 1518 1519 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1520 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1521 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1522 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1523 1524 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1525 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1526 r->ti_len = segs[0].ds_len; 1527 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1528 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1529 r->ti_vlan_tag = 0; 1530 r->ti_tcp_udp_cksum = 0; 1531 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1532 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1533 r->ti_idx = i; 1534 1535 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1536 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1537 return (0); 1538} 1539 1540#else 1541 1542#if (PAGE_SIZE == 4096) 1543#define NPAYLOAD 2 1544#else 1545#define NPAYLOAD 1 1546#endif 1547 1548#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1549#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1550#define NFS_HDR_LEN (UDP_HDR_LEN) 1551static int HDR_LEN = TCP_HDR_LEN; 1552 1553/* 1554 * Initialize a jumbo receive ring descriptor. This allocates 1555 * a jumbo buffer from the pool managed internally by the driver. 1556 */ 1557static int 1558ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1559{ 1560 bus_dmamap_t map; 1561 struct mbuf *cur, *m_new = NULL; 1562 struct mbuf *m[3] = {NULL, NULL, NULL}; 1563 struct ti_rx_desc_ext *r; 1564 vm_page_t frame; 1565 /* 1 extra buf to make nobufs easy*/ 1566 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1567 int i; 1568 bus_dma_segment_t segs[4]; 1569 int nsegs; 1570 1571 if (m_old != NULL) { 1572 m_new = m_old; 1573 cur = m_old->m_next; 1574 for (i = 0; i <= NPAYLOAD; i++){ 1575 m[i] = cur; 1576 cur = cur->m_next; 1577 } 1578 } else { 1579 /* Allocate the mbufs. */ 1580 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1581 if (m_new == NULL) { 1582 device_printf(sc->ti_dev, "mbuf allocation failed " 1583 "-- packet dropped!\n"); 1584 goto nobufs; 1585 } 1586 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1587 if (m[NPAYLOAD] == NULL) { 1588 device_printf(sc->ti_dev, "cluster mbuf allocation " 1589 "failed -- packet dropped!\n"); 1590 goto nobufs; 1591 } 1592 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1593 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1594 device_printf(sc->ti_dev, "mbuf allocation failed " 1595 "-- packet dropped!\n"); 1596 goto nobufs; 1597 } 1598 m[NPAYLOAD]->m_len = MCLBYTES; 1599 1600 for (i = 0; i < NPAYLOAD; i++){ 1601 MGET(m[i], M_DONTWAIT, MT_DATA); 1602 if (m[i] == NULL) { 1603 device_printf(sc->ti_dev, "mbuf allocation " 1604 "failed -- packet dropped!\n"); 1605 goto nobufs; 1606 } 1607 frame = vm_page_alloc(NULL, 0, 1608 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1609 VM_ALLOC_WIRED); 1610 if (frame == NULL) { 1611 device_printf(sc->ti_dev, "buffer allocation " 1612 "failed -- packet dropped!\n"); 1613 printf(" index %d page %d\n", idx, i); 1614 goto nobufs; 1615 } 1616 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1617 if (sf[i] == NULL) { 1618 vm_page_unwire(frame, 0); 1619 vm_page_free(frame); 1620 device_printf(sc->ti_dev, "buffer allocation " 1621 "failed -- packet dropped!\n"); 1622 printf(" index %d page %d\n", idx, i); 1623 goto nobufs; 1624 } 1625 } 1626 for (i = 0; i < NPAYLOAD; i++){ 1627 /* Attach the buffer to the mbuf. */ 1628 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1629 m[i]->m_len = PAGE_SIZE; 1630 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1631 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1632 0, EXT_DISPOSABLE); 1633 m[i]->m_next = m[i+1]; 1634 } 1635 /* link the buffers to the header */ 1636 m_new->m_next = m[0]; 1637 m_new->m_data += ETHER_ALIGN; 1638 if (sc->ti_hdrsplit) 1639 m_new->m_len = MHLEN - ETHER_ALIGN; 1640 else 1641 m_new->m_len = HDR_LEN; 1642 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1643 } 1644 1645 /* Set up the descriptor. */ 1646 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1647 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1648 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1649 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1650 segs, &nsegs, 0)) 1651 return (ENOBUFS); 1652 if ((nsegs < 1) || (nsegs > 4)) 1653 return (ENOBUFS); 1654 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1655 r->ti_len0 = m_new->m_len; 1656 1657 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1658 r->ti_len1 = PAGE_SIZE; 1659 1660 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1661 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1662 1663 if (PAGE_SIZE == 4096) { 1664 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1665 r->ti_len3 = MCLBYTES; 1666 } else { 1667 r->ti_len3 = 0; 1668 } 1669 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1670 1671 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1672 1673 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1674 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1675 1676 r->ti_idx = idx; 1677 1678 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1679 return (0); 1680 1681nobufs: 1682 1683 /* 1684 * Warning! : 1685 * This can only be called before the mbufs are strung together. 1686 * If the mbufs are strung together, m_freem() will free the chain, 1687 * so that the later mbufs will be freed multiple times. 1688 */ 1689 if (m_new) 1690 m_freem(m_new); 1691 1692 for (i = 0; i < 3; i++) { 1693 if (m[i]) 1694 m_freem(m[i]); 1695 if (sf[i]) 1696 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1697 } 1698 return (ENOBUFS); 1699} 1700#endif 1701 1702/* 1703 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1704 * that's 1MB or memory, which is a lot. For now, we fill only the first 1705 * 256 ring entries and hope that our CPU is fast enough to keep up with 1706 * the NIC. 1707 */ 1708static int 1709ti_init_rx_ring_std(struct ti_softc *sc) 1710{ 1711 int i; 1712 struct ti_cmd_desc cmd; 1713 1714 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1715 if (ti_newbuf_std(sc, i) != 0) 1716 return (ENOBUFS); 1717 }; 1718 1719 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1720 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1721 1722 return (0); 1723} 1724 1725static void 1726ti_free_rx_ring_std(struct ti_softc *sc) 1727{ 1728 bus_dmamap_t map; 1729 int i; 1730 1731 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1732 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1733 map = sc->ti_cdata.ti_rx_std_maps[i]; 1734 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1735 BUS_DMASYNC_POSTREAD); 1736 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1737 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1738 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1739 } 1740 } 1741 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1742 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1743 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1744} 1745 1746static int 1747ti_init_rx_ring_jumbo(struct ti_softc *sc) 1748{ 1749 struct ti_cmd_desc cmd; 1750 int i; 1751 1752 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1753 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1754 return (ENOBUFS); 1755 }; 1756 1757 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1758 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1759 1760 return (0); 1761} 1762 1763static void 1764ti_free_rx_ring_jumbo(struct ti_softc *sc) 1765{ 1766 bus_dmamap_t map; 1767 int i; 1768 1769 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1770 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1771 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1772 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1773 BUS_DMASYNC_POSTREAD); 1774 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1775 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1776 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1777 } 1778 } 1779 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1780 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1781 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1782} 1783 1784static int 1785ti_init_rx_ring_mini(struct ti_softc *sc) 1786{ 1787 int i; 1788 1789 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1790 if (ti_newbuf_mini(sc, i) != 0) 1791 return (ENOBUFS); 1792 }; 1793 1794 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1795 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1796 1797 return (0); 1798} 1799 1800static void 1801ti_free_rx_ring_mini(struct ti_softc *sc) 1802{ 1803 bus_dmamap_t map; 1804 int i; 1805 1806 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1807 return; 1808 1809 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1810 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1811 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1812 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1813 BUS_DMASYNC_POSTREAD); 1814 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1815 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1816 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1817 } 1818 } 1819 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1820 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1821 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1822} 1823 1824static void 1825ti_free_tx_ring(struct ti_softc *sc) 1826{ 1827 struct ti_txdesc *txd; 1828 int i; 1829 1830 if (sc->ti_rdata.ti_tx_ring == NULL) 1831 return; 1832 1833 for (i = 0; i < TI_TX_RING_CNT; i++) { 1834 txd = &sc->ti_cdata.ti_txdesc[i]; 1835 if (txd->tx_m != NULL) { 1836 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1837 BUS_DMASYNC_POSTWRITE); 1838 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1839 txd->tx_dmamap); 1840 m_freem(txd->tx_m); 1841 txd->tx_m = NULL; 1842 } 1843 } 1844 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1845 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1846 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1847} 1848 1849static int 1850ti_init_tx_ring(struct ti_softc *sc) 1851{ 1852 struct ti_txdesc *txd; 1853 int i; 1854 1855 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1856 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1857 for (i = 0; i < TI_TX_RING_CNT; i++) { 1858 txd = &sc->ti_cdata.ti_txdesc[i]; 1859 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1860 } 1861 sc->ti_txcnt = 0; 1862 sc->ti_tx_saved_considx = 0; 1863 sc->ti_tx_saved_prodidx = 0; 1864 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1865 return (0); 1866} 1867 1868/* 1869 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1870 * but we have to support the old way too so that Tigon 1 cards will 1871 * work. 1872 */ 1873static void 1874ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1875{ 1876 struct ti_cmd_desc cmd; 1877 uint16_t *m; 1878 uint32_t ext[2] = {0, 0}; 1879 1880 m = (uint16_t *)&addr->octet[0]; 1881 1882 switch (sc->ti_hwrev) { 1883 case TI_HWREV_TIGON: 1884 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1885 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1886 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1887 break; 1888 case TI_HWREV_TIGON_II: 1889 ext[0] = htons(m[0]); 1890 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1891 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1892 break; 1893 default: 1894 device_printf(sc->ti_dev, "unknown hwrev\n"); 1895 break; 1896 } 1897} 1898 1899static void 1900ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1901{ 1902 struct ti_cmd_desc cmd; 1903 uint16_t *m; 1904 uint32_t ext[2] = {0, 0}; 1905 1906 m = (uint16_t *)&addr->octet[0]; 1907 1908 switch (sc->ti_hwrev) { 1909 case TI_HWREV_TIGON: 1910 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1911 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1912 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1913 break; 1914 case TI_HWREV_TIGON_II: 1915 ext[0] = htons(m[0]); 1916 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1917 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1918 break; 1919 default: 1920 device_printf(sc->ti_dev, "unknown hwrev\n"); 1921 break; 1922 } 1923} 1924 1925/* 1926 * Configure the Tigon's multicast address filter. 1927 * 1928 * The actual multicast table management is a bit of a pain, thanks to 1929 * slight brain damage on the part of both Alteon and us. With our 1930 * multicast code, we are only alerted when the multicast address table 1931 * changes and at that point we only have the current list of addresses: 1932 * we only know the current state, not the previous state, so we don't 1933 * actually know what addresses were removed or added. The firmware has 1934 * state, but we can't get our grubby mits on it, and there is no 'delete 1935 * all multicast addresses' command. Hence, we have to maintain our own 1936 * state so we know what addresses have been programmed into the NIC at 1937 * any given time. 1938 */ 1939static void 1940ti_setmulti(struct ti_softc *sc) 1941{ 1942 struct ifnet *ifp; 1943 struct ifmultiaddr *ifma; 1944 struct ti_cmd_desc cmd; 1945 struct ti_mc_entry *mc; 1946 uint32_t intrs; 1947 1948 TI_LOCK_ASSERT(sc); 1949 1950 ifp = sc->ti_ifp; 1951 1952 if (ifp->if_flags & IFF_ALLMULTI) { 1953 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1954 return; 1955 } else { 1956 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1957 } 1958 1959 /* Disable interrupts. */ 1960 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1961 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1962 1963 /* First, zot all the existing filters. */ 1964 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1965 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1966 ti_del_mcast(sc, &mc->mc_addr); 1967 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1968 free(mc, M_DEVBUF); 1969 } 1970 1971 /* Now program new ones. */ 1972 if_maddr_rlock(ifp); 1973 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1974 if (ifma->ifma_addr->sa_family != AF_LINK) 1975 continue; 1976 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1977 if (mc == NULL) { 1978 device_printf(sc->ti_dev, 1979 "no memory for mcast filter entry\n"); 1980 continue; 1981 } 1982 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1983 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1984 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1985 ti_add_mcast(sc, &mc->mc_addr); 1986 } 1987 if_maddr_runlock(ifp); 1988 1989 /* Re-enable interrupts. */ 1990 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1991} 1992 1993/* 1994 * Check to see if the BIOS has configured us for a 64 bit slot when 1995 * we aren't actually in one. If we detect this condition, we can work 1996 * around it on the Tigon 2 by setting a bit in the PCI state register, 1997 * but for the Tigon 1 we must give up and abort the interface attach. 1998 */ 1999static int 2000ti_64bitslot_war(struct ti_softc *sc) 2001{ 2002 2003 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 2004 CSR_WRITE_4(sc, 0x600, 0); 2005 CSR_WRITE_4(sc, 0x604, 0); 2006 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2007 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2008 if (sc->ti_hwrev == TI_HWREV_TIGON) 2009 return (EINVAL); 2010 else { 2011 TI_SETBIT(sc, TI_PCI_STATE, 2012 TI_PCISTATE_32BIT_BUS); 2013 return (0); 2014 } 2015 } 2016 } 2017 2018 return (0); 2019} 2020 2021/* 2022 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2023 * self-test results. 2024 */ 2025static int 2026ti_chipinit(struct ti_softc *sc) 2027{ 2028 uint32_t cacheline; 2029 uint32_t pci_writemax = 0; 2030 uint32_t hdrsplit; 2031 2032 /* Initialize link to down state. */ 2033 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2034 2035 /* Set endianness before we access any non-PCI registers. */ 2036#if 0 && BYTE_ORDER == BIG_ENDIAN 2037 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2038 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2039#else 2040 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2041 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2042#endif 2043 2044 /* Check the ROM failed bit to see if self-tests passed. */ 2045 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2046 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2047 return (ENODEV); 2048 } 2049 2050 /* Halt the CPU. */ 2051 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2052 2053 /* Figure out the hardware revision. */ 2054 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2055 case TI_REV_TIGON_I: 2056 sc->ti_hwrev = TI_HWREV_TIGON; 2057 break; 2058 case TI_REV_TIGON_II: 2059 sc->ti_hwrev = TI_HWREV_TIGON_II; 2060 break; 2061 default: 2062 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2063 return (ENODEV); 2064 } 2065 2066 /* Do special setup for Tigon 2. */ 2067 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2068 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2069 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2070 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2071 } 2072 2073 /* 2074 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2075 * can't do header splitting. 2076 */ 2077#ifdef TI_JUMBO_HDRSPLIT 2078 if (sc->ti_hwrev != TI_HWREV_TIGON) 2079 sc->ti_hdrsplit = 1; 2080 else 2081 device_printf(sc->ti_dev, 2082 "can't do header splitting on a Tigon I board\n"); 2083#endif /* TI_JUMBO_HDRSPLIT */ 2084 2085 /* Set up the PCI state register. */ 2086 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2087 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2088 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2089 } 2090 2091 /* Clear the read/write max DMA parameters. */ 2092 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2093 TI_PCISTATE_READ_MAXDMA)); 2094 2095 /* Get cache line size. */ 2096 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2097 2098 /* 2099 * If the system has set enabled the PCI memory write 2100 * and invalidate command in the command register, set 2101 * the write max parameter accordingly. This is necessary 2102 * to use MWI with the Tigon 2. 2103 */ 2104 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2105 switch (cacheline) { 2106 case 1: 2107 case 4: 2108 case 8: 2109 case 16: 2110 case 32: 2111 case 64: 2112 break; 2113 default: 2114 /* Disable PCI memory write and invalidate. */ 2115 if (bootverbose) 2116 device_printf(sc->ti_dev, "cache line size %d" 2117 " not supported; disabling PCI MWI\n", 2118 cacheline); 2119 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2120 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2121 break; 2122 } 2123 } 2124 2125 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2126 2127 /* This sets the min dma param all the way up (0xff). */ 2128 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2129 2130 if (sc->ti_hdrsplit) 2131 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2132 else 2133 hdrsplit = 0; 2134 2135 /* Configure DMA variables. */ 2136#if BYTE_ORDER == BIG_ENDIAN 2137 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2138 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2139 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2140 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2141#else /* BYTE_ORDER */ 2142 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2143 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2144 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2145#endif /* BYTE_ORDER */ 2146 2147 /* 2148 * Only allow 1 DMA channel to be active at a time. 2149 * I don't think this is a good idea, but without it 2150 * the firmware racks up lots of nicDmaReadRingFull 2151 * errors. This is not compatible with hardware checksums. 2152 */ 2153 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2154 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2155 2156 /* Recommended settings from Tigon manual. */ 2157 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2158 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2159 2160 if (ti_64bitslot_war(sc)) { 2161 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2162 "but we aren't"); 2163 return (EINVAL); 2164 } 2165 2166 return (0); 2167} 2168 2169/* 2170 * Initialize the general information block and firmware, and 2171 * start the CPU(s) running. 2172 */ 2173static int 2174ti_gibinit(struct ti_softc *sc) 2175{ 2176 struct ifnet *ifp; 2177 struct ti_rcb *rcb; 2178 int i; 2179 2180 TI_LOCK_ASSERT(sc); 2181 2182 ifp = sc->ti_ifp; 2183 2184 /* Disable interrupts for now. */ 2185 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2186 2187 /* Tell the chip where to find the general information block. */ 2188 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2189 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2190 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2191 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2192 2193 /* Load the firmware into SRAM. */ 2194 ti_loadfw(sc); 2195 2196 /* Set up the contents of the general info and ring control blocks. */ 2197 2198 /* Set up the event ring and producer pointer. */ 2199 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2200 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2201 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2202 rcb->ti_flags = 0; 2203 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2204 sc->ti_rdata.ti_status_paddr + 2205 offsetof(struct ti_status, ti_ev_prodidx_r)); 2206 sc->ti_ev_prodidx.ti_idx = 0; 2207 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2208 sc->ti_ev_saved_considx = 0; 2209 2210 /* Set up the command ring and producer mailbox. */ 2211 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2212 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2213 rcb->ti_flags = 0; 2214 rcb->ti_max_len = 0; 2215 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2216 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2217 } 2218 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2219 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2220 sc->ti_cmd_saved_prodidx = 0; 2221 2222 /* 2223 * Assign the address of the stats refresh buffer. 2224 * We re-use the current stats buffer for this to 2225 * conserve memory. 2226 */ 2227 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2228 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2229 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2230 2231 /* Set up the standard receive ring. */ 2232 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2233 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2234 rcb->ti_max_len = TI_FRAMELEN; 2235 rcb->ti_flags = 0; 2236 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2237 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2238 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2239 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2240 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2241 2242 /* Set up the jumbo receive ring. */ 2243 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2244 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2245 2246#ifndef TI_SF_BUF_JUMBO 2247 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2248 rcb->ti_flags = 0; 2249#else 2250 rcb->ti_max_len = PAGE_SIZE; 2251 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2252#endif 2253 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2254 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2255 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2256 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2257 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2258 2259 /* 2260 * Set up the mini ring. Only activated on the 2261 * Tigon 2 but the slot in the config block is 2262 * still there on the Tigon 1. 2263 */ 2264 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2265 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2266 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2267 if (sc->ti_hwrev == TI_HWREV_TIGON) 2268 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2269 else 2270 rcb->ti_flags = 0; 2271 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2272 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2273 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2274 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2275 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2276 2277 /* 2278 * Set up the receive return ring. 2279 */ 2280 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2281 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2282 rcb->ti_flags = 0; 2283 rcb->ti_max_len = TI_RETURN_RING_CNT; 2284 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2285 sc->ti_rdata.ti_status_paddr + 2286 offsetof(struct ti_status, ti_return_prodidx_r)); 2287 2288 /* 2289 * Set up the tx ring. Note: for the Tigon 2, we have the option 2290 * of putting the transmit ring in the host's address space and 2291 * letting the chip DMA it instead of leaving the ring in the NIC's 2292 * memory and accessing it through the shared memory region. We 2293 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2294 * so we have to revert to the shared memory scheme if we detect 2295 * a Tigon 1 chip. 2296 */ 2297 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2298 if (sc->ti_rdata.ti_tx_ring != NULL) 2299 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2300 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2301 if (sc->ti_hwrev == TI_HWREV_TIGON) 2302 rcb->ti_flags = 0; 2303 else 2304 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2305 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2306 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2307 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2308 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2309 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2310 rcb->ti_max_len = TI_TX_RING_CNT; 2311 if (sc->ti_hwrev == TI_HWREV_TIGON) 2312 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2313 else 2314 ti_hostaddr64(&rcb->ti_hostaddr, 2315 sc->ti_rdata.ti_tx_ring_paddr); 2316 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2317 sc->ti_rdata.ti_status_paddr + 2318 offsetof(struct ti_status, ti_tx_considx_r)); 2319 2320 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2322 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2324 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2325 sc->ti_cdata.ti_event_ring_map, 2326 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2327 if (sc->ti_rdata.ti_tx_ring != NULL) 2328 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2329 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2330 2331 /* Set up tunables */ 2332#if 0 2333 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2334 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2335 (sc->ti_rx_coal_ticks / 10)); 2336 else 2337#endif 2338 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2339 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2340 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2341 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2342 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2343 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2344 2345 /* Turn interrupts on. */ 2346 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2347 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2348 2349 /* Start CPU. */ 2350 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2351 2352 return (0); 2353} 2354 2355/* 2356 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2357 * against our list and return its name if we find a match. 2358 */ 2359static int 2360ti_probe(device_t dev) 2361{ 2362 const struct ti_type *t; 2363 2364 t = ti_devs; 2365 2366 while (t->ti_name != NULL) { 2367 if ((pci_get_vendor(dev) == t->ti_vid) && 2368 (pci_get_device(dev) == t->ti_did)) { 2369 device_set_desc(dev, t->ti_name); 2370 return (BUS_PROBE_DEFAULT); 2371 } 2372 t++; 2373 } 2374 2375 return (ENXIO); 2376} 2377 2378static int 2379ti_attach(device_t dev) 2380{ 2381 struct ifnet *ifp; 2382 struct ti_softc *sc; 2383 int error = 0, rid; 2384 u_char eaddr[6]; 2385 2386 sc = device_get_softc(dev); 2387 sc->ti_dev = dev; 2388 2389 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2390 MTX_DEF); 2391 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2392 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2393 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2394 if (ifp == NULL) { 2395 device_printf(dev, "can not if_alloc()\n"); 2396 error = ENOSPC; 2397 goto fail; 2398 } 2399 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2400 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2401 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2402 2403 /* 2404 * Map control/status registers. 2405 */ 2406 pci_enable_busmaster(dev); 2407 2408 rid = PCIR_BAR(0); 2409 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2410 RF_ACTIVE); 2411 2412 if (sc->ti_res == NULL) { 2413 device_printf(dev, "couldn't map memory\n"); 2414 error = ENXIO; 2415 goto fail; 2416 } 2417 2418 sc->ti_btag = rman_get_bustag(sc->ti_res); 2419 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2420 2421 /* Allocate interrupt */ 2422 rid = 0; 2423 2424 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2425 RF_SHAREABLE | RF_ACTIVE); 2426 2427 if (sc->ti_irq == NULL) { 2428 device_printf(dev, "couldn't map interrupt\n"); 2429 error = ENXIO; 2430 goto fail; 2431 } 2432 2433 if (ti_chipinit(sc)) { 2434 device_printf(dev, "chip initialization failed\n"); 2435 error = ENXIO; 2436 goto fail; 2437 } 2438 2439 /* Zero out the NIC's on-board SRAM. */ 2440 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2441 2442 /* Init again -- zeroing memory may have clobbered some registers. */ 2443 if (ti_chipinit(sc)) { 2444 device_printf(dev, "chip initialization failed\n"); 2445 error = ENXIO; 2446 goto fail; 2447 } 2448 2449 /* 2450 * Get station address from the EEPROM. Note: the manual states 2451 * that the MAC address is at offset 0x8c, however the data is 2452 * stored as two longwords (since that's how it's loaded into 2453 * the NIC). This means the MAC address is actually preceded 2454 * by two zero bytes. We need to skip over those. 2455 */ 2456 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2457 device_printf(dev, "failed to read station address\n"); 2458 error = ENXIO; 2459 goto fail; 2460 } 2461 2462 /* Allocate working area for memory dump. */ 2463 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2464 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2465 M_NOWAIT); 2466 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2467 device_printf(dev, "cannot allocate memory buffer\n"); 2468 error = ENOMEM; 2469 goto fail; 2470 } 2471 if ((error = ti_dma_alloc(sc)) != 0) 2472 goto fail; 2473 2474 /* 2475 * We really need a better way to tell a 1000baseTX card 2476 * from a 1000baseSX one, since in theory there could be 2477 * OEMed 1000baseTX cards from lame vendors who aren't 2478 * clever enough to change the PCI ID. For the moment 2479 * though, the AceNIC is the only copper card available. 2480 */ 2481 if (pci_get_vendor(dev) == ALT_VENDORID && 2482 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2483 sc->ti_copper = 1; 2484 /* Ok, it's not the only copper card available. */ 2485 if (pci_get_vendor(dev) == NG_VENDORID && 2486 pci_get_device(dev) == NG_DEVICEID_GA620T) 2487 sc->ti_copper = 1; 2488 2489 /* Set default tunable values. */ 2490 ti_sysctl_node(sc); 2491 2492 /* Set up ifnet structure */ 2493 ifp->if_softc = sc; 2494 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2495 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2496 ifp->if_ioctl = ti_ioctl; 2497 ifp->if_start = ti_start; 2498 ifp->if_init = ti_init; 2499 ifp->if_baudrate = IF_Gbps(1UL); 2500 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2501 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2502 IFQ_SET_READY(&ifp->if_snd); 2503 2504 /* Set up ifmedia support. */ 2505 if (sc->ti_copper) { 2506 /* 2507 * Copper cards allow manual 10/100 mode selection, 2508 * but not manual 1000baseTX mode selection. Why? 2509 * Becuase currently there's no way to specify the 2510 * master/slave setting through the firmware interface, 2511 * so Alteon decided to just bag it and handle it 2512 * via autonegotiation. 2513 */ 2514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2515 ifmedia_add(&sc->ifmedia, 2516 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2518 ifmedia_add(&sc->ifmedia, 2519 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2521 ifmedia_add(&sc->ifmedia, 2522 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2523 } else { 2524 /* Fiber cards don't support 10/100 modes. */ 2525 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2526 ifmedia_add(&sc->ifmedia, 2527 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2528 } 2529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2530 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2531 2532 /* 2533 * We're assuming here that card initialization is a sequential 2534 * thing. If it isn't, multiple cards probing at the same time 2535 * could stomp on the list of softcs here. 2536 */ 2537 2538 /* Register the device */ 2539 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2540 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2541 sc->dev->si_drv1 = sc; 2542 2543 /* 2544 * Call MI attach routine. 2545 */ 2546 ether_ifattach(ifp, eaddr); 2547 2548 /* VLAN capability setup. */ 2549 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2550 IFCAP_VLAN_HWTAGGING; 2551 ifp->if_capenable = ifp->if_capabilities; 2552 /* Tell the upper layer we support VLAN over-sized frames. */ 2553 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2554 2555 /* Driver supports link state tracking. */ 2556 ifp->if_capabilities |= IFCAP_LINKSTATE; 2557 ifp->if_capenable |= IFCAP_LINKSTATE; 2558 2559 /* Hook interrupt last to avoid having to lock softc */ 2560 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2561 NULL, ti_intr, sc, &sc->ti_intrhand); 2562 2563 if (error) { 2564 device_printf(dev, "couldn't set up irq\n"); 2565 goto fail; 2566 } 2567 2568fail: 2569 if (error) 2570 ti_detach(dev); 2571 2572 return (error); 2573} 2574 2575/* 2576 * Shutdown hardware and free up resources. This can be called any 2577 * time after the mutex has been initialized. It is called in both 2578 * the error case in attach and the normal detach case so it needs 2579 * to be careful about only freeing resources that have actually been 2580 * allocated. 2581 */ 2582static int 2583ti_detach(device_t dev) 2584{ 2585 struct ti_softc *sc; 2586 struct ifnet *ifp; 2587 2588 sc = device_get_softc(dev); 2589 if (sc->dev) 2590 destroy_dev(sc->dev); 2591 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2592 ifp = sc->ti_ifp; 2593 if (device_is_attached(dev)) { 2594 ether_ifdetach(ifp); 2595 TI_LOCK(sc); 2596 ti_stop(sc); 2597 TI_UNLOCK(sc); 2598 } 2599 2600 /* These should only be active if attach succeeded */ 2601 callout_drain(&sc->ti_watchdog); 2602 bus_generic_detach(dev); 2603 ti_dma_free(sc); 2604 ifmedia_removeall(&sc->ifmedia); 2605 2606 if (sc->ti_intrhand) 2607 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2608 if (sc->ti_irq) 2609 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2610 if (sc->ti_res) { 2611 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2612 sc->ti_res); 2613 } 2614 if (ifp) 2615 if_free(ifp); 2616 if (sc->ti_membuf) 2617 free(sc->ti_membuf, M_DEVBUF); 2618 if (sc->ti_membuf2) 2619 free(sc->ti_membuf2, M_DEVBUF); 2620 2621 mtx_destroy(&sc->ti_mtx); 2622 2623 return (0); 2624} 2625 2626#ifdef TI_JUMBO_HDRSPLIT 2627/* 2628 * If hdr_len is 0, that means that header splitting wasn't done on 2629 * this packet for some reason. The two most likely reasons are that 2630 * the protocol isn't a supported protocol for splitting, or this 2631 * packet had a fragment offset that wasn't 0. 2632 * 2633 * The header length, if it is non-zero, will always be the length of 2634 * the headers on the packet, but that length could be longer than the 2635 * first mbuf. So we take the minimum of the two as the actual 2636 * length. 2637 */ 2638static __inline void 2639ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2640{ 2641 int i = 0; 2642 int lengths[4] = {0, 0, 0, 0}; 2643 struct mbuf *m, *mp; 2644 2645 if (hdr_len != 0) 2646 top->m_len = min(hdr_len, top->m_len); 2647 pkt_len -= top->m_len; 2648 lengths[i++] = top->m_len; 2649 2650 mp = top; 2651 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2652 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2653 pkt_len -= m->m_len; 2654 lengths[i++] = m->m_len; 2655 mp = m; 2656 } 2657 2658#if 0 2659 if (hdr_len != 0) 2660 printf("got split packet: "); 2661 else 2662 printf("got non-split packet: "); 2663 2664 printf("%d,%d,%d,%d = %d\n", lengths[0], 2665 lengths[1], lengths[2], lengths[3], 2666 lengths[0] + lengths[1] + lengths[2] + 2667 lengths[3]); 2668#endif 2669 2670 if (pkt_len) 2671 panic("header splitting didn't"); 2672 2673 if (m) { 2674 m_freem(m); 2675 mp->m_next = NULL; 2676 2677 } 2678 if (mp->m_next != NULL) 2679 panic("ti_hdr_split: last mbuf in chain should be null"); 2680} 2681#endif /* TI_JUMBO_HDRSPLIT */ 2682 2683static void 2684ti_discard_std(struct ti_softc *sc, int i) 2685{ 2686 2687 struct ti_rx_desc *r; 2688 2689 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2690 r->ti_len = MCLBYTES - ETHER_ALIGN; 2691 r->ti_type = TI_BDTYPE_RECV_BD; 2692 r->ti_flags = 0; 2693 r->ti_vlan_tag = 0; 2694 r->ti_tcp_udp_cksum = 0; 2695 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2696 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2697 r->ti_idx = i; 2698} 2699 2700static void 2701ti_discard_mini(struct ti_softc *sc, int i) 2702{ 2703 2704 struct ti_rx_desc *r; 2705 2706 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2707 r->ti_len = MHLEN - ETHER_ALIGN; 2708 r->ti_type = TI_BDTYPE_RECV_BD; 2709 r->ti_flags = TI_BDFLAG_MINI_RING; 2710 r->ti_vlan_tag = 0; 2711 r->ti_tcp_udp_cksum = 0; 2712 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2713 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2714 r->ti_idx = i; 2715} 2716 2717#ifndef TI_SF_BUF_JUMBO 2718static void 2719ti_discard_jumbo(struct ti_softc *sc, int i) 2720{ 2721 2722 struct ti_rx_desc *r; 2723 2724 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2725 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2726 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2727 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2728 r->ti_vlan_tag = 0; 2729 r->ti_tcp_udp_cksum = 0; 2730 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2731 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2732 r->ti_idx = i; 2733} 2734#endif 2735 2736/* 2737 * Frame reception handling. This is called if there's a frame 2738 * on the receive return list. 2739 * 2740 * Note: we have to be able to handle three possibilities here: 2741 * 1) the frame is from the mini receive ring (can only happen) 2742 * on Tigon 2 boards) 2743 * 2) the frame is from the jumbo recieve ring 2744 * 3) the frame is from the standard receive ring 2745 */ 2746 2747static void 2748ti_rxeof(struct ti_softc *sc) 2749{ 2750 struct ifnet *ifp; 2751#ifdef TI_SF_BUF_JUMBO 2752 bus_dmamap_t map; 2753#endif 2754 struct ti_cmd_desc cmd; 2755 int jumbocnt, minicnt, stdcnt, ti_len; 2756 2757 TI_LOCK_ASSERT(sc); 2758 2759 ifp = sc->ti_ifp; 2760 2761 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2762 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2763 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2764 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2765 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2766 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2767 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2768 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2769 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2770 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2771 2772 jumbocnt = minicnt = stdcnt = 0; 2773 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2774 struct ti_rx_desc *cur_rx; 2775 uint32_t rxidx; 2776 struct mbuf *m = NULL; 2777 uint16_t vlan_tag = 0; 2778 int have_tag = 0; 2779 2780 cur_rx = 2781 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2782 rxidx = cur_rx->ti_idx; 2783 ti_len = cur_rx->ti_len; 2784 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2785 2786 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2787 have_tag = 1; 2788 vlan_tag = cur_rx->ti_vlan_tag; 2789 } 2790 2791 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2792 jumbocnt++; 2793 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2794 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2795#ifndef TI_SF_BUF_JUMBO 2796 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2797 ifp->if_ierrors++; 2798 ti_discard_jumbo(sc, rxidx); 2799 continue; 2800 } 2801 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2802 ifp->if_iqdrops++; 2803 ti_discard_jumbo(sc, rxidx); 2804 continue; 2805 } 2806 m->m_len = ti_len; 2807#else /* !TI_SF_BUF_JUMBO */ 2808 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2809 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2810 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2811 BUS_DMASYNC_POSTREAD); 2812 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2813 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2814 ifp->if_ierrors++; 2815 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2816 continue; 2817 } 2818 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2819 ifp->if_iqdrops++; 2820 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2821 continue; 2822 } 2823#ifdef TI_JUMBO_HDRSPLIT 2824 if (sc->ti_hdrsplit) 2825 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2826 ti_len, rxidx); 2827 else 2828#endif /* TI_JUMBO_HDRSPLIT */ 2829 m_adj(m, ti_len - m->m_pkthdr.len); 2830#endif /* TI_SF_BUF_JUMBO */ 2831 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2832 minicnt++; 2833 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2834 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2835 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2836 ifp->if_ierrors++; 2837 ti_discard_mini(sc, rxidx); 2838 continue; 2839 } 2840 if (ti_newbuf_mini(sc, rxidx) != 0) { 2841 ifp->if_iqdrops++; 2842 ti_discard_mini(sc, rxidx); 2843 continue; 2844 } 2845 m->m_len = ti_len; 2846 } else { 2847 stdcnt++; 2848 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2849 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2850 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2851 ifp->if_ierrors++; 2852 ti_discard_std(sc, rxidx); 2853 continue; 2854 } 2855 if (ti_newbuf_std(sc, rxidx) != 0) { 2856 ifp->if_iqdrops++; 2857 ti_discard_std(sc, rxidx); 2858 continue; 2859 } 2860 m->m_len = ti_len; 2861 } 2862 2863 m->m_pkthdr.len = ti_len; 2864 ifp->if_ipackets++; 2865 m->m_pkthdr.rcvif = ifp; 2866 2867 if (ifp->if_capenable & IFCAP_RXCSUM) { 2868 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2869 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2870 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2871 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2872 } 2873 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2874 m->m_pkthdr.csum_data = 2875 cur_rx->ti_tcp_udp_cksum; 2876 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2877 } 2878 } 2879 2880 /* 2881 * If we received a packet with a vlan tag, 2882 * tag it before passing the packet upward. 2883 */ 2884 if (have_tag) { 2885 m->m_pkthdr.ether_vtag = vlan_tag; 2886 m->m_flags |= M_VLANTAG; 2887 } 2888 TI_UNLOCK(sc); 2889 (*ifp->if_input)(ifp, m); 2890 TI_LOCK(sc); 2891 } 2892 2893 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2894 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2895 /* Only necessary on the Tigon 1. */ 2896 if (sc->ti_hwrev == TI_HWREV_TIGON) 2897 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2898 sc->ti_rx_saved_considx); 2899 2900 if (stdcnt > 0) { 2901 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2902 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2903 TI_UPDATE_STDPROD(sc, sc->ti_std); 2904 } 2905 if (minicnt > 0) { 2906 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2907 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2908 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2909 } 2910 if (jumbocnt > 0) { 2911 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2912 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2913 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2914 } 2915} 2916 2917static void 2918ti_txeof(struct ti_softc *sc) 2919{ 2920 struct ti_txdesc *txd; 2921 struct ti_tx_desc txdesc; 2922 struct ti_tx_desc *cur_tx = NULL; 2923 struct ifnet *ifp; 2924 int idx; 2925 2926 ifp = sc->ti_ifp; 2927 2928 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2929 if (txd == NULL) 2930 return; 2931 2932 if (sc->ti_rdata.ti_tx_ring != NULL) 2933 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2934 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2935 /* 2936 * Go through our tx ring and free mbufs for those 2937 * frames that have been sent. 2938 */ 2939 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2940 TI_INC(idx, TI_TX_RING_CNT)) { 2941 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2942 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2943 sizeof(txdesc), &txdesc); 2944 cur_tx = &txdesc; 2945 } else 2946 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2947 sc->ti_txcnt--; 2948 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2949 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2950 continue; 2951 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2952 BUS_DMASYNC_POSTWRITE); 2953 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2954 2955 ifp->if_opackets++; 2956 m_freem(txd->tx_m); 2957 txd->tx_m = NULL; 2958 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2959 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2960 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2961 } 2962 sc->ti_tx_saved_considx = idx; 2963 if (sc->ti_txcnt == 0) 2964 sc->ti_timer = 0; 2965} 2966 2967static void 2968ti_intr(void *xsc) 2969{ 2970 struct ti_softc *sc; 2971 struct ifnet *ifp; 2972 2973 sc = xsc; 2974 TI_LOCK(sc); 2975 ifp = sc->ti_ifp; 2976 2977 /* Make sure this is really our interrupt. */ 2978 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2979 TI_UNLOCK(sc); 2980 return; 2981 } 2982 2983 /* Ack interrupt and stop others from occuring. */ 2984 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2985 2986 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2987 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2988 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2989 /* Check RX return ring producer/consumer */ 2990 ti_rxeof(sc); 2991 2992 /* Check TX ring producer/consumer */ 2993 ti_txeof(sc); 2994 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2995 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 2996 } 2997 2998 ti_handle_events(sc); 2999 3000 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3001 /* Re-enable interrupts. */ 3002 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3003 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3004 ti_start_locked(ifp); 3005 } 3006 3007 TI_UNLOCK(sc); 3008} 3009 3010static void 3011ti_stats_update(struct ti_softc *sc) 3012{ 3013 struct ifnet *ifp; 3014 struct ti_stats *s; 3015 3016 ifp = sc->ti_ifp; 3017 3018 if (sc->ti_stat_ticks == 0) 3019 return; 3020 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3021 BUS_DMASYNC_POSTREAD); 3022 3023 s = &sc->ti_rdata.ti_info->ti_stats; 3024 ifp->if_collisions += (s->dot3StatsSingleCollisionFrames + 3025 s->dot3StatsMultipleCollisionFrames + 3026 s->dot3StatsExcessiveCollisions + s->dot3StatsLateCollisions) - 3027 ifp->if_collisions; 3028 3029 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3030 BUS_DMASYNC_PREREAD); 3031} 3032 3033/* 3034 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3035 * pointers to descriptors. 3036 */ 3037static int 3038ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3039{ 3040 struct ti_txdesc *txd; 3041 struct ti_tx_desc *f; 3042 struct ti_tx_desc txdesc; 3043 struct mbuf *m; 3044 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3045 uint16_t csum_flags; 3046 int error, frag, i, nseg; 3047 3048 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3049 return (ENOBUFS); 3050 3051 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3052 *m_head, txsegs, &nseg, 0); 3053 if (error == EFBIG) { 3054 m = m_defrag(*m_head, M_DONTWAIT); 3055 if (m == NULL) { 3056 m_freem(*m_head); 3057 *m_head = NULL; 3058 return (ENOMEM); 3059 } 3060 *m_head = m; 3061 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3062 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3063 if (error) { 3064 m_freem(*m_head); 3065 *m_head = NULL; 3066 return (error); 3067 } 3068 } else if (error != 0) 3069 return (error); 3070 if (nseg == 0) { 3071 m_freem(*m_head); 3072 *m_head = NULL; 3073 return (EIO); 3074 } 3075 3076 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3077 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3078 return (ENOBUFS); 3079 } 3080 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3081 BUS_DMASYNC_PREWRITE); 3082 3083 m = *m_head; 3084 csum_flags = 0; 3085 if (m->m_pkthdr.csum_flags & CSUM_IP) 3086 csum_flags |= TI_BDFLAG_IP_CKSUM; 3087 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3088 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3089 3090 frag = sc->ti_tx_saved_prodidx; 3091 for (i = 0; i < nseg; i++) { 3092 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3093 bzero(&txdesc, sizeof(txdesc)); 3094 f = &txdesc; 3095 } else 3096 f = &sc->ti_rdata.ti_tx_ring[frag]; 3097 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3098 f->ti_len = txsegs[i].ds_len; 3099 f->ti_flags = csum_flags; 3100 if (m->m_flags & M_VLANTAG) { 3101 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3102 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3103 } else { 3104 f->ti_vlan_tag = 0; 3105 } 3106 3107 if (sc->ti_hwrev == TI_HWREV_TIGON) 3108 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3109 sizeof(txdesc), sizeof(txdesc), &txdesc); 3110 TI_INC(frag, TI_TX_RING_CNT); 3111 } 3112 3113 sc->ti_tx_saved_prodidx = frag; 3114 /* set TI_BDFLAG_END on the last descriptor */ 3115 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3116 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3117 txdesc.ti_flags |= TI_BDFLAG_END; 3118 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3119 sizeof(txdesc), &txdesc); 3120 } else 3121 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3122 3123 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3124 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3125 txd->tx_m = m; 3126 sc->ti_txcnt += nseg; 3127 3128 return (0); 3129} 3130 3131static void 3132ti_start(struct ifnet *ifp) 3133{ 3134 struct ti_softc *sc; 3135 3136 sc = ifp->if_softc; 3137 TI_LOCK(sc); 3138 ti_start_locked(ifp); 3139 TI_UNLOCK(sc); 3140} 3141 3142/* 3143 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3144 * to the mbuf data regions directly in the transmit descriptors. 3145 */ 3146static void 3147ti_start_locked(struct ifnet *ifp) 3148{ 3149 struct ti_softc *sc; 3150 struct mbuf *m_head = NULL; 3151 int enq = 0; 3152 3153 sc = ifp->if_softc; 3154 3155 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3156 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3157 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3158 if (m_head == NULL) 3159 break; 3160 3161 /* 3162 * XXX 3163 * safety overkill. If this is a fragmented packet chain 3164 * with delayed TCP/UDP checksums, then only encapsulate 3165 * it if we have enough descriptors to handle the entire 3166 * chain at once. 3167 * (paranoia -- may not actually be needed) 3168 */ 3169 if (m_head->m_flags & M_FIRSTFRAG && 3170 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3171 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3172 m_head->m_pkthdr.csum_data + 16) { 3173 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3174 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3175 break; 3176 } 3177 } 3178 3179 /* 3180 * Pack the data into the transmit ring. If we 3181 * don't have room, set the OACTIVE flag and wait 3182 * for the NIC to drain the ring. 3183 */ 3184 if (ti_encap(sc, &m_head)) { 3185 if (m_head == NULL) 3186 break; 3187 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3188 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3189 break; 3190 } 3191 3192 enq++; 3193 /* 3194 * If there's a BPF listener, bounce a copy of this frame 3195 * to him. 3196 */ 3197 ETHER_BPF_MTAP(ifp, m_head); 3198 } 3199 3200 if (enq > 0) { 3201 if (sc->ti_rdata.ti_tx_ring != NULL) 3202 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3203 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3204 /* Transmit */ 3205 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3206 3207 /* 3208 * Set a timeout in case the chip goes out to lunch. 3209 */ 3210 sc->ti_timer = 5; 3211 } 3212} 3213 3214static void 3215ti_init(void *xsc) 3216{ 3217 struct ti_softc *sc; 3218 3219 sc = xsc; 3220 TI_LOCK(sc); 3221 ti_init_locked(sc); 3222 TI_UNLOCK(sc); 3223} 3224 3225static void 3226ti_init_locked(void *xsc) 3227{ 3228 struct ti_softc *sc = xsc; 3229 3230 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3231 return; 3232 3233 /* Cancel pending I/O and flush buffers. */ 3234 ti_stop(sc); 3235 3236 /* Init the gen info block, ring control blocks and firmware. */ 3237 if (ti_gibinit(sc)) { 3238 device_printf(sc->ti_dev, "initialization failure\n"); 3239 return; 3240 } 3241} 3242 3243static void ti_init2(struct ti_softc *sc) 3244{ 3245 struct ti_cmd_desc cmd; 3246 struct ifnet *ifp; 3247 uint8_t *ea; 3248 struct ifmedia *ifm; 3249 int tmp; 3250 3251 TI_LOCK_ASSERT(sc); 3252 3253 ifp = sc->ti_ifp; 3254 3255 /* Specify MTU and interface index. */ 3256 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3257 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3258 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3259 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3260 3261 /* Load our MAC address. */ 3262 ea = IF_LLADDR(sc->ti_ifp); 3263 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3264 CSR_WRITE_4(sc, TI_GCR_PAR1, 3265 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3266 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3267 3268 /* Enable or disable promiscuous mode as needed. */ 3269 if (ifp->if_flags & IFF_PROMISC) { 3270 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3271 } else { 3272 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3273 } 3274 3275 /* Program multicast filter. */ 3276 ti_setmulti(sc); 3277 3278 /* 3279 * If this is a Tigon 1, we should tell the 3280 * firmware to use software packet filtering. 3281 */ 3282 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3283 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3284 } 3285 3286 /* Init RX ring. */ 3287 if (ti_init_rx_ring_std(sc) != 0) { 3288 /* XXX */ 3289 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3290 return; 3291 } 3292 3293 /* Init jumbo RX ring. */ 3294 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3295 if (ti_init_rx_ring_jumbo(sc) != 0) { 3296 /* XXX */ 3297 device_printf(sc->ti_dev, 3298 "no memory for jumbo Rx buffers.\n"); 3299 return; 3300 } 3301 } 3302 3303 /* 3304 * If this is a Tigon 2, we can also configure the 3305 * mini ring. 3306 */ 3307 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3308 if (ti_init_rx_ring_mini(sc) != 0) { 3309 /* XXX */ 3310 device_printf(sc->ti_dev, 3311 "no memory for mini Rx buffers.\n"); 3312 return; 3313 } 3314 } 3315 3316 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3317 sc->ti_rx_saved_considx = 0; 3318 3319 /* Init TX ring. */ 3320 ti_init_tx_ring(sc); 3321 3322 /* Tell firmware we're alive. */ 3323 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3324 3325 /* Enable host interrupts. */ 3326 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3327 3328 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3329 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3330 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3331 3332 /* 3333 * Make sure to set media properly. We have to do this 3334 * here since we have to issue commands in order to set 3335 * the link negotiation and we can't issue commands until 3336 * the firmware is running. 3337 */ 3338 ifm = &sc->ifmedia; 3339 tmp = ifm->ifm_media; 3340 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3341 ti_ifmedia_upd_locked(sc); 3342 ifm->ifm_media = tmp; 3343} 3344 3345/* 3346 * Set media options. 3347 */ 3348static int 3349ti_ifmedia_upd(struct ifnet *ifp) 3350{ 3351 struct ti_softc *sc; 3352 int error; 3353 3354 sc = ifp->if_softc; 3355 TI_LOCK(sc); 3356 error = ti_ifmedia_upd(ifp); 3357 TI_UNLOCK(sc); 3358 3359 return (error); 3360} 3361 3362static int 3363ti_ifmedia_upd_locked(struct ti_softc *sc) 3364{ 3365 struct ifmedia *ifm; 3366 struct ti_cmd_desc cmd; 3367 uint32_t flowctl; 3368 3369 ifm = &sc->ifmedia; 3370 3371 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3372 return (EINVAL); 3373 3374 flowctl = 0; 3375 3376 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3377 case IFM_AUTO: 3378 /* 3379 * Transmit flow control doesn't work on the Tigon 1. 3380 */ 3381 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3382 3383 /* 3384 * Transmit flow control can also cause problems on the 3385 * Tigon 2, apparantly with both the copper and fiber 3386 * boards. The symptom is that the interface will just 3387 * hang. This was reproduced with Alteon 180 switches. 3388 */ 3389#if 0 3390 if (sc->ti_hwrev != TI_HWREV_TIGON) 3391 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3392#endif 3393 3394 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3395 TI_GLNK_FULL_DUPLEX| flowctl | 3396 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3397 3398 flowctl = TI_LNK_RX_FLOWCTL_Y; 3399#if 0 3400 if (sc->ti_hwrev != TI_HWREV_TIGON) 3401 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3402#endif 3403 3404 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3405 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3406 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3407 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3408 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3409 break; 3410 case IFM_1000_SX: 3411 case IFM_1000_T: 3412 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3413#if 0 3414 if (sc->ti_hwrev != TI_HWREV_TIGON) 3415 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3416#endif 3417 3418 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3419 flowctl |TI_GLNK_ENB); 3420 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3421 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3422 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3423 } 3424 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3425 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3426 break; 3427 case IFM_100_FX: 3428 case IFM_10_FL: 3429 case IFM_100_TX: 3430 case IFM_10_T: 3431 flowctl = TI_LNK_RX_FLOWCTL_Y; 3432#if 0 3433 if (sc->ti_hwrev != TI_HWREV_TIGON) 3434 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3435#endif 3436 3437 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3438 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3439 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3440 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3441 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3442 } else { 3443 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3444 } 3445 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3446 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3447 } else { 3448 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3449 } 3450 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3451 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3452 break; 3453 } 3454 3455 return (0); 3456} 3457 3458/* 3459 * Report current media status. 3460 */ 3461static void 3462ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3463{ 3464 struct ti_softc *sc; 3465 uint32_t media = 0; 3466 3467 sc = ifp->if_softc; 3468 3469 TI_LOCK(sc); 3470 3471 ifmr->ifm_status = IFM_AVALID; 3472 ifmr->ifm_active = IFM_ETHER; 3473 3474 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3475 TI_UNLOCK(sc); 3476 return; 3477 } 3478 3479 ifmr->ifm_status |= IFM_ACTIVE; 3480 3481 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3482 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3483 if (sc->ti_copper) 3484 ifmr->ifm_active |= IFM_1000_T; 3485 else 3486 ifmr->ifm_active |= IFM_1000_SX; 3487 if (media & TI_GLNK_FULL_DUPLEX) 3488 ifmr->ifm_active |= IFM_FDX; 3489 else 3490 ifmr->ifm_active |= IFM_HDX; 3491 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3492 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3493 if (sc->ti_copper) { 3494 if (media & TI_LNK_100MB) 3495 ifmr->ifm_active |= IFM_100_TX; 3496 if (media & TI_LNK_10MB) 3497 ifmr->ifm_active |= IFM_10_T; 3498 } else { 3499 if (media & TI_LNK_100MB) 3500 ifmr->ifm_active |= IFM_100_FX; 3501 if (media & TI_LNK_10MB) 3502 ifmr->ifm_active |= IFM_10_FL; 3503 } 3504 if (media & TI_LNK_FULL_DUPLEX) 3505 ifmr->ifm_active |= IFM_FDX; 3506 if (media & TI_LNK_HALF_DUPLEX) 3507 ifmr->ifm_active |= IFM_HDX; 3508 } 3509 TI_UNLOCK(sc); 3510} 3511 3512static int 3513ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3514{ 3515 struct ti_softc *sc = ifp->if_softc; 3516 struct ifreq *ifr = (struct ifreq *) data; 3517 struct ti_cmd_desc cmd; 3518 int mask, error = 0; 3519 3520 switch (command) { 3521 case SIOCSIFMTU: 3522 TI_LOCK(sc); 3523 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3524 error = EINVAL; 3525 else { 3526 ifp->if_mtu = ifr->ifr_mtu; 3527 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3528 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3529 ti_init_locked(sc); 3530 } 3531 } 3532 TI_UNLOCK(sc); 3533 break; 3534 case SIOCSIFFLAGS: 3535 TI_LOCK(sc); 3536 if (ifp->if_flags & IFF_UP) { 3537 /* 3538 * If only the state of the PROMISC flag changed, 3539 * then just use the 'set promisc mode' command 3540 * instead of reinitializing the entire NIC. Doing 3541 * a full re-init means reloading the firmware and 3542 * waiting for it to start up, which may take a 3543 * second or two. 3544 */ 3545 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3546 ifp->if_flags & IFF_PROMISC && 3547 !(sc->ti_if_flags & IFF_PROMISC)) { 3548 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3549 TI_CMD_CODE_PROMISC_ENB, 0); 3550 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3551 !(ifp->if_flags & IFF_PROMISC) && 3552 sc->ti_if_flags & IFF_PROMISC) { 3553 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3554 TI_CMD_CODE_PROMISC_DIS, 0); 3555 } else 3556 ti_init_locked(sc); 3557 } else { 3558 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3559 ti_stop(sc); 3560 } 3561 } 3562 sc->ti_if_flags = ifp->if_flags; 3563 TI_UNLOCK(sc); 3564 break; 3565 case SIOCADDMULTI: 3566 case SIOCDELMULTI: 3567 TI_LOCK(sc); 3568 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3569 ti_setmulti(sc); 3570 TI_UNLOCK(sc); 3571 break; 3572 case SIOCSIFMEDIA: 3573 case SIOCGIFMEDIA: 3574 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3575 break; 3576 case SIOCSIFCAP: 3577 TI_LOCK(sc); 3578 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3579 if ((mask & IFCAP_TXCSUM) != 0 && 3580 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3581 ifp->if_capenable ^= IFCAP_TXCSUM; 3582 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3583 ifp->if_hwassist |= TI_CSUM_FEATURES; 3584 else 3585 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3586 } 3587 if ((mask & IFCAP_RXCSUM) != 0 && 3588 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3589 ifp->if_capenable ^= IFCAP_RXCSUM; 3590 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3591 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3592 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3593 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3594 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3595 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3596 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3597 IFCAP_VLAN_HWTAGGING)) != 0) { 3598 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3599 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3600 ti_init_locked(sc); 3601 } 3602 } 3603 TI_UNLOCK(sc); 3604 VLAN_CAPABILITIES(ifp); 3605 break; 3606 default: 3607 error = ether_ioctl(ifp, command, data); 3608 break; 3609 } 3610 3611 return (error); 3612} 3613 3614static int 3615ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3616{ 3617 struct ti_softc *sc; 3618 3619 sc = dev->si_drv1; 3620 if (sc == NULL) 3621 return (ENODEV); 3622 3623 TI_LOCK(sc); 3624 sc->ti_flags |= TI_FLAG_DEBUGING; 3625 TI_UNLOCK(sc); 3626 3627 return (0); 3628} 3629 3630static int 3631ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3632{ 3633 struct ti_softc *sc; 3634 3635 sc = dev->si_drv1; 3636 if (sc == NULL) 3637 return (ENODEV); 3638 3639 TI_LOCK(sc); 3640 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3641 TI_UNLOCK(sc); 3642 3643 return (0); 3644} 3645 3646/* 3647 * This ioctl routine goes along with the Tigon character device. 3648 */ 3649static int 3650ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3651 struct thread *td) 3652{ 3653 struct ti_softc *sc; 3654 int error; 3655 3656 sc = dev->si_drv1; 3657 if (sc == NULL) 3658 return (ENODEV); 3659 3660 error = 0; 3661 3662 switch (cmd) { 3663 case TIIOCGETSTATS: 3664 { 3665 struct ti_stats *outstats; 3666 3667 outstats = (struct ti_stats *)addr; 3668 3669 TI_LOCK(sc); 3670 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3671 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3672 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3673 sizeof(struct ti_stats)); 3674 TI_UNLOCK(sc); 3675 break; 3676 } 3677 case TIIOCGETPARAMS: 3678 { 3679 struct ti_params *params; 3680 3681 params = (struct ti_params *)addr; 3682 3683 TI_LOCK(sc); 3684 params->ti_stat_ticks = sc->ti_stat_ticks; 3685 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3686 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3687 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3688 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3689 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3690 params->param_mask = TI_PARAM_ALL; 3691 TI_UNLOCK(sc); 3692 break; 3693 } 3694 case TIIOCSETPARAMS: 3695 { 3696 struct ti_params *params; 3697 3698 params = (struct ti_params *)addr; 3699 3700 TI_LOCK(sc); 3701 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3702 sc->ti_stat_ticks = params->ti_stat_ticks; 3703 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3704 } 3705 3706 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3707 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3708 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3709 sc->ti_rx_coal_ticks); 3710 } 3711 3712 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3713 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3714 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3715 sc->ti_tx_coal_ticks); 3716 } 3717 3718 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3719 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3720 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3721 sc->ti_rx_max_coal_bds); 3722 } 3723 3724 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3725 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3726 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3727 sc->ti_tx_max_coal_bds); 3728 } 3729 3730 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3731 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3732 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3733 sc->ti_tx_buf_ratio); 3734 } 3735 TI_UNLOCK(sc); 3736 break; 3737 } 3738 case TIIOCSETTRACE: { 3739 ti_trace_type trace_type; 3740 3741 trace_type = *(ti_trace_type *)addr; 3742 3743 /* 3744 * Set tracing to whatever the user asked for. Setting 3745 * this register to 0 should have the effect of disabling 3746 * tracing. 3747 */ 3748 TI_LOCK(sc); 3749 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3750 TI_UNLOCK(sc); 3751 break; 3752 } 3753 case TIIOCGETTRACE: { 3754 struct ti_trace_buf *trace_buf; 3755 uint32_t trace_start, cur_trace_ptr, trace_len; 3756 3757 trace_buf = (struct ti_trace_buf *)addr; 3758 3759 TI_LOCK(sc); 3760 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3761 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3762 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3763#if 0 3764 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3765 "trace_len = %d\n", trace_start, 3766 cur_trace_ptr, trace_len); 3767 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3768 trace_buf->buf_len); 3769#endif 3770 error = ti_copy_mem(sc, trace_start, min(trace_len, 3771 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3772 if (error == 0) { 3773 trace_buf->fill_len = min(trace_len, 3774 trace_buf->buf_len); 3775 if (cur_trace_ptr < trace_start) 3776 trace_buf->cur_trace_ptr = 3777 trace_start - cur_trace_ptr; 3778 else 3779 trace_buf->cur_trace_ptr = 3780 cur_trace_ptr - trace_start; 3781 } else 3782 trace_buf->fill_len = 0; 3783 TI_UNLOCK(sc); 3784 break; 3785 } 3786 3787 /* 3788 * For debugging, five ioctls are needed: 3789 * ALT_ATTACH 3790 * ALT_READ_TG_REG 3791 * ALT_WRITE_TG_REG 3792 * ALT_READ_TG_MEM 3793 * ALT_WRITE_TG_MEM 3794 */ 3795 case ALT_ATTACH: 3796 /* 3797 * From what I can tell, Alteon's Solaris Tigon driver 3798 * only has one character device, so you have to attach 3799 * to the Tigon board you're interested in. This seems 3800 * like a not-so-good way to do things, since unless you 3801 * subsequently specify the unit number of the device 3802 * you're interested in every ioctl, you'll only be 3803 * able to debug one board at a time. 3804 */ 3805 break; 3806 case ALT_READ_TG_MEM: 3807 case ALT_WRITE_TG_MEM: 3808 { 3809 struct tg_mem *mem_param; 3810 uint32_t sram_end, scratch_end; 3811 3812 mem_param = (struct tg_mem *)addr; 3813 3814 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3815 sram_end = TI_END_SRAM_I; 3816 scratch_end = TI_END_SCRATCH_I; 3817 } else { 3818 sram_end = TI_END_SRAM_II; 3819 scratch_end = TI_END_SCRATCH_II; 3820 } 3821 3822 /* 3823 * For now, we'll only handle accessing regular SRAM, 3824 * nothing else. 3825 */ 3826 TI_LOCK(sc); 3827 if (mem_param->tgAddr >= TI_BEG_SRAM && 3828 mem_param->tgAddr + mem_param->len <= sram_end) { 3829 /* 3830 * In this instance, we always copy to/from user 3831 * space, so the user space argument is set to 1. 3832 */ 3833 error = ti_copy_mem(sc, mem_param->tgAddr, 3834 mem_param->len, mem_param->userAddr, 1, 3835 cmd == ALT_READ_TG_MEM ? 1 : 0); 3836 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3837 mem_param->tgAddr <= scratch_end) { 3838 error = ti_copy_scratch(sc, mem_param->tgAddr, 3839 mem_param->len, mem_param->userAddr, 1, 3840 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3841 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3842 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3843 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3844 if_printf(sc->ti_ifp, 3845 "invalid memory range for Tigon I\n"); 3846 error = EINVAL; 3847 break; 3848 } 3849 error = ti_copy_scratch(sc, mem_param->tgAddr - 3850 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3851 mem_param->userAddr, 1, 3852 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3853 } else { 3854 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3855 "out of supported range\n", 3856 mem_param->tgAddr, mem_param->len); 3857 error = EINVAL; 3858 } 3859 TI_UNLOCK(sc); 3860 break; 3861 } 3862 case ALT_READ_TG_REG: 3863 case ALT_WRITE_TG_REG: 3864 { 3865 struct tg_reg *regs; 3866 uint32_t tmpval; 3867 3868 regs = (struct tg_reg *)addr; 3869 3870 /* 3871 * Make sure the address in question isn't out of range. 3872 */ 3873 if (regs->addr > TI_REG_MAX) { 3874 error = EINVAL; 3875 break; 3876 } 3877 TI_LOCK(sc); 3878 if (cmd == ALT_READ_TG_REG) { 3879 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3880 regs->addr, &tmpval, 1); 3881 regs->data = ntohl(tmpval); 3882#if 0 3883 if ((regs->addr == TI_CPU_STATE) 3884 || (regs->addr == TI_CPU_CTL_B)) { 3885 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3886 regs->addr, tmpval); 3887 } 3888#endif 3889 } else { 3890 tmpval = htonl(regs->data); 3891 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3892 regs->addr, &tmpval, 1); 3893 } 3894 TI_UNLOCK(sc); 3895 break; 3896 } 3897 default: 3898 error = ENOTTY; 3899 break; 3900 } 3901 return (error); 3902} 3903 3904static void 3905ti_watchdog(void *arg) 3906{ 3907 struct ti_softc *sc; 3908 struct ifnet *ifp; 3909 3910 sc = arg; 3911 TI_LOCK_ASSERT(sc); 3912 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3913 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3914 return; 3915 3916 /* 3917 * When we're debugging, the chip is often stopped for long periods 3918 * of time, and that would normally cause the watchdog timer to fire. 3919 * Since that impedes debugging, we don't want to do that. 3920 */ 3921 if (sc->ti_flags & TI_FLAG_DEBUGING) 3922 return; 3923 3924 ifp = sc->ti_ifp; 3925 if_printf(ifp, "watchdog timeout -- resetting\n"); 3926 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3927 ti_init_locked(sc); 3928 3929 ifp->if_oerrors++; 3930} 3931 3932/* 3933 * Stop the adapter and free any mbufs allocated to the 3934 * RX and TX lists. 3935 */ 3936static void 3937ti_stop(struct ti_softc *sc) 3938{ 3939 struct ifnet *ifp; 3940 struct ti_cmd_desc cmd; 3941 3942 TI_LOCK_ASSERT(sc); 3943 3944 ifp = sc->ti_ifp; 3945 3946 /* Disable host interrupts. */ 3947 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3948 /* 3949 * Tell firmware we're shutting down. 3950 */ 3951 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3952 3953 /* Halt and reinitialize. */ 3954 if (ti_chipinit(sc) == 0) { 3955 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3956 /* XXX ignore init errors. */ 3957 ti_chipinit(sc); 3958 } 3959 3960 /* Free the RX lists. */ 3961 ti_free_rx_ring_std(sc); 3962 3963 /* Free jumbo RX list. */ 3964 ti_free_rx_ring_jumbo(sc); 3965 3966 /* Free mini RX list. */ 3967 ti_free_rx_ring_mini(sc); 3968 3969 /* Free TX buffers. */ 3970 ti_free_tx_ring(sc); 3971 3972 sc->ti_ev_prodidx.ti_idx = 0; 3973 sc->ti_return_prodidx.ti_idx = 0; 3974 sc->ti_tx_considx.ti_idx = 0; 3975 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3976 3977 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3978 callout_stop(&sc->ti_watchdog); 3979} 3980 3981/* 3982 * Stop all chip I/O so that the kernel's probe routines don't 3983 * get confused by errant DMAs when rebooting. 3984 */ 3985static int 3986ti_shutdown(device_t dev) 3987{ 3988 struct ti_softc *sc; 3989 3990 sc = device_get_softc(dev); 3991 TI_LOCK(sc); 3992 ti_chipinit(sc); 3993 TI_UNLOCK(sc); 3994 3995 return (0); 3996} 3997 3998static void 3999ti_sysctl_node(struct ti_softc *sc) 4000{ 4001 struct sysctl_ctx_list *ctx; 4002 struct sysctl_oid_list *child; 4003 char tname[32]; 4004 4005 ctx = device_get_sysctl_ctx(sc->ti_dev); 4006 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 4007 4008 /* Use DAC */ 4009 sc->ti_dac = 1; 4010 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 4011 device_get_unit(sc->ti_dev)); 4012 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 4013 4014 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 4015 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 4016 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4017 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4018 4019 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4020 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4021 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4022 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4023 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4024 &sc->ti_tx_buf_ratio, 0, 4025 "Ratio of NIC memory devoted to TX buffer"); 4026 4027 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4028 &sc->ti_stat_ticks, 0, 4029 "Number of clock ticks for statistics update interval"); 4030 4031 /* Pull in device tunables. */ 4032 sc->ti_rx_coal_ticks = 170; 4033 resource_int_value(device_get_name(sc->ti_dev), 4034 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4035 &sc->ti_rx_coal_ticks); 4036 sc->ti_rx_max_coal_bds = 64; 4037 resource_int_value(device_get_name(sc->ti_dev), 4038 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4039 &sc->ti_rx_max_coal_bds); 4040 4041 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4042 resource_int_value(device_get_name(sc->ti_dev), 4043 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4044 &sc->ti_tx_coal_ticks); 4045 sc->ti_tx_max_coal_bds = 32; 4046 resource_int_value(device_get_name(sc->ti_dev), 4047 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4048 &sc->ti_tx_max_coal_bds); 4049 sc->ti_tx_buf_ratio = 21; 4050 resource_int_value(device_get_name(sc->ti_dev), 4051 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4052 &sc->ti_tx_buf_ratio); 4053 4054 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4055 resource_int_value(device_get_name(sc->ti_dev), 4056 device_get_unit(sc->ti_dev), "stat_ticks", 4057 &sc->ti_stat_ticks); 4058} 4059