if_ti.c revision 227509
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 227509 2011-11-14 19:10:20Z yongari $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#ifdef TI_SF_BUF_JUMBO 116#include <vm/vm.h> 117#include <vm/vm_page.h> 118#endif 119 120#include <dev/pci/pcireg.h> 121#include <dev/pci/pcivar.h> 122 123#include <sys/tiio.h> 124#include <dev/ti/if_tireg.h> 125#include <dev/ti/ti_fw.h> 126#include <dev/ti/ti_fw2.h> 127 128#include <sys/sysctl.h> 129 130#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 131/* 132 * We can only turn on header splitting if we're using extended receive 133 * BDs. 134 */ 135#if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 136#error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 137#endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 138 139typedef enum { 140 TI_SWAP_HTON, 141 TI_SWAP_NTOH 142} ti_swap_type; 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static const struct ti_type const ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf **); 188 189static void ti_intr(void *); 190static void ti_start(struct ifnet *); 191static void ti_start_locked(struct ifnet *); 192static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193static void ti_init(void *); 194static void ti_init_locked(void *); 195static void ti_init2(struct ti_softc *); 196static void ti_stop(struct ti_softc *); 197static void ti_watchdog(void *); 198static int ti_shutdown(device_t); 199static int ti_ifmedia_upd(struct ifnet *); 200static int ti_ifmedia_upd_locked(struct ti_softc *); 201static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 202 203static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 204static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 205static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 206 207static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 208static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 209static void ti_setmulti(struct ti_softc *); 210 211static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 212static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 213static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 214static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 215 int); 216static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 217 int, int, int); 218static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219static void ti_loadfw(struct ti_softc *); 220static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222static void ti_handle_events(struct ti_softc *); 223static int ti_alloc_dmamaps(struct ti_softc *); 224static void ti_free_dmamaps(struct ti_softc *); 225static int ti_alloc_jumbo_mem(struct ti_softc *); 226static int ti_newbuf_std(struct ti_softc *, int); 227static int ti_newbuf_mini(struct ti_softc *, int); 228static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 229static int ti_init_rx_ring_std(struct ti_softc *); 230static void ti_free_rx_ring_std(struct ti_softc *); 231static int ti_init_rx_ring_jumbo(struct ti_softc *); 232static void ti_free_rx_ring_jumbo(struct ti_softc *); 233static int ti_init_rx_ring_mini(struct ti_softc *); 234static void ti_free_rx_ring_mini(struct ti_softc *); 235static void ti_free_tx_ring(struct ti_softc *); 236static int ti_init_tx_ring(struct ti_softc *); 237static void ti_discard_std(struct ti_softc *, int); 238#ifndef TI_SF_BUF_JUMBO 239static void ti_discard_jumbo(struct ti_softc *, int); 240#endif 241static void ti_discard_mini(struct ti_softc *, int); 242 243static int ti_64bitslot_war(struct ti_softc *); 244static int ti_chipinit(struct ti_softc *); 245static int ti_gibinit(struct ti_softc *); 246 247#ifdef TI_JUMBO_HDRSPLIT 248static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 249 int idx); 250#endif /* TI_JUMBO_HDRSPLIT */ 251 252static void ti_sysctl_node(struct ti_softc *); 253 254static device_method_t ti_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, ti_probe), 257 DEVMETHOD(device_attach, ti_attach), 258 DEVMETHOD(device_detach, ti_detach), 259 DEVMETHOD(device_shutdown, ti_shutdown), 260 { 0, 0 } 261}; 262 263static driver_t ti_driver = { 264 "ti", 265 ti_methods, 266 sizeof(struct ti_softc) 267}; 268 269static devclass_t ti_devclass; 270 271DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 272MODULE_DEPEND(ti, pci, 1, 1, 1); 273MODULE_DEPEND(ti, ether, 1, 1, 1); 274 275/* 276 * Send an instruction or address to the EEPROM, check for ACK. 277 */ 278static uint32_t 279ti_eeprom_putbyte(struct ti_softc *sc, int byte) 280{ 281 int i, ack = 0; 282 283 /* 284 * Make sure we're in TX mode. 285 */ 286 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 287 288 /* 289 * Feed in each bit and stobe the clock. 290 */ 291 for (i = 0x80; i; i >>= 1) { 292 if (byte & i) { 293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 294 } else { 295 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 296 } 297 DELAY(1); 298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 299 DELAY(1); 300 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 301 } 302 303 /* 304 * Turn off TX mode. 305 */ 306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 307 308 /* 309 * Check for ack. 310 */ 311 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 312 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 314 315 return (ack); 316} 317 318/* 319 * Read a byte of data stored in the EEPROM at address 'addr.' 320 * We have to send two address bytes since the EEPROM can hold 321 * more than 256 bytes of data. 322 */ 323static uint8_t 324ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 325{ 326 int i; 327 uint8_t byte = 0; 328 329 EEPROM_START; 330 331 /* 332 * Send write control code to EEPROM. 333 */ 334 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 335 device_printf(sc->ti_dev, 336 "failed to send write command, status: %x\n", 337 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 338 return (1); 339 } 340 341 /* 342 * Send first byte of address of byte we want to read. 343 */ 344 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 345 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 346 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 347 return (1); 348 } 349 /* 350 * Send second byte address of byte we want to read. 351 */ 352 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 353 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 354 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 355 return (1); 356 } 357 358 EEPROM_STOP; 359 EEPROM_START; 360 /* 361 * Send read control code to EEPROM. 362 */ 363 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 364 device_printf(sc->ti_dev, 365 "failed to send read command, status: %x\n", 366 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 367 return (1); 368 } 369 370 /* 371 * Start reading bits from EEPROM. 372 */ 373 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 374 for (i = 0x80; i; i >>= 1) { 375 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 376 DELAY(1); 377 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 378 byte |= i; 379 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 380 DELAY(1); 381 } 382 383 EEPROM_STOP; 384 385 /* 386 * No ACK generated for read, so just return byte. 387 */ 388 389 *dest = byte; 390 391 return (0); 392} 393 394/* 395 * Read a sequence of bytes from the EEPROM. 396 */ 397static int 398ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 399{ 400 int err = 0, i; 401 uint8_t byte = 0; 402 403 for (i = 0; i < cnt; i++) { 404 err = ti_eeprom_getbyte(sc, off + i, &byte); 405 if (err) 406 break; 407 *(dest + i) = byte; 408 } 409 410 return (err ? 1 : 0); 411} 412 413/* 414 * NIC memory read function. 415 * Can be used to copy data from NIC local memory. 416 */ 417static void 418ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 419{ 420 int segptr, segsize, cnt; 421 char *ptr; 422 423 segptr = addr; 424 cnt = len; 425 ptr = buf; 426 427 while (cnt) { 428 if (cnt < TI_WINLEN) 429 segsize = cnt; 430 else 431 segsize = TI_WINLEN - (segptr % TI_WINLEN); 432 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 433 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 434 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 435 segsize / 4); 436 ptr += segsize; 437 segptr += segsize; 438 cnt -= segsize; 439 } 440} 441 442 443/* 444 * NIC memory write function. 445 * Can be used to copy data into NIC local memory. 446 */ 447static void 448ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 449{ 450 int segptr, segsize, cnt; 451 char *ptr; 452 453 segptr = addr; 454 cnt = len; 455 ptr = buf; 456 457 while (cnt) { 458 if (cnt < TI_WINLEN) 459 segsize = cnt; 460 else 461 segsize = TI_WINLEN - (segptr % TI_WINLEN); 462 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 463 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 464 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 465 segsize / 4); 466 ptr += segsize; 467 segptr += segsize; 468 cnt -= segsize; 469 } 470} 471 472/* 473 * NIC memory read function. 474 * Can be used to clear a section of NIC local memory. 475 */ 476static void 477ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 478{ 479 int segptr, segsize, cnt; 480 481 segptr = addr; 482 cnt = len; 483 484 while (cnt) { 485 if (cnt < TI_WINLEN) 486 segsize = cnt; 487 else 488 segsize = TI_WINLEN - (segptr % TI_WINLEN); 489 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 490 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 491 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 492 segptr += segsize; 493 cnt -= segsize; 494 } 495} 496 497static int 498ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 499 caddr_t buf, int useraddr, int readdata) 500{ 501 int segptr, segsize, cnt; 502 caddr_t ptr; 503 uint32_t origwin; 504 int resid, segresid; 505 int first_pass; 506 507 TI_LOCK_ASSERT(sc); 508 509 /* 510 * At the moment, we don't handle non-aligned cases, we just bail. 511 * If this proves to be a problem, it will be fixed. 512 */ 513 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 514 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 515 "word-aligned\n", __func__, tigon_addr); 516 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 517 "yet supported\n", __func__); 518 return (EINVAL); 519 } 520 521 segptr = tigon_addr & ~0x3; 522 segresid = tigon_addr - segptr; 523 524 /* 525 * This is the non-aligned amount left over that we'll need to 526 * copy. 527 */ 528 resid = len & 0x3; 529 530 /* Add in the left over amount at the front of the buffer */ 531 resid += segresid; 532 533 cnt = len & ~0x3; 534 /* 535 * If resid + segresid is >= 4, add multiples of 4 to the count and 536 * decrease the residual by that much. 537 */ 538 cnt += resid & ~0x3; 539 resid -= resid & ~0x3; 540 541 ptr = buf; 542 543 first_pass = 1; 544 545 /* 546 * Save the old window base value. 547 */ 548 origwin = CSR_READ_4(sc, TI_WINBASE); 549 550 while (cnt) { 551 bus_size_t ti_offset; 552 553 if (cnt < TI_WINLEN) 554 segsize = cnt; 555 else 556 segsize = TI_WINLEN - (segptr % TI_WINLEN); 557 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 558 559 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 560 561 if (readdata) { 562 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 563 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 564 if (useraddr) { 565 /* 566 * Yeah, this is a little on the kludgy 567 * side, but at least this code is only 568 * used for debugging. 569 */ 570 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 571 segsize, TI_SWAP_NTOH); 572 573 TI_UNLOCK(sc); 574 if (first_pass) { 575 copyout(&sc->ti_membuf2[segresid], ptr, 576 segsize - segresid); 577 first_pass = 0; 578 } else 579 copyout(sc->ti_membuf2, ptr, segsize); 580 TI_LOCK(sc); 581 } else { 582 if (first_pass) { 583 584 ti_bcopy_swap(sc->ti_membuf, 585 sc->ti_membuf2, segsize, 586 TI_SWAP_NTOH); 587 TI_UNLOCK(sc); 588 bcopy(&sc->ti_membuf2[segresid], ptr, 589 segsize - segresid); 590 TI_LOCK(sc); 591 first_pass = 0; 592 } else 593 ti_bcopy_swap(sc->ti_membuf, ptr, 594 segsize, TI_SWAP_NTOH); 595 } 596 597 } else { 598 if (useraddr) { 599 TI_UNLOCK(sc); 600 copyin(ptr, sc->ti_membuf2, segsize); 601 TI_LOCK(sc); 602 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 603 segsize, TI_SWAP_HTON); 604 } else 605 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 606 TI_SWAP_HTON); 607 608 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 609 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 610 } 611 segptr += segsize; 612 ptr += segsize; 613 cnt -= segsize; 614 } 615 616 /* 617 * Handle leftover, non-word-aligned bytes. 618 */ 619 if (resid != 0) { 620 uint32_t tmpval, tmpval2; 621 bus_size_t ti_offset; 622 623 /* 624 * Set the segment pointer. 625 */ 626 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 627 628 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 629 630 /* 631 * First, grab whatever is in our source/destination. 632 * We'll obviously need this for reads, but also for 633 * writes, since we'll be doing read/modify/write. 634 */ 635 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 636 ti_offset, &tmpval, 1); 637 638 /* 639 * Next, translate this from little-endian to big-endian 640 * (at least on i386 boxes). 641 */ 642 tmpval2 = ntohl(tmpval); 643 644 if (readdata) { 645 /* 646 * If we're reading, just copy the leftover number 647 * of bytes from the host byte order buffer to 648 * the user's buffer. 649 */ 650 if (useraddr) { 651 TI_UNLOCK(sc); 652 copyout(&tmpval2, ptr, resid); 653 TI_LOCK(sc); 654 } else 655 bcopy(&tmpval2, ptr, resid); 656 } else { 657 /* 658 * If we're writing, first copy the bytes to be 659 * written into the network byte order buffer, 660 * leaving the rest of the buffer with whatever was 661 * originally in there. Then, swap the bytes 662 * around into host order and write them out. 663 * 664 * XXX KDM the read side of this has been verified 665 * to work, but the write side of it has not been 666 * verified. So user beware. 667 */ 668 if (useraddr) { 669 TI_UNLOCK(sc); 670 copyin(ptr, &tmpval2, resid); 671 TI_LOCK(sc); 672 } else 673 bcopy(ptr, &tmpval2, resid); 674 675 tmpval = htonl(tmpval2); 676 677 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 678 ti_offset, &tmpval, 1); 679 } 680 } 681 682 CSR_WRITE_4(sc, TI_WINBASE, origwin); 683 684 return (0); 685} 686 687static int 688ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 689 caddr_t buf, int useraddr, int readdata, int cpu) 690{ 691 uint32_t segptr; 692 int cnt; 693 uint32_t tmpval, tmpval2; 694 caddr_t ptr; 695 696 TI_LOCK_ASSERT(sc); 697 698 /* 699 * At the moment, we don't handle non-aligned cases, we just bail. 700 * If this proves to be a problem, it will be fixed. 701 */ 702 if (tigon_addr & 0x3) { 703 device_printf(sc->ti_dev, "%s: tigon address %#x " 704 "isn't word-aligned\n", __func__, tigon_addr); 705 return (EINVAL); 706 } 707 708 if (len & 0x3) { 709 device_printf(sc->ti_dev, "%s: transfer length %d " 710 "isn't word-aligned\n", __func__, len); 711 return (EINVAL); 712 } 713 714 segptr = tigon_addr; 715 cnt = len; 716 ptr = buf; 717 718 while (cnt) { 719 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 720 721 if (readdata) { 722 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 723 724 tmpval = ntohl(tmpval2); 725 726 /* 727 * Note: I've used this debugging interface 728 * extensively with Alteon's 12.3.15 firmware, 729 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 730 * 731 * When you compile the firmware without 732 * optimization, which is necessary sometimes in 733 * order to properly step through it, you sometimes 734 * read out a bogus value of 0xc0017c instead of 735 * whatever was supposed to be in that scratchpad 736 * location. That value is on the stack somewhere, 737 * but I've never been able to figure out what was 738 * causing the problem. 739 * 740 * The address seems to pop up in random places, 741 * often not in the same place on two subsequent 742 * reads. 743 * 744 * In any case, the underlying data doesn't seem 745 * to be affected, just the value read out. 746 * 747 * KDM, 3/7/2000 748 */ 749 750 if (tmpval2 == 0xc0017c) 751 device_printf(sc->ti_dev, "found 0xc0017c at " 752 "%#x (tmpval2)\n", segptr); 753 754 if (tmpval == 0xc0017c) 755 device_printf(sc->ti_dev, "found 0xc0017c at " 756 "%#x (tmpval)\n", segptr); 757 758 if (useraddr) 759 copyout(&tmpval, ptr, 4); 760 else 761 bcopy(&tmpval, ptr, 4); 762 } else { 763 if (useraddr) 764 copyin(ptr, &tmpval2, 4); 765 else 766 bcopy(ptr, &tmpval2, 4); 767 768 tmpval = htonl(tmpval2); 769 770 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 771 } 772 773 cnt -= 4; 774 segptr += 4; 775 ptr += 4; 776 } 777 778 return (0); 779} 780 781static int 782ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 783{ 784 const uint8_t *tmpsrc; 785 uint8_t *tmpdst; 786 size_t tmplen; 787 788 if (len & 0x3) { 789 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 790 return (-1); 791 } 792 793 tmpsrc = src; 794 tmpdst = dst; 795 tmplen = len; 796 797 while (tmplen) { 798 if (swap_type == TI_SWAP_NTOH) 799 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 800 else 801 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 802 tmpsrc += 4; 803 tmpdst += 4; 804 tmplen -= 4; 805 } 806 807 return (0); 808} 809 810/* 811 * Load firmware image into the NIC. Check that the firmware revision 812 * is acceptable and see if we want the firmware for the Tigon 1 or 813 * Tigon 2. 814 */ 815static void 816ti_loadfw(struct ti_softc *sc) 817{ 818 819 TI_LOCK_ASSERT(sc); 820 821 switch (sc->ti_hwrev) { 822 case TI_HWREV_TIGON: 823 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 824 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 825 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 826 device_printf(sc->ti_dev, "firmware revision mismatch; " 827 "want %d.%d.%d, got %d.%d.%d\n", 828 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 829 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 830 tigonFwReleaseMinor, tigonFwReleaseFix); 831 return; 832 } 833 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 834 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 835 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 836 tigonFwRodata); 837 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 838 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 839 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 840 break; 841 case TI_HWREV_TIGON_II: 842 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 843 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 844 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 845 device_printf(sc->ti_dev, "firmware revision mismatch; " 846 "want %d.%d.%d, got %d.%d.%d\n", 847 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 848 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 849 tigon2FwReleaseMinor, tigon2FwReleaseFix); 850 return; 851 } 852 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 853 tigon2FwText); 854 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 855 tigon2FwData); 856 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 857 tigon2FwRodata); 858 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 859 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 860 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 861 break; 862 default: 863 device_printf(sc->ti_dev, 864 "can't load firmware: unknown hardware rev\n"); 865 break; 866 } 867} 868 869/* 870 * Send the NIC a command via the command ring. 871 */ 872static void 873ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 874{ 875 int index; 876 877 index = sc->ti_cmd_saved_prodidx; 878 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 879 TI_INC(index, TI_CMD_RING_CNT); 880 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 881 sc->ti_cmd_saved_prodidx = index; 882} 883 884/* 885 * Send the NIC an extended command. The 'len' parameter specifies the 886 * number of command slots to include after the initial command. 887 */ 888static void 889ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 890{ 891 int index; 892 int i; 893 894 index = sc->ti_cmd_saved_prodidx; 895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 896 TI_INC(index, TI_CMD_RING_CNT); 897 for (i = 0; i < len; i++) { 898 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 899 *(uint32_t *)(&arg[i * 4])); 900 TI_INC(index, TI_CMD_RING_CNT); 901 } 902 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 903 sc->ti_cmd_saved_prodidx = index; 904} 905 906/* 907 * Handle events that have triggered interrupts. 908 */ 909static void 910ti_handle_events(struct ti_softc *sc) 911{ 912 struct ti_event_desc *e; 913 914 if (sc->ti_rdata->ti_event_ring == NULL) 915 return; 916 917 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 918 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 919 switch (TI_EVENT_EVENT(e)) { 920 case TI_EV_LINKSTAT_CHANGED: 921 sc->ti_linkstat = TI_EVENT_CODE(e); 922 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 923 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 924 sc->ti_ifp->if_baudrate = IF_Mbps(100); 925 if (bootverbose) 926 device_printf(sc->ti_dev, 927 "10/100 link up\n"); 928 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 930 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 931 if (bootverbose) 932 device_printf(sc->ti_dev, 933 "gigabit link up\n"); 934 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 935 if_link_state_change(sc->ti_ifp, 936 LINK_STATE_DOWN); 937 sc->ti_ifp->if_baudrate = 0; 938 if (bootverbose) 939 device_printf(sc->ti_dev, 940 "link down\n"); 941 } 942 break; 943 case TI_EV_ERROR: 944 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 945 device_printf(sc->ti_dev, "invalid command\n"); 946 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 947 device_printf(sc->ti_dev, "unknown command\n"); 948 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 949 device_printf(sc->ti_dev, "bad config data\n"); 950 break; 951 case TI_EV_FIRMWARE_UP: 952 ti_init2(sc); 953 break; 954 case TI_EV_STATS_UPDATED: 955 ti_stats_update(sc); 956 break; 957 case TI_EV_RESET_JUMBO_RING: 958 case TI_EV_MCAST_UPDATED: 959 /* Who cares. */ 960 break; 961 default: 962 device_printf(sc->ti_dev, "unknown event: %d\n", 963 TI_EVENT_EVENT(e)); 964 break; 965 } 966 /* Advance the consumer index. */ 967 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 968 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 969 } 970} 971 972static int 973ti_alloc_dmamaps(struct ti_softc *sc) 974{ 975 int i; 976 977 for (i = 0; i < TI_TX_RING_CNT; i++) { 978 sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 979 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 980 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 981 &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) { 982 device_printf(sc->ti_dev, 983 "cannot create DMA map for TX\n"); 984 return (ENOBUFS); 985 } 986 } 987 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 988 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 989 &sc->ti_cdata.ti_rx_std_maps[i])) { 990 device_printf(sc->ti_dev, 991 "cannot create DMA map for RX\n"); 992 return (ENOBUFS); 993 } 994 } 995 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 996 &sc->ti_cdata.ti_rx_std_sparemap)) { 997 device_printf(sc->ti_dev, 998 "cannot create spare DMA map for RX\n"); 999 return (ENOBUFS); 1000 } 1001 1002 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1003 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1004 &sc->ti_cdata.ti_rx_jumbo_maps[i])) { 1005 device_printf(sc->ti_dev, 1006 "cannot create DMA map for jumbo RX\n"); 1007 return (ENOBUFS); 1008 } 1009 } 1010 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1011 &sc->ti_cdata.ti_rx_jumbo_sparemap)) { 1012 device_printf(sc->ti_dev, 1013 "cannot create spare DMA map for jumbo RX\n"); 1014 return (ENOBUFS); 1015 } 1016 1017 /* Mini ring is not available on Tigon 1. */ 1018 if (sc->ti_hwrev == TI_HWREV_TIGON) 1019 return (0); 1020 1021 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1022 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1023 &sc->ti_cdata.ti_rx_mini_maps[i])) { 1024 device_printf(sc->ti_dev, 1025 "cannot create DMA map for mini RX\n"); 1026 return (ENOBUFS); 1027 } 1028 } 1029 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1030 &sc->ti_cdata.ti_rx_mini_sparemap)) { 1031 device_printf(sc->ti_dev, 1032 "cannot create DMA map for mini RX\n"); 1033 return (ENOBUFS); 1034 } 1035 1036 return (0); 1037} 1038 1039static void 1040ti_free_dmamaps(struct ti_softc *sc) 1041{ 1042 int i; 1043 1044 if (sc->ti_mbuftx_dmat) { 1045 for (i = 0; i < TI_TX_RING_CNT; i++) { 1046 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1047 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1048 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1049 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1050 } 1051 } 1052 } 1053 1054 if (sc->ti_mbufrx_dmat) { 1055 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1056 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1057 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1058 sc->ti_cdata.ti_rx_std_maps[i]); 1059 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1060 } 1061 } 1062 if (sc->ti_cdata.ti_rx_std_sparemap) { 1063 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1064 sc->ti_cdata.ti_rx_std_sparemap); 1065 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1066 } 1067 } 1068 1069 if (sc->ti_jumbo_dmat) { 1070 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1071 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1072 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1073 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1074 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1075 } 1076 } 1077 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1078 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1079 sc->ti_cdata.ti_rx_jumbo_sparemap); 1080 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1081 } 1082 } 1083 1084 if (sc->ti_mbufrx_dmat) { 1085 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1086 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1087 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1088 sc->ti_cdata.ti_rx_mini_maps[i]); 1089 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1090 } 1091 } 1092 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1093 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1094 sc->ti_cdata.ti_rx_mini_sparemap); 1095 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1096 } 1097 } 1098} 1099 1100#ifndef TI_SF_BUF_JUMBO 1101 1102static int 1103ti_alloc_jumbo_mem(struct ti_softc *sc) 1104{ 1105 1106 if (bus_dma_tag_create(sc->ti_parent_dmat, 1, 0, BUS_SPACE_MAXADDR, 1107 BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, 1108 NULL, &sc->ti_jumbo_dmat) != 0) { 1109 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1110 return (ENOBUFS); 1111 } 1112 return (0); 1113} 1114 1115#else 1116 1117static int 1118ti_alloc_jumbo_mem(struct ti_softc *sc) 1119{ 1120 1121 /* 1122 * The VM system will take care of providing aligned pages. Alignment 1123 * is set to 1 here so that busdma resources won't be wasted. 1124 */ 1125 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1126 1, 0, /* algnmnt, boundary */ 1127 BUS_SPACE_MAXADDR, /* lowaddr */ 1128 BUS_SPACE_MAXADDR, /* highaddr */ 1129 NULL, NULL, /* filter, filterarg */ 1130 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1131 4, /* nsegments */ 1132 PAGE_SIZE, /* maxsegsize */ 1133 0, /* flags */ 1134 NULL, NULL, /* lockfunc, lockarg */ 1135 &sc->ti_jumbo_dmat) != 0) { 1136 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1137 return (ENOBUFS); 1138 } 1139 1140 return (0); 1141} 1142 1143#endif /* TI_SF_BUF_JUMBO */ 1144 1145/* 1146 * Intialize a standard receive ring descriptor. 1147 */ 1148static int 1149ti_newbuf_std(struct ti_softc *sc, int i) 1150{ 1151 bus_dmamap_t map; 1152 bus_dma_segment_t segs[1]; 1153 struct mbuf *m; 1154 struct ti_rx_desc *r; 1155 int error, nsegs; 1156 1157 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1158 if (m == NULL) 1159 return (ENOBUFS); 1160 m->m_len = m->m_pkthdr.len = MCLBYTES; 1161 m_adj(m, ETHER_ALIGN); 1162 1163 error = bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, 1164 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1165 if (error != 0) { 1166 m_freem(m); 1167 return (error); 1168 } 1169 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1170 1171 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1172 bus_dmamap_sync(sc->ti_mbufrx_dmat, 1173 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1174 bus_dmamap_unload(sc->ti_mbufrx_dmat, 1175 sc->ti_cdata.ti_rx_std_maps[i]); 1176 } 1177 1178 map = sc->ti_cdata.ti_rx_std_maps[i]; 1179 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1180 sc->ti_cdata.ti_rx_std_sparemap = map; 1181 sc->ti_cdata.ti_rx_std_chain[i] = m; 1182 1183 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1184 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1185 r->ti_len = segs[0].ds_len; 1186 r->ti_type = TI_BDTYPE_RECV_BD; 1187 r->ti_flags = 0; 1188 r->ti_vlan_tag = 0; 1189 r->ti_tcp_udp_cksum = 0; 1190 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1191 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1192 r->ti_idx = i; 1193 1194 bus_dmamap_sync(sc->ti_mbufrx_dmat, sc->ti_cdata.ti_rx_std_maps[i], 1195 BUS_DMASYNC_PREREAD); 1196 return (0); 1197} 1198 1199/* 1200 * Intialize a mini receive ring descriptor. This only applies to 1201 * the Tigon 2. 1202 */ 1203static int 1204ti_newbuf_mini(struct ti_softc *sc, int i) 1205{ 1206 bus_dmamap_t map; 1207 bus_dma_segment_t segs[1]; 1208 struct mbuf *m; 1209 struct ti_rx_desc *r; 1210 int error, nsegs; 1211 1212 MGETHDR(m, M_DONTWAIT, MT_DATA); 1213 if (m == NULL) 1214 return (ENOBUFS); 1215 m->m_len = m->m_pkthdr.len = MHLEN; 1216 m_adj(m, ETHER_ALIGN); 1217 1218 error = bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, 1219 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1220 if (error != 0) { 1221 m_freem(m); 1222 return (error); 1223 } 1224 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1225 1226 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1227 bus_dmamap_sync(sc->ti_mbufrx_dmat, 1228 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(sc->ti_mbufrx_dmat, 1230 sc->ti_cdata.ti_rx_mini_maps[i]); 1231 } 1232 1233 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1234 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1235 sc->ti_cdata.ti_rx_mini_sparemap = map; 1236 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1237 1238 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1239 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1240 r->ti_len = segs[0].ds_len; 1241 r->ti_type = TI_BDTYPE_RECV_BD; 1242 r->ti_flags = TI_BDFLAG_MINI_RING; 1243 r->ti_vlan_tag = 0; 1244 r->ti_tcp_udp_cksum = 0; 1245 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1246 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1247 r->ti_idx = i; 1248 1249 bus_dmamap_sync(sc->ti_mbufrx_dmat, sc->ti_cdata.ti_rx_mini_maps[i], 1250 BUS_DMASYNC_PREREAD); 1251 return (0); 1252} 1253 1254#ifndef TI_SF_BUF_JUMBO 1255 1256/* 1257 * Initialize a jumbo receive ring descriptor. This allocates 1258 * a jumbo buffer from the pool managed internally by the driver. 1259 */ 1260static int 1261ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1262{ 1263 bus_dmamap_t map; 1264 bus_dma_segment_t segs[1]; 1265 struct mbuf *m; 1266 struct ti_rx_desc *r; 1267 int error, nsegs; 1268 1269 (void)dummy; 1270 1271 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1272 if (m == NULL) 1273 return (ENOBUFS); 1274 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1275 m_adj(m, ETHER_ALIGN); 1276 1277 error = bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, 1278 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1279 if (error != 0) { 1280 m_freem(m); 1281 return (error); 1282 } 1283 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1284 1285 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1286 bus_dmamap_sync(sc->ti_jumbo_dmat, 1287 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1288 bus_dmamap_unload(sc->ti_jumbo_dmat, 1289 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1290 } 1291 1292 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1293 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1294 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1295 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1296 1297 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1298 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1299 r->ti_len = segs[0].ds_len; 1300 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1301 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1302 r->ti_vlan_tag = 0; 1303 r->ti_tcp_udp_cksum = 0; 1304 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1305 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1306 r->ti_idx = i; 1307 1308 bus_dmamap_sync(sc->ti_jumbo_dmat, sc->ti_cdata.ti_rx_jumbo_maps[i], 1309 BUS_DMASYNC_PREREAD); 1310 return (0); 1311} 1312 1313#else 1314 1315#if (PAGE_SIZE == 4096) 1316#define NPAYLOAD 2 1317#else 1318#define NPAYLOAD 1 1319#endif 1320 1321#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1322#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1323#define NFS_HDR_LEN (UDP_HDR_LEN) 1324static int HDR_LEN = TCP_HDR_LEN; 1325 1326/* 1327 * Initialize a jumbo receive ring descriptor. This allocates 1328 * a jumbo buffer from the pool managed internally by the driver. 1329 */ 1330static int 1331ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1332{ 1333 bus_dmamap_t map; 1334 struct mbuf *cur, *m_new = NULL; 1335 struct mbuf *m[3] = {NULL, NULL, NULL}; 1336 struct ti_rx_desc_ext *r; 1337 vm_page_t frame; 1338 static int color; 1339 /* 1 extra buf to make nobufs easy*/ 1340 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1341 int i; 1342 bus_dma_segment_t segs[4]; 1343 int nsegs; 1344 1345 if (m_old != NULL) { 1346 m_new = m_old; 1347 cur = m_old->m_next; 1348 for (i = 0; i <= NPAYLOAD; i++){ 1349 m[i] = cur; 1350 cur = cur->m_next; 1351 } 1352 } else { 1353 /* Allocate the mbufs. */ 1354 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1355 if (m_new == NULL) { 1356 device_printf(sc->ti_dev, "mbuf allocation failed " 1357 "-- packet dropped!\n"); 1358 goto nobufs; 1359 } 1360 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1361 if (m[NPAYLOAD] == NULL) { 1362 device_printf(sc->ti_dev, "cluster mbuf allocation " 1363 "failed -- packet dropped!\n"); 1364 goto nobufs; 1365 } 1366 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1367 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1368 device_printf(sc->ti_dev, "mbuf allocation failed " 1369 "-- packet dropped!\n"); 1370 goto nobufs; 1371 } 1372 m[NPAYLOAD]->m_len = MCLBYTES; 1373 1374 for (i = 0; i < NPAYLOAD; i++){ 1375 MGET(m[i], M_DONTWAIT, MT_DATA); 1376 if (m[i] == NULL) { 1377 device_printf(sc->ti_dev, "mbuf allocation " 1378 "failed -- packet dropped!\n"); 1379 goto nobufs; 1380 } 1381 frame = vm_page_alloc(NULL, color++, 1382 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1383 VM_ALLOC_WIRED); 1384 if (frame == NULL) { 1385 device_printf(sc->ti_dev, "buffer allocation " 1386 "failed -- packet dropped!\n"); 1387 printf(" index %d page %d\n", idx, i); 1388 goto nobufs; 1389 } 1390 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1391 if (sf[i] == NULL) { 1392 vm_page_unwire(frame, 0); 1393 vm_page_free(frame); 1394 device_printf(sc->ti_dev, "buffer allocation " 1395 "failed -- packet dropped!\n"); 1396 printf(" index %d page %d\n", idx, i); 1397 goto nobufs; 1398 } 1399 } 1400 for (i = 0; i < NPAYLOAD; i++){ 1401 /* Attach the buffer to the mbuf. */ 1402 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1403 m[i]->m_len = PAGE_SIZE; 1404 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1405 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1406 0, EXT_DISPOSABLE); 1407 m[i]->m_next = m[i+1]; 1408 } 1409 /* link the buffers to the header */ 1410 m_new->m_next = m[0]; 1411 m_new->m_data += ETHER_ALIGN; 1412 if (sc->ti_hdrsplit) 1413 m_new->m_len = MHLEN - ETHER_ALIGN; 1414 else 1415 m_new->m_len = HDR_LEN; 1416 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1417 } 1418 1419 /* Set up the descriptor. */ 1420 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1421 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1422 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1423 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1424 &nsegs, 0)) 1425 return (ENOBUFS); 1426 if ((nsegs < 1) || (nsegs > 4)) 1427 return (ENOBUFS); 1428 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1429 r->ti_len0 = m_new->m_len; 1430 1431 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1432 r->ti_len1 = PAGE_SIZE; 1433 1434 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1435 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1436 1437 if (PAGE_SIZE == 4096) { 1438 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1439 r->ti_len3 = MCLBYTES; 1440 } else { 1441 r->ti_len3 = 0; 1442 } 1443 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1444 1445 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1446 1447 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1448 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1449 1450 r->ti_idx = idx; 1451 1452 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1453 return (0); 1454 1455nobufs: 1456 1457 /* 1458 * Warning! : 1459 * This can only be called before the mbufs are strung together. 1460 * If the mbufs are strung together, m_freem() will free the chain, 1461 * so that the later mbufs will be freed multiple times. 1462 */ 1463 if (m_new) 1464 m_freem(m_new); 1465 1466 for (i = 0; i < 3; i++) { 1467 if (m[i]) 1468 m_freem(m[i]); 1469 if (sf[i]) 1470 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1471 } 1472 return (ENOBUFS); 1473} 1474#endif 1475 1476/* 1477 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1478 * that's 1MB or memory, which is a lot. For now, we fill only the first 1479 * 256 ring entries and hope that our CPU is fast enough to keep up with 1480 * the NIC. 1481 */ 1482static int 1483ti_init_rx_ring_std(struct ti_softc *sc) 1484{ 1485 int i; 1486 struct ti_cmd_desc cmd; 1487 1488 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1489 if (ti_newbuf_std(sc, i) != 0) 1490 return (ENOBUFS); 1491 }; 1492 1493 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1494 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1495 1496 return (0); 1497} 1498 1499static void 1500ti_free_rx_ring_std(struct ti_softc *sc) 1501{ 1502 bus_dmamap_t map; 1503 int i; 1504 1505 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1506 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1507 map = sc->ti_cdata.ti_rx_std_maps[i]; 1508 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1509 BUS_DMASYNC_POSTREAD); 1510 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1511 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1512 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1513 } 1514 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1515 sizeof(struct ti_rx_desc)); 1516 } 1517} 1518 1519static int 1520ti_init_rx_ring_jumbo(struct ti_softc *sc) 1521{ 1522 struct ti_cmd_desc cmd; 1523 int i; 1524 1525 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1526 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1527 return (ENOBUFS); 1528 }; 1529 1530 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1531 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1532 1533 return (0); 1534} 1535 1536static void 1537ti_free_rx_ring_jumbo(struct ti_softc *sc) 1538{ 1539 bus_dmamap_t map; 1540 int i; 1541 1542 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1543 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1544 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1545 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1546 BUS_DMASYNC_POSTREAD); 1547 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1548 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1549 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1550 } 1551 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1552 sizeof(struct ti_rx_desc)); 1553 } 1554} 1555 1556static int 1557ti_init_rx_ring_mini(struct ti_softc *sc) 1558{ 1559 int i; 1560 1561 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1562 if (ti_newbuf_mini(sc, i) != 0) 1563 return (ENOBUFS); 1564 }; 1565 1566 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1567 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1568 1569 return (0); 1570} 1571 1572static void 1573ti_free_rx_ring_mini(struct ti_softc *sc) 1574{ 1575 bus_dmamap_t map; 1576 int i; 1577 1578 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1579 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1580 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1581 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1582 BUS_DMASYNC_POSTREAD); 1583 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1584 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1585 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1586 } 1587 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1588 sizeof(struct ti_rx_desc)); 1589 } 1590} 1591 1592static void 1593ti_free_tx_ring(struct ti_softc *sc) 1594{ 1595 struct ti_txdesc *txd; 1596 int i; 1597 1598 if (sc->ti_rdata->ti_tx_ring == NULL) 1599 return; 1600 1601 for (i = 0; i < TI_TX_RING_CNT; i++) { 1602 txd = &sc->ti_cdata.ti_txdesc[i]; 1603 if (txd->tx_m != NULL) { 1604 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1605 BUS_DMASYNC_POSTWRITE); 1606 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1607 m_freem(txd->tx_m); 1608 txd->tx_m = NULL; 1609 } 1610 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1611 sizeof(struct ti_tx_desc)); 1612 } 1613} 1614 1615static int 1616ti_init_tx_ring(struct ti_softc *sc) 1617{ 1618 struct ti_txdesc *txd; 1619 int i; 1620 1621 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1622 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1623 for (i = 0; i < TI_TX_RING_CNT; i++) { 1624 txd = &sc->ti_cdata.ti_txdesc[i]; 1625 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1626 } 1627 sc->ti_txcnt = 0; 1628 sc->ti_tx_saved_considx = 0; 1629 sc->ti_tx_saved_prodidx = 0; 1630 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1631 return (0); 1632} 1633 1634/* 1635 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1636 * but we have to support the old way too so that Tigon 1 cards will 1637 * work. 1638 */ 1639static void 1640ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1641{ 1642 struct ti_cmd_desc cmd; 1643 uint16_t *m; 1644 uint32_t ext[2] = {0, 0}; 1645 1646 m = (uint16_t *)&addr->octet[0]; 1647 1648 switch (sc->ti_hwrev) { 1649 case TI_HWREV_TIGON: 1650 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1651 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1652 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1653 break; 1654 case TI_HWREV_TIGON_II: 1655 ext[0] = htons(m[0]); 1656 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1657 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1658 break; 1659 default: 1660 device_printf(sc->ti_dev, "unknown hwrev\n"); 1661 break; 1662 } 1663} 1664 1665static void 1666ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1667{ 1668 struct ti_cmd_desc cmd; 1669 uint16_t *m; 1670 uint32_t ext[2] = {0, 0}; 1671 1672 m = (uint16_t *)&addr->octet[0]; 1673 1674 switch (sc->ti_hwrev) { 1675 case TI_HWREV_TIGON: 1676 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1677 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1678 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1679 break; 1680 case TI_HWREV_TIGON_II: 1681 ext[0] = htons(m[0]); 1682 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1683 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1684 break; 1685 default: 1686 device_printf(sc->ti_dev, "unknown hwrev\n"); 1687 break; 1688 } 1689} 1690 1691/* 1692 * Configure the Tigon's multicast address filter. 1693 * 1694 * The actual multicast table management is a bit of a pain, thanks to 1695 * slight brain damage on the part of both Alteon and us. With our 1696 * multicast code, we are only alerted when the multicast address table 1697 * changes and at that point we only have the current list of addresses: 1698 * we only know the current state, not the previous state, so we don't 1699 * actually know what addresses were removed or added. The firmware has 1700 * state, but we can't get our grubby mits on it, and there is no 'delete 1701 * all multicast addresses' command. Hence, we have to maintain our own 1702 * state so we know what addresses have been programmed into the NIC at 1703 * any given time. 1704 */ 1705static void 1706ti_setmulti(struct ti_softc *sc) 1707{ 1708 struct ifnet *ifp; 1709 struct ifmultiaddr *ifma; 1710 struct ti_cmd_desc cmd; 1711 struct ti_mc_entry *mc; 1712 uint32_t intrs; 1713 1714 TI_LOCK_ASSERT(sc); 1715 1716 ifp = sc->ti_ifp; 1717 1718 if (ifp->if_flags & IFF_ALLMULTI) { 1719 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1720 return; 1721 } else { 1722 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1723 } 1724 1725 /* Disable interrupts. */ 1726 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1727 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1728 1729 /* First, zot all the existing filters. */ 1730 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1731 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1732 ti_del_mcast(sc, &mc->mc_addr); 1733 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1734 free(mc, M_DEVBUF); 1735 } 1736 1737 /* Now program new ones. */ 1738 if_maddr_rlock(ifp); 1739 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1740 if (ifma->ifma_addr->sa_family != AF_LINK) 1741 continue; 1742 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1743 if (mc == NULL) { 1744 device_printf(sc->ti_dev, 1745 "no memory for mcast filter entry\n"); 1746 continue; 1747 } 1748 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1749 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1750 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1751 ti_add_mcast(sc, &mc->mc_addr); 1752 } 1753 if_maddr_runlock(ifp); 1754 1755 /* Re-enable interrupts. */ 1756 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1757} 1758 1759/* 1760 * Check to see if the BIOS has configured us for a 64 bit slot when 1761 * we aren't actually in one. If we detect this condition, we can work 1762 * around it on the Tigon 2 by setting a bit in the PCI state register, 1763 * but for the Tigon 1 we must give up and abort the interface attach. 1764 */ 1765static int 1766ti_64bitslot_war(struct ti_softc *sc) 1767{ 1768 1769 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1770 CSR_WRITE_4(sc, 0x600, 0); 1771 CSR_WRITE_4(sc, 0x604, 0); 1772 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1773 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1774 if (sc->ti_hwrev == TI_HWREV_TIGON) 1775 return (EINVAL); 1776 else { 1777 TI_SETBIT(sc, TI_PCI_STATE, 1778 TI_PCISTATE_32BIT_BUS); 1779 return (0); 1780 } 1781 } 1782 } 1783 1784 return (0); 1785} 1786 1787/* 1788 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1789 * self-test results. 1790 */ 1791static int 1792ti_chipinit(struct ti_softc *sc) 1793{ 1794 uint32_t cacheline; 1795 uint32_t pci_writemax = 0; 1796 uint32_t hdrsplit; 1797 1798 /* Initialize link to down state. */ 1799 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1800 1801 /* Set endianness before we access any non-PCI registers. */ 1802#if 0 && BYTE_ORDER == BIG_ENDIAN 1803 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1804 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1805#else 1806 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1807 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1808#endif 1809 1810 /* Check the ROM failed bit to see if self-tests passed. */ 1811 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1812 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1813 return (ENODEV); 1814 } 1815 1816 /* Halt the CPU. */ 1817 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1818 1819 /* Figure out the hardware revision. */ 1820 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1821 case TI_REV_TIGON_I: 1822 sc->ti_hwrev = TI_HWREV_TIGON; 1823 break; 1824 case TI_REV_TIGON_II: 1825 sc->ti_hwrev = TI_HWREV_TIGON_II; 1826 break; 1827 default: 1828 device_printf(sc->ti_dev, "unsupported chip revision\n"); 1829 return (ENODEV); 1830 } 1831 1832 /* Do special setup for Tigon 2. */ 1833 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1834 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1835 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1836 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1837 } 1838 1839 /* 1840 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1841 * can't do header splitting. 1842 */ 1843#ifdef TI_JUMBO_HDRSPLIT 1844 if (sc->ti_hwrev != TI_HWREV_TIGON) 1845 sc->ti_hdrsplit = 1; 1846 else 1847 device_printf(sc->ti_dev, 1848 "can't do header splitting on a Tigon I board\n"); 1849#endif /* TI_JUMBO_HDRSPLIT */ 1850 1851 /* Set up the PCI state register. */ 1852 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1853 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1854 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1855 } 1856 1857 /* Clear the read/write max DMA parameters. */ 1858 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1859 TI_PCISTATE_READ_MAXDMA)); 1860 1861 /* Get cache line size. */ 1862 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1863 1864 /* 1865 * If the system has set enabled the PCI memory write 1866 * and invalidate command in the command register, set 1867 * the write max parameter accordingly. This is necessary 1868 * to use MWI with the Tigon 2. 1869 */ 1870 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1871 switch (cacheline) { 1872 case 1: 1873 case 4: 1874 case 8: 1875 case 16: 1876 case 32: 1877 case 64: 1878 break; 1879 default: 1880 /* Disable PCI memory write and invalidate. */ 1881 if (bootverbose) 1882 device_printf(sc->ti_dev, "cache line size %d" 1883 " not supported; disabling PCI MWI\n", 1884 cacheline); 1885 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1886 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1887 break; 1888 } 1889 } 1890 1891 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1892 1893 /* This sets the min dma param all the way up (0xff). */ 1894 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1895 1896 if (sc->ti_hdrsplit) 1897 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1898 else 1899 hdrsplit = 0; 1900 1901 /* Configure DMA variables. */ 1902#if BYTE_ORDER == BIG_ENDIAN 1903 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1904 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1905 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1906 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1907#else /* BYTE_ORDER */ 1908 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1909 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1910 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1911#endif /* BYTE_ORDER */ 1912 1913 /* 1914 * Only allow 1 DMA channel to be active at a time. 1915 * I don't think this is a good idea, but without it 1916 * the firmware racks up lots of nicDmaReadRingFull 1917 * errors. This is not compatible with hardware checksums. 1918 */ 1919 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 1920 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1921 1922 /* Recommended settings from Tigon manual. */ 1923 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1924 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1925 1926 if (ti_64bitslot_war(sc)) { 1927 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 1928 "but we aren't"); 1929 return (EINVAL); 1930 } 1931 1932 return (0); 1933} 1934 1935/* 1936 * Initialize the general information block and firmware, and 1937 * start the CPU(s) running. 1938 */ 1939static int 1940ti_gibinit(struct ti_softc *sc) 1941{ 1942 struct ifnet *ifp; 1943 struct ti_rcb *rcb; 1944 uint32_t rdphys; 1945 int i; 1946 1947 TI_LOCK_ASSERT(sc); 1948 1949 ifp = sc->ti_ifp; 1950 rdphys = sc->ti_rdata_phys; 1951 1952 /* Disable interrupts for now. */ 1953 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1954 1955 /* 1956 * Tell the chip where to find the general information block. 1957 * While this struct could go into >4GB memory, we allocate it in a 1958 * single slab with the other descriptors, and those don't seem to 1959 * support being located in a 64-bit region. 1960 */ 1961 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1962 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 1963 1964 /* Load the firmware into SRAM. */ 1965 ti_loadfw(sc); 1966 1967 /* Set up the contents of the general info and ring control blocks. */ 1968 1969 /* Set up the event ring and producer pointer. */ 1970 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1971 1972 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 1973 rcb->ti_flags = 0; 1974 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1975 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 1976 sc->ti_ev_prodidx.ti_idx = 0; 1977 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1978 sc->ti_ev_saved_considx = 0; 1979 1980 /* Set up the command ring and producer mailbox. */ 1981 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1982 1983 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1984 rcb->ti_flags = 0; 1985 rcb->ti_max_len = 0; 1986 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1987 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1988 } 1989 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1990 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1991 sc->ti_cmd_saved_prodidx = 0; 1992 1993 /* 1994 * Assign the address of the stats refresh buffer. 1995 * We re-use the current stats buffer for this to 1996 * conserve memory. 1997 */ 1998 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1999 rdphys + TI_RD_OFF(ti_info.ti_stats); 2000 2001 /* Set up the standard receive ring. */ 2002 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2003 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2004 rcb->ti_max_len = TI_FRAMELEN; 2005 rcb->ti_flags = 0; 2006 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2007 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2008 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2009 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2010 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2011 2012 /* Set up the jumbo receive ring. */ 2013 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2014 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2015 2016#ifndef TI_SF_BUF_JUMBO 2017 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2018 rcb->ti_flags = 0; 2019#else 2020 rcb->ti_max_len = PAGE_SIZE; 2021 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2022#endif 2023 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2024 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2025 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2026 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2027 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2028 2029 /* 2030 * Set up the mini ring. Only activated on the 2031 * Tigon 2 but the slot in the config block is 2032 * still there on the Tigon 1. 2033 */ 2034 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2035 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2036 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2037 if (sc->ti_hwrev == TI_HWREV_TIGON) 2038 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2039 else 2040 rcb->ti_flags = 0; 2041 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2042 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2043 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2044 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2045 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2046 2047 /* 2048 * Set up the receive return ring. 2049 */ 2050 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2051 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2052 rcb->ti_flags = 0; 2053 rcb->ti_max_len = TI_RETURN_RING_CNT; 2054 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2055 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2056 2057 /* 2058 * Set up the tx ring. Note: for the Tigon 2, we have the option 2059 * of putting the transmit ring in the host's address space and 2060 * letting the chip DMA it instead of leaving the ring in the NIC's 2061 * memory and accessing it through the shared memory region. We 2062 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2063 * so we have to revert to the shared memory scheme if we detect 2064 * a Tigon 1 chip. 2065 */ 2066 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2067 bzero((char *)sc->ti_rdata->ti_tx_ring, 2068 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2069 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2070 if (sc->ti_hwrev == TI_HWREV_TIGON) 2071 rcb->ti_flags = 0; 2072 else 2073 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2074 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2075 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2076 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2077 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2078 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2079 rcb->ti_max_len = TI_TX_RING_CNT; 2080 if (sc->ti_hwrev == TI_HWREV_TIGON) 2081 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2082 else 2083 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2084 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2085 rdphys + TI_RD_OFF(ti_tx_considx_r); 2086 2087 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2088 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2089 2090 /* Set up tunables */ 2091#if 0 2092 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2093 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2094 (sc->ti_rx_coal_ticks / 10)); 2095 else 2096#endif 2097 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2098 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2099 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2100 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2101 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2102 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2103 2104 /* Turn interrupts on. */ 2105 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2106 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2107 2108 /* Start CPU. */ 2109 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2110 2111 return (0); 2112} 2113 2114static void 2115ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2116{ 2117 struct ti_softc *sc; 2118 2119 sc = arg; 2120 if (error || nseg != 1) 2121 return; 2122 2123 /* 2124 * All of the Tigon data structures need to live at <4GB. This 2125 * cast is fine since busdma was told about this constraint. 2126 */ 2127 sc->ti_rdata_phys = segs[0].ds_addr; 2128 return; 2129} 2130 2131/* 2132 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2133 * against our list and return its name if we find a match. 2134 */ 2135static int 2136ti_probe(device_t dev) 2137{ 2138 const struct ti_type *t; 2139 2140 t = ti_devs; 2141 2142 while (t->ti_name != NULL) { 2143 if ((pci_get_vendor(dev) == t->ti_vid) && 2144 (pci_get_device(dev) == t->ti_did)) { 2145 device_set_desc(dev, t->ti_name); 2146 return (BUS_PROBE_DEFAULT); 2147 } 2148 t++; 2149 } 2150 2151 return (ENXIO); 2152} 2153 2154static int 2155ti_attach(device_t dev) 2156{ 2157 struct ifnet *ifp; 2158 struct ti_softc *sc; 2159 int error = 0, rid; 2160 u_char eaddr[6]; 2161 2162 sc = device_get_softc(dev); 2163 sc->ti_dev = dev; 2164 2165 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2166 MTX_DEF); 2167 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2168 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2169 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2170 if (ifp == NULL) { 2171 device_printf(dev, "can not if_alloc()\n"); 2172 error = ENOSPC; 2173 goto fail; 2174 } 2175 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2176 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2177 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2178 2179 /* 2180 * Map control/status registers. 2181 */ 2182 pci_enable_busmaster(dev); 2183 2184 rid = PCIR_BAR(0); 2185 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2186 RF_ACTIVE); 2187 2188 if (sc->ti_res == NULL) { 2189 device_printf(dev, "couldn't map memory\n"); 2190 error = ENXIO; 2191 goto fail; 2192 } 2193 2194 sc->ti_btag = rman_get_bustag(sc->ti_res); 2195 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2196 2197 /* Allocate interrupt */ 2198 rid = 0; 2199 2200 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2201 RF_SHAREABLE | RF_ACTIVE); 2202 2203 if (sc->ti_irq == NULL) { 2204 device_printf(dev, "couldn't map interrupt\n"); 2205 error = ENXIO; 2206 goto fail; 2207 } 2208 2209 if (ti_chipinit(sc)) { 2210 device_printf(dev, "chip initialization failed\n"); 2211 error = ENXIO; 2212 goto fail; 2213 } 2214 2215 /* Zero out the NIC's on-board SRAM. */ 2216 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2217 2218 /* Init again -- zeroing memory may have clobbered some registers. */ 2219 if (ti_chipinit(sc)) { 2220 device_printf(dev, "chip initialization failed\n"); 2221 error = ENXIO; 2222 goto fail; 2223 } 2224 2225 /* 2226 * Get station address from the EEPROM. Note: the manual states 2227 * that the MAC address is at offset 0x8c, however the data is 2228 * stored as two longwords (since that's how it's loaded into 2229 * the NIC). This means the MAC address is actually preceded 2230 * by two zero bytes. We need to skip over those. 2231 */ 2232 if (ti_read_eeprom(sc, eaddr, 2233 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2234 device_printf(dev, "failed to read station address\n"); 2235 error = ENXIO; 2236 goto fail; 2237 } 2238 2239 /* Allocate working area for memory dump. */ 2240 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2241 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2242 M_NOWAIT); 2243 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2244 device_printf(dev, "cannot allocate memory buffer\n"); 2245 error = ENOMEM; 2246 goto fail; 2247 } 2248 2249 /* Allocate the general information block and ring buffers. */ 2250 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2251 1, 0, /* algnmnt, boundary */ 2252 BUS_SPACE_MAXADDR, /* lowaddr */ 2253 BUS_SPACE_MAXADDR, /* highaddr */ 2254 NULL, NULL, /* filter, filterarg */ 2255 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2256 0, /* nsegments */ 2257 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2258 0, /* flags */ 2259 NULL, NULL, /* lockfunc, lockarg */ 2260 &sc->ti_parent_dmat) != 0) { 2261 device_printf(dev, "Failed to allocate parent dmat\n"); 2262 error = ENOMEM; 2263 goto fail; 2264 } 2265 2266 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2267 PAGE_SIZE, 0, /* algnmnt, boundary */ 2268 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2269 BUS_SPACE_MAXADDR, /* highaddr */ 2270 NULL, NULL, /* filter, filterarg */ 2271 sizeof(struct ti_ring_data), /* maxsize */ 2272 1, /* nsegments */ 2273 sizeof(struct ti_ring_data), /* maxsegsize */ 2274 0, /* flags */ 2275 NULL, NULL, /* lockfunc, lockarg */ 2276 &sc->ti_rdata_dmat) != 0) { 2277 device_printf(dev, "Failed to allocate rdata dmat\n"); 2278 error = ENOMEM; 2279 goto fail; 2280 } 2281 2282 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2283 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2284 &sc->ti_rdata_dmamap) != 0) { 2285 device_printf(dev, "Failed to allocate rdata memory\n"); 2286 error = ENOMEM; 2287 goto fail; 2288 } 2289 2290 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2291 sc->ti_rdata, sizeof(struct ti_ring_data), 2292 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2293 device_printf(dev, "Failed to load rdata segments\n"); 2294 error = ENOMEM; 2295 goto fail; 2296 } 2297 2298 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2299 2300 /* Try to allocate memory for jumbo buffers. */ 2301 if (ti_alloc_jumbo_mem(sc)) { 2302 device_printf(dev, "jumbo buffer allocation failed\n"); 2303 error = ENXIO; 2304 goto fail; 2305 } 2306 2307 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2308 1, 0, /* algnmnt, boundary */ 2309 BUS_SPACE_MAXADDR, /* lowaddr */ 2310 BUS_SPACE_MAXADDR, /* highaddr */ 2311 NULL, NULL, /* filter, filterarg */ 2312 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2313 TI_MAXTXSEGS, /* nsegments */ 2314 MCLBYTES, /* maxsegsize */ 2315 0, /* flags */ 2316 NULL, NULL, /* lockfunc, lockarg */ 2317 &sc->ti_mbuftx_dmat) != 0) { 2318 device_printf(dev, "Failed to allocate rdata dmat\n"); 2319 error = ENOMEM; 2320 goto fail; 2321 } 2322 2323 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2324 1, 0, /* algnmnt, boundary */ 2325 BUS_SPACE_MAXADDR, /* lowaddr */ 2326 BUS_SPACE_MAXADDR, /* highaddr */ 2327 NULL, NULL, /* filter, filterarg */ 2328 MCLBYTES, /* maxsize */ 2329 1, /* nsegments */ 2330 MCLBYTES, /* maxsegsize */ 2331 0, /* flags */ 2332 NULL, NULL, /* lockfunc, lockarg */ 2333 &sc->ti_mbufrx_dmat) != 0) { 2334 device_printf(dev, "Failed to allocate rdata dmat\n"); 2335 error = ENOMEM; 2336 goto fail; 2337 } 2338 2339 if (ti_alloc_dmamaps(sc)) { 2340 error = ENXIO; 2341 goto fail; 2342 } 2343 2344 /* 2345 * We really need a better way to tell a 1000baseTX card 2346 * from a 1000baseSX one, since in theory there could be 2347 * OEMed 1000baseTX cards from lame vendors who aren't 2348 * clever enough to change the PCI ID. For the moment 2349 * though, the AceNIC is the only copper card available. 2350 */ 2351 if (pci_get_vendor(dev) == ALT_VENDORID && 2352 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2353 sc->ti_copper = 1; 2354 /* Ok, it's not the only copper card available. */ 2355 if (pci_get_vendor(dev) == NG_VENDORID && 2356 pci_get_device(dev) == NG_DEVICEID_GA620T) 2357 sc->ti_copper = 1; 2358 2359 /* Set default tunable values. */ 2360 ti_sysctl_node(sc); 2361 2362 /* Set up ifnet structure */ 2363 ifp->if_softc = sc; 2364 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2365 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2366 ifp->if_ioctl = ti_ioctl; 2367 ifp->if_start = ti_start; 2368 ifp->if_init = ti_init; 2369 ifp->if_baudrate = IF_Gbps(1UL); 2370 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2371 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2372 IFQ_SET_READY(&ifp->if_snd); 2373 2374 /* Set up ifmedia support. */ 2375 if (sc->ti_copper) { 2376 /* 2377 * Copper cards allow manual 10/100 mode selection, 2378 * but not manual 1000baseTX mode selection. Why? 2379 * Becuase currently there's no way to specify the 2380 * master/slave setting through the firmware interface, 2381 * so Alteon decided to just bag it and handle it 2382 * via autonegotiation. 2383 */ 2384 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2385 ifmedia_add(&sc->ifmedia, 2386 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2387 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2388 ifmedia_add(&sc->ifmedia, 2389 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2390 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2391 ifmedia_add(&sc->ifmedia, 2392 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2393 } else { 2394 /* Fiber cards don't support 10/100 modes. */ 2395 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2396 ifmedia_add(&sc->ifmedia, 2397 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2398 } 2399 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2400 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2401 2402 /* 2403 * We're assuming here that card initialization is a sequential 2404 * thing. If it isn't, multiple cards probing at the same time 2405 * could stomp on the list of softcs here. 2406 */ 2407 2408 /* Register the device */ 2409 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2410 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2411 sc->dev->si_drv1 = sc; 2412 2413 /* 2414 * Call MI attach routine. 2415 */ 2416 ether_ifattach(ifp, eaddr); 2417 2418 /* VLAN capability setup. */ 2419 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2420 IFCAP_VLAN_HWTAGGING; 2421 ifp->if_capenable = ifp->if_capabilities; 2422 /* Tell the upper layer we support VLAN over-sized frames. */ 2423 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2424 2425 /* Driver supports link state tracking. */ 2426 ifp->if_capabilities |= IFCAP_LINKSTATE; 2427 ifp->if_capenable |= IFCAP_LINKSTATE; 2428 2429 /* Hook interrupt last to avoid having to lock softc */ 2430 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2431 NULL, ti_intr, sc, &sc->ti_intrhand); 2432 2433 if (error) { 2434 device_printf(dev, "couldn't set up irq\n"); 2435 goto fail; 2436 } 2437 2438fail: 2439 if (error) 2440 ti_detach(dev); 2441 2442 return (error); 2443} 2444 2445/* 2446 * Shutdown hardware and free up resources. This can be called any 2447 * time after the mutex has been initialized. It is called in both 2448 * the error case in attach and the normal detach case so it needs 2449 * to be careful about only freeing resources that have actually been 2450 * allocated. 2451 */ 2452static int 2453ti_detach(device_t dev) 2454{ 2455 struct ti_softc *sc; 2456 struct ifnet *ifp; 2457 2458 sc = device_get_softc(dev); 2459 if (sc->dev) 2460 destroy_dev(sc->dev); 2461 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2462 ifp = sc->ti_ifp; 2463 if (device_is_attached(dev)) { 2464 ether_ifdetach(ifp); 2465 TI_LOCK(sc); 2466 ti_stop(sc); 2467 TI_UNLOCK(sc); 2468 } 2469 2470 /* These should only be active if attach succeeded */ 2471 callout_drain(&sc->ti_watchdog); 2472 bus_generic_detach(dev); 2473 ti_free_dmamaps(sc); 2474 ifmedia_removeall(&sc->ifmedia); 2475 2476 if (sc->ti_jumbo_dmat) 2477 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2478 if (sc->ti_mbuftx_dmat) 2479 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2480 if (sc->ti_mbufrx_dmat) 2481 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2482 if (sc->ti_rdata && sc->ti_rdata_dmamap) 2483 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap); 2484 if (sc->ti_rdata) 2485 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2486 sc->ti_rdata_dmamap); 2487 if (sc->ti_rdata_dmat) 2488 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2489 if (sc->ti_parent_dmat) 2490 bus_dma_tag_destroy(sc->ti_parent_dmat); 2491 if (sc->ti_intrhand) 2492 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2493 if (sc->ti_irq) 2494 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2495 if (sc->ti_res) { 2496 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2497 sc->ti_res); 2498 } 2499 if (ifp) 2500 if_free(ifp); 2501 if (sc->ti_membuf) 2502 free(sc->ti_membuf, M_DEVBUF); 2503 if (sc->ti_membuf2) 2504 free(sc->ti_membuf2, M_DEVBUF); 2505 2506 mtx_destroy(&sc->ti_mtx); 2507 2508 return (0); 2509} 2510 2511#ifdef TI_JUMBO_HDRSPLIT 2512/* 2513 * If hdr_len is 0, that means that header splitting wasn't done on 2514 * this packet for some reason. The two most likely reasons are that 2515 * the protocol isn't a supported protocol for splitting, or this 2516 * packet had a fragment offset that wasn't 0. 2517 * 2518 * The header length, if it is non-zero, will always be the length of 2519 * the headers on the packet, but that length could be longer than the 2520 * first mbuf. So we take the minimum of the two as the actual 2521 * length. 2522 */ 2523static __inline void 2524ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2525{ 2526 int i = 0; 2527 int lengths[4] = {0, 0, 0, 0}; 2528 struct mbuf *m, *mp; 2529 2530 if (hdr_len != 0) 2531 top->m_len = min(hdr_len, top->m_len); 2532 pkt_len -= top->m_len; 2533 lengths[i++] = top->m_len; 2534 2535 mp = top; 2536 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2537 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2538 pkt_len -= m->m_len; 2539 lengths[i++] = m->m_len; 2540 mp = m; 2541 } 2542 2543#if 0 2544 if (hdr_len != 0) 2545 printf("got split packet: "); 2546 else 2547 printf("got non-split packet: "); 2548 2549 printf("%d,%d,%d,%d = %d\n", lengths[0], 2550 lengths[1], lengths[2], lengths[3], 2551 lengths[0] + lengths[1] + lengths[2] + 2552 lengths[3]); 2553#endif 2554 2555 if (pkt_len) 2556 panic("header splitting didn't"); 2557 2558 if (m) { 2559 m_freem(m); 2560 mp->m_next = NULL; 2561 2562 } 2563 if (mp->m_next != NULL) 2564 panic("ti_hdr_split: last mbuf in chain should be null"); 2565} 2566#endif /* TI_JUMBO_HDRSPLIT */ 2567 2568static void 2569ti_discard_std(struct ti_softc *sc, int i) 2570{ 2571 2572 struct ti_rx_desc *r; 2573 2574 r = &sc->ti_rdata->ti_rx_std_ring[i]; 2575 r->ti_len = MCLBYTES - ETHER_ALIGN; 2576 r->ti_type = TI_BDTYPE_RECV_BD; 2577 r->ti_flags = 0; 2578 r->ti_vlan_tag = 0; 2579 r->ti_tcp_udp_cksum = 0; 2580 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2581 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2582 r->ti_idx = i; 2583} 2584 2585static void 2586ti_discard_mini(struct ti_softc *sc, int i) 2587{ 2588 2589 struct ti_rx_desc *r; 2590 2591 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 2592 r->ti_len = MHLEN - ETHER_ALIGN; 2593 r->ti_type = TI_BDTYPE_RECV_BD; 2594 r->ti_flags = TI_BDFLAG_MINI_RING; 2595 r->ti_vlan_tag = 0; 2596 r->ti_tcp_udp_cksum = 0; 2597 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2598 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2599 r->ti_idx = i; 2600} 2601 2602#ifndef TI_SF_BUF_JUMBO 2603static void 2604ti_discard_jumbo(struct ti_softc *sc, int i) 2605{ 2606 2607 struct ti_rx_desc *r; 2608 2609 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 2610 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2611 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2612 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2613 r->ti_vlan_tag = 0; 2614 r->ti_tcp_udp_cksum = 0; 2615 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2616 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2617 r->ti_idx = i; 2618} 2619#endif 2620 2621/* 2622 * Frame reception handling. This is called if there's a frame 2623 * on the receive return list. 2624 * 2625 * Note: we have to be able to handle three possibilities here: 2626 * 1) the frame is from the mini receive ring (can only happen) 2627 * on Tigon 2 boards) 2628 * 2) the frame is from the jumbo recieve ring 2629 * 3) the frame is from the standard receive ring 2630 */ 2631 2632static void 2633ti_rxeof(struct ti_softc *sc) 2634{ 2635 struct ifnet *ifp; 2636#ifdef TI_SF_BUF_JUMBO 2637 bus_dmamap_t map; 2638#endif 2639 struct ti_cmd_desc cmd; 2640 int jumbocnt, minicnt, stdcnt, ti_len; 2641 2642 TI_LOCK_ASSERT(sc); 2643 2644 ifp = sc->ti_ifp; 2645 2646 jumbocnt = minicnt = stdcnt = 0; 2647 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2648 struct ti_rx_desc *cur_rx; 2649 uint32_t rxidx; 2650 struct mbuf *m = NULL; 2651 uint16_t vlan_tag = 0; 2652 int have_tag = 0; 2653 2654 cur_rx = 2655 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2656 rxidx = cur_rx->ti_idx; 2657 ti_len = cur_rx->ti_len; 2658 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2659 2660 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2661 have_tag = 1; 2662 vlan_tag = cur_rx->ti_vlan_tag; 2663 } 2664 2665 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2666 jumbocnt++; 2667 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2668 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2669#ifndef TI_SF_BUF_JUMBO 2670 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2671 ifp->if_ierrors++; 2672 ti_discard_jumbo(sc, rxidx); 2673 continue; 2674 } 2675 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2676 ifp->if_iqdrops++; 2677 ti_discard_jumbo(sc, rxidx); 2678 continue; 2679 } 2680 m->m_len = ti_len; 2681#else /* !TI_SF_BUF_JUMBO */ 2682 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2683 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2684 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2685 BUS_DMASYNC_POSTREAD); 2686 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2687 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2688 ifp->if_ierrors++; 2689 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2690 continue; 2691 } 2692 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2693 ifp->if_iqdrops++; 2694 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2695 continue; 2696 } 2697#ifdef TI_JUMBO_HDRSPLIT 2698 if (sc->ti_hdrsplit) 2699 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2700 ti_len, rxidx); 2701 else 2702#endif /* TI_JUMBO_HDRSPLIT */ 2703 m_adj(m, ti_len - m->m_pkthdr.len); 2704#endif /* TI_SF_BUF_JUMBO */ 2705 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2706 minicnt++; 2707 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2708 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2709 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2710 ifp->if_ierrors++; 2711 ti_discard_mini(sc, rxidx); 2712 continue; 2713 } 2714 if (ti_newbuf_mini(sc, rxidx) != 0) { 2715 ifp->if_iqdrops++; 2716 ti_discard_mini(sc, rxidx); 2717 continue; 2718 } 2719 m->m_len = ti_len; 2720 } else { 2721 stdcnt++; 2722 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2723 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2724 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2725 ifp->if_ierrors++; 2726 ti_discard_std(sc, rxidx); 2727 continue; 2728 } 2729 if (ti_newbuf_std(sc, rxidx) != 0) { 2730 ifp->if_iqdrops++; 2731 ti_discard_std(sc, rxidx); 2732 continue; 2733 } 2734 m->m_len = ti_len; 2735 } 2736 2737 m->m_pkthdr.len = ti_len; 2738 ifp->if_ipackets++; 2739 m->m_pkthdr.rcvif = ifp; 2740 2741 if (ifp->if_capenable & IFCAP_RXCSUM) { 2742 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2743 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2744 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2745 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2746 } 2747 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2748 m->m_pkthdr.csum_data = 2749 cur_rx->ti_tcp_udp_cksum; 2750 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2751 } 2752 } 2753 2754 /* 2755 * If we received a packet with a vlan tag, 2756 * tag it before passing the packet upward. 2757 */ 2758 if (have_tag) { 2759 m->m_pkthdr.ether_vtag = vlan_tag; 2760 m->m_flags |= M_VLANTAG; 2761 } 2762 TI_UNLOCK(sc); 2763 (*ifp->if_input)(ifp, m); 2764 TI_LOCK(sc); 2765 } 2766 2767 /* Only necessary on the Tigon 1. */ 2768 if (sc->ti_hwrev == TI_HWREV_TIGON) 2769 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2770 sc->ti_rx_saved_considx); 2771 2772 if (stdcnt > 0) 2773 TI_UPDATE_STDPROD(sc, sc->ti_std); 2774 if (minicnt > 0) 2775 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2776 if (jumbocnt > 0) 2777 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2778} 2779 2780static void 2781ti_txeof(struct ti_softc *sc) 2782{ 2783 struct ti_txdesc *txd; 2784 struct ti_tx_desc txdesc; 2785 struct ti_tx_desc *cur_tx = NULL; 2786 struct ifnet *ifp; 2787 int idx; 2788 2789 ifp = sc->ti_ifp; 2790 2791 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2792 if (txd == NULL) 2793 return; 2794 /* 2795 * Go through our tx ring and free mbufs for those 2796 * frames that have been sent. 2797 */ 2798 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2799 TI_INC(idx, TI_TX_RING_CNT)) { 2800 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2801 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2802 sizeof(txdesc), &txdesc); 2803 cur_tx = &txdesc; 2804 } else 2805 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2806 sc->ti_txcnt--; 2807 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2808 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2809 continue; 2810 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2811 BUS_DMASYNC_POSTWRITE); 2812 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2813 2814 ifp->if_opackets++; 2815 m_freem(txd->tx_m); 2816 txd->tx_m = NULL; 2817 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2818 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2819 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2820 } 2821 sc->ti_tx_saved_considx = idx; 2822 2823 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0; 2824} 2825 2826static void 2827ti_intr(void *xsc) 2828{ 2829 struct ti_softc *sc; 2830 struct ifnet *ifp; 2831 2832 sc = xsc; 2833 TI_LOCK(sc); 2834 ifp = sc->ti_ifp; 2835 2836 /* Make sure this is really our interrupt. */ 2837 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2838 TI_UNLOCK(sc); 2839 return; 2840 } 2841 2842 /* Ack interrupt and stop others from occuring. */ 2843 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2844 2845 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2846 /* Check RX return ring producer/consumer */ 2847 ti_rxeof(sc); 2848 2849 /* Check TX ring producer/consumer */ 2850 ti_txeof(sc); 2851 } 2852 2853 ti_handle_events(sc); 2854 2855 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2856 /* Re-enable interrupts. */ 2857 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2858 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2859 ti_start_locked(ifp); 2860 } 2861 2862 TI_UNLOCK(sc); 2863} 2864 2865static void 2866ti_stats_update(struct ti_softc *sc) 2867{ 2868 struct ifnet *ifp; 2869 2870 ifp = sc->ti_ifp; 2871 2872 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2873 BUS_DMASYNC_POSTREAD); 2874 2875 ifp->if_collisions += 2876 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2877 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2878 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2879 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2880 ifp->if_collisions; 2881 2882 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2883 BUS_DMASYNC_PREREAD); 2884} 2885 2886/* 2887 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2888 * pointers to descriptors. 2889 */ 2890static int 2891ti_encap(struct ti_softc *sc, struct mbuf **m_head) 2892{ 2893 struct ti_txdesc *txd; 2894 struct ti_tx_desc *f; 2895 struct ti_tx_desc txdesc; 2896 struct mbuf *m; 2897 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2898 uint16_t csum_flags; 2899 int error, frag, i, nseg; 2900 2901 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2902 return (ENOBUFS); 2903 2904 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2905 *m_head, txsegs, &nseg, 0); 2906 if (error == EFBIG) { 2907 m = m_defrag(*m_head, M_DONTWAIT); 2908 if (m == NULL) { 2909 m_freem(*m_head); 2910 *m_head = NULL; 2911 return (ENOMEM); 2912 } 2913 *m_head = m; 2914 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2915 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2916 if (error) { 2917 m_freem(*m_head); 2918 *m_head = NULL; 2919 return (error); 2920 } 2921 } else if (error != 0) 2922 return (error); 2923 if (nseg == 0) { 2924 m_freem(*m_head); 2925 *m_head = NULL; 2926 return (EIO); 2927 } 2928 2929 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2930 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2931 return (ENOBUFS); 2932 } 2933 2934 m = *m_head; 2935 csum_flags = 0; 2936 if (m->m_pkthdr.csum_flags) { 2937 if (m->m_pkthdr.csum_flags & CSUM_IP) 2938 csum_flags |= TI_BDFLAG_IP_CKSUM; 2939 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2940 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2941 if (m->m_flags & M_LASTFRAG) 2942 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2943 else if (m->m_flags & M_FRAG) 2944 csum_flags |= TI_BDFLAG_IP_FRAG; 2945 } 2946 2947 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2948 BUS_DMASYNC_PREWRITE); 2949 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2950 BUS_DMASYNC_PREWRITE); 2951 2952 frag = sc->ti_tx_saved_prodidx; 2953 for (i = 0; i < nseg; i++) { 2954 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2955 bzero(&txdesc, sizeof(txdesc)); 2956 f = &txdesc; 2957 } else 2958 f = &sc->ti_rdata->ti_tx_ring[frag]; 2959 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 2960 f->ti_len = txsegs[i].ds_len; 2961 f->ti_flags = csum_flags; 2962 if (m->m_flags & M_VLANTAG) { 2963 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2964 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 2965 } else { 2966 f->ti_vlan_tag = 0; 2967 } 2968 2969 if (sc->ti_hwrev == TI_HWREV_TIGON) 2970 ti_mem_write(sc, TI_TX_RING_BASE + frag * 2971 sizeof(txdesc), sizeof(txdesc), &txdesc); 2972 TI_INC(frag, TI_TX_RING_CNT); 2973 } 2974 2975 sc->ti_tx_saved_prodidx = frag; 2976 /* set TI_BDFLAG_END on the last descriptor */ 2977 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 2978 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2979 txdesc.ti_flags |= TI_BDFLAG_END; 2980 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 2981 sizeof(txdesc), &txdesc); 2982 } else 2983 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 2984 2985 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 2986 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 2987 txd->tx_m = m; 2988 sc->ti_txcnt += nseg; 2989 2990 return (0); 2991} 2992 2993static void 2994ti_start(struct ifnet *ifp) 2995{ 2996 struct ti_softc *sc; 2997 2998 sc = ifp->if_softc; 2999 TI_LOCK(sc); 3000 ti_start_locked(ifp); 3001 TI_UNLOCK(sc); 3002} 3003 3004/* 3005 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3006 * to the mbuf data regions directly in the transmit descriptors. 3007 */ 3008static void 3009ti_start_locked(struct ifnet *ifp) 3010{ 3011 struct ti_softc *sc; 3012 struct mbuf *m_head = NULL; 3013 int enq = 0; 3014 3015 sc = ifp->if_softc; 3016 3017 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3018 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3019 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3020 if (m_head == NULL) 3021 break; 3022 3023 /* 3024 * XXX 3025 * safety overkill. If this is a fragmented packet chain 3026 * with delayed TCP/UDP checksums, then only encapsulate 3027 * it if we have enough descriptors to handle the entire 3028 * chain at once. 3029 * (paranoia -- may not actually be needed) 3030 */ 3031 if (m_head->m_flags & M_FIRSTFRAG && 3032 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3033 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3034 m_head->m_pkthdr.csum_data + 16) { 3035 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3036 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3037 break; 3038 } 3039 } 3040 3041 /* 3042 * Pack the data into the transmit ring. If we 3043 * don't have room, set the OACTIVE flag and wait 3044 * for the NIC to drain the ring. 3045 */ 3046 if (ti_encap(sc, &m_head)) { 3047 if (m_head == NULL) 3048 break; 3049 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3050 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3051 break; 3052 } 3053 3054 enq++; 3055 /* 3056 * If there's a BPF listener, bounce a copy of this frame 3057 * to him. 3058 */ 3059 ETHER_BPF_MTAP(ifp, m_head); 3060 } 3061 3062 if (enq > 0) { 3063 /* Transmit */ 3064 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3065 3066 /* 3067 * Set a timeout in case the chip goes out to lunch. 3068 */ 3069 sc->ti_timer = 5; 3070 } 3071} 3072 3073static void 3074ti_init(void *xsc) 3075{ 3076 struct ti_softc *sc; 3077 3078 sc = xsc; 3079 TI_LOCK(sc); 3080 ti_init_locked(sc); 3081 TI_UNLOCK(sc); 3082} 3083 3084static void 3085ti_init_locked(void *xsc) 3086{ 3087 struct ti_softc *sc = xsc; 3088 3089 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3090 return; 3091 3092 /* Cancel pending I/O and flush buffers. */ 3093 ti_stop(sc); 3094 3095 /* Init the gen info block, ring control blocks and firmware. */ 3096 if (ti_gibinit(sc)) { 3097 device_printf(sc->ti_dev, "initialization failure\n"); 3098 return; 3099 } 3100} 3101 3102static void ti_init2(struct ti_softc *sc) 3103{ 3104 struct ti_cmd_desc cmd; 3105 struct ifnet *ifp; 3106 uint8_t *ea; 3107 struct ifmedia *ifm; 3108 int tmp; 3109 3110 TI_LOCK_ASSERT(sc); 3111 3112 ifp = sc->ti_ifp; 3113 3114 /* Specify MTU and interface index. */ 3115 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3116 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3117 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3118 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3119 3120 /* Load our MAC address. */ 3121 ea = IF_LLADDR(sc->ti_ifp); 3122 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3123 CSR_WRITE_4(sc, TI_GCR_PAR1, 3124 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3125 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3126 3127 /* Enable or disable promiscuous mode as needed. */ 3128 if (ifp->if_flags & IFF_PROMISC) { 3129 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3130 } else { 3131 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3132 } 3133 3134 /* Program multicast filter. */ 3135 ti_setmulti(sc); 3136 3137 /* 3138 * If this is a Tigon 1, we should tell the 3139 * firmware to use software packet filtering. 3140 */ 3141 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3142 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3143 } 3144 3145 /* Init RX ring. */ 3146 if (ti_init_rx_ring_std(sc) != 0) { 3147 /* XXX */ 3148 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3149 return; 3150 } 3151 3152 /* Init jumbo RX ring. */ 3153 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3154 if (ti_init_rx_ring_jumbo(sc) != 0) { 3155 /* XXX */ 3156 device_printf(sc->ti_dev, 3157 "no memory for jumbo Rx buffers.\n"); 3158 return; 3159 } 3160 } 3161 3162 /* 3163 * If this is a Tigon 2, we can also configure the 3164 * mini ring. 3165 */ 3166 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3167 if (ti_init_rx_ring_mini(sc) != 0) { 3168 /* XXX */ 3169 device_printf(sc->ti_dev, 3170 "no memory for mini Rx buffers.\n"); 3171 return; 3172 } 3173 } 3174 3175 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3176 sc->ti_rx_saved_considx = 0; 3177 3178 /* Init TX ring. */ 3179 ti_init_tx_ring(sc); 3180 3181 /* Tell firmware we're alive. */ 3182 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3183 3184 /* Enable host interrupts. */ 3185 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3186 3187 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3188 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3189 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3190 3191 /* 3192 * Make sure to set media properly. We have to do this 3193 * here since we have to issue commands in order to set 3194 * the link negotiation and we can't issue commands until 3195 * the firmware is running. 3196 */ 3197 ifm = &sc->ifmedia; 3198 tmp = ifm->ifm_media; 3199 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3200 ti_ifmedia_upd_locked(sc); 3201 ifm->ifm_media = tmp; 3202} 3203 3204/* 3205 * Set media options. 3206 */ 3207static int 3208ti_ifmedia_upd(struct ifnet *ifp) 3209{ 3210 struct ti_softc *sc; 3211 int error; 3212 3213 sc = ifp->if_softc; 3214 TI_LOCK(sc); 3215 error = ti_ifmedia_upd(ifp); 3216 TI_UNLOCK(sc); 3217 3218 return (error); 3219} 3220 3221static int 3222ti_ifmedia_upd_locked(struct ti_softc *sc) 3223{ 3224 struct ifmedia *ifm; 3225 struct ti_cmd_desc cmd; 3226 uint32_t flowctl; 3227 3228 ifm = &sc->ifmedia; 3229 3230 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3231 return (EINVAL); 3232 3233 flowctl = 0; 3234 3235 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3236 case IFM_AUTO: 3237 /* 3238 * Transmit flow control doesn't work on the Tigon 1. 3239 */ 3240 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3241 3242 /* 3243 * Transmit flow control can also cause problems on the 3244 * Tigon 2, apparantly with both the copper and fiber 3245 * boards. The symptom is that the interface will just 3246 * hang. This was reproduced with Alteon 180 switches. 3247 */ 3248#if 0 3249 if (sc->ti_hwrev != TI_HWREV_TIGON) 3250 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3251#endif 3252 3253 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3254 TI_GLNK_FULL_DUPLEX| flowctl | 3255 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3256 3257 flowctl = TI_LNK_RX_FLOWCTL_Y; 3258#if 0 3259 if (sc->ti_hwrev != TI_HWREV_TIGON) 3260 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3261#endif 3262 3263 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3264 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3265 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3266 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3267 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3268 break; 3269 case IFM_1000_SX: 3270 case IFM_1000_T: 3271 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3272#if 0 3273 if (sc->ti_hwrev != TI_HWREV_TIGON) 3274 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3275#endif 3276 3277 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3278 flowctl |TI_GLNK_ENB); 3279 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3280 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3281 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3282 } 3283 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3284 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3285 break; 3286 case IFM_100_FX: 3287 case IFM_10_FL: 3288 case IFM_100_TX: 3289 case IFM_10_T: 3290 flowctl = TI_LNK_RX_FLOWCTL_Y; 3291#if 0 3292 if (sc->ti_hwrev != TI_HWREV_TIGON) 3293 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3294#endif 3295 3296 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3297 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3298 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3299 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3300 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3301 } else { 3302 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3303 } 3304 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3305 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3306 } else { 3307 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3308 } 3309 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3310 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3311 break; 3312 } 3313 3314 return (0); 3315} 3316 3317/* 3318 * Report current media status. 3319 */ 3320static void 3321ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3322{ 3323 struct ti_softc *sc; 3324 uint32_t media = 0; 3325 3326 sc = ifp->if_softc; 3327 3328 TI_LOCK(sc); 3329 3330 ifmr->ifm_status = IFM_AVALID; 3331 ifmr->ifm_active = IFM_ETHER; 3332 3333 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3334 TI_UNLOCK(sc); 3335 return; 3336 } 3337 3338 ifmr->ifm_status |= IFM_ACTIVE; 3339 3340 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3341 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3342 if (sc->ti_copper) 3343 ifmr->ifm_active |= IFM_1000_T; 3344 else 3345 ifmr->ifm_active |= IFM_1000_SX; 3346 if (media & TI_GLNK_FULL_DUPLEX) 3347 ifmr->ifm_active |= IFM_FDX; 3348 else 3349 ifmr->ifm_active |= IFM_HDX; 3350 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3351 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3352 if (sc->ti_copper) { 3353 if (media & TI_LNK_100MB) 3354 ifmr->ifm_active |= IFM_100_TX; 3355 if (media & TI_LNK_10MB) 3356 ifmr->ifm_active |= IFM_10_T; 3357 } else { 3358 if (media & TI_LNK_100MB) 3359 ifmr->ifm_active |= IFM_100_FX; 3360 if (media & TI_LNK_10MB) 3361 ifmr->ifm_active |= IFM_10_FL; 3362 } 3363 if (media & TI_LNK_FULL_DUPLEX) 3364 ifmr->ifm_active |= IFM_FDX; 3365 if (media & TI_LNK_HALF_DUPLEX) 3366 ifmr->ifm_active |= IFM_HDX; 3367 } 3368 TI_UNLOCK(sc); 3369} 3370 3371static int 3372ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3373{ 3374 struct ti_softc *sc = ifp->if_softc; 3375 struct ifreq *ifr = (struct ifreq *) data; 3376 struct ti_cmd_desc cmd; 3377 int mask, error = 0; 3378 3379 switch (command) { 3380 case SIOCSIFMTU: 3381 TI_LOCK(sc); 3382 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3383 error = EINVAL; 3384 else { 3385 ifp->if_mtu = ifr->ifr_mtu; 3386 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3387 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3388 ti_init_locked(sc); 3389 } 3390 } 3391 TI_UNLOCK(sc); 3392 break; 3393 case SIOCSIFFLAGS: 3394 TI_LOCK(sc); 3395 if (ifp->if_flags & IFF_UP) { 3396 /* 3397 * If only the state of the PROMISC flag changed, 3398 * then just use the 'set promisc mode' command 3399 * instead of reinitializing the entire NIC. Doing 3400 * a full re-init means reloading the firmware and 3401 * waiting for it to start up, which may take a 3402 * second or two. 3403 */ 3404 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3405 ifp->if_flags & IFF_PROMISC && 3406 !(sc->ti_if_flags & IFF_PROMISC)) { 3407 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3408 TI_CMD_CODE_PROMISC_ENB, 0); 3409 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3410 !(ifp->if_flags & IFF_PROMISC) && 3411 sc->ti_if_flags & IFF_PROMISC) { 3412 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3413 TI_CMD_CODE_PROMISC_DIS, 0); 3414 } else 3415 ti_init_locked(sc); 3416 } else { 3417 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3418 ti_stop(sc); 3419 } 3420 } 3421 sc->ti_if_flags = ifp->if_flags; 3422 TI_UNLOCK(sc); 3423 break; 3424 case SIOCADDMULTI: 3425 case SIOCDELMULTI: 3426 TI_LOCK(sc); 3427 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3428 ti_setmulti(sc); 3429 TI_UNLOCK(sc); 3430 break; 3431 case SIOCSIFMEDIA: 3432 case SIOCGIFMEDIA: 3433 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3434 break; 3435 case SIOCSIFCAP: 3436 TI_LOCK(sc); 3437 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3438 if ((mask & IFCAP_TXCSUM) != 0 && 3439 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3440 ifp->if_capenable ^= IFCAP_TXCSUM; 3441 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3442 ifp->if_hwassist |= TI_CSUM_FEATURES; 3443 else 3444 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3445 } 3446 if ((mask & IFCAP_RXCSUM) != 0 && 3447 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3448 ifp->if_capenable ^= IFCAP_RXCSUM; 3449 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3450 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3451 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3452 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3453 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3454 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3455 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3456 IFCAP_VLAN_HWTAGGING)) != 0) { 3457 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3458 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3459 ti_init_locked(sc); 3460 } 3461 } 3462 TI_UNLOCK(sc); 3463 VLAN_CAPABILITIES(ifp); 3464 break; 3465 default: 3466 error = ether_ioctl(ifp, command, data); 3467 break; 3468 } 3469 3470 return (error); 3471} 3472 3473static int 3474ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3475{ 3476 struct ti_softc *sc; 3477 3478 sc = dev->si_drv1; 3479 if (sc == NULL) 3480 return (ENODEV); 3481 3482 TI_LOCK(sc); 3483 sc->ti_flags |= TI_FLAG_DEBUGING; 3484 TI_UNLOCK(sc); 3485 3486 return (0); 3487} 3488 3489static int 3490ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3491{ 3492 struct ti_softc *sc; 3493 3494 sc = dev->si_drv1; 3495 if (sc == NULL) 3496 return (ENODEV); 3497 3498 TI_LOCK(sc); 3499 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3500 TI_UNLOCK(sc); 3501 3502 return (0); 3503} 3504 3505/* 3506 * This ioctl routine goes along with the Tigon character device. 3507 */ 3508static int 3509ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3510 struct thread *td) 3511{ 3512 struct ti_softc *sc; 3513 int error; 3514 3515 sc = dev->si_drv1; 3516 if (sc == NULL) 3517 return (ENODEV); 3518 3519 error = 0; 3520 3521 switch (cmd) { 3522 case TIIOCGETSTATS: 3523 { 3524 struct ti_stats *outstats; 3525 3526 outstats = (struct ti_stats *)addr; 3527 3528 TI_LOCK(sc); 3529 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3530 sizeof(struct ti_stats)); 3531 TI_UNLOCK(sc); 3532 break; 3533 } 3534 case TIIOCGETPARAMS: 3535 { 3536 struct ti_params *params; 3537 3538 params = (struct ti_params *)addr; 3539 3540 TI_LOCK(sc); 3541 params->ti_stat_ticks = sc->ti_stat_ticks; 3542 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3543 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3544 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3545 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3546 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3547 params->param_mask = TI_PARAM_ALL; 3548 TI_UNLOCK(sc); 3549 break; 3550 } 3551 case TIIOCSETPARAMS: 3552 { 3553 struct ti_params *params; 3554 3555 params = (struct ti_params *)addr; 3556 3557 TI_LOCK(sc); 3558 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3559 sc->ti_stat_ticks = params->ti_stat_ticks; 3560 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3561 } 3562 3563 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3564 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3565 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3566 sc->ti_rx_coal_ticks); 3567 } 3568 3569 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3570 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3571 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3572 sc->ti_tx_coal_ticks); 3573 } 3574 3575 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3576 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3577 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3578 sc->ti_rx_max_coal_bds); 3579 } 3580 3581 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3582 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3583 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3584 sc->ti_tx_max_coal_bds); 3585 } 3586 3587 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3588 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3589 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3590 sc->ti_tx_buf_ratio); 3591 } 3592 TI_UNLOCK(sc); 3593 break; 3594 } 3595 case TIIOCSETTRACE: { 3596 ti_trace_type trace_type; 3597 3598 trace_type = *(ti_trace_type *)addr; 3599 3600 /* 3601 * Set tracing to whatever the user asked for. Setting 3602 * this register to 0 should have the effect of disabling 3603 * tracing. 3604 */ 3605 TI_LOCK(sc); 3606 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3607 TI_UNLOCK(sc); 3608 break; 3609 } 3610 case TIIOCGETTRACE: { 3611 struct ti_trace_buf *trace_buf; 3612 uint32_t trace_start, cur_trace_ptr, trace_len; 3613 3614 trace_buf = (struct ti_trace_buf *)addr; 3615 3616 TI_LOCK(sc); 3617 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3618 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3619 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3620#if 0 3621 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3622 "trace_len = %d\n", trace_start, 3623 cur_trace_ptr, trace_len); 3624 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3625 trace_buf->buf_len); 3626#endif 3627 error = ti_copy_mem(sc, trace_start, min(trace_len, 3628 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3629 if (error == 0) { 3630 trace_buf->fill_len = min(trace_len, 3631 trace_buf->buf_len); 3632 if (cur_trace_ptr < trace_start) 3633 trace_buf->cur_trace_ptr = 3634 trace_start - cur_trace_ptr; 3635 else 3636 trace_buf->cur_trace_ptr = 3637 cur_trace_ptr - trace_start; 3638 } else 3639 trace_buf->fill_len = 0; 3640 TI_UNLOCK(sc); 3641 break; 3642 } 3643 3644 /* 3645 * For debugging, five ioctls are needed: 3646 * ALT_ATTACH 3647 * ALT_READ_TG_REG 3648 * ALT_WRITE_TG_REG 3649 * ALT_READ_TG_MEM 3650 * ALT_WRITE_TG_MEM 3651 */ 3652 case ALT_ATTACH: 3653 /* 3654 * From what I can tell, Alteon's Solaris Tigon driver 3655 * only has one character device, so you have to attach 3656 * to the Tigon board you're interested in. This seems 3657 * like a not-so-good way to do things, since unless you 3658 * subsequently specify the unit number of the device 3659 * you're interested in every ioctl, you'll only be 3660 * able to debug one board at a time. 3661 */ 3662 break; 3663 case ALT_READ_TG_MEM: 3664 case ALT_WRITE_TG_MEM: 3665 { 3666 struct tg_mem *mem_param; 3667 uint32_t sram_end, scratch_end; 3668 3669 mem_param = (struct tg_mem *)addr; 3670 3671 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3672 sram_end = TI_END_SRAM_I; 3673 scratch_end = TI_END_SCRATCH_I; 3674 } else { 3675 sram_end = TI_END_SRAM_II; 3676 scratch_end = TI_END_SCRATCH_II; 3677 } 3678 3679 /* 3680 * For now, we'll only handle accessing regular SRAM, 3681 * nothing else. 3682 */ 3683 TI_LOCK(sc); 3684 if (mem_param->tgAddr >= TI_BEG_SRAM && 3685 mem_param->tgAddr + mem_param->len <= sram_end) { 3686 /* 3687 * In this instance, we always copy to/from user 3688 * space, so the user space argument is set to 1. 3689 */ 3690 error = ti_copy_mem(sc, mem_param->tgAddr, 3691 mem_param->len, mem_param->userAddr, 1, 3692 cmd == ALT_READ_TG_MEM ? 1 : 0); 3693 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3694 mem_param->tgAddr <= scratch_end) { 3695 error = ti_copy_scratch(sc, mem_param->tgAddr, 3696 mem_param->len, mem_param->userAddr, 1, 3697 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3698 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3699 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3700 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3701 if_printf(sc->ti_ifp, 3702 "invalid memory range for Tigon I\n"); 3703 error = EINVAL; 3704 break; 3705 } 3706 error = ti_copy_scratch(sc, mem_param->tgAddr - 3707 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3708 mem_param->userAddr, 1, 3709 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3710 } else { 3711 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3712 "out of supported range\n", 3713 mem_param->tgAddr, mem_param->len); 3714 error = EINVAL; 3715 } 3716 TI_UNLOCK(sc); 3717 break; 3718 } 3719 case ALT_READ_TG_REG: 3720 case ALT_WRITE_TG_REG: 3721 { 3722 struct tg_reg *regs; 3723 uint32_t tmpval; 3724 3725 regs = (struct tg_reg *)addr; 3726 3727 /* 3728 * Make sure the address in question isn't out of range. 3729 */ 3730 if (regs->addr > TI_REG_MAX) { 3731 error = EINVAL; 3732 break; 3733 } 3734 TI_LOCK(sc); 3735 if (cmd == ALT_READ_TG_REG) { 3736 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3737 regs->addr, &tmpval, 1); 3738 regs->data = ntohl(tmpval); 3739#if 0 3740 if ((regs->addr == TI_CPU_STATE) 3741 || (regs->addr == TI_CPU_CTL_B)) { 3742 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3743 regs->addr, tmpval); 3744 } 3745#endif 3746 } else { 3747 tmpval = htonl(regs->data); 3748 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3749 regs->addr, &tmpval, 1); 3750 } 3751 TI_UNLOCK(sc); 3752 break; 3753 } 3754 default: 3755 error = ENOTTY; 3756 break; 3757 } 3758 return (error); 3759} 3760 3761static void 3762ti_watchdog(void *arg) 3763{ 3764 struct ti_softc *sc; 3765 struct ifnet *ifp; 3766 3767 sc = arg; 3768 TI_LOCK_ASSERT(sc); 3769 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3770 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3771 return; 3772 3773 /* 3774 * When we're debugging, the chip is often stopped for long periods 3775 * of time, and that would normally cause the watchdog timer to fire. 3776 * Since that impedes debugging, we don't want to do that. 3777 */ 3778 if (sc->ti_flags & TI_FLAG_DEBUGING) 3779 return; 3780 3781 ifp = sc->ti_ifp; 3782 if_printf(ifp, "watchdog timeout -- resetting\n"); 3783 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3784 ti_init_locked(sc); 3785 3786 ifp->if_oerrors++; 3787} 3788 3789/* 3790 * Stop the adapter and free any mbufs allocated to the 3791 * RX and TX lists. 3792 */ 3793static void 3794ti_stop(struct ti_softc *sc) 3795{ 3796 struct ifnet *ifp; 3797 struct ti_cmd_desc cmd; 3798 3799 TI_LOCK_ASSERT(sc); 3800 3801 ifp = sc->ti_ifp; 3802 3803 /* Disable host interrupts. */ 3804 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3805 /* 3806 * Tell firmware we're shutting down. 3807 */ 3808 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3809 3810 /* Halt and reinitialize. */ 3811 if (ti_chipinit(sc) == 0) { 3812 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3813 /* XXX ignore init errors. */ 3814 ti_chipinit(sc); 3815 } 3816 3817 /* Free the RX lists. */ 3818 ti_free_rx_ring_std(sc); 3819 3820 /* Free jumbo RX list. */ 3821 ti_free_rx_ring_jumbo(sc); 3822 3823 /* Free mini RX list. */ 3824 ti_free_rx_ring_mini(sc); 3825 3826 /* Free TX buffers. */ 3827 ti_free_tx_ring(sc); 3828 3829 sc->ti_ev_prodidx.ti_idx = 0; 3830 sc->ti_return_prodidx.ti_idx = 0; 3831 sc->ti_tx_considx.ti_idx = 0; 3832 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3833 3834 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3835 callout_stop(&sc->ti_watchdog); 3836} 3837 3838/* 3839 * Stop all chip I/O so that the kernel's probe routines don't 3840 * get confused by errant DMAs when rebooting. 3841 */ 3842static int 3843ti_shutdown(device_t dev) 3844{ 3845 struct ti_softc *sc; 3846 3847 sc = device_get_softc(dev); 3848 TI_LOCK(sc); 3849 ti_chipinit(sc); 3850 TI_UNLOCK(sc); 3851 3852 return (0); 3853} 3854 3855static void 3856ti_sysctl_node(struct ti_softc *sc) 3857{ 3858 struct sysctl_ctx_list *ctx; 3859 struct sysctl_oid_list *child; 3860 3861 ctx = device_get_sysctl_ctx(sc->ti_dev); 3862 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 3863 3864 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 3865 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 3866 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 3867 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 3868 3869 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 3870 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 3871 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 3872 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 3873 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 3874 &sc->ti_tx_buf_ratio, 0, 3875 "Ratio of NIC memory devoted to TX buffer"); 3876 3877 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 3878 &sc->ti_stat_ticks, 0, 3879 "Number of clock ticks for statistics update interval"); 3880 3881 /* Pull in device tunables. */ 3882 sc->ti_rx_coal_ticks = 170; 3883 resource_int_value(device_get_name(sc->ti_dev), 3884 device_get_unit(sc->ti_dev), "rx_coal_ticks", 3885 &sc->ti_rx_coal_ticks); 3886 sc->ti_rx_max_coal_bds = 64; 3887 resource_int_value(device_get_name(sc->ti_dev), 3888 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 3889 &sc->ti_rx_max_coal_bds); 3890 3891 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 3892 resource_int_value(device_get_name(sc->ti_dev), 3893 device_get_unit(sc->ti_dev), "tx_coal_ticks", 3894 &sc->ti_tx_coal_ticks); 3895 sc->ti_tx_max_coal_bds = 32; 3896 resource_int_value(device_get_name(sc->ti_dev), 3897 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 3898 &sc->ti_tx_max_coal_bds); 3899 sc->ti_tx_buf_ratio = 21; 3900 resource_int_value(device_get_name(sc->ti_dev), 3901 device_get_unit(sc->ti_dev), "tx_buf_ratio", 3902 &sc->ti_tx_buf_ratio); 3903 3904 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 3905 resource_int_value(device_get_name(sc->ti_dev), 3906 device_get_unit(sc->ti_dev), "stat_ticks", 3907 &sc->ti_stat_ticks); 3908} 3909