if_ti.c revision 162321
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 162321 2006-09-15 15:16:12Z glebius $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116#ifndef TI_PRIVATE_JUMBOS 117#include <vm/vm.h> 118#include <vm/vm_page.h> 119#endif 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123 124#include <sys/tiio.h> 125#include <dev/ti/if_tireg.h> 126#include <dev/ti/ti_fw.h> 127#include <dev/ti/ti_fw2.h> 128 129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130/* 131 * We can only turn on header splitting if we're using extended receive 132 * BDs. 133 */ 134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 137 138typedef enum { 139 TI_SWAP_HTON, 140 TI_SWAP_NTOH 141} ti_swap_type; 142 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static struct ti_type ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf **); 188 189static void ti_intr(void *); 190static void ti_start(struct ifnet *); 191static void ti_start_locked(struct ifnet *); 192static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193static void ti_init(void *); 194static void ti_init_locked(void *); 195static void ti_init2(struct ti_softc *); 196static void ti_stop(struct ti_softc *); 197static void ti_watchdog(struct ifnet *); 198static void ti_shutdown(device_t); 199static int ti_ifmedia_upd(struct ifnet *); 200static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 201 202static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 203static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 204static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 205 206static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 207static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 208static void ti_setmulti(struct ti_softc *); 209 210static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 211static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 212static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 213static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 214static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 215 int, int, int); 216static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 217static void ti_loadfw(struct ti_softc *); 218static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 219static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 220static void ti_handle_events(struct ti_softc *); 221static int ti_alloc_dmamaps(struct ti_softc *); 222static void ti_free_dmamaps(struct ti_softc *); 223static int ti_alloc_jumbo_mem(struct ti_softc *); 224#ifdef TI_PRIVATE_JUMBOS 225static void *ti_jalloc(struct ti_softc *); 226static void ti_jfree(void *, void *); 227#endif /* TI_PRIVATE_JUMBOS */ 228static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 229static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 230static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 231static int ti_init_rx_ring_std(struct ti_softc *); 232static void ti_free_rx_ring_std(struct ti_softc *); 233static int ti_init_rx_ring_jumbo(struct ti_softc *); 234static void ti_free_rx_ring_jumbo(struct ti_softc *); 235static int ti_init_rx_ring_mini(struct ti_softc *); 236static void ti_free_rx_ring_mini(struct ti_softc *); 237static void ti_free_tx_ring(struct ti_softc *); 238static int ti_init_tx_ring(struct ti_softc *); 239 240static int ti_64bitslot_war(struct ti_softc *); 241static int ti_chipinit(struct ti_softc *); 242static int ti_gibinit(struct ti_softc *); 243 244#ifdef TI_JUMBO_HDRSPLIT 245static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 246 int pkt_len, int idx); 247#endif /* TI_JUMBO_HDRSPLIT */ 248 249static device_method_t ti_methods[] = { 250 /* Device interface */ 251 DEVMETHOD(device_probe, ti_probe), 252 DEVMETHOD(device_attach, ti_attach), 253 DEVMETHOD(device_detach, ti_detach), 254 DEVMETHOD(device_shutdown, ti_shutdown), 255 { 0, 0 } 256}; 257 258static driver_t ti_driver = { 259 "ti", 260 ti_methods, 261 sizeof(struct ti_softc) 262}; 263 264static devclass_t ti_devclass; 265 266DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 267MODULE_DEPEND(ti, pci, 1, 1, 1); 268MODULE_DEPEND(ti, ether, 1, 1, 1); 269 270/* 271 * Send an instruction or address to the EEPROM, check for ACK. 272 */ 273static u_int32_t ti_eeprom_putbyte(sc, byte) 274 struct ti_softc *sc; 275 int byte; 276{ 277 int i, ack = 0; 278 279 /* 280 * Make sure we're in TX mode. 281 */ 282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x80; i; i >>= 1) { 288 if (byte & i) { 289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 290 } else { 291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 292 } 293 DELAY(1); 294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 295 DELAY(1); 296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 297 } 298 299 /* 300 * Turn off TX mode. 301 */ 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 303 304 /* 305 * Check for ack. 306 */ 307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 311 return (ack); 312} 313 314/* 315 * Read a byte of data stored in the EEPROM at address 'addr.' 316 * We have to send two address bytes since the EEPROM can hold 317 * more than 256 bytes of data. 318 */ 319static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 320 struct ti_softc *sc; 321 int addr; 322 u_int8_t *dest; 323{ 324 int i; 325 u_int8_t byte = 0; 326 327 EEPROM_START; 328 329 /* 330 * Send write control code to EEPROM. 331 */ 332 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 333 device_printf(sc->ti_dev, 334 "failed to send write command, status: %x\n", 335 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 336 return (1); 337 } 338 339 /* 340 * Send first byte of address of byte we want to read. 341 */ 342 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 343 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 344 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 345 return (1); 346 } 347 /* 348 * Send second byte address of byte we want to read. 349 */ 350 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 351 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 352 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 353 return (1); 354 } 355 356 EEPROM_STOP; 357 EEPROM_START; 358 /* 359 * Send read control code to EEPROM. 360 */ 361 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 362 device_printf(sc->ti_dev, 363 "failed to send read command, status: %x\n", 364 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 365 return (1); 366 } 367 368 /* 369 * Start reading bits from EEPROM. 370 */ 371 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 372 for (i = 0x80; i; i >>= 1) { 373 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 374 DELAY(1); 375 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 376 byte |= i; 377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 378 DELAY(1); 379 } 380 381 EEPROM_STOP; 382 383 /* 384 * No ACK generated for read, so just return byte. 385 */ 386 387 *dest = byte; 388 389 return (0); 390} 391 392/* 393 * Read a sequence of bytes from the EEPROM. 394 */ 395static int 396ti_read_eeprom(sc, dest, off, cnt) 397 struct ti_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401{ 402 int err = 0, i; 403 u_int8_t byte = 0; 404 405 for (i = 0; i < cnt; i++) { 406 err = ti_eeprom_getbyte(sc, off + i, &byte); 407 if (err) 408 break; 409 *(dest + i) = byte; 410 } 411 412 return (err ? 1 : 0); 413} 414 415/* 416 * NIC memory read function. 417 * Can be used to copy data from NIC local memory. 418 */ 419static void 420ti_mem_read(sc, addr, len, buf) 421 struct ti_softc *sc; 422 u_int32_t addr, len; 423 void *buf; 424{ 425 int segptr, segsize, cnt; 426 char *ptr; 427 428 segptr = addr; 429 cnt = len; 430 ptr = buf; 431 432 while (cnt) { 433 if (cnt < TI_WINLEN) 434 segsize = cnt; 435 else 436 segsize = TI_WINLEN - (segptr % TI_WINLEN); 437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 440 segsize / 4); 441 ptr += segsize; 442 segptr += segsize; 443 cnt -= segsize; 444 } 445} 446 447 448/* 449 * NIC memory write function. 450 * Can be used to copy data into NIC local memory. 451 */ 452static void 453ti_mem_write(sc, addr, len, buf) 454 struct ti_softc *sc; 455 u_int32_t addr, len; 456 void *buf; 457{ 458 int segptr, segsize, cnt; 459 char *ptr; 460 461 segptr = addr; 462 cnt = len; 463 ptr = buf; 464 465 while (cnt) { 466 if (cnt < TI_WINLEN) 467 segsize = cnt; 468 else 469 segsize = TI_WINLEN - (segptr % TI_WINLEN); 470 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 471 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 472 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 473 segsize / 4); 474 ptr += segsize; 475 segptr += segsize; 476 cnt -= segsize; 477 } 478} 479 480/* 481 * NIC memory read function. 482 * Can be used to clear a section of NIC local memory. 483 */ 484static void 485ti_mem_zero(sc, addr, len) 486 struct ti_softc *sc; 487 u_int32_t addr, len; 488{ 489 int segptr, segsize, cnt; 490 491 segptr = addr; 492 cnt = len; 493 494 while (cnt) { 495 if (cnt < TI_WINLEN) 496 segsize = cnt; 497 else 498 segsize = TI_WINLEN - (segptr % TI_WINLEN); 499 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 500 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 501 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 502 segptr += segsize; 503 cnt -= segsize; 504 } 505} 506 507static int 508ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 509 struct ti_softc *sc; 510 u_int32_t tigon_addr, len; 511 caddr_t buf; 512 int useraddr, readdata; 513{ 514 int segptr, segsize, cnt; 515 caddr_t ptr; 516 u_int32_t origwin; 517 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 518 int resid, segresid; 519 int first_pass; 520 521 TI_LOCK_ASSERT(sc); 522 523 /* 524 * At the moment, we don't handle non-aligned cases, we just bail. 525 * If this proves to be a problem, it will be fixed. 526 */ 527 if ((readdata == 0) 528 && (tigon_addr & 0x3)) { 529 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 530 "word-aligned\n", __func__, tigon_addr); 531 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 532 "yet supported\n", __func__); 533 return (EINVAL); 534 } 535 536 segptr = tigon_addr & ~0x3; 537 segresid = tigon_addr - segptr; 538 539 /* 540 * This is the non-aligned amount left over that we'll need to 541 * copy. 542 */ 543 resid = len & 0x3; 544 545 /* Add in the left over amount at the front of the buffer */ 546 resid += segresid; 547 548 cnt = len & ~0x3; 549 /* 550 * If resid + segresid is >= 4, add multiples of 4 to the count and 551 * decrease the residual by that much. 552 */ 553 cnt += resid & ~0x3; 554 resid -= resid & ~0x3; 555 556 ptr = buf; 557 558 first_pass = 1; 559 560 /* 561 * Save the old window base value. 562 */ 563 origwin = CSR_READ_4(sc, TI_WINBASE); 564 565 while (cnt) { 566 bus_size_t ti_offset; 567 568 if (cnt < TI_WINLEN) 569 segsize = cnt; 570 else 571 segsize = TI_WINLEN - (segptr % TI_WINLEN); 572 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 573 574 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 575 576 if (readdata) { 577 578 bus_space_read_region_4(sc->ti_btag, 579 sc->ti_bhandle, ti_offset, 580 (u_int32_t *)tmparray, 581 segsize >> 2); 582 if (useraddr) { 583 /* 584 * Yeah, this is a little on the kludgy 585 * side, but at least this code is only 586 * used for debugging. 587 */ 588 ti_bcopy_swap(tmparray, tmparray2, segsize, 589 TI_SWAP_NTOH); 590 591 TI_UNLOCK(sc); 592 if (first_pass) { 593 copyout(&tmparray2[segresid], ptr, 594 segsize - segresid); 595 first_pass = 0; 596 } else 597 copyout(tmparray2, ptr, segsize); 598 TI_LOCK(sc); 599 } else { 600 if (first_pass) { 601 602 ti_bcopy_swap(tmparray, tmparray2, 603 segsize, TI_SWAP_NTOH); 604 TI_UNLOCK(sc); 605 bcopy(&tmparray2[segresid], ptr, 606 segsize - segresid); 607 TI_LOCK(sc); 608 first_pass = 0; 609 } else 610 ti_bcopy_swap(tmparray, ptr, segsize, 611 TI_SWAP_NTOH); 612 } 613 614 } else { 615 if (useraddr) { 616 TI_UNLOCK(sc); 617 copyin(ptr, tmparray2, segsize); 618 TI_LOCK(sc); 619 ti_bcopy_swap(tmparray2, tmparray, segsize, 620 TI_SWAP_HTON); 621 } else 622 ti_bcopy_swap(ptr, tmparray, segsize, 623 TI_SWAP_HTON); 624 625 bus_space_write_region_4(sc->ti_btag, 626 sc->ti_bhandle, ti_offset, 627 (u_int32_t *)tmparray, 628 segsize >> 2); 629 } 630 segptr += segsize; 631 ptr += segsize; 632 cnt -= segsize; 633 } 634 635 /* 636 * Handle leftover, non-word-aligned bytes. 637 */ 638 if (resid != 0) { 639 u_int32_t tmpval, tmpval2; 640 bus_size_t ti_offset; 641 642 /* 643 * Set the segment pointer. 644 */ 645 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 646 647 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 648 649 /* 650 * First, grab whatever is in our source/destination. 651 * We'll obviously need this for reads, but also for 652 * writes, since we'll be doing read/modify/write. 653 */ 654 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 655 ti_offset, &tmpval, 1); 656 657 /* 658 * Next, translate this from little-endian to big-endian 659 * (at least on i386 boxes). 660 */ 661 tmpval2 = ntohl(tmpval); 662 663 if (readdata) { 664 /* 665 * If we're reading, just copy the leftover number 666 * of bytes from the host byte order buffer to 667 * the user's buffer. 668 */ 669 if (useraddr) { 670 TI_UNLOCK(sc); 671 copyout(&tmpval2, ptr, resid); 672 TI_LOCK(sc); 673 } else 674 bcopy(&tmpval2, ptr, resid); 675 } else { 676 /* 677 * If we're writing, first copy the bytes to be 678 * written into the network byte order buffer, 679 * leaving the rest of the buffer with whatever was 680 * originally in there. Then, swap the bytes 681 * around into host order and write them out. 682 * 683 * XXX KDM the read side of this has been verified 684 * to work, but the write side of it has not been 685 * verified. So user beware. 686 */ 687 if (useraddr) { 688 TI_UNLOCK(sc); 689 copyin(ptr, &tmpval2, resid); 690 TI_LOCK(sc); 691 } else 692 bcopy(ptr, &tmpval2, resid); 693 694 tmpval = htonl(tmpval2); 695 696 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 697 ti_offset, &tmpval, 1); 698 } 699 } 700 701 CSR_WRITE_4(sc, TI_WINBASE, origwin); 702 703 return (0); 704} 705 706static int 707ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 708 struct ti_softc *sc; 709 u_int32_t tigon_addr, len; 710 caddr_t buf; 711 int useraddr, readdata; 712 int cpu; 713{ 714 u_int32_t segptr; 715 int cnt; 716 u_int32_t tmpval, tmpval2; 717 caddr_t ptr; 718 719 TI_LOCK_ASSERT(sc); 720 721 /* 722 * At the moment, we don't handle non-aligned cases, we just bail. 723 * If this proves to be a problem, it will be fixed. 724 */ 725 if (tigon_addr & 0x3) { 726 device_printf(sc->ti_dev, "%s: tigon address %#x " 727 "isn't word-aligned\n", __func__, tigon_addr); 728 return (EINVAL); 729 } 730 731 if (len & 0x3) { 732 device_printf(sc->ti_dev, "%s: transfer length %d " 733 "isn't word-aligned\n", __func__, len); 734 return (EINVAL); 735 } 736 737 segptr = tigon_addr; 738 cnt = len; 739 ptr = buf; 740 741 while (cnt) { 742 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 743 744 if (readdata) { 745 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 746 747 tmpval = ntohl(tmpval2); 748 749 /* 750 * Note: I've used this debugging interface 751 * extensively with Alteon's 12.3.15 firmware, 752 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 753 * 754 * When you compile the firmware without 755 * optimization, which is necessary sometimes in 756 * order to properly step through it, you sometimes 757 * read out a bogus value of 0xc0017c instead of 758 * whatever was supposed to be in that scratchpad 759 * location. That value is on the stack somewhere, 760 * but I've never been able to figure out what was 761 * causing the problem. 762 * 763 * The address seems to pop up in random places, 764 * often not in the same place on two subsequent 765 * reads. 766 * 767 * In any case, the underlying data doesn't seem 768 * to be affected, just the value read out. 769 * 770 * KDM, 3/7/2000 771 */ 772 773 if (tmpval2 == 0xc0017c) 774 device_printf(sc->ti_dev, "found 0xc0017c at " 775 "%#x (tmpval2)\n", segptr); 776 777 if (tmpval == 0xc0017c) 778 device_printf(sc->ti_dev, "found 0xc0017c at " 779 "%#x (tmpval)\n", segptr); 780 781 if (useraddr) 782 copyout(&tmpval, ptr, 4); 783 else 784 bcopy(&tmpval, ptr, 4); 785 } else { 786 if (useraddr) 787 copyin(ptr, &tmpval2, 4); 788 else 789 bcopy(ptr, &tmpval2, 4); 790 791 tmpval = htonl(tmpval2); 792 793 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 794 } 795 796 cnt -= 4; 797 segptr += 4; 798 ptr += 4; 799 } 800 801 return (0); 802} 803 804static int 805ti_bcopy_swap(src, dst, len, swap_type) 806 const void *src; 807 void *dst; 808 size_t len; 809 ti_swap_type swap_type; 810{ 811 const u_int8_t *tmpsrc; 812 u_int8_t *tmpdst; 813 size_t tmplen; 814 815 if (len & 0x3) { 816 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 817 len); 818 return (-1); 819 } 820 821 tmpsrc = src; 822 tmpdst = dst; 823 tmplen = len; 824 825 while (tmplen) { 826 if (swap_type == TI_SWAP_NTOH) 827 *(u_int32_t *)tmpdst = 828 ntohl(*(const u_int32_t *)tmpsrc); 829 else 830 *(u_int32_t *)tmpdst = 831 htonl(*(const u_int32_t *)tmpsrc); 832 833 tmpsrc += 4; 834 tmpdst += 4; 835 tmplen -= 4; 836 } 837 838 return (0); 839} 840 841/* 842 * Load firmware image into the NIC. Check that the firmware revision 843 * is acceptable and see if we want the firmware for the Tigon 1 or 844 * Tigon 2. 845 */ 846static void 847ti_loadfw(sc) 848 struct ti_softc *sc; 849{ 850 851 TI_LOCK_ASSERT(sc); 852 853 switch (sc->ti_hwrev) { 854 case TI_HWREV_TIGON: 855 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 856 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 857 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 858 device_printf(sc->ti_dev, "firmware revision mismatch; " 859 "want %d.%d.%d, got %d.%d.%d\n", 860 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 861 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 862 tigonFwReleaseMinor, tigonFwReleaseFix); 863 return; 864 } 865 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 866 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 867 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 868 tigonFwRodata); 869 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 870 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 871 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 872 break; 873 case TI_HWREV_TIGON_II: 874 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 875 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 876 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 877 device_printf(sc->ti_dev, "firmware revision mismatch; " 878 "want %d.%d.%d, got %d.%d.%d\n", 879 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 880 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 881 tigon2FwReleaseMinor, tigon2FwReleaseFix); 882 return; 883 } 884 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 885 tigon2FwText); 886 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 887 tigon2FwData); 888 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 889 tigon2FwRodata); 890 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 891 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 892 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 893 break; 894 default: 895 device_printf(sc->ti_dev, 896 "can't load firmware: unknown hardware rev\n"); 897 break; 898 } 899} 900 901/* 902 * Send the NIC a command via the command ring. 903 */ 904static void 905ti_cmd(sc, cmd) 906 struct ti_softc *sc; 907 struct ti_cmd_desc *cmd; 908{ 909 int index; 910 911 index = sc->ti_cmd_saved_prodidx; 912 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 913 TI_INC(index, TI_CMD_RING_CNT); 914 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 915 sc->ti_cmd_saved_prodidx = index; 916} 917 918/* 919 * Send the NIC an extended command. The 'len' parameter specifies the 920 * number of command slots to include after the initial command. 921 */ 922static void 923ti_cmd_ext(sc, cmd, arg, len) 924 struct ti_softc *sc; 925 struct ti_cmd_desc *cmd; 926 caddr_t arg; 927 int len; 928{ 929 int index; 930 int i; 931 932 index = sc->ti_cmd_saved_prodidx; 933 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 934 TI_INC(index, TI_CMD_RING_CNT); 935 for (i = 0; i < len; i++) { 936 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 937 *(u_int32_t *)(&arg[i * 4])); 938 TI_INC(index, TI_CMD_RING_CNT); 939 } 940 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 941 sc->ti_cmd_saved_prodidx = index; 942} 943 944/* 945 * Handle events that have triggered interrupts. 946 */ 947static void 948ti_handle_events(sc) 949 struct ti_softc *sc; 950{ 951 struct ti_event_desc *e; 952 953 if (sc->ti_rdata->ti_event_ring == NULL) 954 return; 955 956 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 957 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 958 switch (TI_EVENT_EVENT(e)) { 959 case TI_EV_LINKSTAT_CHANGED: 960 sc->ti_linkstat = TI_EVENT_CODE(e); 961 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 962 device_printf(sc->ti_dev, "10/100 link up\n"); 963 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 964 device_printf(sc->ti_dev, "gigabit link up\n"); 965 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 966 device_printf(sc->ti_dev, "link down\n"); 967 break; 968 case TI_EV_ERROR: 969 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 970 device_printf(sc->ti_dev, "invalid command\n"); 971 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 972 device_printf(sc->ti_dev, "unknown command\n"); 973 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 974 device_printf(sc->ti_dev, "bad config data\n"); 975 break; 976 case TI_EV_FIRMWARE_UP: 977 ti_init2(sc); 978 break; 979 case TI_EV_STATS_UPDATED: 980 ti_stats_update(sc); 981 break; 982 case TI_EV_RESET_JUMBO_RING: 983 case TI_EV_MCAST_UPDATED: 984 /* Who cares. */ 985 break; 986 default: 987 device_printf(sc->ti_dev, "unknown event: %d\n", 988 TI_EVENT_EVENT(e)); 989 break; 990 } 991 /* Advance the consumer index. */ 992 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 993 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 994 } 995} 996 997static int 998ti_alloc_dmamaps(struct ti_softc *sc) 999{ 1000 int i; 1001 1002 for (i = 0; i < TI_TX_RING_CNT; i++) { 1003 sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 1004 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1005 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006 &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) 1007 return (ENOBUFS); 1008 } 1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011 &sc->ti_cdata.ti_rx_std_maps[i])) 1012 return (ENOBUFS); 1013 } 1014 1015 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018 return (ENOBUFS); 1019 } 1020 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022 &sc->ti_cdata.ti_rx_mini_maps[i])) 1023 return (ENOBUFS); 1024 } 1025 1026 return (0); 1027} 1028 1029static void 1030ti_free_dmamaps(struct ti_softc *sc) 1031{ 1032 int i; 1033 1034 if (sc->ti_mbuftx_dmat) 1035 for (i = 0; i < TI_TX_RING_CNT; i++) 1036 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1037 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1039 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1040 } 1041 1042 if (sc->ti_mbufrx_dmat) 1043 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046 sc->ti_cdata.ti_rx_std_maps[i]); 1047 sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048 } 1049 1050 if (sc->ti_jumbo_dmat) 1051 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056 } 1057 if (sc->ti_mbufrx_dmat) 1058 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061 sc->ti_cdata.ti_rx_mini_maps[i]); 1062 sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063 } 1064} 1065 1066#ifdef TI_PRIVATE_JUMBOS 1067 1068/* 1069 * Memory management for the jumbo receive ring is a pain in the 1070 * butt. We need to allocate at least 9018 bytes of space per frame, 1071 * _and_ it has to be contiguous (unless you use the extended 1072 * jumbo descriptor format). Using malloc() all the time won't 1073 * work: malloc() allocates memory in powers of two, which means we 1074 * would end up wasting a considerable amount of space by allocating 1075 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1076 * to do our own memory management. 1077 * 1078 * The driver needs to allocate a contiguous chunk of memory at boot 1079 * time. We then chop this up ourselves into 9K pieces and use them 1080 * as external mbuf storage. 1081 * 1082 * One issue here is how much memory to allocate. The jumbo ring has 1083 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1084 * RAM. This is a bit much, especially considering we also need 1085 * RAM for the standard ring and mini ring (on the Tigon 2). To 1086 * save space, we only actually allocate enough memory for 64 slots 1087 * by default, which works out to between 500 and 600K. This can 1088 * be tuned by changing a #define in if_tireg.h. 1089 */ 1090 1091static int 1092ti_alloc_jumbo_mem(sc) 1093 struct ti_softc *sc; 1094{ 1095 caddr_t ptr; 1096 int i; 1097 struct ti_jpool_entry *entry; 1098 1099 /* 1100 * Grab a big chunk o' storage. Since we are chopping this pool up 1101 * into ~9k chunks, there doesn't appear to be a need to use page 1102 * alignment. 1103 */ 1104 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105 1, 0, /* algnmnt, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 TI_JMEM, /* maxsize */ 1110 1, /* nsegments */ 1111 TI_JMEM, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ti_jumbo_dmat) != 0) { 1115 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116 return (ENOBUFS); 1117 } 1118 1119 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120 (void**)&sc->ti_cdata.ti_jumbo_buf, 1121 BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) { 1122 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1123 return (ENOBUFS); 1124 } 1125 1126 SLIST_INIT(&sc->ti_jfree_listhead); 1127 SLIST_INIT(&sc->ti_jinuse_listhead); 1128 1129 /* 1130 * Now divide it up into 9K pieces and save the addresses 1131 * in an array. 1132 */ 1133 ptr = sc->ti_cdata.ti_jumbo_buf; 1134 for (i = 0; i < TI_JSLOTS; i++) { 1135 sc->ti_cdata.ti_jslots[i] = ptr; 1136 ptr += TI_JLEN; 1137 entry = malloc(sizeof(struct ti_jpool_entry), 1138 M_DEVBUF, M_NOWAIT); 1139 if (entry == NULL) { 1140 device_printf(sc->ti_dev, "no memory for jumbo " 1141 "buffer queue!\n"); 1142 return (ENOBUFS); 1143 } 1144 entry->slot = i; 1145 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1146 } 1147 1148 return (0); 1149} 1150 1151/* 1152 * Allocate a jumbo buffer. 1153 */ 1154static void *ti_jalloc(sc) 1155 struct ti_softc *sc; 1156{ 1157 struct ti_jpool_entry *entry; 1158 1159 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1160 1161 if (entry == NULL) { 1162 device_printf(sc->ti_dev, "no free jumbo buffers\n"); 1163 return (NULL); 1164 } 1165 1166 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1167 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1168 return (sc->ti_cdata.ti_jslots[entry->slot]); 1169} 1170 1171/* 1172 * Release a jumbo buffer. 1173 */ 1174static void 1175ti_jfree(buf, args) 1176 void *buf; 1177 void *args; 1178{ 1179 struct ti_softc *sc; 1180 int i; 1181 struct ti_jpool_entry *entry; 1182 1183 /* Extract the softc struct pointer. */ 1184 sc = (struct ti_softc *)args; 1185 1186 if (sc == NULL) 1187 panic("ti_jfree: didn't get softc pointer!"); 1188 1189 /* calculate the slot this buffer belongs to */ 1190 i = ((vm_offset_t)buf 1191 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1192 1193 if ((i < 0) || (i >= TI_JSLOTS)) 1194 panic("ti_jfree: asked to free buffer that we don't manage!"); 1195 1196 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1197 if (entry == NULL) 1198 panic("ti_jfree: buffer not in use!"); 1199 entry->slot = i; 1200 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1201 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1202} 1203 1204#else 1205 1206static int 1207ti_alloc_jumbo_mem(sc) 1208 struct ti_softc *sc; 1209{ 1210 1211 /* 1212 * The VM system will take care of providing aligned pages. Alignment 1213 * is set to 1 here so that busdma resources won't be wasted. 1214 */ 1215 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1216 1, 0, /* algnmnt, boundary */ 1217 BUS_SPACE_MAXADDR, /* lowaddr */ 1218 BUS_SPACE_MAXADDR, /* highaddr */ 1219 NULL, NULL, /* filter, filterarg */ 1220 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1221 4, /* nsegments */ 1222 PAGE_SIZE, /* maxsegsize */ 1223 0, /* flags */ 1224 NULL, NULL, /* lockfunc, lockarg */ 1225 &sc->ti_jumbo_dmat) != 0) { 1226 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1227 return (ENOBUFS); 1228 } 1229 1230 return (0); 1231} 1232 1233#endif /* TI_PRIVATE_JUMBOS */ 1234 1235/* 1236 * Intialize a standard receive ring descriptor. 1237 */ 1238static int 1239ti_newbuf_std(sc, i, m) 1240 struct ti_softc *sc; 1241 int i; 1242 struct mbuf *m; 1243{ 1244 bus_dmamap_t map; 1245 bus_dma_segment_t segs; 1246 struct mbuf *m_new = NULL; 1247 struct ti_rx_desc *r; 1248 int nsegs; 1249 1250 nsegs = 0; 1251 if (m == NULL) { 1252 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1253 if (m_new == NULL) 1254 return (ENOBUFS); 1255 1256 MCLGET(m_new, M_DONTWAIT); 1257 if (!(m_new->m_flags & M_EXT)) { 1258 m_freem(m_new); 1259 return (ENOBUFS); 1260 } 1261 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1262 } else { 1263 m_new = m; 1264 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1265 m_new->m_data = m_new->m_ext.ext_buf; 1266 } 1267 1268 m_adj(m_new, ETHER_ALIGN); 1269 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1270 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1271 map = sc->ti_cdata.ti_rx_std_maps[i]; 1272 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1273 &nsegs, 0)) 1274 return (ENOBUFS); 1275 if (nsegs != 1) 1276 return (ENOBUFS); 1277 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1278 r->ti_len = segs.ds_len; 1279 r->ti_type = TI_BDTYPE_RECV_BD; 1280 r->ti_flags = 0; 1281 if (sc->ti_ifp->if_hwassist) 1282 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1283 r->ti_idx = i; 1284 1285 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1286 return (0); 1287} 1288 1289/* 1290 * Intialize a mini receive ring descriptor. This only applies to 1291 * the Tigon 2. 1292 */ 1293static int 1294ti_newbuf_mini(sc, i, m) 1295 struct ti_softc *sc; 1296 int i; 1297 struct mbuf *m; 1298{ 1299 bus_dma_segment_t segs; 1300 bus_dmamap_t map; 1301 struct mbuf *m_new = NULL; 1302 struct ti_rx_desc *r; 1303 int nsegs; 1304 1305 nsegs = 0; 1306 if (m == NULL) { 1307 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1308 if (m_new == NULL) { 1309 return (ENOBUFS); 1310 } 1311 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1312 } else { 1313 m_new = m; 1314 m_new->m_data = m_new->m_pktdat; 1315 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1316 } 1317 1318 m_adj(m_new, ETHER_ALIGN); 1319 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1320 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1321 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1322 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1323 &nsegs, 0)) 1324 return (ENOBUFS); 1325 if (nsegs != 1) 1326 return (ENOBUFS); 1327 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1328 r->ti_len = segs.ds_len; 1329 r->ti_type = TI_BDTYPE_RECV_BD; 1330 r->ti_flags = TI_BDFLAG_MINI_RING; 1331 if (sc->ti_ifp->if_hwassist) 1332 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1333 r->ti_idx = i; 1334 1335 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1336 return (0); 1337} 1338 1339#ifdef TI_PRIVATE_JUMBOS 1340 1341/* 1342 * Initialize a jumbo receive ring descriptor. This allocates 1343 * a jumbo buffer from the pool managed internally by the driver. 1344 */ 1345static int 1346ti_newbuf_jumbo(sc, i, m) 1347 struct ti_softc *sc; 1348 int i; 1349 struct mbuf *m; 1350{ 1351 bus_dmamap_t map; 1352 struct mbuf *m_new = NULL; 1353 struct ti_rx_desc *r; 1354 int nsegs; 1355 bus_dma_segment_t segs; 1356 1357 if (m == NULL) { 1358 caddr_t *buf = NULL; 1359 1360 /* Allocate the mbuf. */ 1361 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1362 if (m_new == NULL) { 1363 return (ENOBUFS); 1364 } 1365 1366 /* Allocate the jumbo buffer */ 1367 buf = ti_jalloc(sc); 1368 if (buf == NULL) { 1369 m_freem(m_new); 1370 device_printf(sc->ti_dev, "jumbo allocation failed " 1371 "-- packet dropped!\n"); 1372 return (ENOBUFS); 1373 } 1374 1375 /* Attach the buffer to the mbuf. */ 1376 m_new->m_data = (void *) buf; 1377 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1378 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1379 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1380 } else { 1381 m_new = m; 1382 m_new->m_data = m_new->m_ext.ext_buf; 1383 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1384 } 1385 1386 m_adj(m_new, ETHER_ALIGN); 1387 /* Set up the descriptor. */ 1388 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1389 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1390 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1391 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1392 &nsegs, 0)) 1393 return (ENOBUFS); 1394 if (nsegs != 1) 1395 return (ENOBUFS); 1396 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1397 r->ti_len = segs.ds_len; 1398 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1399 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1400 if (sc->ti_ifp->if_hwassist) 1401 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1402 r->ti_idx = i; 1403 1404 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1405 return (0); 1406} 1407 1408#else 1409 1410#if (PAGE_SIZE == 4096) 1411#define NPAYLOAD 2 1412#else 1413#define NPAYLOAD 1 1414#endif 1415 1416#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1417#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1418#define NFS_HDR_LEN (UDP_HDR_LEN) 1419static int HDR_LEN = TCP_HDR_LEN; 1420 1421 1422/* 1423 * Initialize a jumbo receive ring descriptor. This allocates 1424 * a jumbo buffer from the pool managed internally by the driver. 1425 */ 1426static int 1427ti_newbuf_jumbo(sc, idx, m_old) 1428 struct ti_softc *sc; 1429 int idx; 1430 struct mbuf *m_old; 1431{ 1432 bus_dmamap_t map; 1433 struct mbuf *cur, *m_new = NULL; 1434 struct mbuf *m[3] = {NULL, NULL, NULL}; 1435 struct ti_rx_desc_ext *r; 1436 vm_page_t frame; 1437 static int color; 1438 /* 1 extra buf to make nobufs easy*/ 1439 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1440 int i; 1441 bus_dma_segment_t segs[4]; 1442 int nsegs; 1443 1444 if (m_old != NULL) { 1445 m_new = m_old; 1446 cur = m_old->m_next; 1447 for (i = 0; i <= NPAYLOAD; i++){ 1448 m[i] = cur; 1449 cur = cur->m_next; 1450 } 1451 } else { 1452 /* Allocate the mbufs. */ 1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1454 if (m_new == NULL) { 1455 device_printf(sc->ti_dev, "mbuf allocation failed " 1456 "-- packet dropped!\n"); 1457 goto nobufs; 1458 } 1459 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1460 if (m[NPAYLOAD] == NULL) { 1461 device_printf(sc->ti_dev, "cluster mbuf allocation " 1462 "failed -- packet dropped!\n"); 1463 goto nobufs; 1464 } 1465 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1466 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1467 device_printf(sc->ti_dev, "mbuf allocation failed " 1468 "-- packet dropped!\n"); 1469 goto nobufs; 1470 } 1471 m[NPAYLOAD]->m_len = MCLBYTES; 1472 1473 for (i = 0; i < NPAYLOAD; i++){ 1474 MGET(m[i], M_DONTWAIT, MT_DATA); 1475 if (m[i] == NULL) { 1476 device_printf(sc->ti_dev, "mbuf allocation " 1477 "failed -- packet dropped!\n"); 1478 goto nobufs; 1479 } 1480 frame = vm_page_alloc(NULL, color++, 1481 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1482 VM_ALLOC_WIRED); 1483 if (frame == NULL) { 1484 device_printf(sc->ti_dev, "buffer allocation " 1485 "failed -- packet dropped!\n"); 1486 printf(" index %d page %d\n", idx, i); 1487 goto nobufs; 1488 } 1489 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1490 if (sf[i] == NULL) { 1491 vm_page_lock_queues(); 1492 vm_page_unwire(frame, 0); 1493 vm_page_free(frame); 1494 vm_page_unlock_queues(); 1495 device_printf(sc->ti_dev, "buffer allocation " 1496 "failed -- packet dropped!\n"); 1497 printf(" index %d page %d\n", idx, i); 1498 goto nobufs; 1499 } 1500 } 1501 for (i = 0; i < NPAYLOAD; i++){ 1502 /* Attach the buffer to the mbuf. */ 1503 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1504 m[i]->m_len = PAGE_SIZE; 1505 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1506 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 1507 m[i]->m_next = m[i+1]; 1508 } 1509 /* link the buffers to the header */ 1510 m_new->m_next = m[0]; 1511 m_new->m_data += ETHER_ALIGN; 1512 if (sc->ti_hdrsplit) 1513 m_new->m_len = MHLEN - ETHER_ALIGN; 1514 else 1515 m_new->m_len = HDR_LEN; 1516 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1517 } 1518 1519 /* Set up the descriptor. */ 1520 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1521 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1522 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1523 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1524 &nsegs, 0)) 1525 return (ENOBUFS); 1526 if ((nsegs < 1) || (nsegs > 4)) 1527 return (ENOBUFS); 1528 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1529 r->ti_len0 = m_new->m_len; 1530 1531 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1532 r->ti_len1 = PAGE_SIZE; 1533 1534 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1535 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1536 1537 if (PAGE_SIZE == 4096) { 1538 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1539 r->ti_len3 = MCLBYTES; 1540 } else { 1541 r->ti_len3 = 0; 1542 } 1543 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1544 1545 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1546 1547 if (sc->ti_ifp->if_hwassist) 1548 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1549 1550 r->ti_idx = idx; 1551 1552 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1553 return (0); 1554 1555nobufs: 1556 1557 /* 1558 * Warning! : 1559 * This can only be called before the mbufs are strung together. 1560 * If the mbufs are strung together, m_freem() will free the chain, 1561 * so that the later mbufs will be freed multiple times. 1562 */ 1563 if (m_new) 1564 m_freem(m_new); 1565 1566 for (i = 0; i < 3; i++) { 1567 if (m[i]) 1568 m_freem(m[i]); 1569 if (sf[i]) 1570 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1571 } 1572 return (ENOBUFS); 1573} 1574#endif 1575 1576 1577 1578/* 1579 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1580 * that's 1MB or memory, which is a lot. For now, we fill only the first 1581 * 256 ring entries and hope that our CPU is fast enough to keep up with 1582 * the NIC. 1583 */ 1584static int 1585ti_init_rx_ring_std(sc) 1586 struct ti_softc *sc; 1587{ 1588 int i; 1589 struct ti_cmd_desc cmd; 1590 1591 for (i = 0; i < TI_SSLOTS; i++) { 1592 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1593 return (ENOBUFS); 1594 }; 1595 1596 TI_UPDATE_STDPROD(sc, i - 1); 1597 sc->ti_std = i - 1; 1598 1599 return (0); 1600} 1601 1602static void 1603ti_free_rx_ring_std(sc) 1604 struct ti_softc *sc; 1605{ 1606 bus_dmamap_t map; 1607 int i; 1608 1609 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1610 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1611 map = sc->ti_cdata.ti_rx_std_maps[i]; 1612 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1613 BUS_DMASYNC_POSTREAD); 1614 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1615 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1616 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1617 } 1618 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1619 sizeof(struct ti_rx_desc)); 1620 } 1621} 1622 1623static int 1624ti_init_rx_ring_jumbo(sc) 1625 struct ti_softc *sc; 1626{ 1627 int i; 1628 struct ti_cmd_desc cmd; 1629 1630 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1631 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1632 return (ENOBUFS); 1633 }; 1634 1635 TI_UPDATE_JUMBOPROD(sc, i - 1); 1636 sc->ti_jumbo = i - 1; 1637 1638 return (0); 1639} 1640 1641static void 1642ti_free_rx_ring_jumbo(sc) 1643 struct ti_softc *sc; 1644{ 1645 bus_dmamap_t map; 1646 int i; 1647 1648 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1649 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1650 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1651 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1652 BUS_DMASYNC_POSTREAD); 1653 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1654 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1655 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1656 } 1657 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1658 sizeof(struct ti_rx_desc)); 1659 } 1660} 1661 1662static int 1663ti_init_rx_ring_mini(sc) 1664 struct ti_softc *sc; 1665{ 1666 int i; 1667 1668 for (i = 0; i < TI_MSLOTS; i++) { 1669 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1670 return (ENOBUFS); 1671 }; 1672 1673 TI_UPDATE_MINIPROD(sc, i - 1); 1674 sc->ti_mini = i - 1; 1675 1676 return (0); 1677} 1678 1679static void 1680ti_free_rx_ring_mini(sc) 1681 struct ti_softc *sc; 1682{ 1683 bus_dmamap_t map; 1684 int i; 1685 1686 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1687 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1688 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1689 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1690 BUS_DMASYNC_POSTREAD); 1691 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1692 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1693 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1694 } 1695 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1696 sizeof(struct ti_rx_desc)); 1697 } 1698} 1699 1700static void 1701ti_free_tx_ring(sc) 1702 struct ti_softc *sc; 1703{ 1704 struct ti_txdesc *txd; 1705 int i; 1706 1707 if (sc->ti_rdata->ti_tx_ring == NULL) 1708 return; 1709 1710 for (i = 0; i < TI_TX_RING_CNT; i++) { 1711 txd = &sc->ti_cdata.ti_txdesc[i]; 1712 if (txd->tx_m != NULL) { 1713 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1716 m_freem(txd->tx_m); 1717 txd->tx_m = NULL; 1718 } 1719 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1720 sizeof(struct ti_tx_desc)); 1721 } 1722} 1723 1724static int 1725ti_init_tx_ring(sc) 1726 struct ti_softc *sc; 1727{ 1728 struct ti_txdesc *txd; 1729 int i; 1730 1731 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1732 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1733 for (i = 0; i < TI_TX_RING_CNT; i++) { 1734 txd = &sc->ti_cdata.ti_txdesc[i]; 1735 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1736 } 1737 sc->ti_txcnt = 0; 1738 sc->ti_tx_saved_considx = 0; 1739 sc->ti_tx_saved_prodidx = 0; 1740 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1741 return (0); 1742} 1743 1744/* 1745 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1746 * but we have to support the old way too so that Tigon 1 cards will 1747 * work. 1748 */ 1749static void 1750ti_add_mcast(sc, addr) 1751 struct ti_softc *sc; 1752 struct ether_addr *addr; 1753{ 1754 struct ti_cmd_desc cmd; 1755 u_int16_t *m; 1756 u_int32_t ext[2] = {0, 0}; 1757 1758 m = (u_int16_t *)&addr->octet[0]; 1759 1760 switch (sc->ti_hwrev) { 1761 case TI_HWREV_TIGON: 1762 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1763 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1764 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1765 break; 1766 case TI_HWREV_TIGON_II: 1767 ext[0] = htons(m[0]); 1768 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1769 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1770 break; 1771 default: 1772 device_printf(sc->ti_dev, "unknown hwrev\n"); 1773 break; 1774 } 1775} 1776 1777static void 1778ti_del_mcast(sc, addr) 1779 struct ti_softc *sc; 1780 struct ether_addr *addr; 1781{ 1782 struct ti_cmd_desc cmd; 1783 u_int16_t *m; 1784 u_int32_t ext[2] = {0, 0}; 1785 1786 m = (u_int16_t *)&addr->octet[0]; 1787 1788 switch (sc->ti_hwrev) { 1789 case TI_HWREV_TIGON: 1790 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1791 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1792 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1793 break; 1794 case TI_HWREV_TIGON_II: 1795 ext[0] = htons(m[0]); 1796 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1797 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1798 break; 1799 default: 1800 device_printf(sc->ti_dev, "unknown hwrev\n"); 1801 break; 1802 } 1803} 1804 1805/* 1806 * Configure the Tigon's multicast address filter. 1807 * 1808 * The actual multicast table management is a bit of a pain, thanks to 1809 * slight brain damage on the part of both Alteon and us. With our 1810 * multicast code, we are only alerted when the multicast address table 1811 * changes and at that point we only have the current list of addresses: 1812 * we only know the current state, not the previous state, so we don't 1813 * actually know what addresses were removed or added. The firmware has 1814 * state, but we can't get our grubby mits on it, and there is no 'delete 1815 * all multicast addresses' command. Hence, we have to maintain our own 1816 * state so we know what addresses have been programmed into the NIC at 1817 * any given time. 1818 */ 1819static void 1820ti_setmulti(sc) 1821 struct ti_softc *sc; 1822{ 1823 struct ifnet *ifp; 1824 struct ifmultiaddr *ifma; 1825 struct ti_cmd_desc cmd; 1826 struct ti_mc_entry *mc; 1827 u_int32_t intrs; 1828 1829 TI_LOCK_ASSERT(sc); 1830 1831 ifp = sc->ti_ifp; 1832 1833 if (ifp->if_flags & IFF_ALLMULTI) { 1834 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1835 return; 1836 } else { 1837 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1838 } 1839 1840 /* Disable interrupts. */ 1841 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1842 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1843 1844 /* First, zot all the existing filters. */ 1845 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1846 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1847 ti_del_mcast(sc, &mc->mc_addr); 1848 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1849 free(mc, M_DEVBUF); 1850 } 1851 1852 /* Now program new ones. */ 1853 IF_ADDR_LOCK(ifp); 1854 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1855 if (ifma->ifma_addr->sa_family != AF_LINK) 1856 continue; 1857 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1858 if (mc == NULL) { 1859 device_printf(sc->ti_dev, 1860 "no memory for mcast filter entry\n"); 1861 continue; 1862 } 1863 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1864 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1865 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1866 ti_add_mcast(sc, &mc->mc_addr); 1867 } 1868 IF_ADDR_UNLOCK(ifp); 1869 1870 /* Re-enable interrupts. */ 1871 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1872} 1873 1874/* 1875 * Check to see if the BIOS has configured us for a 64 bit slot when 1876 * we aren't actually in one. If we detect this condition, we can work 1877 * around it on the Tigon 2 by setting a bit in the PCI state register, 1878 * but for the Tigon 1 we must give up and abort the interface attach. 1879 */ 1880static int ti_64bitslot_war(sc) 1881 struct ti_softc *sc; 1882{ 1883 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1884 CSR_WRITE_4(sc, 0x600, 0); 1885 CSR_WRITE_4(sc, 0x604, 0); 1886 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1887 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1888 if (sc->ti_hwrev == TI_HWREV_TIGON) 1889 return (EINVAL); 1890 else { 1891 TI_SETBIT(sc, TI_PCI_STATE, 1892 TI_PCISTATE_32BIT_BUS); 1893 return (0); 1894 } 1895 } 1896 } 1897 1898 return (0); 1899} 1900 1901/* 1902 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1903 * self-test results. 1904 */ 1905static int 1906ti_chipinit(sc) 1907 struct ti_softc *sc; 1908{ 1909 u_int32_t cacheline; 1910 u_int32_t pci_writemax = 0; 1911 u_int32_t hdrsplit; 1912 1913 /* Initialize link to down state. */ 1914 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1915 1916 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1917 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1918 else 1919 sc->ti_ifp->if_hwassist = 0; 1920 1921 /* Set endianness before we access any non-PCI registers. */ 1922#if 0 && BYTE_ORDER == BIG_ENDIAN 1923 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1924 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1925#else 1926 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1927 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1928#endif 1929 1930 /* Check the ROM failed bit to see if self-tests passed. */ 1931 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1932 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1933 return (ENODEV); 1934 } 1935 1936 /* Halt the CPU. */ 1937 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1938 1939 /* Figure out the hardware revision. */ 1940 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1941 case TI_REV_TIGON_I: 1942 sc->ti_hwrev = TI_HWREV_TIGON; 1943 break; 1944 case TI_REV_TIGON_II: 1945 sc->ti_hwrev = TI_HWREV_TIGON_II; 1946 break; 1947 default: 1948 device_printf(sc->ti_dev, "unsupported chip revision\n"); 1949 return (ENODEV); 1950 } 1951 1952 /* Do special setup for Tigon 2. */ 1953 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1954 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1955 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1956 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1957 } 1958 1959 /* 1960 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1961 * can't do header splitting. 1962 */ 1963#ifdef TI_JUMBO_HDRSPLIT 1964 if (sc->ti_hwrev != TI_HWREV_TIGON) 1965 sc->ti_hdrsplit = 1; 1966 else 1967 device_printf(sc->ti_dev, 1968 "can't do header splitting on a Tigon I board\n"); 1969#endif /* TI_JUMBO_HDRSPLIT */ 1970 1971 /* Set up the PCI state register. */ 1972 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1973 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1974 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1975 } 1976 1977 /* Clear the read/write max DMA parameters. */ 1978 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1979 TI_PCISTATE_READ_MAXDMA)); 1980 1981 /* Get cache line size. */ 1982 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1983 1984 /* 1985 * If the system has set enabled the PCI memory write 1986 * and invalidate command in the command register, set 1987 * the write max parameter accordingly. This is necessary 1988 * to use MWI with the Tigon 2. 1989 */ 1990 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1991 switch (cacheline) { 1992 case 1: 1993 case 4: 1994 case 8: 1995 case 16: 1996 case 32: 1997 case 64: 1998 break; 1999 default: 2000 /* Disable PCI memory write and invalidate. */ 2001 if (bootverbose) 2002 device_printf(sc->ti_dev, "cache line size %d" 2003 " not supported; disabling PCI MWI\n", 2004 cacheline); 2005 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2006 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2007 break; 2008 } 2009 } 2010 2011#ifdef __brokenalpha__ 2012 /* 2013 * From the Alteon sample driver: 2014 * Must insure that we do not cross an 8K (bytes) boundary 2015 * for DMA reads. Our highest limit is 1K bytes. This is a 2016 * restriction on some ALPHA platforms with early revision 2017 * 21174 PCI chipsets, such as the AlphaPC 164lx 2018 */ 2019 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 2020#else 2021 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2022#endif 2023 2024 /* This sets the min dma param all the way up (0xff). */ 2025 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2026 2027 if (sc->ti_hdrsplit) 2028 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2029 else 2030 hdrsplit = 0; 2031 2032 /* Configure DMA variables. */ 2033#if BYTE_ORDER == BIG_ENDIAN 2034 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2035 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2036 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2037 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2038#else /* BYTE_ORDER */ 2039 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2040 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2041 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2042#endif /* BYTE_ORDER */ 2043 2044 /* 2045 * Only allow 1 DMA channel to be active at a time. 2046 * I don't think this is a good idea, but without it 2047 * the firmware racks up lots of nicDmaReadRingFull 2048 * errors. This is not compatible with hardware checksums. 2049 */ 2050 if (sc->ti_ifp->if_hwassist == 0) 2051 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2052 2053 /* Recommended settings from Tigon manual. */ 2054 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2055 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2056 2057 if (ti_64bitslot_war(sc)) { 2058 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2059 "but we aren't"); 2060 return (EINVAL); 2061 } 2062 2063 return (0); 2064} 2065 2066/* 2067 * Initialize the general information block and firmware, and 2068 * start the CPU(s) running. 2069 */ 2070static int 2071ti_gibinit(sc) 2072 struct ti_softc *sc; 2073{ 2074 struct ti_rcb *rcb; 2075 int i; 2076 struct ifnet *ifp; 2077 uint32_t rdphys; 2078 2079 TI_LOCK_ASSERT(sc); 2080 2081 ifp = sc->ti_ifp; 2082 rdphys = sc->ti_rdata_phys; 2083 2084 /* Disable interrupts for now. */ 2085 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2086 2087 /* 2088 * Tell the chip where to find the general information block. 2089 * While this struct could go into >4GB memory, we allocate it in a 2090 * single slab with the other descriptors, and those don't seem to 2091 * support being located in a 64-bit region. 2092 */ 2093 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2094 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2095 2096 /* Load the firmware into SRAM. */ 2097 ti_loadfw(sc); 2098 2099 /* Set up the contents of the general info and ring control blocks. */ 2100 2101 /* Set up the event ring and producer pointer. */ 2102 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2103 2104 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2105 rcb->ti_flags = 0; 2106 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2107 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2108 sc->ti_ev_prodidx.ti_idx = 0; 2109 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2110 sc->ti_ev_saved_considx = 0; 2111 2112 /* Set up the command ring and producer mailbox. */ 2113 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2114 2115 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2116 rcb->ti_flags = 0; 2117 rcb->ti_max_len = 0; 2118 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2119 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2120 } 2121 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2122 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2123 sc->ti_cmd_saved_prodidx = 0; 2124 2125 /* 2126 * Assign the address of the stats refresh buffer. 2127 * We re-use the current stats buffer for this to 2128 * conserve memory. 2129 */ 2130 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2131 rdphys + TI_RD_OFF(ti_info.ti_stats); 2132 2133 /* Set up the standard receive ring. */ 2134 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2135 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2136 rcb->ti_max_len = TI_FRAMELEN; 2137 rcb->ti_flags = 0; 2138 if (sc->ti_ifp->if_hwassist) 2139 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2140 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2141 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2142 2143 /* Set up the jumbo receive ring. */ 2144 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2145 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2146 2147#ifdef TI_PRIVATE_JUMBOS 2148 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2149 rcb->ti_flags = 0; 2150#else 2151 rcb->ti_max_len = PAGE_SIZE; 2152 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2153#endif 2154 if (sc->ti_ifp->if_hwassist) 2155 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2156 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2157 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2158 2159 /* 2160 * Set up the mini ring. Only activated on the 2161 * Tigon 2 but the slot in the config block is 2162 * still there on the Tigon 1. 2163 */ 2164 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2165 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2166 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2167 if (sc->ti_hwrev == TI_HWREV_TIGON) 2168 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2169 else 2170 rcb->ti_flags = 0; 2171 if (sc->ti_ifp->if_hwassist) 2172 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2173 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2174 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2175 2176 /* 2177 * Set up the receive return ring. 2178 */ 2179 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2180 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2181 rcb->ti_flags = 0; 2182 rcb->ti_max_len = TI_RETURN_RING_CNT; 2183 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2184 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2185 2186 /* 2187 * Set up the tx ring. Note: for the Tigon 2, we have the option 2188 * of putting the transmit ring in the host's address space and 2189 * letting the chip DMA it instead of leaving the ring in the NIC's 2190 * memory and accessing it through the shared memory region. We 2191 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2192 * so we have to revert to the shared memory scheme if we detect 2193 * a Tigon 1 chip. 2194 */ 2195 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2196 bzero((char *)sc->ti_rdata->ti_tx_ring, 2197 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2198 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2199 if (sc->ti_hwrev == TI_HWREV_TIGON) 2200 rcb->ti_flags = 0; 2201 else 2202 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2203 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2204 if (sc->ti_ifp->if_hwassist) 2205 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2206 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2207 rcb->ti_max_len = TI_TX_RING_CNT; 2208 if (sc->ti_hwrev == TI_HWREV_TIGON) 2209 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2210 else 2211 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2212 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2213 rdphys + TI_RD_OFF(ti_tx_considx_r); 2214 2215 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2217 2218 /* Set up tuneables */ 2219#if 0 2220 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2221 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2222 (sc->ti_rx_coal_ticks / 10)); 2223 else 2224#endif 2225 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2226 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2227 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2228 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2229 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2230 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2231 2232 /* Turn interrupts on. */ 2233 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2234 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2235 2236 /* Start CPU. */ 2237 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2238 2239 return (0); 2240} 2241 2242static void 2243ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2244{ 2245 struct ti_softc *sc; 2246 2247 sc = arg; 2248 if (error || nseg != 1) 2249 return; 2250 2251 /* 2252 * All of the Tigon data structures need to live at <4GB. This 2253 * cast is fine since busdma was told about this constraint. 2254 */ 2255 sc->ti_rdata_phys = segs[0].ds_addr; 2256 return; 2257} 2258 2259/* 2260 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2261 * against our list and return its name if we find a match. 2262 */ 2263static int 2264ti_probe(dev) 2265 device_t dev; 2266{ 2267 struct ti_type *t; 2268 2269 t = ti_devs; 2270 2271 while (t->ti_name != NULL) { 2272 if ((pci_get_vendor(dev) == t->ti_vid) && 2273 (pci_get_device(dev) == t->ti_did)) { 2274 device_set_desc(dev, t->ti_name); 2275 return (BUS_PROBE_DEFAULT); 2276 } 2277 t++; 2278 } 2279 2280 return (ENXIO); 2281} 2282 2283static int 2284ti_attach(dev) 2285 device_t dev; 2286{ 2287 struct ifnet *ifp; 2288 struct ti_softc *sc; 2289 int error = 0, rid; 2290 u_char eaddr[6]; 2291 2292 sc = device_get_softc(dev); 2293 sc->ti_unit = device_get_unit(dev); 2294 sc->ti_dev = dev; 2295 2296 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2297 MTX_DEF); 2298 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2299 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2300 if (ifp == NULL) { 2301 device_printf(dev, "can not if_alloc()\n"); 2302 error = ENOSPC; 2303 goto fail; 2304 } 2305 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2306 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2307 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2308 2309 /* 2310 * Map control/status registers. 2311 */ 2312 pci_enable_busmaster(dev); 2313 2314 rid = TI_PCI_LOMEM; 2315 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2316 RF_ACTIVE|PCI_RF_DENSE); 2317 2318 if (sc->ti_res == NULL) { 2319 device_printf(dev, "couldn't map memory\n"); 2320 error = ENXIO; 2321 goto fail; 2322 } 2323 2324 sc->ti_btag = rman_get_bustag(sc->ti_res); 2325 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2326 2327 /* Allocate interrupt */ 2328 rid = 0; 2329 2330 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2331 RF_SHAREABLE | RF_ACTIVE); 2332 2333 if (sc->ti_irq == NULL) { 2334 device_printf(dev, "couldn't map interrupt\n"); 2335 error = ENXIO; 2336 goto fail; 2337 } 2338 2339 if (ti_chipinit(sc)) { 2340 device_printf(dev, "chip initialization failed\n"); 2341 error = ENXIO; 2342 goto fail; 2343 } 2344 2345 /* Zero out the NIC's on-board SRAM. */ 2346 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2347 2348 /* Init again -- zeroing memory may have clobbered some registers. */ 2349 if (ti_chipinit(sc)) { 2350 device_printf(dev, "chip initialization failed\n"); 2351 error = ENXIO; 2352 goto fail; 2353 } 2354 2355 /* 2356 * Get station address from the EEPROM. Note: the manual states 2357 * that the MAC address is at offset 0x8c, however the data is 2358 * stored as two longwords (since that's how it's loaded into 2359 * the NIC). This means the MAC address is actually preceded 2360 * by two zero bytes. We need to skip over those. 2361 */ 2362 if (ti_read_eeprom(sc, eaddr, 2363 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2364 device_printf(dev, "failed to read station address\n"); 2365 error = ENXIO; 2366 goto fail; 2367 } 2368 2369 /* Allocate the general information block and ring buffers. */ 2370 if (bus_dma_tag_create(NULL, /* parent */ 2371 1, 0, /* algnmnt, boundary */ 2372 BUS_SPACE_MAXADDR, /* lowaddr */ 2373 BUS_SPACE_MAXADDR, /* highaddr */ 2374 NULL, NULL, /* filter, filterarg */ 2375 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2376 0, /* nsegments */ 2377 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2378 0, /* flags */ 2379 NULL, NULL, /* lockfunc, lockarg */ 2380 &sc->ti_parent_dmat) != 0) { 2381 device_printf(dev, "Failed to allocate parent dmat\n"); 2382 error = ENOMEM; 2383 goto fail; 2384 } 2385 2386 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2387 PAGE_SIZE, 0, /* algnmnt, boundary */ 2388 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2389 BUS_SPACE_MAXADDR, /* highaddr */ 2390 NULL, NULL, /* filter, filterarg */ 2391 sizeof(struct ti_ring_data), /* maxsize */ 2392 1, /* nsegments */ 2393 sizeof(struct ti_ring_data), /* maxsegsize */ 2394 0, /* flags */ 2395 NULL, NULL, /* lockfunc, lockarg */ 2396 &sc->ti_rdata_dmat) != 0) { 2397 device_printf(dev, "Failed to allocate rdata dmat\n"); 2398 error = ENOMEM; 2399 goto fail; 2400 } 2401 2402 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2403 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2404 device_printf(dev, "Failed to allocate rdata memory\n"); 2405 error = ENOMEM; 2406 goto fail; 2407 } 2408 2409 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2410 sc->ti_rdata, sizeof(struct ti_ring_data), 2411 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2412 device_printf(dev, "Failed to load rdata segments\n"); 2413 error = ENOMEM; 2414 goto fail; 2415 } 2416 2417 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2418 2419 /* Try to allocate memory for jumbo buffers. */ 2420 if (ti_alloc_jumbo_mem(sc)) { 2421 device_printf(dev, "jumbo buffer allocation failed\n"); 2422 error = ENXIO; 2423 goto fail; 2424 } 2425 2426 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2427 1, 0, /* algnmnt, boundary */ 2428 BUS_SPACE_MAXADDR, /* lowaddr */ 2429 BUS_SPACE_MAXADDR, /* highaddr */ 2430 NULL, NULL, /* filter, filterarg */ 2431 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2432 TI_MAXTXSEGS, /* nsegments */ 2433 MCLBYTES, /* maxsegsize */ 2434 0, /* flags */ 2435 NULL, NULL, /* lockfunc, lockarg */ 2436 &sc->ti_mbuftx_dmat) != 0) { 2437 device_printf(dev, "Failed to allocate rdata dmat\n"); 2438 error = ENOMEM; 2439 goto fail; 2440 } 2441 2442 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2443 1, 0, /* algnmnt, boundary */ 2444 BUS_SPACE_MAXADDR, /* lowaddr */ 2445 BUS_SPACE_MAXADDR, /* highaddr */ 2446 NULL, NULL, /* filter, filterarg */ 2447 MCLBYTES, /* maxsize */ 2448 1, /* nsegments */ 2449 MCLBYTES, /* maxsegsize */ 2450 0, /* flags */ 2451 NULL, NULL, /* lockfunc, lockarg */ 2452 &sc->ti_mbufrx_dmat) != 0) { 2453 device_printf(dev, "Failed to allocate rdata dmat\n"); 2454 error = ENOMEM; 2455 goto fail; 2456 } 2457 2458 if (ti_alloc_dmamaps(sc)) { 2459 device_printf(dev, "dma map creation failed\n"); 2460 error = ENXIO; 2461 goto fail; 2462 } 2463 2464 /* 2465 * We really need a better way to tell a 1000baseTX card 2466 * from a 1000baseSX one, since in theory there could be 2467 * OEMed 1000baseTX cards from lame vendors who aren't 2468 * clever enough to change the PCI ID. For the moment 2469 * though, the AceNIC is the only copper card available. 2470 */ 2471 if (pci_get_vendor(dev) == ALT_VENDORID && 2472 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2473 sc->ti_copper = 1; 2474 /* Ok, it's not the only copper card available. */ 2475 if (pci_get_vendor(dev) == NG_VENDORID && 2476 pci_get_device(dev) == NG_DEVICEID_GA620T) 2477 sc->ti_copper = 1; 2478 2479 /* Set default tuneable values. */ 2480 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2481#if 0 2482 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2483#endif 2484 sc->ti_rx_coal_ticks = 170; 2485 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2486 sc->ti_rx_max_coal_bds = 64; 2487#if 0 2488 sc->ti_tx_max_coal_bds = 128; 2489#endif 2490 sc->ti_tx_max_coal_bds = 32; 2491 sc->ti_tx_buf_ratio = 21; 2492 2493 /* Set up ifnet structure */ 2494 ifp->if_softc = sc; 2495 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2497 ifp->if_ioctl = ti_ioctl; 2498 ifp->if_start = ti_start; 2499 ifp->if_watchdog = ti_watchdog; 2500 ifp->if_init = ti_init; 2501 ifp->if_mtu = ETHERMTU; 2502 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2503 2504 /* Set up ifmedia support. */ 2505 if (sc->ti_copper) { 2506 /* 2507 * Copper cards allow manual 10/100 mode selection, 2508 * but not manual 1000baseTX mode selection. Why? 2509 * Becuase currently there's no way to specify the 2510 * master/slave setting through the firmware interface, 2511 * so Alteon decided to just bag it and handle it 2512 * via autonegotiation. 2513 */ 2514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2515 ifmedia_add(&sc->ifmedia, 2516 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2518 ifmedia_add(&sc->ifmedia, 2519 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2521 ifmedia_add(&sc->ifmedia, 2522 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2523 } else { 2524 /* Fiber cards don't support 10/100 modes. */ 2525 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2526 ifmedia_add(&sc->ifmedia, 2527 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2528 } 2529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2530 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2531 2532 /* 2533 * We're assuming here that card initialization is a sequential 2534 * thing. If it isn't, multiple cards probing at the same time 2535 * could stomp on the list of softcs here. 2536 */ 2537 2538 /* Register the device */ 2539 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2540 0600, "ti%d", sc->ti_unit); 2541 sc->dev->si_drv1 = sc; 2542 2543 /* 2544 * Call MI attach routine. 2545 */ 2546 ether_ifattach(ifp, eaddr); 2547 2548 /* Hook interrupt last to avoid having to lock softc */ 2549 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2550 ti_intr, sc, &sc->ti_intrhand); 2551 2552 if (error) { 2553 device_printf(dev, "couldn't set up irq\n"); 2554 goto fail; 2555 } 2556 2557fail: 2558 if (error) 2559 ti_detach(dev); 2560 2561 return (error); 2562} 2563 2564/* 2565 * Shutdown hardware and free up resources. This can be called any 2566 * time after the mutex has been initialized. It is called in both 2567 * the error case in attach and the normal detach case so it needs 2568 * to be careful about only freeing resources that have actually been 2569 * allocated. 2570 */ 2571static int 2572ti_detach(dev) 2573 device_t dev; 2574{ 2575 struct ti_softc *sc; 2576 struct ifnet *ifp; 2577 int attached; 2578 2579 sc = device_get_softc(dev); 2580 if (sc->dev) 2581 destroy_dev(sc->dev); 2582 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2583 attached = device_is_attached(dev); 2584 TI_LOCK(sc); 2585 ifp = sc->ti_ifp; 2586 if (attached) 2587 ti_stop(sc); 2588 TI_UNLOCK(sc); 2589 if (attached) 2590 ether_ifdetach(ifp); 2591 2592 /* These should only be active if attach succeeded */ 2593 if (attached) 2594 bus_generic_detach(dev); 2595 ti_free_dmamaps(sc); 2596 ifmedia_removeall(&sc->ifmedia); 2597 2598#ifdef TI_PRIVATE_JUMBOS 2599 if (sc->ti_cdata.ti_jumbo_buf) 2600 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2601 sc->ti_jumbo_dmamap); 2602#endif 2603 if (sc->ti_jumbo_dmat) 2604 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2605 if (sc->ti_mbuftx_dmat) 2606 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2607 if (sc->ti_mbufrx_dmat) 2608 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2609 if (sc->ti_rdata) 2610 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2611 sc->ti_rdata_dmamap); 2612 if (sc->ti_rdata_dmat) 2613 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2614 if (sc->ti_parent_dmat) 2615 bus_dma_tag_destroy(sc->ti_parent_dmat); 2616 if (sc->ti_intrhand) 2617 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2618 if (sc->ti_irq) 2619 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2620 if (sc->ti_res) { 2621 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2622 sc->ti_res); 2623 } 2624 if (ifp) 2625 if_free(ifp); 2626 2627 mtx_destroy(&sc->ti_mtx); 2628 2629 return (0); 2630} 2631 2632#ifdef TI_JUMBO_HDRSPLIT 2633/* 2634 * If hdr_len is 0, that means that header splitting wasn't done on 2635 * this packet for some reason. The two most likely reasons are that 2636 * the protocol isn't a supported protocol for splitting, or this 2637 * packet had a fragment offset that wasn't 0. 2638 * 2639 * The header length, if it is non-zero, will always be the length of 2640 * the headers on the packet, but that length could be longer than the 2641 * first mbuf. So we take the minimum of the two as the actual 2642 * length. 2643 */ 2644static __inline void 2645ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2646{ 2647 int i = 0; 2648 int lengths[4] = {0, 0, 0, 0}; 2649 struct mbuf *m, *mp; 2650 2651 if (hdr_len != 0) 2652 top->m_len = min(hdr_len, top->m_len); 2653 pkt_len -= top->m_len; 2654 lengths[i++] = top->m_len; 2655 2656 mp = top; 2657 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2658 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2659 pkt_len -= m->m_len; 2660 lengths[i++] = m->m_len; 2661 mp = m; 2662 } 2663 2664#if 0 2665 if (hdr_len != 0) 2666 printf("got split packet: "); 2667 else 2668 printf("got non-split packet: "); 2669 2670 printf("%d,%d,%d,%d = %d\n", lengths[0], 2671 lengths[1], lengths[2], lengths[3], 2672 lengths[0] + lengths[1] + lengths[2] + 2673 lengths[3]); 2674#endif 2675 2676 if (pkt_len) 2677 panic("header splitting didn't"); 2678 2679 if (m) { 2680 m_freem(m); 2681 mp->m_next = NULL; 2682 2683 } 2684 if (mp->m_next != NULL) 2685 panic("ti_hdr_split: last mbuf in chain should be null"); 2686} 2687#endif /* TI_JUMBO_HDRSPLIT */ 2688 2689/* 2690 * Frame reception handling. This is called if there's a frame 2691 * on the receive return list. 2692 * 2693 * Note: we have to be able to handle three possibilities here: 2694 * 1) the frame is from the mini receive ring (can only happen) 2695 * on Tigon 2 boards) 2696 * 2) the frame is from the jumbo recieve ring 2697 * 3) the frame is from the standard receive ring 2698 */ 2699 2700static void 2701ti_rxeof(sc) 2702 struct ti_softc *sc; 2703{ 2704 bus_dmamap_t map; 2705 struct ifnet *ifp; 2706 struct ti_cmd_desc cmd; 2707 2708 TI_LOCK_ASSERT(sc); 2709 2710 ifp = sc->ti_ifp; 2711 2712 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2713 struct ti_rx_desc *cur_rx; 2714 u_int32_t rxidx; 2715 struct mbuf *m = NULL; 2716 u_int16_t vlan_tag = 0; 2717 int have_tag = 0; 2718 2719 cur_rx = 2720 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2721 rxidx = cur_rx->ti_idx; 2722 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2723 2724 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2725 have_tag = 1; 2726 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2727 } 2728 2729 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2730 2731 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2732 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2733 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2734 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2735 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2736 BUS_DMASYNC_POSTREAD); 2737 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2738 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2739 ifp->if_ierrors++; 2740 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2741 continue; 2742 } 2743 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2744 ifp->if_ierrors++; 2745 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2746 continue; 2747 } 2748#ifdef TI_PRIVATE_JUMBOS 2749 m->m_len = cur_rx->ti_len; 2750#else /* TI_PRIVATE_JUMBOS */ 2751#ifdef TI_JUMBO_HDRSPLIT 2752 if (sc->ti_hdrsplit) 2753 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2754 cur_rx->ti_len, rxidx); 2755 else 2756#endif /* TI_JUMBO_HDRSPLIT */ 2757 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2758#endif /* TI_PRIVATE_JUMBOS */ 2759 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2760 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2761 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2762 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2763 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2764 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2765 BUS_DMASYNC_POSTREAD); 2766 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2767 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2768 ifp->if_ierrors++; 2769 ti_newbuf_mini(sc, sc->ti_mini, m); 2770 continue; 2771 } 2772 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2773 ifp->if_ierrors++; 2774 ti_newbuf_mini(sc, sc->ti_mini, m); 2775 continue; 2776 } 2777 m->m_len = cur_rx->ti_len; 2778 } else { 2779 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2780 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2781 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2782 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2783 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2784 BUS_DMASYNC_POSTREAD); 2785 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2786 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2787 ifp->if_ierrors++; 2788 ti_newbuf_std(sc, sc->ti_std, m); 2789 continue; 2790 } 2791 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2792 ifp->if_ierrors++; 2793 ti_newbuf_std(sc, sc->ti_std, m); 2794 continue; 2795 } 2796 m->m_len = cur_rx->ti_len; 2797 } 2798 2799 m->m_pkthdr.len = cur_rx->ti_len; 2800 ifp->if_ipackets++; 2801 m->m_pkthdr.rcvif = ifp; 2802 2803 if (ifp->if_hwassist) { 2804 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2805 CSUM_DATA_VALID; 2806 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2807 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2808 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2809 } 2810 2811 /* 2812 * If we received a packet with a vlan tag, 2813 * tag it before passing the packet upward. 2814 */ 2815 if (have_tag) { 2816 VLAN_INPUT_TAG(ifp, m, vlan_tag); 2817 if (m == NULL) 2818 continue; 2819 } 2820 TI_UNLOCK(sc); 2821 (*ifp->if_input)(ifp, m); 2822 TI_LOCK(sc); 2823 } 2824 2825 /* Only necessary on the Tigon 1. */ 2826 if (sc->ti_hwrev == TI_HWREV_TIGON) 2827 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2828 sc->ti_rx_saved_considx); 2829 2830 TI_UPDATE_STDPROD(sc, sc->ti_std); 2831 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2832 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2833} 2834 2835static void 2836ti_txeof(sc) 2837 struct ti_softc *sc; 2838{ 2839 struct ti_txdesc *txd; 2840 struct ti_tx_desc txdesc; 2841 struct ti_tx_desc *cur_tx = NULL; 2842 struct ifnet *ifp; 2843 int idx; 2844 2845 ifp = sc->ti_ifp; 2846 2847 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2848 if (txd == NULL) 2849 return; 2850 /* 2851 * Go through our tx ring and free mbufs for those 2852 * frames that have been sent. 2853 */ 2854 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2855 TI_INC(idx, TI_TX_RING_CNT)) { 2856 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2857 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2858 sizeof(txdesc), &txdesc); 2859 cur_tx = &txdesc; 2860 } else 2861 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2862 sc->ti_txcnt--; 2863 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2864 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2865 continue; 2866 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2867 BUS_DMASYNC_POSTWRITE); 2868 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2869 2870 ifp->if_opackets++; 2871 m_freem(txd->tx_m); 2872 txd->tx_m = NULL; 2873 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2874 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2875 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2876 } 2877 sc->ti_tx_saved_considx = idx; 2878 2879 ifp->if_timer = sc->ti_txcnt > 0 ? 5 : 0; 2880} 2881 2882static void 2883ti_intr(xsc) 2884 void *xsc; 2885{ 2886 struct ti_softc *sc; 2887 struct ifnet *ifp; 2888 2889 sc = xsc; 2890 TI_LOCK(sc); 2891 ifp = sc->ti_ifp; 2892 2893/*#ifdef notdef*/ 2894 /* Avoid this for now -- checking this register is expensive. */ 2895 /* Make sure this is really our interrupt. */ 2896 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2897 TI_UNLOCK(sc); 2898 return; 2899 } 2900/*#endif*/ 2901 2902 /* Ack interrupt and stop others from occuring. */ 2903 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2904 2905 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2906 /* Check RX return ring producer/consumer */ 2907 ti_rxeof(sc); 2908 2909 /* Check TX ring producer/consumer */ 2910 ti_txeof(sc); 2911 } 2912 2913 ti_handle_events(sc); 2914 2915 /* Re-enable interrupts. */ 2916 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2917 2918 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2919 ifp->if_snd.ifq_head != NULL) 2920 ti_start_locked(ifp); 2921 2922 TI_UNLOCK(sc); 2923} 2924 2925static void 2926ti_stats_update(sc) 2927 struct ti_softc *sc; 2928{ 2929 struct ifnet *ifp; 2930 2931 ifp = sc->ti_ifp; 2932 2933 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2934 BUS_DMASYNC_POSTREAD); 2935 2936 ifp->if_collisions += 2937 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2938 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2939 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2940 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2941 ifp->if_collisions; 2942 2943 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2944 BUS_DMASYNC_PREREAD); 2945} 2946 2947/* 2948 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2949 * pointers to descriptors. 2950 */ 2951static int 2952ti_encap(sc, m_head) 2953 struct ti_softc *sc; 2954 struct mbuf **m_head; 2955{ 2956 struct ti_txdesc *txd; 2957 struct ti_tx_desc *f; 2958 struct ti_tx_desc txdesc; 2959 struct mbuf *m; 2960 struct m_tag *mtag; 2961 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2962 u_int16_t csum_flags; 2963 int error, frag, i, nseg; 2964 2965 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2966 return (ENOBUFS); 2967 2968 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2969 *m_head, txsegs, &nseg, 0); 2970 if (error == EFBIG) { 2971 m = m_defrag(*m_head, M_DONTWAIT); 2972 if (m == NULL) { 2973 m_freem(*m_head); 2974 *m_head = NULL; 2975 return (ENOMEM); 2976 } 2977 *m_head = m; 2978 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2979 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2980 if (error) { 2981 m_freem(*m_head); 2982 *m_head = NULL; 2983 return (error); 2984 } 2985 } else if (error != 0) 2986 return (error); 2987 if (nseg == 0) { 2988 m_freem(*m_head); 2989 *m_head = NULL; 2990 return (EIO); 2991 } 2992 2993 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2994 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2995 return (ENOBUFS); 2996 } 2997 2998 m = *m_head; 2999 csum_flags = 0; 3000 if (m->m_pkthdr.csum_flags) { 3001 if (m->m_pkthdr.csum_flags & CSUM_IP) 3002 csum_flags |= TI_BDFLAG_IP_CKSUM; 3003 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3004 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3005 if (m->m_flags & M_LASTFRAG) 3006 csum_flags |= TI_BDFLAG_IP_FRAG_END; 3007 else if (m->m_flags & M_FRAG) 3008 csum_flags |= TI_BDFLAG_IP_FRAG; 3009 } 3010 3011 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 3012 BUS_DMASYNC_PREWRITE); 3013 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 3014 BUS_DMASYNC_PREWRITE); 3015 3016 mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m); 3017 frag = sc->ti_tx_saved_prodidx; 3018 for (i = 0; i < nseg; i++) { 3019 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3020 bzero(&txdesc, sizeof(txdesc)); 3021 f = &txdesc; 3022 } else 3023 f = &sc->ti_rdata->ti_tx_ring[frag]; 3024 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3025 f->ti_len = txsegs[i].ds_len; 3026 f->ti_flags = csum_flags; 3027 if (mtag != NULL) { 3028 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3029 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 3030 } else { 3031 f->ti_vlan_tag = 0; 3032 } 3033 3034 if (sc->ti_hwrev == TI_HWREV_TIGON) 3035 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3036 sizeof(txdesc), sizeof(txdesc), &txdesc); 3037 TI_INC(frag, TI_TX_RING_CNT); 3038 } 3039 3040 sc->ti_tx_saved_prodidx = frag; 3041 /* set TI_BDFLAG_END on the last descriptor */ 3042 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3043 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3044 txdesc.ti_flags |= TI_BDFLAG_END; 3045 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3046 sizeof(txdesc), &txdesc); 3047 } else 3048 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3049 3050 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3051 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3052 txd->tx_m = m; 3053 sc->ti_txcnt += nseg; 3054 3055 return (0); 3056} 3057 3058static void 3059ti_start(ifp) 3060 struct ifnet *ifp; 3061{ 3062 struct ti_softc *sc; 3063 3064 sc = ifp->if_softc; 3065 TI_LOCK(sc); 3066 ti_start_locked(ifp); 3067 TI_UNLOCK(sc); 3068} 3069 3070/* 3071 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3072 * to the mbuf data regions directly in the transmit descriptors. 3073 */ 3074static void 3075ti_start_locked(ifp) 3076 struct ifnet *ifp; 3077{ 3078 struct ti_softc *sc; 3079 struct mbuf *m_head = NULL; 3080 int enq = 0; 3081 3082 sc = ifp->if_softc; 3083 3084 for (; ifp->if_snd.ifq_head != NULL && 3085 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3086 IF_DEQUEUE(&ifp->if_snd, m_head); 3087 if (m_head == NULL) 3088 break; 3089 3090 /* 3091 * XXX 3092 * safety overkill. If this is a fragmented packet chain 3093 * with delayed TCP/UDP checksums, then only encapsulate 3094 * it if we have enough descriptors to handle the entire 3095 * chain at once. 3096 * (paranoia -- may not actually be needed) 3097 */ 3098 if (m_head->m_flags & M_FIRSTFRAG && 3099 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3100 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3101 m_head->m_pkthdr.csum_data + 16) { 3102 IF_PREPEND(&ifp->if_snd, m_head); 3103 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3104 break; 3105 } 3106 } 3107 3108 /* 3109 * Pack the data into the transmit ring. If we 3110 * don't have room, set the OACTIVE flag and wait 3111 * for the NIC to drain the ring. 3112 */ 3113 if (ti_encap(sc, &m_head)) { 3114 if (m_head == NULL) 3115 break; 3116 IF_PREPEND(&ifp->if_snd, m_head); 3117 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3118 break; 3119 } 3120 3121 enq++; 3122 /* 3123 * If there's a BPF listener, bounce a copy of this frame 3124 * to him. 3125 */ 3126 BPF_MTAP(ifp, m_head); 3127 } 3128 3129 if (enq > 0) { 3130 /* Transmit */ 3131 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3132 3133 /* 3134 * Set a timeout in case the chip goes out to lunch. 3135 */ 3136 ifp->if_timer = 5; 3137 } 3138} 3139 3140static void 3141ti_init(xsc) 3142 void *xsc; 3143{ 3144 struct ti_softc *sc; 3145 3146 sc = xsc; 3147 TI_LOCK(sc); 3148 ti_init_locked(sc); 3149 TI_UNLOCK(sc); 3150} 3151 3152static void 3153ti_init_locked(xsc) 3154 void *xsc; 3155{ 3156 struct ti_softc *sc = xsc; 3157 3158 /* Cancel pending I/O and flush buffers. */ 3159 ti_stop(sc); 3160 3161 /* Init the gen info block, ring control blocks and firmware. */ 3162 if (ti_gibinit(sc)) { 3163 device_printf(sc->ti_dev, "initialization failure\n"); 3164 return; 3165 } 3166} 3167 3168static void ti_init2(sc) 3169 struct ti_softc *sc; 3170{ 3171 struct ti_cmd_desc cmd; 3172 struct ifnet *ifp; 3173 u_int8_t *ea; 3174 struct ifmedia *ifm; 3175 int tmp; 3176 3177 TI_LOCK_ASSERT(sc); 3178 3179 ifp = sc->ti_ifp; 3180 3181 /* Specify MTU and interface index. */ 3182 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 3183 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3184 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3185 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3186 3187 /* Load our MAC address. */ 3188 ea = IF_LLADDR(sc->ti_ifp); 3189 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3190 CSR_WRITE_4(sc, TI_GCR_PAR1, 3191 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3192 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3193 3194 /* Enable or disable promiscuous mode as needed. */ 3195 if (ifp->if_flags & IFF_PROMISC) { 3196 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3197 } else { 3198 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3199 } 3200 3201 /* Program multicast filter. */ 3202 ti_setmulti(sc); 3203 3204 /* 3205 * If this is a Tigon 1, we should tell the 3206 * firmware to use software packet filtering. 3207 */ 3208 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3209 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3210 } 3211 3212 /* Init RX ring. */ 3213 ti_init_rx_ring_std(sc); 3214 3215 /* Init jumbo RX ring. */ 3216 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3217 ti_init_rx_ring_jumbo(sc); 3218 3219 /* 3220 * If this is a Tigon 2, we can also configure the 3221 * mini ring. 3222 */ 3223 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 3224 ti_init_rx_ring_mini(sc); 3225 3226 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3227 sc->ti_rx_saved_considx = 0; 3228 3229 /* Init TX ring. */ 3230 ti_init_tx_ring(sc); 3231 3232 /* Tell firmware we're alive. */ 3233 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3234 3235 /* Enable host interrupts. */ 3236 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3237 3238 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3239 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3240 3241 /* 3242 * Make sure to set media properly. We have to do this 3243 * here since we have to issue commands in order to set 3244 * the link negotiation and we can't issue commands until 3245 * the firmware is running. 3246 */ 3247 ifm = &sc->ifmedia; 3248 tmp = ifm->ifm_media; 3249 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3250 ti_ifmedia_upd(ifp); 3251 ifm->ifm_media = tmp; 3252} 3253 3254/* 3255 * Set media options. 3256 */ 3257static int 3258ti_ifmedia_upd(ifp) 3259 struct ifnet *ifp; 3260{ 3261 struct ti_softc *sc; 3262 struct ifmedia *ifm; 3263 struct ti_cmd_desc cmd; 3264 u_int32_t flowctl; 3265 3266 sc = ifp->if_softc; 3267 ifm = &sc->ifmedia; 3268 3269 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3270 return (EINVAL); 3271 3272 flowctl = 0; 3273 3274 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3275 case IFM_AUTO: 3276 /* 3277 * Transmit flow control doesn't work on the Tigon 1. 3278 */ 3279 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3280 3281 /* 3282 * Transmit flow control can also cause problems on the 3283 * Tigon 2, apparantly with both the copper and fiber 3284 * boards. The symptom is that the interface will just 3285 * hang. This was reproduced with Alteon 180 switches. 3286 */ 3287#if 0 3288 if (sc->ti_hwrev != TI_HWREV_TIGON) 3289 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3290#endif 3291 3292 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3293 TI_GLNK_FULL_DUPLEX| flowctl | 3294 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3295 3296 flowctl = TI_LNK_RX_FLOWCTL_Y; 3297#if 0 3298 if (sc->ti_hwrev != TI_HWREV_TIGON) 3299 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3300#endif 3301 3302 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3303 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3304 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3305 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3306 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3307 break; 3308 case IFM_1000_SX: 3309 case IFM_1000_T: 3310 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3311#if 0 3312 if (sc->ti_hwrev != TI_HWREV_TIGON) 3313 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3314#endif 3315 3316 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3317 flowctl |TI_GLNK_ENB); 3318 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3319 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3320 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3321 } 3322 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3323 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3324 break; 3325 case IFM_100_FX: 3326 case IFM_10_FL: 3327 case IFM_100_TX: 3328 case IFM_10_T: 3329 flowctl = TI_LNK_RX_FLOWCTL_Y; 3330#if 0 3331 if (sc->ti_hwrev != TI_HWREV_TIGON) 3332 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3333#endif 3334 3335 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3336 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3337 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3338 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3339 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3340 } else { 3341 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3342 } 3343 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3344 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3345 } else { 3346 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3347 } 3348 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3349 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3350 break; 3351 } 3352 3353 return (0); 3354} 3355 3356/* 3357 * Report current media status. 3358 */ 3359static void 3360ti_ifmedia_sts(ifp, ifmr) 3361 struct ifnet *ifp; 3362 struct ifmediareq *ifmr; 3363{ 3364 struct ti_softc *sc; 3365 u_int32_t media = 0; 3366 3367 sc = ifp->if_softc; 3368 3369 ifmr->ifm_status = IFM_AVALID; 3370 ifmr->ifm_active = IFM_ETHER; 3371 3372 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3373 return; 3374 3375 ifmr->ifm_status |= IFM_ACTIVE; 3376 3377 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3378 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3379 if (sc->ti_copper) 3380 ifmr->ifm_active |= IFM_1000_T; 3381 else 3382 ifmr->ifm_active |= IFM_1000_SX; 3383 if (media & TI_GLNK_FULL_DUPLEX) 3384 ifmr->ifm_active |= IFM_FDX; 3385 else 3386 ifmr->ifm_active |= IFM_HDX; 3387 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3388 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3389 if (sc->ti_copper) { 3390 if (media & TI_LNK_100MB) 3391 ifmr->ifm_active |= IFM_100_TX; 3392 if (media & TI_LNK_10MB) 3393 ifmr->ifm_active |= IFM_10_T; 3394 } else { 3395 if (media & TI_LNK_100MB) 3396 ifmr->ifm_active |= IFM_100_FX; 3397 if (media & TI_LNK_10MB) 3398 ifmr->ifm_active |= IFM_10_FL; 3399 } 3400 if (media & TI_LNK_FULL_DUPLEX) 3401 ifmr->ifm_active |= IFM_FDX; 3402 if (media & TI_LNK_HALF_DUPLEX) 3403 ifmr->ifm_active |= IFM_HDX; 3404 } 3405} 3406 3407static int 3408ti_ioctl(ifp, command, data) 3409 struct ifnet *ifp; 3410 u_long command; 3411 caddr_t data; 3412{ 3413 struct ti_softc *sc = ifp->if_softc; 3414 struct ifreq *ifr = (struct ifreq *) data; 3415 int mask, error = 0; 3416 struct ti_cmd_desc cmd; 3417 3418 switch (command) { 3419 case SIOCSIFMTU: 3420 TI_LOCK(sc); 3421 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3422 error = EINVAL; 3423 else { 3424 ifp->if_mtu = ifr->ifr_mtu; 3425 ti_init_locked(sc); 3426 } 3427 TI_UNLOCK(sc); 3428 break; 3429 case SIOCSIFFLAGS: 3430 TI_LOCK(sc); 3431 if (ifp->if_flags & IFF_UP) { 3432 /* 3433 * If only the state of the PROMISC flag changed, 3434 * then just use the 'set promisc mode' command 3435 * instead of reinitializing the entire NIC. Doing 3436 * a full re-init means reloading the firmware and 3437 * waiting for it to start up, which may take a 3438 * second or two. 3439 */ 3440 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3441 ifp->if_flags & IFF_PROMISC && 3442 !(sc->ti_if_flags & IFF_PROMISC)) { 3443 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3444 TI_CMD_CODE_PROMISC_ENB, 0); 3445 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3446 !(ifp->if_flags & IFF_PROMISC) && 3447 sc->ti_if_flags & IFF_PROMISC) { 3448 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3449 TI_CMD_CODE_PROMISC_DIS, 0); 3450 } else 3451 ti_init_locked(sc); 3452 } else { 3453 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3454 ti_stop(sc); 3455 } 3456 } 3457 sc->ti_if_flags = ifp->if_flags; 3458 TI_UNLOCK(sc); 3459 break; 3460 case SIOCADDMULTI: 3461 case SIOCDELMULTI: 3462 TI_LOCK(sc); 3463 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3464 ti_setmulti(sc); 3465 TI_UNLOCK(sc); 3466 break; 3467 case SIOCSIFMEDIA: 3468 case SIOCGIFMEDIA: 3469 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3470 break; 3471 case SIOCSIFCAP: 3472 TI_LOCK(sc); 3473 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3474 if (mask & IFCAP_HWCSUM) { 3475 if (IFCAP_HWCSUM & ifp->if_capenable) 3476 ifp->if_capenable &= ~IFCAP_HWCSUM; 3477 else 3478 ifp->if_capenable |= IFCAP_HWCSUM; 3479 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3480 ti_init_locked(sc); 3481 } 3482 TI_UNLOCK(sc); 3483 break; 3484 default: 3485 error = ether_ioctl(ifp, command, data); 3486 break; 3487 } 3488 3489 return (error); 3490} 3491 3492static int 3493ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3494{ 3495 struct ti_softc *sc; 3496 3497 sc = dev->si_drv1; 3498 if (sc == NULL) 3499 return (ENODEV); 3500 3501 TI_LOCK(sc); 3502 sc->ti_flags |= TI_FLAG_DEBUGING; 3503 TI_UNLOCK(sc); 3504 3505 return (0); 3506} 3507 3508static int 3509ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3510{ 3511 struct ti_softc *sc; 3512 3513 sc = dev->si_drv1; 3514 if (sc == NULL) 3515 return (ENODEV); 3516 3517 TI_LOCK(sc); 3518 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3519 TI_UNLOCK(sc); 3520 3521 return (0); 3522} 3523 3524/* 3525 * This ioctl routine goes along with the Tigon character device. 3526 */ 3527static int 3528ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3529 struct thread *td) 3530{ 3531 int error; 3532 struct ti_softc *sc; 3533 3534 sc = dev->si_drv1; 3535 if (sc == NULL) 3536 return (ENODEV); 3537 3538 error = 0; 3539 3540 switch (cmd) { 3541 case TIIOCGETSTATS: 3542 { 3543 struct ti_stats *outstats; 3544 3545 outstats = (struct ti_stats *)addr; 3546 3547 TI_LOCK(sc); 3548 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3549 sizeof(struct ti_stats)); 3550 TI_UNLOCK(sc); 3551 break; 3552 } 3553 case TIIOCGETPARAMS: 3554 { 3555 struct ti_params *params; 3556 3557 params = (struct ti_params *)addr; 3558 3559 TI_LOCK(sc); 3560 params->ti_stat_ticks = sc->ti_stat_ticks; 3561 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3562 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3563 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3564 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3565 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3566 params->param_mask = TI_PARAM_ALL; 3567 TI_UNLOCK(sc); 3568 3569 error = 0; 3570 3571 break; 3572 } 3573 case TIIOCSETPARAMS: 3574 { 3575 struct ti_params *params; 3576 3577 params = (struct ti_params *)addr; 3578 3579 TI_LOCK(sc); 3580 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3581 sc->ti_stat_ticks = params->ti_stat_ticks; 3582 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3583 } 3584 3585 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3586 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3587 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3588 sc->ti_rx_coal_ticks); 3589 } 3590 3591 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3592 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3593 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3594 sc->ti_tx_coal_ticks); 3595 } 3596 3597 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3598 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3599 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3600 sc->ti_rx_max_coal_bds); 3601 } 3602 3603 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3604 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3605 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3606 sc->ti_tx_max_coal_bds); 3607 } 3608 3609 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3610 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3611 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3612 sc->ti_tx_buf_ratio); 3613 } 3614 TI_UNLOCK(sc); 3615 3616 error = 0; 3617 3618 break; 3619 } 3620 case TIIOCSETTRACE: { 3621 ti_trace_type trace_type; 3622 3623 trace_type = *(ti_trace_type *)addr; 3624 3625 /* 3626 * Set tracing to whatever the user asked for. Setting 3627 * this register to 0 should have the effect of disabling 3628 * tracing. 3629 */ 3630 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3631 3632 error = 0; 3633 3634 break; 3635 } 3636 case TIIOCGETTRACE: { 3637 struct ti_trace_buf *trace_buf; 3638 u_int32_t trace_start, cur_trace_ptr, trace_len; 3639 3640 trace_buf = (struct ti_trace_buf *)addr; 3641 3642 TI_LOCK(sc); 3643 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3644 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3645 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3646 3647#if 0 3648 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3649 "trace_len = %d\n", trace_start, 3650 cur_trace_ptr, trace_len); 3651 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3652 trace_buf->buf_len); 3653#endif 3654 3655 error = ti_copy_mem(sc, trace_start, min(trace_len, 3656 trace_buf->buf_len), 3657 (caddr_t)trace_buf->buf, 1, 1); 3658 3659 if (error == 0) { 3660 trace_buf->fill_len = min(trace_len, 3661 trace_buf->buf_len); 3662 if (cur_trace_ptr < trace_start) 3663 trace_buf->cur_trace_ptr = 3664 trace_start - cur_trace_ptr; 3665 else 3666 trace_buf->cur_trace_ptr = 3667 cur_trace_ptr - trace_start; 3668 } else 3669 trace_buf->fill_len = 0; 3670 TI_UNLOCK(sc); 3671 3672 break; 3673 } 3674 3675 /* 3676 * For debugging, five ioctls are needed: 3677 * ALT_ATTACH 3678 * ALT_READ_TG_REG 3679 * ALT_WRITE_TG_REG 3680 * ALT_READ_TG_MEM 3681 * ALT_WRITE_TG_MEM 3682 */ 3683 case ALT_ATTACH: 3684 /* 3685 * From what I can tell, Alteon's Solaris Tigon driver 3686 * only has one character device, so you have to attach 3687 * to the Tigon board you're interested in. This seems 3688 * like a not-so-good way to do things, since unless you 3689 * subsequently specify the unit number of the device 3690 * you're interested in in every ioctl, you'll only be 3691 * able to debug one board at a time. 3692 */ 3693 error = 0; 3694 break; 3695 case ALT_READ_TG_MEM: 3696 case ALT_WRITE_TG_MEM: 3697 { 3698 struct tg_mem *mem_param; 3699 u_int32_t sram_end, scratch_end; 3700 3701 mem_param = (struct tg_mem *)addr; 3702 3703 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3704 sram_end = TI_END_SRAM_I; 3705 scratch_end = TI_END_SCRATCH_I; 3706 } else { 3707 sram_end = TI_END_SRAM_II; 3708 scratch_end = TI_END_SCRATCH_II; 3709 } 3710 3711 /* 3712 * For now, we'll only handle accessing regular SRAM, 3713 * nothing else. 3714 */ 3715 TI_LOCK(sc); 3716 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3717 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3718 /* 3719 * In this instance, we always copy to/from user 3720 * space, so the user space argument is set to 1. 3721 */ 3722 error = ti_copy_mem(sc, mem_param->tgAddr, 3723 mem_param->len, 3724 mem_param->userAddr, 1, 3725 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3726 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3727 && (mem_param->tgAddr <= scratch_end)) { 3728 error = ti_copy_scratch(sc, mem_param->tgAddr, 3729 mem_param->len, 3730 mem_param->userAddr, 1, 3731 (cmd == ALT_READ_TG_MEM) ? 3732 1 : 0, TI_PROCESSOR_A); 3733 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3734 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3735 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3736 if_printf(sc->ti_ifp, 3737 "invalid memory range for Tigon I\n"); 3738 error = EINVAL; 3739 break; 3740 } 3741 error = ti_copy_scratch(sc, mem_param->tgAddr - 3742 TI_SCRATCH_DEBUG_OFF, 3743 mem_param->len, 3744 mem_param->userAddr, 1, 3745 (cmd == ALT_READ_TG_MEM) ? 3746 1 : 0, TI_PROCESSOR_B); 3747 } else { 3748 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3749 "out of supported range\n", 3750 mem_param->tgAddr, mem_param->len); 3751 error = EINVAL; 3752 } 3753 TI_UNLOCK(sc); 3754 3755 break; 3756 } 3757 case ALT_READ_TG_REG: 3758 case ALT_WRITE_TG_REG: 3759 { 3760 struct tg_reg *regs; 3761 u_int32_t tmpval; 3762 3763 regs = (struct tg_reg *)addr; 3764 3765 /* 3766 * Make sure the address in question isn't out of range. 3767 */ 3768 if (regs->addr > TI_REG_MAX) { 3769 error = EINVAL; 3770 break; 3771 } 3772 TI_LOCK(sc); 3773 if (cmd == ALT_READ_TG_REG) { 3774 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3775 regs->addr, &tmpval, 1); 3776 regs->data = ntohl(tmpval); 3777#if 0 3778 if ((regs->addr == TI_CPU_STATE) 3779 || (regs->addr == TI_CPU_CTL_B)) { 3780 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3781 regs->addr, tmpval); 3782 } 3783#endif 3784 } else { 3785 tmpval = htonl(regs->data); 3786 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3787 regs->addr, &tmpval, 1); 3788 } 3789 TI_UNLOCK(sc); 3790 3791 break; 3792 } 3793 default: 3794 error = ENOTTY; 3795 break; 3796 } 3797 return (error); 3798} 3799 3800static void 3801ti_watchdog(ifp) 3802 struct ifnet *ifp; 3803{ 3804 struct ti_softc *sc; 3805 3806 sc = ifp->if_softc; 3807 TI_LOCK(sc); 3808 3809 /* 3810 * When we're debugging, the chip is often stopped for long periods 3811 * of time, and that would normally cause the watchdog timer to fire. 3812 * Since that impedes debugging, we don't want to do that. 3813 */ 3814 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3815 TI_UNLOCK(sc); 3816 return; 3817 } 3818 3819 if_printf(ifp, "watchdog timeout -- resetting\n"); 3820 ti_stop(sc); 3821 ti_init_locked(sc); 3822 3823 ifp->if_oerrors++; 3824 TI_UNLOCK(sc); 3825} 3826 3827/* 3828 * Stop the adapter and free any mbufs allocated to the 3829 * RX and TX lists. 3830 */ 3831static void 3832ti_stop(sc) 3833 struct ti_softc *sc; 3834{ 3835 struct ifnet *ifp; 3836 struct ti_cmd_desc cmd; 3837 3838 TI_LOCK_ASSERT(sc); 3839 3840 ifp = sc->ti_ifp; 3841 3842 /* Disable host interrupts. */ 3843 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3844 /* 3845 * Tell firmware we're shutting down. 3846 */ 3847 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3848 3849 /* Halt and reinitialize. */ 3850 if (ti_chipinit(sc) != 0) 3851 return; 3852 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3853 if (ti_chipinit(sc) != 0) 3854 return; 3855 3856 /* Free the RX lists. */ 3857 ti_free_rx_ring_std(sc); 3858 3859 /* Free jumbo RX list. */ 3860 ti_free_rx_ring_jumbo(sc); 3861 3862 /* Free mini RX list. */ 3863 ti_free_rx_ring_mini(sc); 3864 3865 /* Free TX buffers. */ 3866 ti_free_tx_ring(sc); 3867 3868 sc->ti_ev_prodidx.ti_idx = 0; 3869 sc->ti_return_prodidx.ti_idx = 0; 3870 sc->ti_tx_considx.ti_idx = 0; 3871 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3872 3873 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3874} 3875 3876/* 3877 * Stop all chip I/O so that the kernel's probe routines don't 3878 * get confused by errant DMAs when rebooting. 3879 */ 3880static void 3881ti_shutdown(dev) 3882 device_t dev; 3883{ 3884 struct ti_softc *sc; 3885 3886 sc = device_get_softc(dev); 3887 TI_LOCK(sc); 3888 ti_chipinit(sc); 3889 TI_UNLOCK(sc); 3890} 3891