if_ti.c revision 153778
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 153778 2005-12-28 08:36:32Z scottl $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116#ifndef TI_PRIVATE_JUMBOS 117#include <vm/vm.h> 118#include <vm/vm_page.h> 119#endif 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123 124#include <sys/tiio.h> 125#include <dev/ti/if_tireg.h> 126#include <dev/ti/ti_fw.h> 127#include <dev/ti/ti_fw2.h> 128 129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130/* 131 * We can only turn on header splitting if we're using extended receive 132 * BDs. 133 */ 134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 137 138typedef enum { 139 TI_SWAP_HTON, 140 TI_SWAP_NTOH 141} ti_swap_type; 142 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static struct ti_type ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *); 188static void ti_encap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 189 bus_size_t mapsize, int error); 190 191static void ti_intr(void *); 192static void ti_start(struct ifnet *); 193static void ti_start_locked(struct ifnet *); 194static int ti_ioctl(struct ifnet *, u_long, caddr_t); 195static void ti_init(void *); 196static void ti_init_locked(void *); 197static void ti_init2(struct ti_softc *); 198static void ti_stop(struct ti_softc *); 199static void ti_watchdog(struct ifnet *); 200static void ti_shutdown(device_t); 201static int ti_ifmedia_upd(struct ifnet *); 202static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 203 204static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 205static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 206static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 207 208static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 209static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 210static void ti_setmulti(struct ti_softc *); 211 212static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 213static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 214static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 215static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 216static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 217 int, int, int); 218static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219static void ti_loadfw(struct ti_softc *); 220static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222static void ti_handle_events(struct ti_softc *); 223static int ti_alloc_dmamaps(struct ti_softc *); 224static void ti_free_dmamaps(struct ti_softc *); 225static int ti_alloc_jumbo_mem(struct ti_softc *); 226#ifdef TI_PRIVATE_JUMBOS 227static void *ti_jalloc(struct ti_softc *); 228static void ti_jfree(void *, void *); 229#endif /* TI_PRIVATE_JUMBOS */ 230static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 231static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 232static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 233static int ti_init_rx_ring_std(struct ti_softc *); 234static void ti_free_rx_ring_std(struct ti_softc *); 235static int ti_init_rx_ring_jumbo(struct ti_softc *); 236static void ti_free_rx_ring_jumbo(struct ti_softc *); 237static int ti_init_rx_ring_mini(struct ti_softc *); 238static void ti_free_rx_ring_mini(struct ti_softc *); 239static void ti_free_tx_ring(struct ti_softc *); 240static int ti_init_tx_ring(struct ti_softc *); 241 242static int ti_64bitslot_war(struct ti_softc *); 243static int ti_chipinit(struct ti_softc *); 244static int ti_gibinit(struct ti_softc *); 245 246#ifdef TI_JUMBO_HDRSPLIT 247static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 248 int pkt_len, int idx); 249#endif /* TI_JUMBO_HDRSPLIT */ 250 251static device_method_t ti_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, ti_probe), 254 DEVMETHOD(device_attach, ti_attach), 255 DEVMETHOD(device_detach, ti_detach), 256 DEVMETHOD(device_shutdown, ti_shutdown), 257 { 0, 0 } 258}; 259 260static driver_t ti_driver = { 261 "ti", 262 ti_methods, 263 sizeof(struct ti_softc) 264}; 265 266static devclass_t ti_devclass; 267 268DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 269MODULE_DEPEND(ti, pci, 1, 1, 1); 270MODULE_DEPEND(ti, ether, 1, 1, 1); 271 272/* 273 * Send an instruction or address to the EEPROM, check for ACK. 274 */ 275static u_int32_t ti_eeprom_putbyte(sc, byte) 276 struct ti_softc *sc; 277 int byte; 278{ 279 int i, ack = 0; 280 281 /* 282 * Make sure we're in TX mode. 283 */ 284 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 285 286 /* 287 * Feed in each bit and stobe the clock. 288 */ 289 for (i = 0x80; i; i >>= 1) { 290 if (byte & i) { 291 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 292 } else { 293 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 294 } 295 DELAY(1); 296 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 297 DELAY(1); 298 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 299 } 300 301 /* 302 * Turn off TX mode. 303 */ 304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 305 306 /* 307 * Check for ack. 308 */ 309 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 312 313 return (ack); 314} 315 316/* 317 * Read a byte of data stored in the EEPROM at address 'addr.' 318 * We have to send two address bytes since the EEPROM can hold 319 * more than 256 bytes of data. 320 */ 321static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 322 struct ti_softc *sc; 323 int addr; 324 u_int8_t *dest; 325{ 326 int i; 327 u_int8_t byte = 0; 328 329 EEPROM_START; 330 331 /* 332 * Send write control code to EEPROM. 333 */ 334 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 335 if_printf(sc->ti_ifp, 336 "failed to send write command, status: %x\n", 337 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 338 return (1); 339 } 340 341 /* 342 * Send first byte of address of byte we want to read. 343 */ 344 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 345 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 346 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 347 return (1); 348 } 349 /* 350 * Send second byte address of byte we want to read. 351 */ 352 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 353 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 354 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 355 return (1); 356 } 357 358 EEPROM_STOP; 359 EEPROM_START; 360 /* 361 * Send read control code to EEPROM. 362 */ 363 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 364 if_printf(sc->ti_ifp, 365 "failed to send read command, status: %x\n", 366 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 367 return (1); 368 } 369 370 /* 371 * Start reading bits from EEPROM. 372 */ 373 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 374 for (i = 0x80; i; i >>= 1) { 375 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 376 DELAY(1); 377 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 378 byte |= i; 379 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 380 DELAY(1); 381 } 382 383 EEPROM_STOP; 384 385 /* 386 * No ACK generated for read, so just return byte. 387 */ 388 389 *dest = byte; 390 391 return (0); 392} 393 394/* 395 * Read a sequence of bytes from the EEPROM. 396 */ 397static int 398ti_read_eeprom(sc, dest, off, cnt) 399 struct ti_softc *sc; 400 caddr_t dest; 401 int off; 402 int cnt; 403{ 404 int err = 0, i; 405 u_int8_t byte = 0; 406 407 for (i = 0; i < cnt; i++) { 408 err = ti_eeprom_getbyte(sc, off + i, &byte); 409 if (err) 410 break; 411 *(dest + i) = byte; 412 } 413 414 return (err ? 1 : 0); 415} 416 417/* 418 * NIC memory read function. 419 * Can be used to copy data from NIC local memory. 420 */ 421static void 422ti_mem_read(sc, addr, len, buf) 423 struct ti_softc *sc; 424 u_int32_t addr, len; 425 void *buf; 426{ 427 int segptr, segsize, cnt; 428 char *ptr; 429 430 segptr = addr; 431 cnt = len; 432 ptr = buf; 433 434 while (cnt) { 435 if (cnt < TI_WINLEN) 436 segsize = cnt; 437 else 438 segsize = TI_WINLEN - (segptr % TI_WINLEN); 439 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 440 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 441 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 442 segsize / 4); 443 ptr += segsize; 444 segptr += segsize; 445 cnt -= segsize; 446 } 447} 448 449 450/* 451 * NIC memory write function. 452 * Can be used to copy data into NIC local memory. 453 */ 454static void 455ti_mem_write(sc, addr, len, buf) 456 struct ti_softc *sc; 457 u_int32_t addr, len; 458 void *buf; 459{ 460 int segptr, segsize, cnt; 461 char *ptr; 462 463 segptr = addr; 464 cnt = len; 465 ptr = buf; 466 467 while (cnt) { 468 if (cnt < TI_WINLEN) 469 segsize = cnt; 470 else 471 segsize = TI_WINLEN - (segptr % TI_WINLEN); 472 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 473 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 474 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 475 segsize / 4); 476 ptr += segsize; 477 segptr += segsize; 478 cnt -= segsize; 479 } 480} 481 482/* 483 * NIC memory read function. 484 * Can be used to clear a section of NIC local memory. 485 */ 486static void 487ti_mem_zero(sc, addr, len) 488 struct ti_softc *sc; 489 u_int32_t addr, len; 490{ 491 int segptr, segsize, cnt; 492 493 segptr = addr; 494 cnt = len; 495 496 while (cnt) { 497 if (cnt < TI_WINLEN) 498 segsize = cnt; 499 else 500 segsize = TI_WINLEN - (segptr % TI_WINLEN); 501 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 502 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 503 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 504 segptr += segsize; 505 cnt -= segsize; 506 } 507} 508 509static int 510ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 511 struct ti_softc *sc; 512 u_int32_t tigon_addr, len; 513 caddr_t buf; 514 int useraddr, readdata; 515{ 516 int segptr, segsize, cnt; 517 caddr_t ptr; 518 u_int32_t origwin; 519 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 520 int resid, segresid; 521 int first_pass; 522 523 TI_LOCK_ASSERT(sc); 524 525 /* 526 * At the moment, we don't handle non-aligned cases, we just bail. 527 * If this proves to be a problem, it will be fixed. 528 */ 529 if ((readdata == 0) 530 && (tigon_addr & 0x3)) { 531 if_printf(sc->ti_ifp, "ti_copy_mem: tigon address %#x isn't " 532 "word-aligned\n", tigon_addr); 533 if_printf(sc->ti_ifp, "ti_copy_mem: unaligned writes aren't " 534 "yet supported\n"); 535 return (EINVAL); 536 } 537 538 segptr = tigon_addr & ~0x3; 539 segresid = tigon_addr - segptr; 540 541 /* 542 * This is the non-aligned amount left over that we'll need to 543 * copy. 544 */ 545 resid = len & 0x3; 546 547 /* Add in the left over amount at the front of the buffer */ 548 resid += segresid; 549 550 cnt = len & ~0x3; 551 /* 552 * If resid + segresid is >= 4, add multiples of 4 to the count and 553 * decrease the residual by that much. 554 */ 555 cnt += resid & ~0x3; 556 resid -= resid & ~0x3; 557 558 ptr = buf; 559 560 first_pass = 1; 561 562 /* 563 * Save the old window base value. 564 */ 565 origwin = CSR_READ_4(sc, TI_WINBASE); 566 567 while (cnt) { 568 bus_size_t ti_offset; 569 570 if (cnt < TI_WINLEN) 571 segsize = cnt; 572 else 573 segsize = TI_WINLEN - (segptr % TI_WINLEN); 574 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 575 576 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 577 578 if (readdata) { 579 580 bus_space_read_region_4(sc->ti_btag, 581 sc->ti_bhandle, ti_offset, 582 (u_int32_t *)tmparray, 583 segsize >> 2); 584 if (useraddr) { 585 /* 586 * Yeah, this is a little on the kludgy 587 * side, but at least this code is only 588 * used for debugging. 589 */ 590 ti_bcopy_swap(tmparray, tmparray2, segsize, 591 TI_SWAP_NTOH); 592 593 TI_UNLOCK(sc); 594 if (first_pass) { 595 copyout(&tmparray2[segresid], ptr, 596 segsize - segresid); 597 first_pass = 0; 598 } else 599 copyout(tmparray2, ptr, segsize); 600 TI_LOCK(sc); 601 } else { 602 if (first_pass) { 603 604 ti_bcopy_swap(tmparray, tmparray2, 605 segsize, TI_SWAP_NTOH); 606 TI_UNLOCK(sc); 607 bcopy(&tmparray2[segresid], ptr, 608 segsize - segresid); 609 TI_LOCK(sc); 610 first_pass = 0; 611 } else 612 ti_bcopy_swap(tmparray, ptr, segsize, 613 TI_SWAP_NTOH); 614 } 615 616 } else { 617 if (useraddr) { 618 TI_UNLOCK(sc); 619 copyin(ptr, tmparray2, segsize); 620 TI_LOCK(sc); 621 ti_bcopy_swap(tmparray2, tmparray, segsize, 622 TI_SWAP_HTON); 623 } else 624 ti_bcopy_swap(ptr, tmparray, segsize, 625 TI_SWAP_HTON); 626 627 bus_space_write_region_4(sc->ti_btag, 628 sc->ti_bhandle, ti_offset, 629 (u_int32_t *)tmparray, 630 segsize >> 2); 631 } 632 segptr += segsize; 633 ptr += segsize; 634 cnt -= segsize; 635 } 636 637 /* 638 * Handle leftover, non-word-aligned bytes. 639 */ 640 if (resid != 0) { 641 u_int32_t tmpval, tmpval2; 642 bus_size_t ti_offset; 643 644 /* 645 * Set the segment pointer. 646 */ 647 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 648 649 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 650 651 /* 652 * First, grab whatever is in our source/destination. 653 * We'll obviously need this for reads, but also for 654 * writes, since we'll be doing read/modify/write. 655 */ 656 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 657 ti_offset, &tmpval, 1); 658 659 /* 660 * Next, translate this from little-endian to big-endian 661 * (at least on i386 boxes). 662 */ 663 tmpval2 = ntohl(tmpval); 664 665 if (readdata) { 666 /* 667 * If we're reading, just copy the leftover number 668 * of bytes from the host byte order buffer to 669 * the user's buffer. 670 */ 671 if (useraddr) { 672 TI_UNLOCK(sc); 673 copyout(&tmpval2, ptr, resid); 674 TI_LOCK(sc); 675 } else 676 bcopy(&tmpval2, ptr, resid); 677 } else { 678 /* 679 * If we're writing, first copy the bytes to be 680 * written into the network byte order buffer, 681 * leaving the rest of the buffer with whatever was 682 * originally in there. Then, swap the bytes 683 * around into host order and write them out. 684 * 685 * XXX KDM the read side of this has been verified 686 * to work, but the write side of it has not been 687 * verified. So user beware. 688 */ 689 if (useraddr) { 690 TI_UNLOCK(sc); 691 copyin(ptr, &tmpval2, resid); 692 TI_LOCK(sc); 693 } else 694 bcopy(ptr, &tmpval2, resid); 695 696 tmpval = htonl(tmpval2); 697 698 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 699 ti_offset, &tmpval, 1); 700 } 701 } 702 703 CSR_WRITE_4(sc, TI_WINBASE, origwin); 704 705 return (0); 706} 707 708static int 709ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 710 struct ti_softc *sc; 711 u_int32_t tigon_addr, len; 712 caddr_t buf; 713 int useraddr, readdata; 714 int cpu; 715{ 716 u_int32_t segptr; 717 int cnt; 718 u_int32_t tmpval, tmpval2; 719 caddr_t ptr; 720 721 TI_LOCK_ASSERT(sc); 722 723 /* 724 * At the moment, we don't handle non-aligned cases, we just bail. 725 * If this proves to be a problem, it will be fixed. 726 */ 727 if (tigon_addr & 0x3) { 728 if_printf(sc->ti_ifp, "ti_copy_scratch: tigon address %#x " 729 "isn't word-aligned\n", tigon_addr); 730 return (EINVAL); 731 } 732 733 if (len & 0x3) { 734 if_printf(sc->ti_ifp, "ti_copy_scratch: transfer length %d " 735 "isn't word-aligned\n", len); 736 return (EINVAL); 737 } 738 739 segptr = tigon_addr; 740 cnt = len; 741 ptr = buf; 742 743 while (cnt) { 744 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 745 746 if (readdata) { 747 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 748 749 tmpval = ntohl(tmpval2); 750 751 /* 752 * Note: I've used this debugging interface 753 * extensively with Alteon's 12.3.15 firmware, 754 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 755 * 756 * When you compile the firmware without 757 * optimization, which is necessary sometimes in 758 * order to properly step through it, you sometimes 759 * read out a bogus value of 0xc0017c instead of 760 * whatever was supposed to be in that scratchpad 761 * location. That value is on the stack somewhere, 762 * but I've never been able to figure out what was 763 * causing the problem. 764 * 765 * The address seems to pop up in random places, 766 * often not in the same place on two subsequent 767 * reads. 768 * 769 * In any case, the underlying data doesn't seem 770 * to be affected, just the value read out. 771 * 772 * KDM, 3/7/2000 773 */ 774 775 if (tmpval2 == 0xc0017c) 776 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 777 "(tmpval2)\n", segptr); 778 779 if (tmpval == 0xc0017c) 780 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 781 "(tmpval)\n", segptr); 782 783 if (useraddr) 784 copyout(&tmpval, ptr, 4); 785 else 786 bcopy(&tmpval, ptr, 4); 787 } else { 788 if (useraddr) 789 copyin(ptr, &tmpval2, 4); 790 else 791 bcopy(ptr, &tmpval2, 4); 792 793 tmpval = htonl(tmpval2); 794 795 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 796 } 797 798 cnt -= 4; 799 segptr += 4; 800 ptr += 4; 801 } 802 803 return (0); 804} 805 806static int 807ti_bcopy_swap(src, dst, len, swap_type) 808 const void *src; 809 void *dst; 810 size_t len; 811 ti_swap_type swap_type; 812{ 813 const u_int8_t *tmpsrc; 814 u_int8_t *tmpdst; 815 size_t tmplen; 816 817 if (len & 0x3) { 818 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 819 len); 820 return (-1); 821 } 822 823 tmpsrc = src; 824 tmpdst = dst; 825 tmplen = len; 826 827 while (tmplen) { 828 if (swap_type == TI_SWAP_NTOH) 829 *(u_int32_t *)tmpdst = 830 ntohl(*(const u_int32_t *)tmpsrc); 831 else 832 *(u_int32_t *)tmpdst = 833 htonl(*(const u_int32_t *)tmpsrc); 834 835 tmpsrc += 4; 836 tmpdst += 4; 837 tmplen -= 4; 838 } 839 840 return (0); 841} 842 843/* 844 * Load firmware image into the NIC. Check that the firmware revision 845 * is acceptable and see if we want the firmware for the Tigon 1 or 846 * Tigon 2. 847 */ 848static void 849ti_loadfw(sc) 850 struct ti_softc *sc; 851{ 852 853 TI_LOCK_ASSERT(sc); 854 855 switch (sc->ti_hwrev) { 856 case TI_HWREV_TIGON: 857 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 858 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 859 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 860 if_printf(sc->ti_ifp, "firmware revision mismatch; " 861 "want %d.%d.%d, got %d.%d.%d\n", 862 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 863 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 864 tigonFwReleaseMinor, tigonFwReleaseFix); 865 return; 866 } 867 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 868 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 869 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 870 tigonFwRodata); 871 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 872 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 873 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 874 break; 875 case TI_HWREV_TIGON_II: 876 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 877 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 878 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 879 if_printf(sc->ti_ifp, "firmware revision mismatch; " 880 "want %d.%d.%d, got %d.%d.%d\n", 881 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 882 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 883 tigon2FwReleaseMinor, tigon2FwReleaseFix); 884 return; 885 } 886 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 887 tigon2FwText); 888 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 889 tigon2FwData); 890 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 891 tigon2FwRodata); 892 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 893 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 894 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 895 break; 896 default: 897 if_printf(sc->ti_ifp, 898 "can't load firmware: unknown hardware rev\n"); 899 break; 900 } 901} 902 903/* 904 * Send the NIC a command via the command ring. 905 */ 906static void 907ti_cmd(sc, cmd) 908 struct ti_softc *sc; 909 struct ti_cmd_desc *cmd; 910{ 911 u_int32_t index; 912 913 index = sc->ti_cmd_saved_prodidx; 914 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 915 TI_INC(index, TI_CMD_RING_CNT); 916 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 917 sc->ti_cmd_saved_prodidx = index; 918} 919 920/* 921 * Send the NIC an extended command. The 'len' parameter specifies the 922 * number of command slots to include after the initial command. 923 */ 924static void 925ti_cmd_ext(sc, cmd, arg, len) 926 struct ti_softc *sc; 927 struct ti_cmd_desc *cmd; 928 caddr_t arg; 929 int len; 930{ 931 u_int32_t index; 932 int i; 933 934 index = sc->ti_cmd_saved_prodidx; 935 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 936 TI_INC(index, TI_CMD_RING_CNT); 937 for (i = 0; i < len; i++) { 938 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 939 *(u_int32_t *)(&arg[i * 4])); 940 TI_INC(index, TI_CMD_RING_CNT); 941 } 942 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 943 sc->ti_cmd_saved_prodidx = index; 944} 945 946/* 947 * Handle events that have triggered interrupts. 948 */ 949static void 950ti_handle_events(sc) 951 struct ti_softc *sc; 952{ 953 struct ti_event_desc *e; 954 955 if (sc->ti_rdata->ti_event_ring == NULL) 956 return; 957 958 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 959 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 960 switch (TI_EVENT_EVENT(e)) { 961 case TI_EV_LINKSTAT_CHANGED: 962 sc->ti_linkstat = TI_EVENT_CODE(e); 963 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 964 if_printf(sc->ti_ifp, "10/100 link up\n"); 965 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 966 if_printf(sc->ti_ifp, "gigabit link up\n"); 967 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 968 if_printf(sc->ti_ifp, "link down\n"); 969 break; 970 case TI_EV_ERROR: 971 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 972 if_printf(sc->ti_ifp, "invalid command\n"); 973 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 974 if_printf(sc->ti_ifp, "unknown command\n"); 975 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 976 if_printf(sc->ti_ifp, "bad config data\n"); 977 break; 978 case TI_EV_FIRMWARE_UP: 979 ti_init2(sc); 980 break; 981 case TI_EV_STATS_UPDATED: 982 ti_stats_update(sc); 983 break; 984 case TI_EV_RESET_JUMBO_RING: 985 case TI_EV_MCAST_UPDATED: 986 /* Who cares. */ 987 break; 988 default: 989 if_printf(sc->ti_ifp, "unknown event: %d\n", 990 TI_EVENT_EVENT(e)); 991 break; 992 } 993 /* Advance the consumer index. */ 994 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 995 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 996 } 997} 998 999static int 1000ti_alloc_dmamaps(struct ti_softc *sc) 1001{ 1002 int i; 1003 1004 for (i = 0; i < TI_TX_RING_CNT; i++) { 1005 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006 &sc->ti_cdata.ti_tx_maps[i])) 1007 return (ENOBUFS); 1008 } 1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011 &sc->ti_cdata.ti_rx_std_maps[i])) 1012 return (ENOBUFS); 1013 } 1014 1015 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018 return (ENOBUFS); 1019 } 1020 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022 &sc->ti_cdata.ti_rx_mini_maps[i])) 1023 return (ENOBUFS); 1024 } 1025 1026 return (0); 1027} 1028 1029static void 1030ti_free_dmamaps(struct ti_softc *sc) 1031{ 1032 int i; 1033 1034 if (sc->ti_mbuftx_dmat) 1035 for (i = 0; i < TI_TX_RING_CNT; i++) 1036 if (sc->ti_cdata.ti_tx_maps[i]) { 1037 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038 sc->ti_cdata.ti_tx_maps[i]); 1039 sc->ti_cdata.ti_tx_maps[i] = 0; 1040 } 1041 1042 if (sc->ti_mbufrx_dmat) 1043 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046 sc->ti_cdata.ti_rx_std_maps[i]); 1047 sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048 } 1049 1050 if (sc->ti_jumbo_dmat) 1051 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056 } 1057 if (sc->ti_mbufrx_dmat) 1058 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061 sc->ti_cdata.ti_rx_mini_maps[i]); 1062 sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063 } 1064} 1065 1066#ifdef TI_PRIVATE_JUMBOS 1067 1068/* 1069 * Memory management for the jumbo receive ring is a pain in the 1070 * butt. We need to allocate at least 9018 bytes of space per frame, 1071 * _and_ it has to be contiguous (unless you use the extended 1072 * jumbo descriptor format). Using malloc() all the time won't 1073 * work: malloc() allocates memory in powers of two, which means we 1074 * would end up wasting a considerable amount of space by allocating 1075 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1076 * to do our own memory management. 1077 * 1078 * The driver needs to allocate a contiguous chunk of memory at boot 1079 * time. We then chop this up ourselves into 9K pieces and use them 1080 * as external mbuf storage. 1081 * 1082 * One issue here is how much memory to allocate. The jumbo ring has 1083 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1084 * RAM. This is a bit much, especially considering we also need 1085 * RAM for the standard ring and mini ring (on the Tigon 2). To 1086 * save space, we only actually allocate enough memory for 64 slots 1087 * by default, which works out to between 500 and 600K. This can 1088 * be tuned by changing a #define in if_tireg.h. 1089 */ 1090 1091static int 1092ti_alloc_jumbo_mem(sc) 1093 struct ti_softc *sc; 1094{ 1095 caddr_t ptr; 1096 int i; 1097 struct ti_jpool_entry *entry; 1098 1099 /* 1100 * Grab a big chunk o' storage. Since we are chopping this pool up 1101 * into ~9k chunks, there doesn't appear to be a need to use page 1102 * alignment. 1103 */ 1104 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105 1, 0, /* algnmnt, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 TI_JMEM, /* maxsize */ 1110 1, /* nsegments */ 1111 TI_JMEM, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ti_jumbo_dmat) != 0) { 1115 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116 return (ENOBUFS); 1117 } 1118 1119 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120 (void**)&sc->ti_cdata.ti_jumbo_buf, 1121 BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) { 1122 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1123 return (ENOBUFS); 1124 } 1125 1126 SLIST_INIT(&sc->ti_jfree_listhead); 1127 SLIST_INIT(&sc->ti_jinuse_listhead); 1128 1129 /* 1130 * Now divide it up into 9K pieces and save the addresses 1131 * in an array. 1132 */ 1133 ptr = sc->ti_cdata.ti_jumbo_buf; 1134 for (i = 0; i < TI_JSLOTS; i++) { 1135 sc->ti_cdata.ti_jslots[i] = ptr; 1136 ptr += TI_JLEN; 1137 entry = malloc(sizeof(struct ti_jpool_entry), 1138 M_DEVBUF, M_NOWAIT); 1139 if (entry == NULL) { 1140 device_printf(sc->ti_dev, "no memory for jumbo " 1141 "buffer queue!\n"); 1142 return (ENOBUFS); 1143 } 1144 entry->slot = i; 1145 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1146 } 1147 1148 return (0); 1149} 1150 1151/* 1152 * Allocate a jumbo buffer. 1153 */ 1154static void *ti_jalloc(sc) 1155 struct ti_softc *sc; 1156{ 1157 struct ti_jpool_entry *entry; 1158 1159 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1160 1161 if (entry == NULL) { 1162 if_printf(sc->ti_ifp, "no free jumbo buffers\n"); 1163 return (NULL); 1164 } 1165 1166 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1167 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1168 return (sc->ti_cdata.ti_jslots[entry->slot]); 1169} 1170 1171/* 1172 * Release a jumbo buffer. 1173 */ 1174static void 1175ti_jfree(buf, args) 1176 void *buf; 1177 void *args; 1178{ 1179 struct ti_softc *sc; 1180 int i; 1181 struct ti_jpool_entry *entry; 1182 1183 /* Extract the softc struct pointer. */ 1184 sc = (struct ti_softc *)args; 1185 1186 if (sc == NULL) 1187 panic("ti_jfree: didn't get softc pointer!"); 1188 1189 /* calculate the slot this buffer belongs to */ 1190 i = ((vm_offset_t)buf 1191 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1192 1193 if ((i < 0) || (i >= TI_JSLOTS)) 1194 panic("ti_jfree: asked to free buffer that we don't manage!"); 1195 1196 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1197 if (entry == NULL) 1198 panic("ti_jfree: buffer not in use!"); 1199 entry->slot = i; 1200 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1201 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1202} 1203 1204#else 1205 1206static int 1207ti_alloc_jumbo_mem(sc) 1208 struct ti_softc *sc; 1209{ 1210 1211 /* 1212 * The VM system will take care of providing aligned pages. Alignment 1213 * is set to 1 here so that busdma resources won't be wasted. 1214 */ 1215 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1216 1, 0, /* algnmnt, boundary */ 1217 BUS_SPACE_MAXADDR, /* lowaddr */ 1218 BUS_SPACE_MAXADDR, /* highaddr */ 1219 NULL, NULL, /* filter, filterarg */ 1220 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1221 4, /* nsegments */ 1222 PAGE_SIZE, /* maxsegsize */ 1223 0, /* flags */ 1224 NULL, NULL, /* lockfunc, lockarg */ 1225 &sc->ti_jumbo_dmat) != 0) { 1226 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1227 return (ENOBUFS); 1228 } 1229 1230 return (0); 1231} 1232 1233#endif /* TI_PRIVATE_JUMBOS */ 1234 1235/* 1236 * Intialize a standard receive ring descriptor. 1237 */ 1238static int 1239ti_newbuf_std(sc, i, m) 1240 struct ti_softc *sc; 1241 int i; 1242 struct mbuf *m; 1243{ 1244 bus_dmamap_t map; 1245 bus_dma_segment_t segs; 1246 struct mbuf *m_new = NULL; 1247 struct ti_rx_desc *r; 1248 int nsegs; 1249 1250 nsegs = 0; 1251 if (m == NULL) { 1252 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1253 if (m_new == NULL) 1254 return (ENOBUFS); 1255 1256 MCLGET(m_new, M_DONTWAIT); 1257 if (!(m_new->m_flags & M_EXT)) { 1258 m_freem(m_new); 1259 return (ENOBUFS); 1260 } 1261 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1262 } else { 1263 m_new = m; 1264 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1265 m_new->m_data = m_new->m_ext.ext_buf; 1266 } 1267 1268 m_adj(m_new, ETHER_ALIGN); 1269 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1270 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1271 map = sc->ti_cdata.ti_rx_std_maps[i]; 1272 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1273 &nsegs, 0)) 1274 return (ENOBUFS); 1275 if (nsegs != 1) 1276 return (ENOBUFS); 1277 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1278 r->ti_len = segs.ds_len; 1279 r->ti_type = TI_BDTYPE_RECV_BD; 1280 r->ti_flags = 0; 1281 if (sc->ti_ifp->if_hwassist) 1282 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1283 r->ti_idx = i; 1284 1285 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1286 return (0); 1287} 1288 1289/* 1290 * Intialize a mini receive ring descriptor. This only applies to 1291 * the Tigon 2. 1292 */ 1293static int 1294ti_newbuf_mini(sc, i, m) 1295 struct ti_softc *sc; 1296 int i; 1297 struct mbuf *m; 1298{ 1299 bus_dma_segment_t segs; 1300 bus_dmamap_t map; 1301 struct mbuf *m_new = NULL; 1302 struct ti_rx_desc *r; 1303 int nsegs; 1304 1305 nsegs = 0; 1306 if (m == NULL) { 1307 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1308 if (m_new == NULL) { 1309 return (ENOBUFS); 1310 } 1311 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1312 } else { 1313 m_new = m; 1314 m_new->m_data = m_new->m_pktdat; 1315 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1316 } 1317 1318 m_adj(m_new, ETHER_ALIGN); 1319 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1320 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1321 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1322 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1323 &nsegs, 0)) 1324 return (ENOBUFS); 1325 if (nsegs != 1) 1326 return (ENOBUFS); 1327 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1328 r->ti_len = segs.ds_len; 1329 r->ti_type = TI_BDTYPE_RECV_BD; 1330 r->ti_flags = TI_BDFLAG_MINI_RING; 1331 if (sc->ti_ifp->if_hwassist) 1332 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1333 r->ti_idx = i; 1334 1335 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1336 return (0); 1337} 1338 1339#ifdef TI_PRIVATE_JUMBOS 1340 1341/* 1342 * Initialize a jumbo receive ring descriptor. This allocates 1343 * a jumbo buffer from the pool managed internally by the driver. 1344 */ 1345static int 1346ti_newbuf_jumbo(sc, i, m) 1347 struct ti_softc *sc; 1348 int i; 1349 struct mbuf *m; 1350{ 1351 bus_dmamap_t map; 1352 struct mbuf *m_new = NULL; 1353 struct ti_rx_desc *r; 1354 int nsegs; 1355 bus_dma_segment_t segs; 1356 1357 if (m == NULL) { 1358 caddr_t *buf = NULL; 1359 1360 /* Allocate the mbuf. */ 1361 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1362 if (m_new == NULL) { 1363 return (ENOBUFS); 1364 } 1365 1366 /* Allocate the jumbo buffer */ 1367 buf = ti_jalloc(sc); 1368 if (buf == NULL) { 1369 m_freem(m_new); 1370 if_printf(sc->ti_ifp, "jumbo allocation failed " 1371 "-- packet dropped!\n"); 1372 return (ENOBUFS); 1373 } 1374 1375 /* Attach the buffer to the mbuf. */ 1376 m_new->m_data = (void *) buf; 1377 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1378 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1379 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1380 } else { 1381 m_new = m; 1382 m_new->m_data = m_new->m_ext.ext_buf; 1383 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1384 } 1385 1386 m_adj(m_new, ETHER_ALIGN); 1387 /* Set up the descriptor. */ 1388 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1389 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1390 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1391 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1392 &nsegs, 0)) 1393 return (ENOBUFS); 1394 if (nsegs != 1) 1395 return (ENOBUFS); 1396 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1397 r->ti_len = segs.ds_len; 1398 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1399 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1400 if (sc->ti_ifp->if_hwassist) 1401 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1402 r->ti_idx = i; 1403 1404 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1405 return (0); 1406} 1407 1408#else 1409 1410#if (PAGE_SIZE == 4096) 1411#define NPAYLOAD 2 1412#else 1413#define NPAYLOAD 1 1414#endif 1415 1416#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1417#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1418#define NFS_HDR_LEN (UDP_HDR_LEN) 1419static int HDR_LEN = TCP_HDR_LEN; 1420 1421 1422/* 1423 * Initialize a jumbo receive ring descriptor. This allocates 1424 * a jumbo buffer from the pool managed internally by the driver. 1425 */ 1426static int 1427ti_newbuf_jumbo(sc, idx, m_old) 1428 struct ti_softc *sc; 1429 int idx; 1430 struct mbuf *m_old; 1431{ 1432 bus_dmamap_t map; 1433 struct mbuf *cur, *m_new = NULL; 1434 struct mbuf *m[3] = {NULL, NULL, NULL}; 1435 struct ti_rx_desc_ext *r; 1436 vm_page_t frame; 1437 static int color; 1438 /* 1 extra buf to make nobufs easy*/ 1439 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1440 int i; 1441 bus_dma_segment_t segs[4]; 1442 int nsegs; 1443 1444 if (m_old != NULL) { 1445 m_new = m_old; 1446 cur = m_old->m_next; 1447 for (i = 0; i <= NPAYLOAD; i++){ 1448 m[i] = cur; 1449 cur = cur->m_next; 1450 } 1451 } else { 1452 /* Allocate the mbufs. */ 1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1454 if (m_new == NULL) { 1455 if_printf(sc->ti_ifp, "mbuf allocation failed " 1456 "-- packet dropped!\n"); 1457 goto nobufs; 1458 } 1459 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1460 if (m[NPAYLOAD] == NULL) { 1461 if_printf(sc->ti_ifp, "cluster mbuf allocation failed " 1462 "-- packet dropped!\n"); 1463 goto nobufs; 1464 } 1465 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1466 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1467 if_printf(sc->ti_ifp, "mbuf allocation failed " 1468 "-- packet dropped!\n"); 1469 goto nobufs; 1470 } 1471 m[NPAYLOAD]->m_len = MCLBYTES; 1472 1473 for (i = 0; i < NPAYLOAD; i++){ 1474 MGET(m[i], M_DONTWAIT, MT_DATA); 1475 if (m[i] == NULL) { 1476 if_printf(sc->ti_ifp, "mbuf allocation failed " 1477 "-- packet dropped!\n"); 1478 goto nobufs; 1479 } 1480 frame = vm_page_alloc(NULL, color++, 1481 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1482 VM_ALLOC_WIRED); 1483 if (frame == NULL) { 1484 if_printf(sc->ti_ifp, "buffer allocation " 1485 "failed -- packet dropped!\n"); 1486 printf(" index %d page %d\n", idx, i); 1487 goto nobufs; 1488 } 1489 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1490 if (sf[i] == NULL) { 1491 vm_page_lock_queues(); 1492 vm_page_unwire(frame, 0); 1493 vm_page_free(frame); 1494 vm_page_unlock_queues(); 1495 if_printf(sc->ti_ifp, "buffer allocation " 1496 "failed -- packet dropped!\n"); 1497 printf(" index %d page %d\n", idx, i); 1498 goto nobufs; 1499 } 1500 } 1501 for (i = 0; i < NPAYLOAD; i++){ 1502 /* Attach the buffer to the mbuf. */ 1503 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1504 m[i]->m_len = PAGE_SIZE; 1505 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1506 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 1507 m[i]->m_next = m[i+1]; 1508 } 1509 /* link the buffers to the header */ 1510 m_new->m_next = m[0]; 1511 m_new->m_data += ETHER_ALIGN; 1512 if (sc->ti_hdrsplit) 1513 m_new->m_len = MHLEN - ETHER_ALIGN; 1514 else 1515 m_new->m_len = HDR_LEN; 1516 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1517 } 1518 1519 /* Set up the descriptor. */ 1520 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1521 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1522 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1523 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1524 &nsegs, 0)) 1525 return (ENOBUFS); 1526 if ((nsegs < 1) || (nsegs > 4)) 1527 return (ENOBUFS); 1528 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1529 r->ti_len0 = m_new->m_len; 1530 1531 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1532 r->ti_len1 = PAGE_SIZE; 1533 1534 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1535 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1536 1537 if (PAGE_SIZE == 4096) { 1538 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1539 r->ti_len3 = MCLBYTES; 1540 } else { 1541 r->ti_len3 = 0; 1542 } 1543 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1544 1545 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1546 1547 if (sc->ti_ifp->if_hwassist) 1548 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1549 1550 r->ti_idx = idx; 1551 1552 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1553 return (0); 1554 1555nobufs: 1556 1557 /* 1558 * Warning! : 1559 * This can only be called before the mbufs are strung together. 1560 * If the mbufs are strung together, m_freem() will free the chain, 1561 * so that the later mbufs will be freed multiple times. 1562 */ 1563 if (m_new) 1564 m_freem(m_new); 1565 1566 for (i = 0; i < 3; i++) { 1567 if (m[i]) 1568 m_freem(m[i]); 1569 if (sf[i]) 1570 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1571 } 1572 return (ENOBUFS); 1573} 1574#endif 1575 1576 1577 1578/* 1579 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1580 * that's 1MB or memory, which is a lot. For now, we fill only the first 1581 * 256 ring entries and hope that our CPU is fast enough to keep up with 1582 * the NIC. 1583 */ 1584static int 1585ti_init_rx_ring_std(sc) 1586 struct ti_softc *sc; 1587{ 1588 int i; 1589 struct ti_cmd_desc cmd; 1590 1591 for (i = 0; i < TI_SSLOTS; i++) { 1592 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1593 return (ENOBUFS); 1594 }; 1595 1596 TI_UPDATE_STDPROD(sc, i - 1); 1597 sc->ti_std = i - 1; 1598 1599 return (0); 1600} 1601 1602static void 1603ti_free_rx_ring_std(sc) 1604 struct ti_softc *sc; 1605{ 1606 bus_dmamap_t map; 1607 int i; 1608 1609 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1610 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1611 map = sc->ti_cdata.ti_rx_std_maps[i]; 1612 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1613 BUS_DMASYNC_POSTREAD); 1614 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1615 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1616 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1617 } 1618 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1619 sizeof(struct ti_rx_desc)); 1620 } 1621} 1622 1623static int 1624ti_init_rx_ring_jumbo(sc) 1625 struct ti_softc *sc; 1626{ 1627 int i; 1628 struct ti_cmd_desc cmd; 1629 1630 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1631 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1632 return (ENOBUFS); 1633 }; 1634 1635 TI_UPDATE_JUMBOPROD(sc, i - 1); 1636 sc->ti_jumbo = i - 1; 1637 1638 return (0); 1639} 1640 1641static void 1642ti_free_rx_ring_jumbo(sc) 1643 struct ti_softc *sc; 1644{ 1645 bus_dmamap_t map; 1646 int i; 1647 1648 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1649 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1650 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1651 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1652 BUS_DMASYNC_POSTREAD); 1653 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1654 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1655 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1656 } 1657 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1658 sizeof(struct ti_rx_desc)); 1659 } 1660} 1661 1662static int 1663ti_init_rx_ring_mini(sc) 1664 struct ti_softc *sc; 1665{ 1666 int i; 1667 1668 for (i = 0; i < TI_MSLOTS; i++) { 1669 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1670 return (ENOBUFS); 1671 }; 1672 1673 TI_UPDATE_MINIPROD(sc, i - 1); 1674 sc->ti_mini = i - 1; 1675 1676 return (0); 1677} 1678 1679static void 1680ti_free_rx_ring_mini(sc) 1681 struct ti_softc *sc; 1682{ 1683 bus_dmamap_t map; 1684 int i; 1685 1686 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1687 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1688 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1689 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1690 BUS_DMASYNC_POSTREAD); 1691 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1692 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1693 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1694 } 1695 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1696 sizeof(struct ti_rx_desc)); 1697 } 1698} 1699 1700static void 1701ti_free_tx_ring(sc) 1702 struct ti_softc *sc; 1703{ 1704 bus_dmamap_t map; 1705 int i; 1706 1707 if (sc->ti_rdata->ti_tx_ring == NULL) 1708 return; 1709 1710 for (i = 0; i < TI_TX_RING_CNT; i++) { 1711 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1712 map = sc->ti_cdata.ti_tx_maps[i]; 1713 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 1716 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1717 sc->ti_cdata.ti_tx_chain[i] = NULL; 1718 } 1719 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1720 sizeof(struct ti_tx_desc)); 1721 } 1722} 1723 1724static int 1725ti_init_tx_ring(sc) 1726 struct ti_softc *sc; 1727{ 1728 sc->ti_txcnt = 0; 1729 sc->ti_tx_saved_considx = 0; 1730 sc->ti_tx_saved_prodidx = 0; 1731 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1732 return (0); 1733} 1734 1735/* 1736 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1737 * but we have to support the old way too so that Tigon 1 cards will 1738 * work. 1739 */ 1740static void 1741ti_add_mcast(sc, addr) 1742 struct ti_softc *sc; 1743 struct ether_addr *addr; 1744{ 1745 struct ti_cmd_desc cmd; 1746 u_int16_t *m; 1747 u_int32_t ext[2] = {0, 0}; 1748 1749 m = (u_int16_t *)&addr->octet[0]; 1750 1751 switch (sc->ti_hwrev) { 1752 case TI_HWREV_TIGON: 1753 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1754 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1755 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1756 break; 1757 case TI_HWREV_TIGON_II: 1758 ext[0] = htons(m[0]); 1759 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1760 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1761 break; 1762 default: 1763 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1764 break; 1765 } 1766} 1767 1768static void 1769ti_del_mcast(sc, addr) 1770 struct ti_softc *sc; 1771 struct ether_addr *addr; 1772{ 1773 struct ti_cmd_desc cmd; 1774 u_int16_t *m; 1775 u_int32_t ext[2] = {0, 0}; 1776 1777 m = (u_int16_t *)&addr->octet[0]; 1778 1779 switch (sc->ti_hwrev) { 1780 case TI_HWREV_TIGON: 1781 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1782 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1783 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1784 break; 1785 case TI_HWREV_TIGON_II: 1786 ext[0] = htons(m[0]); 1787 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1788 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1789 break; 1790 default: 1791 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1792 break; 1793 } 1794} 1795 1796/* 1797 * Configure the Tigon's multicast address filter. 1798 * 1799 * The actual multicast table management is a bit of a pain, thanks to 1800 * slight brain damage on the part of both Alteon and us. With our 1801 * multicast code, we are only alerted when the multicast address table 1802 * changes and at that point we only have the current list of addresses: 1803 * we only know the current state, not the previous state, so we don't 1804 * actually know what addresses were removed or added. The firmware has 1805 * state, but we can't get our grubby mits on it, and there is no 'delete 1806 * all multicast addresses' command. Hence, we have to maintain our own 1807 * state so we know what addresses have been programmed into the NIC at 1808 * any given time. 1809 */ 1810static void 1811ti_setmulti(sc) 1812 struct ti_softc *sc; 1813{ 1814 struct ifnet *ifp; 1815 struct ifmultiaddr *ifma; 1816 struct ti_cmd_desc cmd; 1817 struct ti_mc_entry *mc; 1818 u_int32_t intrs; 1819 1820 TI_LOCK_ASSERT(sc); 1821 1822 ifp = sc->ti_ifp; 1823 1824 if (ifp->if_flags & IFF_ALLMULTI) { 1825 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1826 return; 1827 } else { 1828 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1829 } 1830 1831 /* Disable interrupts. */ 1832 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1833 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1834 1835 /* First, zot all the existing filters. */ 1836 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1837 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1838 ti_del_mcast(sc, &mc->mc_addr); 1839 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1840 free(mc, M_DEVBUF); 1841 } 1842 1843 /* Now program new ones. */ 1844 IF_ADDR_LOCK(ifp); 1845 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1846 if (ifma->ifma_addr->sa_family != AF_LINK) 1847 continue; 1848 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1849 if (mc == NULL) { 1850 if_printf(ifp, "no memory for mcast filter entry\n"); 1851 continue; 1852 } 1853 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1854 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1855 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1856 ti_add_mcast(sc, &mc->mc_addr); 1857 } 1858 IF_ADDR_UNLOCK(ifp); 1859 1860 /* Re-enable interrupts. */ 1861 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1862} 1863 1864/* 1865 * Check to see if the BIOS has configured us for a 64 bit slot when 1866 * we aren't actually in one. If we detect this condition, we can work 1867 * around it on the Tigon 2 by setting a bit in the PCI state register, 1868 * but for the Tigon 1 we must give up and abort the interface attach. 1869 */ 1870static int ti_64bitslot_war(sc) 1871 struct ti_softc *sc; 1872{ 1873 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1874 CSR_WRITE_4(sc, 0x600, 0); 1875 CSR_WRITE_4(sc, 0x604, 0); 1876 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1877 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1878 if (sc->ti_hwrev == TI_HWREV_TIGON) 1879 return (EINVAL); 1880 else { 1881 TI_SETBIT(sc, TI_PCI_STATE, 1882 TI_PCISTATE_32BIT_BUS); 1883 return (0); 1884 } 1885 } 1886 } 1887 1888 return (0); 1889} 1890 1891/* 1892 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1893 * self-test results. 1894 */ 1895static int 1896ti_chipinit(sc) 1897 struct ti_softc *sc; 1898{ 1899 u_int32_t cacheline; 1900 u_int32_t pci_writemax = 0; 1901 u_int32_t hdrsplit; 1902 1903 /* Initialize link to down state. */ 1904 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1905 1906 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1907 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1908 else 1909 sc->ti_ifp->if_hwassist = 0; 1910 1911 /* Set endianness before we access any non-PCI registers. */ 1912#if 0 && BYTE_ORDER == BIG_ENDIAN 1913 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1914 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1915#else 1916 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1917 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1918#endif 1919 1920 /* Check the ROM failed bit to see if self-tests passed. */ 1921 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1922 if_printf(sc->ti_ifp, "board self-diagnostics failed!\n"); 1923 return (ENODEV); 1924 } 1925 1926 /* Halt the CPU. */ 1927 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1928 1929 /* Figure out the hardware revision. */ 1930 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1931 case TI_REV_TIGON_I: 1932 sc->ti_hwrev = TI_HWREV_TIGON; 1933 break; 1934 case TI_REV_TIGON_II: 1935 sc->ti_hwrev = TI_HWREV_TIGON_II; 1936 break; 1937 default: 1938 if_printf(sc->ti_ifp, "unsupported chip revision\n"); 1939 return (ENODEV); 1940 } 1941 1942 /* Do special setup for Tigon 2. */ 1943 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1944 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1945 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1946 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1947 } 1948 1949 /* 1950 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1951 * can't do header splitting. 1952 */ 1953#ifdef TI_JUMBO_HDRSPLIT 1954 if (sc->ti_hwrev != TI_HWREV_TIGON) 1955 sc->ti_hdrsplit = 1; 1956 else 1957 if_printf(sc->ti_ifp, 1958 "can't do header splitting on a Tigon I board\n"); 1959#endif /* TI_JUMBO_HDRSPLIT */ 1960 1961 /* Set up the PCI state register. */ 1962 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1963 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1964 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1965 } 1966 1967 /* Clear the read/write max DMA parameters. */ 1968 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1969 TI_PCISTATE_READ_MAXDMA)); 1970 1971 /* Get cache line size. */ 1972 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1973 1974 /* 1975 * If the system has set enabled the PCI memory write 1976 * and invalidate command in the command register, set 1977 * the write max parameter accordingly. This is necessary 1978 * to use MWI with the Tigon 2. 1979 */ 1980 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1981 switch (cacheline) { 1982 case 1: 1983 case 4: 1984 case 8: 1985 case 16: 1986 case 32: 1987 case 64: 1988 break; 1989 default: 1990 /* Disable PCI memory write and invalidate. */ 1991 if (bootverbose) 1992 if_printf(sc->ti_ifp, "cache line size %d not " 1993 "supported; disabling PCI MWI\n", 1994 cacheline); 1995 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1996 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1997 break; 1998 } 1999 } 2000 2001#ifdef __brokenalpha__ 2002 /* 2003 * From the Alteon sample driver: 2004 * Must insure that we do not cross an 8K (bytes) boundary 2005 * for DMA reads. Our highest limit is 1K bytes. This is a 2006 * restriction on some ALPHA platforms with early revision 2007 * 21174 PCI chipsets, such as the AlphaPC 164lx 2008 */ 2009 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 2010#else 2011 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2012#endif 2013 2014 /* This sets the min dma param all the way up (0xff). */ 2015 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2016 2017 if (sc->ti_hdrsplit) 2018 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2019 else 2020 hdrsplit = 0; 2021 2022 /* Configure DMA variables. */ 2023#if BYTE_ORDER == BIG_ENDIAN 2024 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2025 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2026 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2027 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2028#else /* BYTE_ORDER */ 2029 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2030 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2031 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2032#endif /* BYTE_ORDER */ 2033 2034 /* 2035 * Only allow 1 DMA channel to be active at a time. 2036 * I don't think this is a good idea, but without it 2037 * the firmware racks up lots of nicDmaReadRingFull 2038 * errors. This is not compatible with hardware checksums. 2039 */ 2040 if (sc->ti_ifp->if_hwassist == 0) 2041 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2042 2043 /* Recommended settings from Tigon manual. */ 2044 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2045 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2046 2047 if (ti_64bitslot_war(sc)) { 2048 if_printf(sc->ti_ifp, "bios thinks we're in a 64 bit slot, " 2049 "but we aren't"); 2050 return (EINVAL); 2051 } 2052 2053 return (0); 2054} 2055 2056/* 2057 * Initialize the general information block and firmware, and 2058 * start the CPU(s) running. 2059 */ 2060static int 2061ti_gibinit(sc) 2062 struct ti_softc *sc; 2063{ 2064 struct ti_rcb *rcb; 2065 int i; 2066 struct ifnet *ifp; 2067 uint32_t rdphys; 2068 2069 TI_LOCK_ASSERT(sc); 2070 2071 ifp = sc->ti_ifp; 2072 rdphys = sc->ti_rdata_phys; 2073 2074 /* Disable interrupts for now. */ 2075 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2076 2077 /* 2078 * Tell the chip where to find the general information block. 2079 * While this struct could go into >4GB memory, we allocate it in a 2080 * single slab with the other descriptors, and those don't seem to 2081 * support being located in a 64-bit region. 2082 */ 2083 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2084 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2085 2086 /* Load the firmware into SRAM. */ 2087 ti_loadfw(sc); 2088 2089 /* Set up the contents of the general info and ring control blocks. */ 2090 2091 /* Set up the event ring and producer pointer. */ 2092 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2093 2094 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2095 rcb->ti_flags = 0; 2096 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2097 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2098 sc->ti_ev_prodidx.ti_idx = 0; 2099 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2100 sc->ti_ev_saved_considx = 0; 2101 2102 /* Set up the command ring and producer mailbox. */ 2103 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2104 2105 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2106 rcb->ti_flags = 0; 2107 rcb->ti_max_len = 0; 2108 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2109 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2110 } 2111 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2112 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2113 sc->ti_cmd_saved_prodidx = 0; 2114 2115 /* 2116 * Assign the address of the stats refresh buffer. 2117 * We re-use the current stats buffer for this to 2118 * conserve memory. 2119 */ 2120 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2121 rdphys + TI_RD_OFF(ti_info.ti_stats); 2122 2123 /* Set up the standard receive ring. */ 2124 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2125 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2126 rcb->ti_max_len = TI_FRAMELEN; 2127 rcb->ti_flags = 0; 2128 if (sc->ti_ifp->if_hwassist) 2129 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2130 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2131 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2132 2133 /* Set up the jumbo receive ring. */ 2134 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2135 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2136 2137#ifdef TI_PRIVATE_JUMBOS 2138 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2139 rcb->ti_flags = 0; 2140#else 2141 rcb->ti_max_len = PAGE_SIZE; 2142 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2143#endif 2144 if (sc->ti_ifp->if_hwassist) 2145 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2146 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2147 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2148 2149 /* 2150 * Set up the mini ring. Only activated on the 2151 * Tigon 2 but the slot in the config block is 2152 * still there on the Tigon 1. 2153 */ 2154 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2155 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2156 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2157 if (sc->ti_hwrev == TI_HWREV_TIGON) 2158 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2159 else 2160 rcb->ti_flags = 0; 2161 if (sc->ti_ifp->if_hwassist) 2162 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2163 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2164 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2165 2166 /* 2167 * Set up the receive return ring. 2168 */ 2169 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2170 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2171 rcb->ti_flags = 0; 2172 rcb->ti_max_len = TI_RETURN_RING_CNT; 2173 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2174 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2175 2176 /* 2177 * Set up the tx ring. Note: for the Tigon 2, we have the option 2178 * of putting the transmit ring in the host's address space and 2179 * letting the chip DMA it instead of leaving the ring in the NIC's 2180 * memory and accessing it through the shared memory region. We 2181 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2182 * so we have to revert to the shared memory scheme if we detect 2183 * a Tigon 1 chip. 2184 */ 2185 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2186 bzero((char *)sc->ti_rdata->ti_tx_ring, 2187 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2188 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2189 if (sc->ti_hwrev == TI_HWREV_TIGON) 2190 rcb->ti_flags = 0; 2191 else 2192 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2193 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2194 if (sc->ti_ifp->if_hwassist) 2195 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2196 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2197 rcb->ti_max_len = TI_TX_RING_CNT; 2198 if (sc->ti_hwrev == TI_HWREV_TIGON) 2199 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2200 else 2201 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2202 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2203 rdphys + TI_RD_OFF(ti_tx_considx_r); 2204 2205 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2206 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2207 2208 /* Set up tuneables */ 2209#if 0 2210 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2211 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2212 (sc->ti_rx_coal_ticks / 10)); 2213 else 2214#endif 2215 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2216 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2217 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2218 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2219 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2220 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2221 2222 /* Turn interrupts on. */ 2223 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2225 2226 /* Start CPU. */ 2227 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2228 2229 return (0); 2230} 2231 2232static void 2233ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2234{ 2235 struct ti_softc *sc; 2236 2237 sc = arg; 2238 if (error || nseg != 1) 2239 return; 2240 2241 /* 2242 * All of the Tigon data structures need to live at <4GB. This 2243 * cast is fine since busdma was told about this constraint. 2244 */ 2245 sc->ti_rdata_phys = segs[0].ds_addr; 2246 return; 2247} 2248 2249/* 2250 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2251 * against our list and return its name if we find a match. 2252 */ 2253static int 2254ti_probe(dev) 2255 device_t dev; 2256{ 2257 struct ti_type *t; 2258 2259 t = ti_devs; 2260 2261 while (t->ti_name != NULL) { 2262 if ((pci_get_vendor(dev) == t->ti_vid) && 2263 (pci_get_device(dev) == t->ti_did)) { 2264 device_set_desc(dev, t->ti_name); 2265 return (BUS_PROBE_DEFAULT); 2266 } 2267 t++; 2268 } 2269 2270 return (ENXIO); 2271} 2272 2273static int 2274ti_attach(dev) 2275 device_t dev; 2276{ 2277 struct ifnet *ifp; 2278 struct ti_softc *sc; 2279 int error = 0, rid; 2280 u_char eaddr[6]; 2281 2282 sc = device_get_softc(dev); 2283 sc->ti_unit = device_get_unit(dev); 2284 sc->ti_dev = dev; 2285 2286 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2287 MTX_DEF); 2288 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2289 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2290 if (ifp == NULL) { 2291 device_printf(dev, "can not if_alloc()\n"); 2292 error = ENOSPC; 2293 goto fail; 2294 } 2295 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2296 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2297 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2298 2299 /* 2300 * Map control/status registers. 2301 */ 2302 pci_enable_busmaster(dev); 2303 2304 rid = TI_PCI_LOMEM; 2305 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2306 RF_ACTIVE|PCI_RF_DENSE); 2307 2308 if (sc->ti_res == NULL) { 2309 device_printf(dev, "couldn't map memory\n"); 2310 error = ENXIO; 2311 goto fail; 2312 } 2313 2314 sc->ti_btag = rman_get_bustag(sc->ti_res); 2315 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2316 2317 /* Allocate interrupt */ 2318 rid = 0; 2319 2320 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2321 RF_SHAREABLE | RF_ACTIVE); 2322 2323 if (sc->ti_irq == NULL) { 2324 device_printf(dev, "couldn't map interrupt\n"); 2325 error = ENXIO; 2326 goto fail; 2327 } 2328 2329 if (ti_chipinit(sc)) { 2330 device_printf(dev, "chip initialization failed\n"); 2331 error = ENXIO; 2332 goto fail; 2333 } 2334 2335 /* Zero out the NIC's on-board SRAM. */ 2336 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2337 2338 /* Init again -- zeroing memory may have clobbered some registers. */ 2339 if (ti_chipinit(sc)) { 2340 device_printf(dev, "chip initialization failed\n"); 2341 error = ENXIO; 2342 goto fail; 2343 } 2344 2345 /* 2346 * Get station address from the EEPROM. Note: the manual states 2347 * that the MAC address is at offset 0x8c, however the data is 2348 * stored as two longwords (since that's how it's loaded into 2349 * the NIC). This means the MAC address is actually preceded 2350 * by two zero bytes. We need to skip over those. 2351 */ 2352 if (ti_read_eeprom(sc, eaddr, 2353 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2354 device_printf(dev, "failed to read station address\n"); 2355 error = ENXIO; 2356 goto fail; 2357 } 2358 2359 /* Allocate the general information block and ring buffers. */ 2360 if (bus_dma_tag_create(NULL, /* parent */ 2361 1, 0, /* algnmnt, boundary */ 2362 BUS_SPACE_MAXADDR, /* lowaddr */ 2363 BUS_SPACE_MAXADDR, /* highaddr */ 2364 NULL, NULL, /* filter, filterarg */ 2365 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2366 0, /* nsegments */ 2367 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2368 0, /* flags */ 2369 NULL, NULL, /* lockfunc, lockarg */ 2370 &sc->ti_parent_dmat) != 0) { 2371 device_printf(dev, "Failed to allocate parent dmat\n"); 2372 error = ENOMEM; 2373 goto fail; 2374 } 2375 2376 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2377 PAGE_SIZE, 0, /* algnmnt, boundary */ 2378 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2379 BUS_SPACE_MAXADDR, /* highaddr */ 2380 NULL, NULL, /* filter, filterarg */ 2381 sizeof(struct ti_ring_data), /* maxsize */ 2382 1, /* nsegments */ 2383 sizeof(struct ti_ring_data), /* maxsegsize */ 2384 0, /* flags */ 2385 NULL, NULL, /* lockfunc, lockarg */ 2386 &sc->ti_rdata_dmat) != 0) { 2387 device_printf(dev, "Failed to allocate rdata dmat\n"); 2388 error = ENOMEM; 2389 goto fail; 2390 } 2391 2392 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2393 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2394 device_printf(dev, "Failed to allocate rdata memory\n"); 2395 error = ENOMEM; 2396 goto fail; 2397 } 2398 2399 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2400 sc->ti_rdata, sizeof(struct ti_ring_data), 2401 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2402 device_printf(dev, "Failed to load rdata segments\n"); 2403 error = ENOMEM; 2404 goto fail; 2405 } 2406 2407 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2408 2409 /* Try to allocate memory for jumbo buffers. */ 2410 if (ti_alloc_jumbo_mem(sc)) { 2411 device_printf(dev, "jumbo buffer allocation failed\n"); 2412 error = ENXIO; 2413 goto fail; 2414 } 2415 2416 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2417 1, 0, /* algnmnt, boundary */ 2418 BUS_SPACE_MAXADDR, /* lowaddr */ 2419 BUS_SPACE_MAXADDR, /* highaddr */ 2420 NULL, NULL, /* filter, filterarg */ 2421 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2422 TI_MAXTXSEGS, /* nsegments */ 2423 MCLBYTES, /* maxsegsize */ 2424 0, /* flags */ 2425 NULL, NULL, /* lockfunc, lockarg */ 2426 &sc->ti_mbuftx_dmat) != 0) { 2427 device_printf(dev, "Failed to allocate rdata dmat\n"); 2428 error = ENOMEM; 2429 goto fail; 2430 } 2431 2432 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2433 1, 0, /* algnmnt, boundary */ 2434 BUS_SPACE_MAXADDR, /* lowaddr */ 2435 BUS_SPACE_MAXADDR, /* highaddr */ 2436 NULL, NULL, /* filter, filterarg */ 2437 MCLBYTES, /* maxsize */ 2438 1, /* nsegments */ 2439 MCLBYTES, /* maxsegsize */ 2440 0, /* flags */ 2441 NULL, NULL, /* lockfunc, lockarg */ 2442 &sc->ti_mbufrx_dmat) != 0) { 2443 device_printf(dev, "Failed to allocate rdata dmat\n"); 2444 error = ENOMEM; 2445 goto fail; 2446 } 2447 2448 if (ti_alloc_dmamaps(sc)) { 2449 device_printf(dev, "dma map creation failed\n"); 2450 error = ENXIO; 2451 goto fail; 2452 } 2453 2454 /* 2455 * We really need a better way to tell a 1000baseTX card 2456 * from a 1000baseSX one, since in theory there could be 2457 * OEMed 1000baseTX cards from lame vendors who aren't 2458 * clever enough to change the PCI ID. For the moment 2459 * though, the AceNIC is the only copper card available. 2460 */ 2461 if (pci_get_vendor(dev) == ALT_VENDORID && 2462 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2463 sc->ti_copper = 1; 2464 /* Ok, it's not the only copper card available. */ 2465 if (pci_get_vendor(dev) == NG_VENDORID && 2466 pci_get_device(dev) == NG_DEVICEID_GA620T) 2467 sc->ti_copper = 1; 2468 2469 /* Set default tuneable values. */ 2470 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2471#if 0 2472 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2473#endif 2474 sc->ti_rx_coal_ticks = 170; 2475 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2476 sc->ti_rx_max_coal_bds = 64; 2477#if 0 2478 sc->ti_tx_max_coal_bds = 128; 2479#endif 2480 sc->ti_tx_max_coal_bds = 32; 2481 sc->ti_tx_buf_ratio = 21; 2482 2483 /* Set up ifnet structure */ 2484 ifp->if_softc = sc; 2485 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2486 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2487 ifp->if_ioctl = ti_ioctl; 2488 ifp->if_start = ti_start; 2489 ifp->if_watchdog = ti_watchdog; 2490 ifp->if_init = ti_init; 2491 ifp->if_mtu = ETHERMTU; 2492 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2493 2494 /* Set up ifmedia support. */ 2495 if (sc->ti_copper) { 2496 /* 2497 * Copper cards allow manual 10/100 mode selection, 2498 * but not manual 1000baseTX mode selection. Why? 2499 * Becuase currently there's no way to specify the 2500 * master/slave setting through the firmware interface, 2501 * so Alteon decided to just bag it and handle it 2502 * via autonegotiation. 2503 */ 2504 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2505 ifmedia_add(&sc->ifmedia, 2506 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2507 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2508 ifmedia_add(&sc->ifmedia, 2509 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2510 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2511 ifmedia_add(&sc->ifmedia, 2512 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2513 } else { 2514 /* Fiber cards don't support 10/100 modes. */ 2515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2516 ifmedia_add(&sc->ifmedia, 2517 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2518 } 2519 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2520 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2521 2522 /* 2523 * We're assuming here that card initialization is a sequential 2524 * thing. If it isn't, multiple cards probing at the same time 2525 * could stomp on the list of softcs here. 2526 */ 2527 2528 /* Register the device */ 2529 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2530 0600, "ti%d", sc->ti_unit); 2531 sc->dev->si_drv1 = sc; 2532 2533 /* 2534 * Call MI attach routine. 2535 */ 2536 ether_ifattach(ifp, eaddr); 2537 2538 /* Hook interrupt last to avoid having to lock softc */ 2539 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2540 ti_intr, sc, &sc->ti_intrhand); 2541 2542 if (error) { 2543 device_printf(dev, "couldn't set up irq\n"); 2544 goto fail; 2545 } 2546 2547fail: 2548 if (error) 2549 ti_detach(dev); 2550 2551 return (error); 2552} 2553 2554/* 2555 * Shutdown hardware and free up resources. This can be called any 2556 * time after the mutex has been initialized. It is called in both 2557 * the error case in attach and the normal detach case so it needs 2558 * to be careful about only freeing resources that have actually been 2559 * allocated. 2560 */ 2561static int 2562ti_detach(dev) 2563 device_t dev; 2564{ 2565 struct ti_softc *sc; 2566 struct ifnet *ifp; 2567 int attached; 2568 2569 sc = device_get_softc(dev); 2570 if (sc->dev) 2571 destroy_dev(sc->dev); 2572 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2573 attached = device_is_attached(dev); 2574 TI_LOCK(sc); 2575 ifp = sc->ti_ifp; 2576 if (attached) 2577 ti_stop(sc); 2578 TI_UNLOCK(sc); 2579 if (attached) 2580 ether_ifdetach(ifp); 2581 2582 /* These should only be active if attach succeeded */ 2583 if (attached) 2584 bus_generic_detach(dev); 2585 ti_free_dmamaps(sc); 2586 ifmedia_removeall(&sc->ifmedia); 2587 2588#ifdef TI_PRIVATE_JUMBOS 2589 if (sc->ti_cdata.ti_jumbo_buf) 2590 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2591 sc->ti_jumbo_dmamap); 2592#endif 2593 if (sc->ti_jumbo_dmat) 2594 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2595 if (sc->ti_mbuftx_dmat) 2596 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2597 if (sc->ti_mbufrx_dmat) 2598 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2599 if (sc->ti_rdata) 2600 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2601 sc->ti_rdata_dmamap); 2602 if (sc->ti_rdata_dmat) 2603 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2604 if (sc->ti_parent_dmat) 2605 bus_dma_tag_destroy(sc->ti_parent_dmat); 2606 if (sc->ti_intrhand) 2607 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2608 if (sc->ti_irq) 2609 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2610 if (sc->ti_res) { 2611 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2612 sc->ti_res); 2613 } 2614 if (ifp) 2615 if_free(ifp); 2616 2617 mtx_destroy(&sc->ti_mtx); 2618 2619 return (0); 2620} 2621 2622#ifdef TI_JUMBO_HDRSPLIT 2623/* 2624 * If hdr_len is 0, that means that header splitting wasn't done on 2625 * this packet for some reason. The two most likely reasons are that 2626 * the protocol isn't a supported protocol for splitting, or this 2627 * packet had a fragment offset that wasn't 0. 2628 * 2629 * The header length, if it is non-zero, will always be the length of 2630 * the headers on the packet, but that length could be longer than the 2631 * first mbuf. So we take the minimum of the two as the actual 2632 * length. 2633 */ 2634static __inline void 2635ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2636{ 2637 int i = 0; 2638 int lengths[4] = {0, 0, 0, 0}; 2639 struct mbuf *m, *mp; 2640 2641 if (hdr_len != 0) 2642 top->m_len = min(hdr_len, top->m_len); 2643 pkt_len -= top->m_len; 2644 lengths[i++] = top->m_len; 2645 2646 mp = top; 2647 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2648 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2649 pkt_len -= m->m_len; 2650 lengths[i++] = m->m_len; 2651 mp = m; 2652 } 2653 2654#if 0 2655 if (hdr_len != 0) 2656 printf("got split packet: "); 2657 else 2658 printf("got non-split packet: "); 2659 2660 printf("%d,%d,%d,%d = %d\n", lengths[0], 2661 lengths[1], lengths[2], lengths[3], 2662 lengths[0] + lengths[1] + lengths[2] + 2663 lengths[3]); 2664#endif 2665 2666 if (pkt_len) 2667 panic("header splitting didn't"); 2668 2669 if (m) { 2670 m_freem(m); 2671 mp->m_next = NULL; 2672 2673 } 2674 if (mp->m_next != NULL) 2675 panic("ti_hdr_split: last mbuf in chain should be null"); 2676} 2677#endif /* TI_JUMBO_HDRSPLIT */ 2678 2679/* 2680 * Frame reception handling. This is called if there's a frame 2681 * on the receive return list. 2682 * 2683 * Note: we have to be able to handle three possibilities here: 2684 * 1) the frame is from the mini receive ring (can only happen) 2685 * on Tigon 2 boards) 2686 * 2) the frame is from the jumbo recieve ring 2687 * 3) the frame is from the standard receive ring 2688 */ 2689 2690static void 2691ti_rxeof(sc) 2692 struct ti_softc *sc; 2693{ 2694 bus_dmamap_t map; 2695 struct ifnet *ifp; 2696 struct ti_cmd_desc cmd; 2697 2698 TI_LOCK_ASSERT(sc); 2699 2700 ifp = sc->ti_ifp; 2701 2702 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2703 struct ti_rx_desc *cur_rx; 2704 u_int32_t rxidx; 2705 struct mbuf *m = NULL; 2706 u_int16_t vlan_tag = 0; 2707 int have_tag = 0; 2708 2709 cur_rx = 2710 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2711 rxidx = cur_rx->ti_idx; 2712 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2713 2714 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2715 have_tag = 1; 2716 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2717 } 2718 2719 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2720 2721 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2722 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2723 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2724 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2725 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2726 BUS_DMASYNC_POSTREAD); 2727 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2728 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2729 ifp->if_ierrors++; 2730 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2731 continue; 2732 } 2733 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2734 ifp->if_ierrors++; 2735 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2736 continue; 2737 } 2738#ifdef TI_PRIVATE_JUMBOS 2739 m->m_len = cur_rx->ti_len; 2740#else /* TI_PRIVATE_JUMBOS */ 2741#ifdef TI_JUMBO_HDRSPLIT 2742 if (sc->ti_hdrsplit) 2743 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2744 cur_rx->ti_len, rxidx); 2745 else 2746#endif /* TI_JUMBO_HDRSPLIT */ 2747 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2748#endif /* TI_PRIVATE_JUMBOS */ 2749 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2750 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2751 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2752 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2753 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2754 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2755 BUS_DMASYNC_POSTREAD); 2756 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2757 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2758 ifp->if_ierrors++; 2759 ti_newbuf_mini(sc, sc->ti_mini, m); 2760 continue; 2761 } 2762 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2763 ifp->if_ierrors++; 2764 ti_newbuf_mini(sc, sc->ti_mini, m); 2765 continue; 2766 } 2767 m->m_len = cur_rx->ti_len; 2768 } else { 2769 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2770 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2771 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2772 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2773 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2774 BUS_DMASYNC_POSTREAD); 2775 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2776 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2777 ifp->if_ierrors++; 2778 ti_newbuf_std(sc, sc->ti_std, m); 2779 continue; 2780 } 2781 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2782 ifp->if_ierrors++; 2783 ti_newbuf_std(sc, sc->ti_std, m); 2784 continue; 2785 } 2786 m->m_len = cur_rx->ti_len; 2787 } 2788 2789 m->m_pkthdr.len = cur_rx->ti_len; 2790 ifp->if_ipackets++; 2791 m->m_pkthdr.rcvif = ifp; 2792 2793 if (ifp->if_hwassist) { 2794 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2795 CSUM_DATA_VALID; 2796 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2797 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2798 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2799 } 2800 2801 /* 2802 * If we received a packet with a vlan tag, 2803 * tag it before passing the packet upward. 2804 */ 2805 if (have_tag) { 2806 VLAN_INPUT_TAG(ifp, m, vlan_tag); 2807 if (m == NULL) 2808 continue; 2809 } 2810 TI_UNLOCK(sc); 2811 (*ifp->if_input)(ifp, m); 2812 TI_LOCK(sc); 2813 } 2814 2815 /* Only necessary on the Tigon 1. */ 2816 if (sc->ti_hwrev == TI_HWREV_TIGON) 2817 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2818 sc->ti_rx_saved_considx); 2819 2820 TI_UPDATE_STDPROD(sc, sc->ti_std); 2821 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2822 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2823} 2824 2825static void 2826ti_txeof(sc) 2827 struct ti_softc *sc; 2828{ 2829 struct ti_tx_desc *cur_tx = NULL; 2830 struct ifnet *ifp; 2831 bus_dmamap_t map; 2832 2833 ifp = sc->ti_ifp; 2834 2835 /* 2836 * Go through our tx ring and free mbufs for those 2837 * frames that have been sent. 2838 */ 2839 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2840 u_int32_t idx = 0; 2841 struct ti_tx_desc txdesc; 2842 2843 idx = sc->ti_tx_saved_considx; 2844 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2845 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2846 sizeof(txdesc), &txdesc); 2847 cur_tx = &txdesc; 2848 } else 2849 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2850 if (cur_tx->ti_flags & TI_BDFLAG_END) 2851 ifp->if_opackets++; 2852 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2853 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2854 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2855 map = sc->ti_cdata.ti_tx_maps[idx]; 2856 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, 2857 BUS_DMASYNC_POSTWRITE); 2858 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 2859 } 2860 sc->ti_txcnt--; 2861 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2862 ifp->if_timer = 0; 2863 } 2864 2865 if (cur_tx != NULL) 2866 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2867} 2868 2869static void 2870ti_intr(xsc) 2871 void *xsc; 2872{ 2873 struct ti_softc *sc; 2874 struct ifnet *ifp; 2875 2876 sc = xsc; 2877 TI_LOCK(sc); 2878 ifp = sc->ti_ifp; 2879 2880/*#ifdef notdef*/ 2881 /* Avoid this for now -- checking this register is expensive. */ 2882 /* Make sure this is really our interrupt. */ 2883 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2884 TI_UNLOCK(sc); 2885 return; 2886 } 2887/*#endif*/ 2888 2889 /* Ack interrupt and stop others from occuring. */ 2890 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2891 2892 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2893 /* Check RX return ring producer/consumer */ 2894 ti_rxeof(sc); 2895 2896 /* Check TX ring producer/consumer */ 2897 ti_txeof(sc); 2898 } 2899 2900 ti_handle_events(sc); 2901 2902 /* Re-enable interrupts. */ 2903 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2904 2905 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2906 ifp->if_snd.ifq_head != NULL) 2907 ti_start_locked(ifp); 2908 2909 TI_UNLOCK(sc); 2910} 2911 2912static void 2913ti_stats_update(sc) 2914 struct ti_softc *sc; 2915{ 2916 struct ifnet *ifp; 2917 2918 ifp = sc->ti_ifp; 2919 2920 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2921 BUS_DMASYNC_POSTREAD); 2922 2923 ifp->if_collisions += 2924 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2925 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2926 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2927 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2928 ifp->if_collisions; 2929 2930 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2931 BUS_DMASYNC_PREREAD); 2932} 2933 2934struct ti_dmamap_arg { 2935 struct ti_softc *sc; 2936 struct m_tag *mtag; 2937 struct mbuf *m_head; 2938 u_int16_t csum_flags; 2939 int idx; 2940 int error; 2941}; 2942 2943static void 2944ti_encap_cb(arg, segs, nseg, mapsize, error) 2945 void *arg; 2946 bus_dma_segment_t *segs; 2947 int nseg; 2948 bus_size_t mapsize; 2949 int error; 2950{ 2951 struct ti_softc *sc; 2952 struct ti_dmamap_arg *ctx; 2953 struct ti_tx_desc *f = NULL; 2954 struct ti_tx_desc txdesc; 2955 struct m_tag *mtag; 2956 u_int32_t frag, cur, cnt = 0; 2957 u_int16_t csum_flags; 2958 2959 if (error) 2960 return; 2961 2962 ctx = (struct ti_dmamap_arg *)arg; 2963 sc = ctx->sc; 2964 cur = frag = ctx->idx; 2965 mtag = ctx->mtag; 2966 csum_flags = ctx->csum_flags; 2967 2968 /* 2969 * Sanity check: avoid coming within 16 descriptors 2970 * of the end of the ring. 2971 */ 2972 if ((TI_TX_RING_CNT - (sc->ti_txcnt + nseg)) < 16) { 2973 ctx->error = ENOBUFS; 2974 return; 2975 } 2976 2977 /* 2978 * Start packing the mbufs in this chain into 2979 * the fragment pointers. Stop when we run out 2980 * of fragments or hit the end of the mbuf chain. 2981 */ 2982 while (nseg-- > 0) { 2983 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2984 bzero(&txdesc, sizeof(txdesc)); 2985 f = &txdesc; 2986 } else 2987 f = &sc->ti_rdata->ti_tx_ring[frag]; 2988 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) { 2989 ctx->error = ENOBUFS; 2990 return; 2991 } 2992 ti_hostaddr64(&f->ti_addr, segs[cnt].ds_addr); 2993 f->ti_len = segs[cnt].ds_len; 2994 f->ti_flags = csum_flags; 2995 2996 if (mtag != NULL) { 2997 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2998 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2999 } else { 3000 f->ti_vlan_tag = 0; 3001 } 3002 3003 if (sc->ti_hwrev == TI_HWREV_TIGON) 3004 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3005 sizeof(txdesc), sizeof(txdesc), &txdesc); 3006 cur = frag; 3007 TI_INC(frag, TI_TX_RING_CNT); 3008 cnt++; 3009 } 3010 3011 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3012 txdesc.ti_flags |= TI_BDFLAG_END; 3013 ti_mem_write(sc, TI_TX_RING_BASE + cur * sizeof(txdesc), 3014 sizeof(txdesc), &txdesc); 3015 } else 3016 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 3017 sc->ti_cdata.ti_tx_chain[cur] = ctx->m_head; 3018 sc->ti_txcnt += cnt; 3019 3020 ctx->idx = frag; 3021 ctx->error = 0; 3022} 3023 3024/* 3025 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3026 * pointers to descriptors. 3027 */ 3028static int 3029ti_encap(sc, m_head, txidx) 3030 struct ti_softc *sc; 3031 struct mbuf *m_head; 3032 u_int32_t *txidx; 3033{ 3034 bus_dmamap_t map; 3035 struct ti_dmamap_arg ctx; 3036 u_int32_t frag, cnt; 3037 u_int16_t csum_flags = 0; 3038 int error; 3039 3040 frag = *txidx; 3041 3042 if (m_head->m_pkthdr.csum_flags) { 3043 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3044 csum_flags |= TI_BDFLAG_IP_CKSUM; 3045 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3046 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3047 if (m_head->m_flags & M_LASTFRAG) 3048 csum_flags |= TI_BDFLAG_IP_FRAG_END; 3049 else if (m_head->m_flags & M_FRAG) 3050 csum_flags |= TI_BDFLAG_IP_FRAG; 3051 } 3052 3053 ctx.sc = sc; 3054 ctx.idx = frag; 3055 ctx.csum_flags = csum_flags; 3056 ctx.mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m_head); 3057 ctx.m_head = m_head; 3058 3059 map = sc->ti_cdata.ti_tx_maps[frag]; 3060 error = bus_dmamap_load_mbuf(sc->ti_mbuftx_dmat, map, m_head, 3061 ti_encap_cb, &ctx, 0); 3062 if (error) 3063 return (ENOBUFS); 3064 3065 cnt = ctx.idx - frag; 3066 frag = ctx.idx; 3067 3068 if ((ctx.error != 0) || (frag == sc->ti_tx_saved_considx)) { 3069 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 3070 return (ENOBUFS); 3071 } 3072 3073 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, BUS_DMASYNC_PREWRITE); 3074 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 3075 BUS_DMASYNC_PREWRITE); 3076 *txidx = frag; 3077 return (0); 3078} 3079 3080static void 3081ti_start(ifp) 3082 struct ifnet *ifp; 3083{ 3084 struct ti_softc *sc; 3085 3086 sc = ifp->if_softc; 3087 TI_LOCK(sc); 3088 ti_start_locked(ifp); 3089 TI_UNLOCK(sc); 3090} 3091 3092/* 3093 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3094 * to the mbuf data regions directly in the transmit descriptors. 3095 */ 3096static void 3097ti_start_locked(ifp) 3098 struct ifnet *ifp; 3099{ 3100 struct ti_softc *sc; 3101 struct mbuf *m_head = NULL; 3102 u_int32_t prodidx = 0; 3103 3104 sc = ifp->if_softc; 3105 3106 prodidx = sc->ti_tx_saved_prodidx; 3107 3108 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 3109 IF_DEQUEUE(&ifp->if_snd, m_head); 3110 if (m_head == NULL) 3111 break; 3112 3113 /* 3114 * XXX 3115 * safety overkill. If this is a fragmented packet chain 3116 * with delayed TCP/UDP checksums, then only encapsulate 3117 * it if we have enough descriptors to handle the entire 3118 * chain at once. 3119 * (paranoia -- may not actually be needed) 3120 */ 3121 if (m_head->m_flags & M_FIRSTFRAG && 3122 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3123 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3124 m_head->m_pkthdr.csum_data + 16) { 3125 IF_PREPEND(&ifp->if_snd, m_head); 3126 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3127 break; 3128 } 3129 } 3130 3131 /* 3132 * Pack the data into the transmit ring. If we 3133 * don't have room, set the OACTIVE flag and wait 3134 * for the NIC to drain the ring. 3135 */ 3136 if (ti_encap(sc, m_head, &prodidx)) { 3137 IF_PREPEND(&ifp->if_snd, m_head); 3138 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3139 break; 3140 } 3141 3142 /* 3143 * If there's a BPF listener, bounce a copy of this frame 3144 * to him. 3145 */ 3146 BPF_MTAP(ifp, m_head); 3147 } 3148 3149 /* Transmit */ 3150 sc->ti_tx_saved_prodidx = prodidx; 3151 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 3152 3153 /* 3154 * Set a timeout in case the chip goes out to lunch. 3155 */ 3156 ifp->if_timer = 5; 3157} 3158 3159static void 3160ti_init(xsc) 3161 void *xsc; 3162{ 3163 struct ti_softc *sc; 3164 3165 sc = xsc; 3166 TI_LOCK(sc); 3167 ti_init_locked(sc); 3168 TI_UNLOCK(sc); 3169} 3170 3171static void 3172ti_init_locked(xsc) 3173 void *xsc; 3174{ 3175 struct ti_softc *sc = xsc; 3176 3177 /* Cancel pending I/O and flush buffers. */ 3178 ti_stop(sc); 3179 3180 /* Init the gen info block, ring control blocks and firmware. */ 3181 if (ti_gibinit(sc)) { 3182 if_printf(sc->ti_ifp, "initialization failure\n"); 3183 return; 3184 } 3185} 3186 3187static void ti_init2(sc) 3188 struct ti_softc *sc; 3189{ 3190 struct ti_cmd_desc cmd; 3191 struct ifnet *ifp; 3192 u_int8_t *ea; 3193 struct ifmedia *ifm; 3194 int tmp; 3195 3196 TI_LOCK_ASSERT(sc); 3197 3198 ifp = sc->ti_ifp; 3199 3200 /* Specify MTU and interface index. */ 3201 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 3202 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3203 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3204 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3205 3206 /* Load our MAC address. */ 3207 ea = IF_LLADDR(sc->ti_ifp); 3208 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3209 CSR_WRITE_4(sc, TI_GCR_PAR1, 3210 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3211 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3212 3213 /* Enable or disable promiscuous mode as needed. */ 3214 if (ifp->if_flags & IFF_PROMISC) { 3215 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3216 } else { 3217 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3218 } 3219 3220 /* Program multicast filter. */ 3221 ti_setmulti(sc); 3222 3223 /* 3224 * If this is a Tigon 1, we should tell the 3225 * firmware to use software packet filtering. 3226 */ 3227 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3228 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3229 } 3230 3231 /* Init RX ring. */ 3232 ti_init_rx_ring_std(sc); 3233 3234 /* Init jumbo RX ring. */ 3235 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3236 ti_init_rx_ring_jumbo(sc); 3237 3238 /* 3239 * If this is a Tigon 2, we can also configure the 3240 * mini ring. 3241 */ 3242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 3243 ti_init_rx_ring_mini(sc); 3244 3245 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3246 sc->ti_rx_saved_considx = 0; 3247 3248 /* Init TX ring. */ 3249 ti_init_tx_ring(sc); 3250 3251 /* Tell firmware we're alive. */ 3252 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3253 3254 /* Enable host interrupts. */ 3255 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3256 3257 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3258 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3259 3260 /* 3261 * Make sure to set media properly. We have to do this 3262 * here since we have to issue commands in order to set 3263 * the link negotiation and we can't issue commands until 3264 * the firmware is running. 3265 */ 3266 ifm = &sc->ifmedia; 3267 tmp = ifm->ifm_media; 3268 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3269 ti_ifmedia_upd(ifp); 3270 ifm->ifm_media = tmp; 3271} 3272 3273/* 3274 * Set media options. 3275 */ 3276static int 3277ti_ifmedia_upd(ifp) 3278 struct ifnet *ifp; 3279{ 3280 struct ti_softc *sc; 3281 struct ifmedia *ifm; 3282 struct ti_cmd_desc cmd; 3283 u_int32_t flowctl; 3284 3285 sc = ifp->if_softc; 3286 ifm = &sc->ifmedia; 3287 3288 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3289 return (EINVAL); 3290 3291 flowctl = 0; 3292 3293 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3294 case IFM_AUTO: 3295 /* 3296 * Transmit flow control doesn't work on the Tigon 1. 3297 */ 3298 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3299 3300 /* 3301 * Transmit flow control can also cause problems on the 3302 * Tigon 2, apparantly with both the copper and fiber 3303 * boards. The symptom is that the interface will just 3304 * hang. This was reproduced with Alteon 180 switches. 3305 */ 3306#if 0 3307 if (sc->ti_hwrev != TI_HWREV_TIGON) 3308 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3309#endif 3310 3311 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3312 TI_GLNK_FULL_DUPLEX| flowctl | 3313 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3314 3315 flowctl = TI_LNK_RX_FLOWCTL_Y; 3316#if 0 3317 if (sc->ti_hwrev != TI_HWREV_TIGON) 3318 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3319#endif 3320 3321 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3322 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3323 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3324 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3325 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3326 break; 3327 case IFM_1000_SX: 3328 case IFM_1000_T: 3329 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3330#if 0 3331 if (sc->ti_hwrev != TI_HWREV_TIGON) 3332 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3333#endif 3334 3335 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3336 flowctl |TI_GLNK_ENB); 3337 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3338 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3339 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3340 } 3341 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3342 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3343 break; 3344 case IFM_100_FX: 3345 case IFM_10_FL: 3346 case IFM_100_TX: 3347 case IFM_10_T: 3348 flowctl = TI_LNK_RX_FLOWCTL_Y; 3349#if 0 3350 if (sc->ti_hwrev != TI_HWREV_TIGON) 3351 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3352#endif 3353 3354 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3355 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3356 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3357 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3358 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3359 } else { 3360 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3361 } 3362 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3363 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3364 } else { 3365 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3366 } 3367 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3368 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3369 break; 3370 } 3371 3372 return (0); 3373} 3374 3375/* 3376 * Report current media status. 3377 */ 3378static void 3379ti_ifmedia_sts(ifp, ifmr) 3380 struct ifnet *ifp; 3381 struct ifmediareq *ifmr; 3382{ 3383 struct ti_softc *sc; 3384 u_int32_t media = 0; 3385 3386 sc = ifp->if_softc; 3387 3388 ifmr->ifm_status = IFM_AVALID; 3389 ifmr->ifm_active = IFM_ETHER; 3390 3391 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3392 return; 3393 3394 ifmr->ifm_status |= IFM_ACTIVE; 3395 3396 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3397 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3398 if (sc->ti_copper) 3399 ifmr->ifm_active |= IFM_1000_T; 3400 else 3401 ifmr->ifm_active |= IFM_1000_SX; 3402 if (media & TI_GLNK_FULL_DUPLEX) 3403 ifmr->ifm_active |= IFM_FDX; 3404 else 3405 ifmr->ifm_active |= IFM_HDX; 3406 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3407 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3408 if (sc->ti_copper) { 3409 if (media & TI_LNK_100MB) 3410 ifmr->ifm_active |= IFM_100_TX; 3411 if (media & TI_LNK_10MB) 3412 ifmr->ifm_active |= IFM_10_T; 3413 } else { 3414 if (media & TI_LNK_100MB) 3415 ifmr->ifm_active |= IFM_100_FX; 3416 if (media & TI_LNK_10MB) 3417 ifmr->ifm_active |= IFM_10_FL; 3418 } 3419 if (media & TI_LNK_FULL_DUPLEX) 3420 ifmr->ifm_active |= IFM_FDX; 3421 if (media & TI_LNK_HALF_DUPLEX) 3422 ifmr->ifm_active |= IFM_HDX; 3423 } 3424} 3425 3426static int 3427ti_ioctl(ifp, command, data) 3428 struct ifnet *ifp; 3429 u_long command; 3430 caddr_t data; 3431{ 3432 struct ti_softc *sc = ifp->if_softc; 3433 struct ifreq *ifr = (struct ifreq *) data; 3434 int mask, error = 0; 3435 struct ti_cmd_desc cmd; 3436 3437 switch (command) { 3438 case SIOCSIFMTU: 3439 TI_LOCK(sc); 3440 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3441 error = EINVAL; 3442 else { 3443 ifp->if_mtu = ifr->ifr_mtu; 3444 ti_init_locked(sc); 3445 } 3446 TI_UNLOCK(sc); 3447 break; 3448 case SIOCSIFFLAGS: 3449 TI_LOCK(sc); 3450 if (ifp->if_flags & IFF_UP) { 3451 /* 3452 * If only the state of the PROMISC flag changed, 3453 * then just use the 'set promisc mode' command 3454 * instead of reinitializing the entire NIC. Doing 3455 * a full re-init means reloading the firmware and 3456 * waiting for it to start up, which may take a 3457 * second or two. 3458 */ 3459 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3460 ifp->if_flags & IFF_PROMISC && 3461 !(sc->ti_if_flags & IFF_PROMISC)) { 3462 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3463 TI_CMD_CODE_PROMISC_ENB, 0); 3464 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3465 !(ifp->if_flags & IFF_PROMISC) && 3466 sc->ti_if_flags & IFF_PROMISC) { 3467 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3468 TI_CMD_CODE_PROMISC_DIS, 0); 3469 } else 3470 ti_init_locked(sc); 3471 } else { 3472 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3473 ti_stop(sc); 3474 } 3475 } 3476 sc->ti_if_flags = ifp->if_flags; 3477 TI_UNLOCK(sc); 3478 break; 3479 case SIOCADDMULTI: 3480 case SIOCDELMULTI: 3481 TI_LOCK(sc); 3482 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3483 ti_setmulti(sc); 3484 TI_UNLOCK(sc); 3485 break; 3486 case SIOCSIFMEDIA: 3487 case SIOCGIFMEDIA: 3488 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3489 break; 3490 case SIOCSIFCAP: 3491 TI_LOCK(sc); 3492 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3493 if (mask & IFCAP_HWCSUM) { 3494 if (IFCAP_HWCSUM & ifp->if_capenable) 3495 ifp->if_capenable &= ~IFCAP_HWCSUM; 3496 else 3497 ifp->if_capenable |= IFCAP_HWCSUM; 3498 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3499 ti_init_locked(sc); 3500 } 3501 TI_UNLOCK(sc); 3502 break; 3503 default: 3504 error = ether_ioctl(ifp, command, data); 3505 break; 3506 } 3507 3508 return (error); 3509} 3510 3511static int 3512ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3513{ 3514 struct ti_softc *sc; 3515 3516 sc = dev->si_drv1; 3517 if (sc == NULL) 3518 return (ENODEV); 3519 3520 TI_LOCK(sc); 3521 sc->ti_flags |= TI_FLAG_DEBUGING; 3522 TI_UNLOCK(sc); 3523 3524 return (0); 3525} 3526 3527static int 3528ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3529{ 3530 struct ti_softc *sc; 3531 3532 sc = dev->si_drv1; 3533 if (sc == NULL) 3534 return (ENODEV); 3535 3536 TI_LOCK(sc); 3537 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3538 TI_UNLOCK(sc); 3539 3540 return (0); 3541} 3542 3543/* 3544 * This ioctl routine goes along with the Tigon character device. 3545 */ 3546static int 3547ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3548 struct thread *td) 3549{ 3550 int error; 3551 struct ti_softc *sc; 3552 3553 sc = dev->si_drv1; 3554 if (sc == NULL) 3555 return (ENODEV); 3556 3557 error = 0; 3558 3559 switch (cmd) { 3560 case TIIOCGETSTATS: 3561 { 3562 struct ti_stats *outstats; 3563 3564 outstats = (struct ti_stats *)addr; 3565 3566 TI_LOCK(sc); 3567 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3568 sizeof(struct ti_stats)); 3569 TI_UNLOCK(sc); 3570 break; 3571 } 3572 case TIIOCGETPARAMS: 3573 { 3574 struct ti_params *params; 3575 3576 params = (struct ti_params *)addr; 3577 3578 TI_LOCK(sc); 3579 params->ti_stat_ticks = sc->ti_stat_ticks; 3580 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3581 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3582 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3583 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3584 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3585 params->param_mask = TI_PARAM_ALL; 3586 TI_UNLOCK(sc); 3587 3588 error = 0; 3589 3590 break; 3591 } 3592 case TIIOCSETPARAMS: 3593 { 3594 struct ti_params *params; 3595 3596 params = (struct ti_params *)addr; 3597 3598 TI_LOCK(sc); 3599 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3600 sc->ti_stat_ticks = params->ti_stat_ticks; 3601 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3602 } 3603 3604 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3605 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3606 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3607 sc->ti_rx_coal_ticks); 3608 } 3609 3610 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3611 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3612 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3613 sc->ti_tx_coal_ticks); 3614 } 3615 3616 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3617 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3618 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3619 sc->ti_rx_max_coal_bds); 3620 } 3621 3622 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3623 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3624 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3625 sc->ti_tx_max_coal_bds); 3626 } 3627 3628 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3629 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3630 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3631 sc->ti_tx_buf_ratio); 3632 } 3633 TI_UNLOCK(sc); 3634 3635 error = 0; 3636 3637 break; 3638 } 3639 case TIIOCSETTRACE: { 3640 ti_trace_type trace_type; 3641 3642 trace_type = *(ti_trace_type *)addr; 3643 3644 /* 3645 * Set tracing to whatever the user asked for. Setting 3646 * this register to 0 should have the effect of disabling 3647 * tracing. 3648 */ 3649 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3650 3651 error = 0; 3652 3653 break; 3654 } 3655 case TIIOCGETTRACE: { 3656 struct ti_trace_buf *trace_buf; 3657 u_int32_t trace_start, cur_trace_ptr, trace_len; 3658 3659 trace_buf = (struct ti_trace_buf *)addr; 3660 3661 TI_LOCK(sc); 3662 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3663 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3664 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3665 3666#if 0 3667 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3668 "trace_len = %d\n", trace_start, 3669 cur_trace_ptr, trace_len); 3670 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3671 trace_buf->buf_len); 3672#endif 3673 3674 error = ti_copy_mem(sc, trace_start, min(trace_len, 3675 trace_buf->buf_len), 3676 (caddr_t)trace_buf->buf, 1, 1); 3677 3678 if (error == 0) { 3679 trace_buf->fill_len = min(trace_len, 3680 trace_buf->buf_len); 3681 if (cur_trace_ptr < trace_start) 3682 trace_buf->cur_trace_ptr = 3683 trace_start - cur_trace_ptr; 3684 else 3685 trace_buf->cur_trace_ptr = 3686 cur_trace_ptr - trace_start; 3687 } else 3688 trace_buf->fill_len = 0; 3689 TI_UNLOCK(sc); 3690 3691 break; 3692 } 3693 3694 /* 3695 * For debugging, five ioctls are needed: 3696 * ALT_ATTACH 3697 * ALT_READ_TG_REG 3698 * ALT_WRITE_TG_REG 3699 * ALT_READ_TG_MEM 3700 * ALT_WRITE_TG_MEM 3701 */ 3702 case ALT_ATTACH: 3703 /* 3704 * From what I can tell, Alteon's Solaris Tigon driver 3705 * only has one character device, so you have to attach 3706 * to the Tigon board you're interested in. This seems 3707 * like a not-so-good way to do things, since unless you 3708 * subsequently specify the unit number of the device 3709 * you're interested in in every ioctl, you'll only be 3710 * able to debug one board at a time. 3711 */ 3712 error = 0; 3713 break; 3714 case ALT_READ_TG_MEM: 3715 case ALT_WRITE_TG_MEM: 3716 { 3717 struct tg_mem *mem_param; 3718 u_int32_t sram_end, scratch_end; 3719 3720 mem_param = (struct tg_mem *)addr; 3721 3722 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3723 sram_end = TI_END_SRAM_I; 3724 scratch_end = TI_END_SCRATCH_I; 3725 } else { 3726 sram_end = TI_END_SRAM_II; 3727 scratch_end = TI_END_SCRATCH_II; 3728 } 3729 3730 /* 3731 * For now, we'll only handle accessing regular SRAM, 3732 * nothing else. 3733 */ 3734 TI_LOCK(sc); 3735 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3736 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3737 /* 3738 * In this instance, we always copy to/from user 3739 * space, so the user space argument is set to 1. 3740 */ 3741 error = ti_copy_mem(sc, mem_param->tgAddr, 3742 mem_param->len, 3743 mem_param->userAddr, 1, 3744 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3745 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3746 && (mem_param->tgAddr <= scratch_end)) { 3747 error = ti_copy_scratch(sc, mem_param->tgAddr, 3748 mem_param->len, 3749 mem_param->userAddr, 1, 3750 (cmd == ALT_READ_TG_MEM) ? 3751 1 : 0, TI_PROCESSOR_A); 3752 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3753 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3754 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3755 if_printf(sc->ti_ifp, 3756 "invalid memory range for Tigon I\n"); 3757 error = EINVAL; 3758 break; 3759 } 3760 error = ti_copy_scratch(sc, mem_param->tgAddr - 3761 TI_SCRATCH_DEBUG_OFF, 3762 mem_param->len, 3763 mem_param->userAddr, 1, 3764 (cmd == ALT_READ_TG_MEM) ? 3765 1 : 0, TI_PROCESSOR_B); 3766 } else { 3767 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3768 "out of supported range\n", 3769 mem_param->tgAddr, mem_param->len); 3770 error = EINVAL; 3771 } 3772 TI_UNLOCK(sc); 3773 3774 break; 3775 } 3776 case ALT_READ_TG_REG: 3777 case ALT_WRITE_TG_REG: 3778 { 3779 struct tg_reg *regs; 3780 u_int32_t tmpval; 3781 3782 regs = (struct tg_reg *)addr; 3783 3784 /* 3785 * Make sure the address in question isn't out of range. 3786 */ 3787 if (regs->addr > TI_REG_MAX) { 3788 error = EINVAL; 3789 break; 3790 } 3791 TI_LOCK(sc); 3792 if (cmd == ALT_READ_TG_REG) { 3793 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3794 regs->addr, &tmpval, 1); 3795 regs->data = ntohl(tmpval); 3796#if 0 3797 if ((regs->addr == TI_CPU_STATE) 3798 || (regs->addr == TI_CPU_CTL_B)) { 3799 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3800 regs->addr, tmpval); 3801 } 3802#endif 3803 } else { 3804 tmpval = htonl(regs->data); 3805 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3806 regs->addr, &tmpval, 1); 3807 } 3808 TI_UNLOCK(sc); 3809 3810 break; 3811 } 3812 default: 3813 error = ENOTTY; 3814 break; 3815 } 3816 return (error); 3817} 3818 3819static void 3820ti_watchdog(ifp) 3821 struct ifnet *ifp; 3822{ 3823 struct ti_softc *sc; 3824 3825 sc = ifp->if_softc; 3826 TI_LOCK(sc); 3827 3828 /* 3829 * When we're debugging, the chip is often stopped for long periods 3830 * of time, and that would normally cause the watchdog timer to fire. 3831 * Since that impedes debugging, we don't want to do that. 3832 */ 3833 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3834 TI_UNLOCK(sc); 3835 return; 3836 } 3837 3838 if_printf(ifp, "watchdog timeout -- resetting\n"); 3839 ti_stop(sc); 3840 ti_init_locked(sc); 3841 3842 ifp->if_oerrors++; 3843 TI_UNLOCK(sc); 3844} 3845 3846/* 3847 * Stop the adapter and free any mbufs allocated to the 3848 * RX and TX lists. 3849 */ 3850static void 3851ti_stop(sc) 3852 struct ti_softc *sc; 3853{ 3854 struct ifnet *ifp; 3855 struct ti_cmd_desc cmd; 3856 3857 TI_LOCK_ASSERT(sc); 3858 3859 ifp = sc->ti_ifp; 3860 3861 /* Disable host interrupts. */ 3862 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3863 /* 3864 * Tell firmware we're shutting down. 3865 */ 3866 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3867 3868 /* Halt and reinitialize. */ 3869 if (ti_chipinit(sc) != 0) 3870 return; 3871 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3872 if (ti_chipinit(sc) != 0) 3873 return; 3874 3875 /* Free the RX lists. */ 3876 ti_free_rx_ring_std(sc); 3877 3878 /* Free jumbo RX list. */ 3879 ti_free_rx_ring_jumbo(sc); 3880 3881 /* Free mini RX list. */ 3882 ti_free_rx_ring_mini(sc); 3883 3884 /* Free TX buffers. */ 3885 ti_free_tx_ring(sc); 3886 3887 sc->ti_ev_prodidx.ti_idx = 0; 3888 sc->ti_return_prodidx.ti_idx = 0; 3889 sc->ti_tx_considx.ti_idx = 0; 3890 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3891 3892 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3893} 3894 3895/* 3896 * Stop all chip I/O so that the kernel's probe routines don't 3897 * get confused by errant DMAs when rebooting. 3898 */ 3899static void 3900ti_shutdown(dev) 3901 device_t dev; 3902{ 3903 struct ti_softc *sc; 3904 3905 sc = device_get_softc(dev); 3906 TI_LOCK(sc); 3907 ti_chipinit(sc); 3908 TI_UNLOCK(sc); 3909} 3910