if_ti.c revision 153770
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 153770 2005-12-28 02:57:19Z yongari $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116#ifndef TI_PRIVATE_JUMBOS 117#include <vm/vm.h> 118#include <vm/vm_page.h> 119#endif 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123 124#include <sys/tiio.h> 125#include <dev/ti/if_tireg.h> 126#include <dev/ti/ti_fw.h> 127#include <dev/ti/ti_fw2.h> 128 129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130/* 131 * We can only turn on header splitting if we're using extended receive 132 * BDs. 133 */ 134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 137 138typedef enum { 139 TI_SWAP_HTON, 140 TI_SWAP_NTOH 141} ti_swap_type; 142 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static struct ti_type ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *); 188static void ti_encap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 189 bus_size_t mapsize, int error); 190 191static void ti_intr(void *); 192static void ti_start(struct ifnet *); 193static void ti_start_locked(struct ifnet *); 194static int ti_ioctl(struct ifnet *, u_long, caddr_t); 195static void ti_init(void *); 196static void ti_init_locked(void *); 197static void ti_init2(struct ti_softc *); 198static void ti_stop(struct ti_softc *); 199static void ti_watchdog(struct ifnet *); 200static void ti_shutdown(device_t); 201static int ti_ifmedia_upd(struct ifnet *); 202static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 203 204static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 205static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 206static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 207 208static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 209static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 210static void ti_setmulti(struct ti_softc *); 211 212static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 213static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 214static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 215static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 216static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 217 int, int, int); 218static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219static void ti_loadfw(struct ti_softc *); 220static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222static void ti_handle_events(struct ti_softc *); 223static int ti_alloc_dmamaps(struct ti_softc *); 224static void ti_free_dmamaps(struct ti_softc *); 225static int ti_alloc_jumbo_mem(struct ti_softc *); 226#ifdef TI_PRIVATE_JUMBOS 227static void *ti_jalloc(struct ti_softc *); 228static void ti_jfree(void *, void *); 229#endif /* TI_PRIVATE_JUMBOS */ 230static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 231static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 232static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 233static int ti_init_rx_ring_std(struct ti_softc *); 234static void ti_free_rx_ring_std(struct ti_softc *); 235static int ti_init_rx_ring_jumbo(struct ti_softc *); 236static void ti_free_rx_ring_jumbo(struct ti_softc *); 237static int ti_init_rx_ring_mini(struct ti_softc *); 238static void ti_free_rx_ring_mini(struct ti_softc *); 239static void ti_free_tx_ring(struct ti_softc *); 240static int ti_init_tx_ring(struct ti_softc *); 241 242static int ti_64bitslot_war(struct ti_softc *); 243static int ti_chipinit(struct ti_softc *); 244static int ti_gibinit(struct ti_softc *); 245 246#ifdef TI_JUMBO_HDRSPLIT 247static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 248 int pkt_len, int idx); 249#endif /* TI_JUMBO_HDRSPLIT */ 250 251static device_method_t ti_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, ti_probe), 254 DEVMETHOD(device_attach, ti_attach), 255 DEVMETHOD(device_detach, ti_detach), 256 DEVMETHOD(device_shutdown, ti_shutdown), 257 { 0, 0 } 258}; 259 260static driver_t ti_driver = { 261 "ti", 262 ti_methods, 263 sizeof(struct ti_softc) 264}; 265 266static devclass_t ti_devclass; 267 268DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 269MODULE_DEPEND(ti, pci, 1, 1, 1); 270MODULE_DEPEND(ti, ether, 1, 1, 1); 271 272/* 273 * Send an instruction or address to the EEPROM, check for ACK. 274 */ 275static u_int32_t ti_eeprom_putbyte(sc, byte) 276 struct ti_softc *sc; 277 int byte; 278{ 279 int i, ack = 0; 280 281 /* 282 * Make sure we're in TX mode. 283 */ 284 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 285 286 /* 287 * Feed in each bit and stobe the clock. 288 */ 289 for (i = 0x80; i; i >>= 1) { 290 if (byte & i) { 291 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 292 } else { 293 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 294 } 295 DELAY(1); 296 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 297 DELAY(1); 298 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 299 } 300 301 /* 302 * Turn off TX mode. 303 */ 304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 305 306 /* 307 * Check for ack. 308 */ 309 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 312 313 return (ack); 314} 315 316/* 317 * Read a byte of data stored in the EEPROM at address 'addr.' 318 * We have to send two address bytes since the EEPROM can hold 319 * more than 256 bytes of data. 320 */ 321static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 322 struct ti_softc *sc; 323 int addr; 324 u_int8_t *dest; 325{ 326 int i; 327 u_int8_t byte = 0; 328 329 EEPROM_START; 330 331 /* 332 * Send write control code to EEPROM. 333 */ 334 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 335 if_printf(sc->ti_ifp, 336 "failed to send write command, status: %x\n", 337 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 338 return (1); 339 } 340 341 /* 342 * Send first byte of address of byte we want to read. 343 */ 344 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 345 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 346 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 347 return (1); 348 } 349 /* 350 * Send second byte address of byte we want to read. 351 */ 352 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 353 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 354 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 355 return (1); 356 } 357 358 EEPROM_STOP; 359 EEPROM_START; 360 /* 361 * Send read control code to EEPROM. 362 */ 363 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 364 if_printf(sc->ti_ifp, 365 "failed to send read command, status: %x\n", 366 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 367 return (1); 368 } 369 370 /* 371 * Start reading bits from EEPROM. 372 */ 373 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 374 for (i = 0x80; i; i >>= 1) { 375 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 376 DELAY(1); 377 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 378 byte |= i; 379 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 380 DELAY(1); 381 } 382 383 EEPROM_STOP; 384 385 /* 386 * No ACK generated for read, so just return byte. 387 */ 388 389 *dest = byte; 390 391 return (0); 392} 393 394/* 395 * Read a sequence of bytes from the EEPROM. 396 */ 397static int 398ti_read_eeprom(sc, dest, off, cnt) 399 struct ti_softc *sc; 400 caddr_t dest; 401 int off; 402 int cnt; 403{ 404 int err = 0, i; 405 u_int8_t byte = 0; 406 407 for (i = 0; i < cnt; i++) { 408 err = ti_eeprom_getbyte(sc, off + i, &byte); 409 if (err) 410 break; 411 *(dest + i) = byte; 412 } 413 414 return (err ? 1 : 0); 415} 416 417/* 418 * NIC memory read function. 419 * Can be used to copy data from NIC local memory. 420 */ 421static void 422ti_mem_read(sc, addr, len, buf) 423 struct ti_softc *sc; 424 u_int32_t addr, len; 425 void *buf; 426{ 427 int segptr, segsize, cnt; 428 char *ptr; 429 430 segptr = addr; 431 cnt = len; 432 ptr = buf; 433 434 while (cnt) { 435 if (cnt < TI_WINLEN) 436 segsize = cnt; 437 else 438 segsize = TI_WINLEN - (segptr % TI_WINLEN); 439 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 440 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 441 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 442 segsize / 4); 443 ptr += segsize; 444 segptr += segsize; 445 cnt -= segsize; 446 } 447} 448 449 450/* 451 * NIC memory write function. 452 * Can be used to copy data into NIC local memory. 453 */ 454static void 455ti_mem_write(sc, addr, len, buf) 456 struct ti_softc *sc; 457 u_int32_t addr, len; 458 void *buf; 459{ 460 int segptr, segsize, cnt; 461 char *ptr; 462 463 segptr = addr; 464 cnt = len; 465 ptr = buf; 466 467 while (cnt) { 468 if (cnt < TI_WINLEN) 469 segsize = cnt; 470 else 471 segsize = TI_WINLEN - (segptr % TI_WINLEN); 472 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 473 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 474 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 475 segsize / 4); 476 ptr += segsize; 477 segptr += segsize; 478 cnt -= segsize; 479 } 480} 481 482/* 483 * NIC memory read function. 484 * Can be used to clear a section of NIC local memory. 485 */ 486static void 487ti_mem_zero(sc, addr, len) 488 struct ti_softc *sc; 489 u_int32_t addr, len; 490{ 491 int segptr, segsize, cnt; 492 493 segptr = addr; 494 cnt = len; 495 496 while (cnt) { 497 if (cnt < TI_WINLEN) 498 segsize = cnt; 499 else 500 segsize = TI_WINLEN - (segptr % TI_WINLEN); 501 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 502 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 503 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 504 segptr += segsize; 505 cnt -= segsize; 506 } 507} 508 509static int 510ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 511 struct ti_softc *sc; 512 u_int32_t tigon_addr, len; 513 caddr_t buf; 514 int useraddr, readdata; 515{ 516 int segptr, segsize, cnt; 517 caddr_t ptr; 518 u_int32_t origwin; 519 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 520 int resid, segresid; 521 int first_pass; 522 523 TI_LOCK_ASSERT(sc); 524 525 /* 526 * At the moment, we don't handle non-aligned cases, we just bail. 527 * If this proves to be a problem, it will be fixed. 528 */ 529 if ((readdata == 0) 530 && (tigon_addr & 0x3)) { 531 if_printf(sc->ti_ifp, "ti_copy_mem: tigon address %#x isn't " 532 "word-aligned\n", tigon_addr); 533 if_printf(sc->ti_ifp, "ti_copy_mem: unaligned writes aren't " 534 "yet supported\n"); 535 return (EINVAL); 536 } 537 538 segptr = tigon_addr & ~0x3; 539 segresid = tigon_addr - segptr; 540 541 /* 542 * This is the non-aligned amount left over that we'll need to 543 * copy. 544 */ 545 resid = len & 0x3; 546 547 /* Add in the left over amount at the front of the buffer */ 548 resid += segresid; 549 550 cnt = len & ~0x3; 551 /* 552 * If resid + segresid is >= 4, add multiples of 4 to the count and 553 * decrease the residual by that much. 554 */ 555 cnt += resid & ~0x3; 556 resid -= resid & ~0x3; 557 558 ptr = buf; 559 560 first_pass = 1; 561 562 /* 563 * Save the old window base value. 564 */ 565 origwin = CSR_READ_4(sc, TI_WINBASE); 566 567 while (cnt) { 568 bus_size_t ti_offset; 569 570 if (cnt < TI_WINLEN) 571 segsize = cnt; 572 else 573 segsize = TI_WINLEN - (segptr % TI_WINLEN); 574 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 575 576 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 577 578 if (readdata) { 579 580 bus_space_read_region_4(sc->ti_btag, 581 sc->ti_bhandle, ti_offset, 582 (u_int32_t *)tmparray, 583 segsize >> 2); 584 if (useraddr) { 585 /* 586 * Yeah, this is a little on the kludgy 587 * side, but at least this code is only 588 * used for debugging. 589 */ 590 ti_bcopy_swap(tmparray, tmparray2, segsize, 591 TI_SWAP_NTOH); 592 593 TI_UNLOCK(sc); 594 if (first_pass) { 595 copyout(&tmparray2[segresid], ptr, 596 segsize - segresid); 597 first_pass = 0; 598 } else 599 copyout(tmparray2, ptr, segsize); 600 TI_LOCK(sc); 601 } else { 602 if (first_pass) { 603 604 ti_bcopy_swap(tmparray, tmparray2, 605 segsize, TI_SWAP_NTOH); 606 TI_UNLOCK(sc); 607 bcopy(&tmparray2[segresid], ptr, 608 segsize - segresid); 609 TI_LOCK(sc); 610 first_pass = 0; 611 } else 612 ti_bcopy_swap(tmparray, ptr, segsize, 613 TI_SWAP_NTOH); 614 } 615 616 } else { 617 if (useraddr) { 618 TI_UNLOCK(sc); 619 copyin(ptr, tmparray2, segsize); 620 TI_LOCK(sc); 621 ti_bcopy_swap(tmparray2, tmparray, segsize, 622 TI_SWAP_HTON); 623 } else 624 ti_bcopy_swap(ptr, tmparray, segsize, 625 TI_SWAP_HTON); 626 627 bus_space_write_region_4(sc->ti_btag, 628 sc->ti_bhandle, ti_offset, 629 (u_int32_t *)tmparray, 630 segsize >> 2); 631 } 632 segptr += segsize; 633 ptr += segsize; 634 cnt -= segsize; 635 } 636 637 /* 638 * Handle leftover, non-word-aligned bytes. 639 */ 640 if (resid != 0) { 641 u_int32_t tmpval, tmpval2; 642 bus_size_t ti_offset; 643 644 /* 645 * Set the segment pointer. 646 */ 647 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 648 649 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 650 651 /* 652 * First, grab whatever is in our source/destination. 653 * We'll obviously need this for reads, but also for 654 * writes, since we'll be doing read/modify/write. 655 */ 656 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 657 ti_offset, &tmpval, 1); 658 659 /* 660 * Next, translate this from little-endian to big-endian 661 * (at least on i386 boxes). 662 */ 663 tmpval2 = ntohl(tmpval); 664 665 if (readdata) { 666 /* 667 * If we're reading, just copy the leftover number 668 * of bytes from the host byte order buffer to 669 * the user's buffer. 670 */ 671 if (useraddr) { 672 TI_UNLOCK(sc); 673 copyout(&tmpval2, ptr, resid); 674 TI_LOCK(sc); 675 } else 676 bcopy(&tmpval2, ptr, resid); 677 } else { 678 /* 679 * If we're writing, first copy the bytes to be 680 * written into the network byte order buffer, 681 * leaving the rest of the buffer with whatever was 682 * originally in there. Then, swap the bytes 683 * around into host order and write them out. 684 * 685 * XXX KDM the read side of this has been verified 686 * to work, but the write side of it has not been 687 * verified. So user beware. 688 */ 689 if (useraddr) { 690 TI_UNLOCK(sc); 691 copyin(ptr, &tmpval2, resid); 692 TI_LOCK(sc); 693 } else 694 bcopy(ptr, &tmpval2, resid); 695 696 tmpval = htonl(tmpval2); 697 698 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 699 ti_offset, &tmpval, 1); 700 } 701 } 702 703 CSR_WRITE_4(sc, TI_WINBASE, origwin); 704 705 return (0); 706} 707 708static int 709ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 710 struct ti_softc *sc; 711 u_int32_t tigon_addr, len; 712 caddr_t buf; 713 int useraddr, readdata; 714 int cpu; 715{ 716 u_int32_t segptr; 717 int cnt; 718 u_int32_t tmpval, tmpval2; 719 caddr_t ptr; 720 721 TI_LOCK_ASSERT(sc); 722 723 /* 724 * At the moment, we don't handle non-aligned cases, we just bail. 725 * If this proves to be a problem, it will be fixed. 726 */ 727 if (tigon_addr & 0x3) { 728 if_printf(sc->ti_ifp, "ti_copy_scratch: tigon address %#x " 729 "isn't word-aligned\n", tigon_addr); 730 return (EINVAL); 731 } 732 733 if (len & 0x3) { 734 if_printf(sc->ti_ifp, "ti_copy_scratch: transfer length %d " 735 "isn't word-aligned\n", len); 736 return (EINVAL); 737 } 738 739 segptr = tigon_addr; 740 cnt = len; 741 ptr = buf; 742 743 while (cnt) { 744 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 745 746 if (readdata) { 747 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 748 749 tmpval = ntohl(tmpval2); 750 751 /* 752 * Note: I've used this debugging interface 753 * extensively with Alteon's 12.3.15 firmware, 754 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 755 * 756 * When you compile the firmware without 757 * optimization, which is necessary sometimes in 758 * order to properly step through it, you sometimes 759 * read out a bogus value of 0xc0017c instead of 760 * whatever was supposed to be in that scratchpad 761 * location. That value is on the stack somewhere, 762 * but I've never been able to figure out what was 763 * causing the problem. 764 * 765 * The address seems to pop up in random places, 766 * often not in the same place on two subsequent 767 * reads. 768 * 769 * In any case, the underlying data doesn't seem 770 * to be affected, just the value read out. 771 * 772 * KDM, 3/7/2000 773 */ 774 775 if (tmpval2 == 0xc0017c) 776 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 777 "(tmpval2)\n", segptr); 778 779 if (tmpval == 0xc0017c) 780 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 781 "(tmpval)\n", segptr); 782 783 if (useraddr) 784 copyout(&tmpval, ptr, 4); 785 else 786 bcopy(&tmpval, ptr, 4); 787 } else { 788 if (useraddr) 789 copyin(ptr, &tmpval2, 4); 790 else 791 bcopy(ptr, &tmpval2, 4); 792 793 tmpval = htonl(tmpval2); 794 795 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 796 } 797 798 cnt -= 4; 799 segptr += 4; 800 ptr += 4; 801 } 802 803 return (0); 804} 805 806static int 807ti_bcopy_swap(src, dst, len, swap_type) 808 const void *src; 809 void *dst; 810 size_t len; 811 ti_swap_type swap_type; 812{ 813 const u_int8_t *tmpsrc; 814 u_int8_t *tmpdst; 815 size_t tmplen; 816 817 if (len & 0x3) { 818 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 819 len); 820 return (-1); 821 } 822 823 tmpsrc = src; 824 tmpdst = dst; 825 tmplen = len; 826 827 while (tmplen) { 828 if (swap_type == TI_SWAP_NTOH) 829 *(u_int32_t *)tmpdst = 830 ntohl(*(const u_int32_t *)tmpsrc); 831 else 832 *(u_int32_t *)tmpdst = 833 htonl(*(const u_int32_t *)tmpsrc); 834 835 tmpsrc += 4; 836 tmpdst += 4; 837 tmplen -= 4; 838 } 839 840 return (0); 841} 842 843/* 844 * Load firmware image into the NIC. Check that the firmware revision 845 * is acceptable and see if we want the firmware for the Tigon 1 or 846 * Tigon 2. 847 */ 848static void 849ti_loadfw(sc) 850 struct ti_softc *sc; 851{ 852 853 TI_LOCK_ASSERT(sc); 854 855 switch (sc->ti_hwrev) { 856 case TI_HWREV_TIGON: 857 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 858 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 859 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 860 if_printf(sc->ti_ifp, "firmware revision mismatch; " 861 "want %d.%d.%d, got %d.%d.%d\n", 862 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 863 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 864 tigonFwReleaseMinor, tigonFwReleaseFix); 865 return; 866 } 867 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 868 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 869 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 870 tigonFwRodata); 871 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 872 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 873 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 874 break; 875 case TI_HWREV_TIGON_II: 876 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 877 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 878 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 879 if_printf(sc->ti_ifp, "firmware revision mismatch; " 880 "want %d.%d.%d, got %d.%d.%d\n", 881 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 882 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 883 tigon2FwReleaseMinor, tigon2FwReleaseFix); 884 return; 885 } 886 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 887 tigon2FwText); 888 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 889 tigon2FwData); 890 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 891 tigon2FwRodata); 892 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 893 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 894 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 895 break; 896 default: 897 if_printf(sc->ti_ifp, 898 "can't load firmware: unknown hardware rev\n"); 899 break; 900 } 901} 902 903/* 904 * Send the NIC a command via the command ring. 905 */ 906static void 907ti_cmd(sc, cmd) 908 struct ti_softc *sc; 909 struct ti_cmd_desc *cmd; 910{ 911 u_int32_t index; 912 913 index = sc->ti_cmd_saved_prodidx; 914 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 915 TI_INC(index, TI_CMD_RING_CNT); 916 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 917 sc->ti_cmd_saved_prodidx = index; 918} 919 920/* 921 * Send the NIC an extended command. The 'len' parameter specifies the 922 * number of command slots to include after the initial command. 923 */ 924static void 925ti_cmd_ext(sc, cmd, arg, len) 926 struct ti_softc *sc; 927 struct ti_cmd_desc *cmd; 928 caddr_t arg; 929 int len; 930{ 931 u_int32_t index; 932 int i; 933 934 index = sc->ti_cmd_saved_prodidx; 935 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 936 TI_INC(index, TI_CMD_RING_CNT); 937 for (i = 0; i < len; i++) { 938 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 939 *(u_int32_t *)(&arg[i * 4])); 940 TI_INC(index, TI_CMD_RING_CNT); 941 } 942 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 943 sc->ti_cmd_saved_prodidx = index; 944} 945 946/* 947 * Handle events that have triggered interrupts. 948 */ 949static void 950ti_handle_events(sc) 951 struct ti_softc *sc; 952{ 953 struct ti_event_desc *e; 954 955 if (sc->ti_rdata->ti_event_ring == NULL) 956 return; 957 958 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 959 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 960 switch (TI_EVENT_EVENT(e)) { 961 case TI_EV_LINKSTAT_CHANGED: 962 sc->ti_linkstat = TI_EVENT_CODE(e); 963 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 964 if_printf(sc->ti_ifp, "10/100 link up\n"); 965 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 966 if_printf(sc->ti_ifp, "gigabit link up\n"); 967 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 968 if_printf(sc->ti_ifp, "link down\n"); 969 break; 970 case TI_EV_ERROR: 971 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 972 if_printf(sc->ti_ifp, "invalid command\n"); 973 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 974 if_printf(sc->ti_ifp, "unknown command\n"); 975 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 976 if_printf(sc->ti_ifp, "bad config data\n"); 977 break; 978 case TI_EV_FIRMWARE_UP: 979 ti_init2(sc); 980 break; 981 case TI_EV_STATS_UPDATED: 982 ti_stats_update(sc); 983 break; 984 case TI_EV_RESET_JUMBO_RING: 985 case TI_EV_MCAST_UPDATED: 986 /* Who cares. */ 987 break; 988 default: 989 if_printf(sc->ti_ifp, "unknown event: %d\n", 990 TI_EVENT_EVENT(e)); 991 break; 992 } 993 /* Advance the consumer index. */ 994 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 995 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 996 } 997} 998 999static int 1000ti_alloc_dmamaps(struct ti_softc *sc) 1001{ 1002 int i; 1003 1004 for (i = 0; i < TI_TX_RING_CNT; i++) { 1005 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006 &sc->ti_cdata.ti_tx_maps[i])) 1007 return (ENOBUFS); 1008 } 1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011 &sc->ti_cdata.ti_rx_std_maps[i])) 1012 return (ENOBUFS); 1013 } 1014 1015 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018 return (ENOBUFS); 1019 } 1020 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022 &sc->ti_cdata.ti_rx_mini_maps[i])) 1023 return (ENOBUFS); 1024 } 1025 1026 return (0); 1027} 1028 1029static void 1030ti_free_dmamaps(struct ti_softc *sc) 1031{ 1032 int i; 1033 1034 if (sc->ti_mbuftx_dmat) 1035 for (i = 0; i < TI_TX_RING_CNT; i++) 1036 if (sc->ti_cdata.ti_tx_maps[i]) { 1037 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038 sc->ti_cdata.ti_tx_maps[i]); 1039 sc->ti_cdata.ti_tx_maps[i] = 0; 1040 } 1041 1042 if (sc->ti_mbufrx_dmat) 1043 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046 sc->ti_cdata.ti_rx_std_maps[i]); 1047 sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048 } 1049 1050 if (sc->ti_jumbo_dmat) 1051 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056 } 1057 if (sc->ti_mbufrx_dmat) 1058 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061 sc->ti_cdata.ti_rx_mini_maps[i]); 1062 sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063 } 1064} 1065 1066#ifdef TI_PRIVATE_JUMBOS 1067 1068/* 1069 * Memory management for the jumbo receive ring is a pain in the 1070 * butt. We need to allocate at least 9018 bytes of space per frame, 1071 * _and_ it has to be contiguous (unless you use the extended 1072 * jumbo descriptor format). Using malloc() all the time won't 1073 * work: malloc() allocates memory in powers of two, which means we 1074 * would end up wasting a considerable amount of space by allocating 1075 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1076 * to do our own memory management. 1077 * 1078 * The driver needs to allocate a contiguous chunk of memory at boot 1079 * time. We then chop this up ourselves into 9K pieces and use them 1080 * as external mbuf storage. 1081 * 1082 * One issue here is how much memory to allocate. The jumbo ring has 1083 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1084 * RAM. This is a bit much, especially considering we also need 1085 * RAM for the standard ring and mini ring (on the Tigon 2). To 1086 * save space, we only actually allocate enough memory for 64 slots 1087 * by default, which works out to between 500 and 600K. This can 1088 * be tuned by changing a #define in if_tireg.h. 1089 */ 1090 1091static int 1092ti_alloc_jumbo_mem(sc) 1093 struct ti_softc *sc; 1094{ 1095 caddr_t ptr; 1096 int i; 1097 struct ti_jpool_entry *entry; 1098 1099 /* 1100 * Grab a big chunk o' storage. Since we are chopping this pool up 1101 * into ~9k chunks, there doesn't appear to be a need to use page 1102 * alignment. 1103 */ 1104 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105 1, 0, /* algnmnt, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 TI_JMEM, /* maxsize */ 1110 1, /* nsegments */ 1111 TI_JMEM, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ti_jumbo_dmat) != 0) { 1115 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116 return (ENOBUFS); 1117 } 1118 1119 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120 (void**)&sc->ti_cdata.ti_jumbo_buf, 1121 BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) { 1122 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1123 return (ENOBUFS); 1124 } 1125 1126 SLIST_INIT(&sc->ti_jfree_listhead); 1127 SLIST_INIT(&sc->ti_jinuse_listhead); 1128 1129 /* 1130 * Now divide it up into 9K pieces and save the addresses 1131 * in an array. 1132 */ 1133 ptr = sc->ti_cdata.ti_jumbo_buf; 1134 for (i = 0; i < TI_JSLOTS; i++) { 1135 sc->ti_cdata.ti_jslots[i] = ptr; 1136 ptr += TI_JLEN; 1137 entry = malloc(sizeof(struct ti_jpool_entry), 1138 M_DEVBUF, M_NOWAIT); 1139 if (entry == NULL) { 1140 device_printf(sc->ti_dev, "no memory for jumbo " 1141 "buffer queue!\n"); 1142 return (ENOBUFS); 1143 } 1144 entry->slot = i; 1145 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1146 } 1147 1148 return (0); 1149} 1150 1151/* 1152 * Allocate a jumbo buffer. 1153 */ 1154static void *ti_jalloc(sc) 1155 struct ti_softc *sc; 1156{ 1157 struct ti_jpool_entry *entry; 1158 1159 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1160 1161 if (entry == NULL) { 1162 if_printf(sc->ti_ifp, "no free jumbo buffers\n"); 1163 return (NULL); 1164 } 1165 1166 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1167 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1168 return (sc->ti_cdata.ti_jslots[entry->slot]); 1169} 1170 1171/* 1172 * Release a jumbo buffer. 1173 */ 1174static void 1175ti_jfree(buf, args) 1176 void *buf; 1177 void *args; 1178{ 1179 struct ti_softc *sc; 1180 int i; 1181 struct ti_jpool_entry *entry; 1182 1183 /* Extract the softc struct pointer. */ 1184 sc = (struct ti_softc *)args; 1185 1186 if (sc == NULL) 1187 panic("ti_jfree: didn't get softc pointer!"); 1188 1189 /* calculate the slot this buffer belongs to */ 1190 i = ((vm_offset_t)buf 1191 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1192 1193 if ((i < 0) || (i >= TI_JSLOTS)) 1194 panic("ti_jfree: asked to free buffer that we don't manage!"); 1195 1196 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1197 if (entry == NULL) 1198 panic("ti_jfree: buffer not in use!"); 1199 entry->slot = i; 1200 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1201 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1202} 1203 1204#else 1205 1206static int 1207ti_alloc_jumbo_mem(sc) 1208 struct ti_softc *sc; 1209{ 1210 1211 /* 1212 * The VM system will take care of providing aligned pages. Alignment 1213 * is set to 1 here so that busdma resources won't be wasted. 1214 */ 1215 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1216 1, 0, /* algnmnt, boundary */ 1217 BUS_SPACE_MAXADDR, /* lowaddr */ 1218 BUS_SPACE_MAXADDR, /* highaddr */ 1219 NULL, NULL, /* filter, filterarg */ 1220 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1221 4, /* nsegments */ 1222 PAGE_SIZE, /* maxsegsize */ 1223 0, /* flags */ 1224 NULL, NULL, /* lockfunc, lockarg */ 1225 &sc->ti_jumbo_dmat) != 0) { 1226 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1227 return (ENOBUFS); 1228 } 1229 1230 return (0); 1231} 1232 1233#endif /* TI_PRIVATE_JUMBOS */ 1234 1235/* 1236 * Intialize a standard receive ring descriptor. 1237 */ 1238static int 1239ti_newbuf_std(sc, i, m) 1240 struct ti_softc *sc; 1241 int i; 1242 struct mbuf *m; 1243{ 1244 bus_dmamap_t map; 1245 bus_dma_segment_t segs; 1246 struct mbuf *m_new = NULL; 1247 struct ti_rx_desc *r; 1248 int nsegs; 1249 1250 nsegs = 0; 1251 if (m == NULL) { 1252 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1253 if (m_new == NULL) 1254 return (ENOBUFS); 1255 1256 MCLGET(m_new, M_DONTWAIT); 1257 if (!(m_new->m_flags & M_EXT)) { 1258 m_freem(m_new); 1259 return (ENOBUFS); 1260 } 1261 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1262 } else { 1263 m_new = m; 1264 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1265 m_new->m_data = m_new->m_ext.ext_buf; 1266 } 1267 1268 m_adj(m_new, ETHER_ALIGN); 1269 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1270 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1271 map = sc->ti_cdata.ti_rx_std_maps[i]; 1272 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1273 &nsegs, 0)) 1274 return (ENOBUFS); 1275 if (nsegs != 1) 1276 return (ENOBUFS); 1277 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1278 r->ti_len = segs.ds_len; 1279 r->ti_type = TI_BDTYPE_RECV_BD; 1280 r->ti_flags = 0; 1281 if (sc->ti_ifp->if_hwassist) 1282 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1283 r->ti_idx = i; 1284 1285 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1286 return (0); 1287} 1288 1289/* 1290 * Intialize a mini receive ring descriptor. This only applies to 1291 * the Tigon 2. 1292 */ 1293static int 1294ti_newbuf_mini(sc, i, m) 1295 struct ti_softc *sc; 1296 int i; 1297 struct mbuf *m; 1298{ 1299 bus_dma_segment_t segs; 1300 bus_dmamap_t map; 1301 struct mbuf *m_new = NULL; 1302 struct ti_rx_desc *r; 1303 int nsegs; 1304 1305 nsegs = 0; 1306 if (m == NULL) { 1307 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1308 if (m_new == NULL) { 1309 return (ENOBUFS); 1310 } 1311 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1312 } else { 1313 m_new = m; 1314 m_new->m_data = m_new->m_pktdat; 1315 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1316 } 1317 1318 m_adj(m_new, ETHER_ALIGN); 1319 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1320 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1321 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1322 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1323 &nsegs, 0)) 1324 return (ENOBUFS); 1325 if (nsegs != 1) 1326 return (ENOBUFS); 1327 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1328 r->ti_len = segs.ds_len; 1329 r->ti_type = TI_BDTYPE_RECV_BD; 1330 r->ti_flags = TI_BDFLAG_MINI_RING; 1331 if (sc->ti_ifp->if_hwassist) 1332 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1333 r->ti_idx = i; 1334 1335 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1336 return (0); 1337} 1338 1339#ifdef TI_PRIVATE_JUMBOS 1340 1341/* 1342 * Initialize a jumbo receive ring descriptor. This allocates 1343 * a jumbo buffer from the pool managed internally by the driver. 1344 */ 1345static int 1346ti_newbuf_jumbo(sc, i, m) 1347 struct ti_softc *sc; 1348 int i; 1349 struct mbuf *m; 1350{ 1351 bus_dmamap_t map; 1352 struct mbuf *m_new = NULL; 1353 struct ti_rx_desc *r; 1354 int nsegs; 1355 bus_dma_segment_t segs; 1356 1357 if (m == NULL) { 1358 caddr_t *buf = NULL; 1359 1360 /* Allocate the mbuf. */ 1361 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1362 if (m_new == NULL) { 1363 return (ENOBUFS); 1364 } 1365 1366 /* Allocate the jumbo buffer */ 1367 buf = ti_jalloc(sc); 1368 if (buf == NULL) { 1369 m_freem(m_new); 1370 if_printf(sc->ti_ifp, "jumbo allocation failed " 1371 "-- packet dropped!\n"); 1372 return (ENOBUFS); 1373 } 1374 1375 /* Attach the buffer to the mbuf. */ 1376 m_new->m_data = (void *) buf; 1377 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1378 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1379 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1380 } else { 1381 m_new = m; 1382 m_new->m_data = m_new->m_ext.ext_buf; 1383 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1384 } 1385 1386 m_adj(m_new, ETHER_ALIGN); 1387 /* Set up the descriptor. */ 1388 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1389 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1390 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1391 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1392 &nsegs, 0)) 1393 return (ENOBUFS); 1394 if (nsegs != 1) 1395 return (ENOBUFS); 1396 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1397 r->ti_len = segs.ds_len; 1398 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1399 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1400 if (sc->ti_ifp->if_hwassist) 1401 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1402 r->ti_idx = i; 1403 1404 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1405 return (0); 1406} 1407 1408#else 1409 1410#if (PAGE_SIZE == 4096) 1411#define NPAYLOAD 2 1412#else 1413#define NPAYLOAD 1 1414#endif 1415 1416#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1417#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1418#define NFS_HDR_LEN (UDP_HDR_LEN) 1419static int HDR_LEN = TCP_HDR_LEN; 1420 1421 1422/* 1423 * Initialize a jumbo receive ring descriptor. This allocates 1424 * a jumbo buffer from the pool managed internally by the driver. 1425 */ 1426static int 1427ti_newbuf_jumbo(sc, idx, m_old) 1428 struct ti_softc *sc; 1429 int idx; 1430 struct mbuf *m_old; 1431{ 1432 bus_dmamap_t map; 1433 struct mbuf *cur, *m_new = NULL; 1434 struct mbuf *m[3] = {NULL, NULL, NULL}; 1435 struct ti_rx_desc_ext *r; 1436 vm_page_t frame; 1437 static int color; 1438 /* 1 extra buf to make nobufs easy*/ 1439 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1440 int i; 1441 bus_dma_segment_t segs[4]; 1442 int nsegs; 1443 1444 if (m_old != NULL) { 1445 m_new = m_old; 1446 cur = m_old->m_next; 1447 for (i = 0; i <= NPAYLOAD; i++){ 1448 m[i] = cur; 1449 cur = cur->m_next; 1450 } 1451 } else { 1452 /* Allocate the mbufs. */ 1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1454 if (m_new == NULL) { 1455 if_printf(sc->ti_ifp, "mbuf allocation failed " 1456 "-- packet dropped!\n"); 1457 goto nobufs; 1458 } 1459 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1460 if (m[NPAYLOAD] == NULL) { 1461 if_printf(sc->ti_ifp, "cluster mbuf allocation failed " 1462 "-- packet dropped!\n"); 1463 goto nobufs; 1464 } 1465 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1466 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1467 if_printf(sc->ti_ifp, "mbuf allocation failed " 1468 "-- packet dropped!\n"); 1469 goto nobufs; 1470 } 1471 m[NPAYLOAD]->m_len = MCLBYTES; 1472 1473 for (i = 0; i < NPAYLOAD; i++){ 1474 MGET(m[i], M_DONTWAIT, MT_DATA); 1475 if (m[i] == NULL) { 1476 if_printf(sc->ti_ifp, "mbuf allocation failed " 1477 "-- packet dropped!\n"); 1478 goto nobufs; 1479 } 1480 frame = vm_page_alloc(NULL, color++, 1481 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1482 VM_ALLOC_WIRED); 1483 if (frame == NULL) { 1484 if_printf(sc->ti_ifp, "buffer allocation " 1485 "failed -- packet dropped!\n"); 1486 printf(" index %d page %d\n", idx, i); 1487 goto nobufs; 1488 } 1489 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1490 if (sf[i] == NULL) { 1491 vm_page_lock_queues(); 1492 vm_page_unwire(frame, 0); 1493 vm_page_free(frame); 1494 vm_page_unlock_queues(); 1495 if_printf(sc->ti_ifp, "buffer allocation " 1496 "failed -- packet dropped!\n"); 1497 printf(" index %d page %d\n", idx, i); 1498 goto nobufs; 1499 } 1500 } 1501 for (i = 0; i < NPAYLOAD; i++){ 1502 /* Attach the buffer to the mbuf. */ 1503 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1504 m[i]->m_len = PAGE_SIZE; 1505 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1506 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 1507 m[i]->m_next = m[i+1]; 1508 } 1509 /* link the buffers to the header */ 1510 m_new->m_next = m[0]; 1511 m_new->m_data += ETHER_ALIGN; 1512 if (sc->ti_hdrsplit) 1513 m_new->m_len = MHLEN - ETHER_ALIGN; 1514 else 1515 m_new->m_len = HDR_LEN; 1516 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1517 } 1518 1519 /* Set up the descriptor. */ 1520 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1521 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1522 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1523 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1524 &nsegs, 0)) 1525 return (ENOBUFS); 1526 if ((nsegs < 1) || (nsegs > 4)) 1527 return (ENOBUFS); 1528 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1529 r->ti_len0 = m_new->m_len; 1530 1531 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1532 r->ti_len1 = PAGE_SIZE; 1533 1534 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1535 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1536 1537 if (PAGE_SIZE == 4096) { 1538 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1539 r->ti_len3 = MCLBYTES; 1540 } else { 1541 r->ti_len3 = 0; 1542 } 1543 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1544 1545 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1546 1547 if (sc->ti_ifp->if_hwassist) 1548 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1549 1550 r->ti_idx = idx; 1551 1552 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1553 return (0); 1554 1555nobufs: 1556 1557 /* 1558 * Warning! : 1559 * This can only be called before the mbufs are strung together. 1560 * If the mbufs are strung together, m_freem() will free the chain, 1561 * so that the later mbufs will be freed multiple times. 1562 */ 1563 if (m_new) 1564 m_freem(m_new); 1565 1566 for (i = 0; i < 3; i++) { 1567 if (m[i]) 1568 m_freem(m[i]); 1569 if (sf[i]) 1570 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1571 } 1572 return (ENOBUFS); 1573} 1574#endif 1575 1576 1577 1578/* 1579 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1580 * that's 1MB or memory, which is a lot. For now, we fill only the first 1581 * 256 ring entries and hope that our CPU is fast enough to keep up with 1582 * the NIC. 1583 */ 1584static int 1585ti_init_rx_ring_std(sc) 1586 struct ti_softc *sc; 1587{ 1588 int i; 1589 struct ti_cmd_desc cmd; 1590 1591 for (i = 0; i < TI_SSLOTS; i++) { 1592 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1593 return (ENOBUFS); 1594 }; 1595 1596 TI_UPDATE_STDPROD(sc, i - 1); 1597 sc->ti_std = i - 1; 1598 1599 return (0); 1600} 1601 1602static void 1603ti_free_rx_ring_std(sc) 1604 struct ti_softc *sc; 1605{ 1606 bus_dmamap_t map; 1607 int i; 1608 1609 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1610 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1611 map = sc->ti_cdata.ti_rx_std_maps[i]; 1612 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1613 BUS_DMASYNC_POSTREAD); 1614 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1615 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1616 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1617 } 1618 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1619 sizeof(struct ti_rx_desc)); 1620 } 1621} 1622 1623static int 1624ti_init_rx_ring_jumbo(sc) 1625 struct ti_softc *sc; 1626{ 1627 int i; 1628 struct ti_cmd_desc cmd; 1629 1630 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1631 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1632 return (ENOBUFS); 1633 }; 1634 1635 TI_UPDATE_JUMBOPROD(sc, i - 1); 1636 sc->ti_jumbo = i - 1; 1637 1638 return (0); 1639} 1640 1641static void 1642ti_free_rx_ring_jumbo(sc) 1643 struct ti_softc *sc; 1644{ 1645 bus_dmamap_t map; 1646 int i; 1647 1648 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1649 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1650 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1651 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1652 BUS_DMASYNC_POSTREAD); 1653 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1654 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1655 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1656 } 1657 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1658 sizeof(struct ti_rx_desc)); 1659 } 1660} 1661 1662static int 1663ti_init_rx_ring_mini(sc) 1664 struct ti_softc *sc; 1665{ 1666 int i; 1667 1668 for (i = 0; i < TI_MSLOTS; i++) { 1669 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1670 return (ENOBUFS); 1671 }; 1672 1673 TI_UPDATE_MINIPROD(sc, i - 1); 1674 sc->ti_mini = i - 1; 1675 1676 return (0); 1677} 1678 1679static void 1680ti_free_rx_ring_mini(sc) 1681 struct ti_softc *sc; 1682{ 1683 bus_dmamap_t map; 1684 int i; 1685 1686 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1687 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1688 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1689 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1690 BUS_DMASYNC_POSTREAD); 1691 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1692 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1693 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1694 } 1695 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1696 sizeof(struct ti_rx_desc)); 1697 } 1698} 1699 1700static void 1701ti_free_tx_ring(sc) 1702 struct ti_softc *sc; 1703{ 1704 bus_dmamap_t map; 1705 int i; 1706 1707 if (sc->ti_rdata->ti_tx_ring == NULL) 1708 return; 1709 1710 for (i = 0; i < TI_TX_RING_CNT; i++) { 1711 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1712 map = sc->ti_cdata.ti_tx_maps[i]; 1713 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 1716 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1717 sc->ti_cdata.ti_tx_chain[i] = NULL; 1718 } 1719 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1720 sizeof(struct ti_tx_desc)); 1721 } 1722} 1723 1724static int 1725ti_init_tx_ring(sc) 1726 struct ti_softc *sc; 1727{ 1728 sc->ti_txcnt = 0; 1729 sc->ti_tx_saved_considx = 0; 1730 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1731 return (0); 1732} 1733 1734/* 1735 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1736 * but we have to support the old way too so that Tigon 1 cards will 1737 * work. 1738 */ 1739static void 1740ti_add_mcast(sc, addr) 1741 struct ti_softc *sc; 1742 struct ether_addr *addr; 1743{ 1744 struct ti_cmd_desc cmd; 1745 u_int16_t *m; 1746 u_int32_t ext[2] = {0, 0}; 1747 1748 m = (u_int16_t *)&addr->octet[0]; 1749 1750 switch (sc->ti_hwrev) { 1751 case TI_HWREV_TIGON: 1752 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1753 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1754 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1755 break; 1756 case TI_HWREV_TIGON_II: 1757 ext[0] = htons(m[0]); 1758 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1759 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1760 break; 1761 default: 1762 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1763 break; 1764 } 1765} 1766 1767static void 1768ti_del_mcast(sc, addr) 1769 struct ti_softc *sc; 1770 struct ether_addr *addr; 1771{ 1772 struct ti_cmd_desc cmd; 1773 u_int16_t *m; 1774 u_int32_t ext[2] = {0, 0}; 1775 1776 m = (u_int16_t *)&addr->octet[0]; 1777 1778 switch (sc->ti_hwrev) { 1779 case TI_HWREV_TIGON: 1780 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1781 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1782 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1783 break; 1784 case TI_HWREV_TIGON_II: 1785 ext[0] = htons(m[0]); 1786 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1787 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1788 break; 1789 default: 1790 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1791 break; 1792 } 1793} 1794 1795/* 1796 * Configure the Tigon's multicast address filter. 1797 * 1798 * The actual multicast table management is a bit of a pain, thanks to 1799 * slight brain damage on the part of both Alteon and us. With our 1800 * multicast code, we are only alerted when the multicast address table 1801 * changes and at that point we only have the current list of addresses: 1802 * we only know the current state, not the previous state, so we don't 1803 * actually know what addresses were removed or added. The firmware has 1804 * state, but we can't get our grubby mits on it, and there is no 'delete 1805 * all multicast addresses' command. Hence, we have to maintain our own 1806 * state so we know what addresses have been programmed into the NIC at 1807 * any given time. 1808 */ 1809static void 1810ti_setmulti(sc) 1811 struct ti_softc *sc; 1812{ 1813 struct ifnet *ifp; 1814 struct ifmultiaddr *ifma; 1815 struct ti_cmd_desc cmd; 1816 struct ti_mc_entry *mc; 1817 u_int32_t intrs; 1818 1819 TI_LOCK_ASSERT(sc); 1820 1821 ifp = sc->ti_ifp; 1822 1823 if (ifp->if_flags & IFF_ALLMULTI) { 1824 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1825 return; 1826 } else { 1827 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1828 } 1829 1830 /* Disable interrupts. */ 1831 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1832 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1833 1834 /* First, zot all the existing filters. */ 1835 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1836 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1837 ti_del_mcast(sc, &mc->mc_addr); 1838 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1839 free(mc, M_DEVBUF); 1840 } 1841 1842 /* Now program new ones. */ 1843 IF_ADDR_LOCK(ifp); 1844 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1845 if (ifma->ifma_addr->sa_family != AF_LINK) 1846 continue; 1847 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1848 if (mc == NULL) { 1849 if_printf(ifp, "no memory for mcast filter entry\n"); 1850 continue; 1851 } 1852 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1853 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1854 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1855 ti_add_mcast(sc, &mc->mc_addr); 1856 } 1857 IF_ADDR_UNLOCK(ifp); 1858 1859 /* Re-enable interrupts. */ 1860 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1861} 1862 1863/* 1864 * Check to see if the BIOS has configured us for a 64 bit slot when 1865 * we aren't actually in one. If we detect this condition, we can work 1866 * around it on the Tigon 2 by setting a bit in the PCI state register, 1867 * but for the Tigon 1 we must give up and abort the interface attach. 1868 */ 1869static int ti_64bitslot_war(sc) 1870 struct ti_softc *sc; 1871{ 1872 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1873 CSR_WRITE_4(sc, 0x600, 0); 1874 CSR_WRITE_4(sc, 0x604, 0); 1875 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1876 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1877 if (sc->ti_hwrev == TI_HWREV_TIGON) 1878 return (EINVAL); 1879 else { 1880 TI_SETBIT(sc, TI_PCI_STATE, 1881 TI_PCISTATE_32BIT_BUS); 1882 return (0); 1883 } 1884 } 1885 } 1886 1887 return (0); 1888} 1889 1890/* 1891 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1892 * self-test results. 1893 */ 1894static int 1895ti_chipinit(sc) 1896 struct ti_softc *sc; 1897{ 1898 u_int32_t cacheline; 1899 u_int32_t pci_writemax = 0; 1900 u_int32_t hdrsplit; 1901 1902 /* Initialize link to down state. */ 1903 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1904 1905 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1906 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1907 else 1908 sc->ti_ifp->if_hwassist = 0; 1909 1910 /* Set endianness before we access any non-PCI registers. */ 1911#if 0 && BYTE_ORDER == BIG_ENDIAN 1912 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1913 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1914#else 1915 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1916 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1917#endif 1918 1919 /* Check the ROM failed bit to see if self-tests passed. */ 1920 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1921 if_printf(sc->ti_ifp, "board self-diagnostics failed!\n"); 1922 return (ENODEV); 1923 } 1924 1925 /* Halt the CPU. */ 1926 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1927 1928 /* Figure out the hardware revision. */ 1929 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1930 case TI_REV_TIGON_I: 1931 sc->ti_hwrev = TI_HWREV_TIGON; 1932 break; 1933 case TI_REV_TIGON_II: 1934 sc->ti_hwrev = TI_HWREV_TIGON_II; 1935 break; 1936 default: 1937 if_printf(sc->ti_ifp, "unsupported chip revision\n"); 1938 return (ENODEV); 1939 } 1940 1941 /* Do special setup for Tigon 2. */ 1942 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1943 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1944 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1945 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1946 } 1947 1948 /* 1949 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1950 * can't do header splitting. 1951 */ 1952#ifdef TI_JUMBO_HDRSPLIT 1953 if (sc->ti_hwrev != TI_HWREV_TIGON) 1954 sc->ti_hdrsplit = 1; 1955 else 1956 if_printf(sc->ti_ifp, 1957 "can't do header splitting on a Tigon I board\n"); 1958#endif /* TI_JUMBO_HDRSPLIT */ 1959 1960 /* Set up the PCI state register. */ 1961 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1962 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1963 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1964 } 1965 1966 /* Clear the read/write max DMA parameters. */ 1967 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1968 TI_PCISTATE_READ_MAXDMA)); 1969 1970 /* Get cache line size. */ 1971 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1972 1973 /* 1974 * If the system has set enabled the PCI memory write 1975 * and invalidate command in the command register, set 1976 * the write max parameter accordingly. This is necessary 1977 * to use MWI with the Tigon 2. 1978 */ 1979 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1980 switch (cacheline) { 1981 case 1: 1982 case 4: 1983 case 8: 1984 case 16: 1985 case 32: 1986 case 64: 1987 break; 1988 default: 1989 /* Disable PCI memory write and invalidate. */ 1990 if (bootverbose) 1991 if_printf(sc->ti_ifp, "cache line size %d not " 1992 "supported; disabling PCI MWI\n", 1993 cacheline); 1994 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1995 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1996 break; 1997 } 1998 } 1999 2000#ifdef __brokenalpha__ 2001 /* 2002 * From the Alteon sample driver: 2003 * Must insure that we do not cross an 8K (bytes) boundary 2004 * for DMA reads. Our highest limit is 1K bytes. This is a 2005 * restriction on some ALPHA platforms with early revision 2006 * 21174 PCI chipsets, such as the AlphaPC 164lx 2007 */ 2008 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 2009#else 2010 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2011#endif 2012 2013 /* This sets the min dma param all the way up (0xff). */ 2014 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2015 2016 if (sc->ti_hdrsplit) 2017 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2018 else 2019 hdrsplit = 0; 2020 2021 /* Configure DMA variables. */ 2022#if BYTE_ORDER == BIG_ENDIAN 2023 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2024 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2025 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2026 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2027#else /* BYTE_ORDER */ 2028 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2029 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2030 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2031#endif /* BYTE_ORDER */ 2032 2033 /* 2034 * Only allow 1 DMA channel to be active at a time. 2035 * I don't think this is a good idea, but without it 2036 * the firmware racks up lots of nicDmaReadRingFull 2037 * errors. This is not compatible with hardware checksums. 2038 */ 2039 if (sc->ti_ifp->if_hwassist == 0) 2040 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2041 2042 /* Recommended settings from Tigon manual. */ 2043 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2044 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2045 2046 if (ti_64bitslot_war(sc)) { 2047 if_printf(sc->ti_ifp, "bios thinks we're in a 64 bit slot, " 2048 "but we aren't"); 2049 return (EINVAL); 2050 } 2051 2052 return (0); 2053} 2054 2055/* 2056 * Initialize the general information block and firmware, and 2057 * start the CPU(s) running. 2058 */ 2059static int 2060ti_gibinit(sc) 2061 struct ti_softc *sc; 2062{ 2063 struct ti_rcb *rcb; 2064 int i; 2065 struct ifnet *ifp; 2066 uint32_t rdphys; 2067 2068 TI_LOCK_ASSERT(sc); 2069 2070 ifp = sc->ti_ifp; 2071 rdphys = sc->ti_rdata_phys; 2072 2073 /* Disable interrupts for now. */ 2074 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2075 2076 /* 2077 * Tell the chip where to find the general information block. 2078 * While this struct could go into >4GB memory, we allocate it in a 2079 * single slab with the other descriptors, and those don't seem to 2080 * support being located in a 64-bit region. 2081 */ 2082 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2083 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2084 2085 /* Load the firmware into SRAM. */ 2086 ti_loadfw(sc); 2087 2088 /* Set up the contents of the general info and ring control blocks. */ 2089 2090 /* Set up the event ring and producer pointer. */ 2091 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2092 2093 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2094 rcb->ti_flags = 0; 2095 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2096 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2097 sc->ti_ev_prodidx.ti_idx = 0; 2098 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2099 sc->ti_ev_saved_considx = 0; 2100 2101 /* Set up the command ring and producer mailbox. */ 2102 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2103 2104 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2105 rcb->ti_flags = 0; 2106 rcb->ti_max_len = 0; 2107 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2108 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2109 } 2110 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2111 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2112 sc->ti_cmd_saved_prodidx = 0; 2113 2114 /* 2115 * Assign the address of the stats refresh buffer. 2116 * We re-use the current stats buffer for this to 2117 * conserve memory. 2118 */ 2119 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2120 rdphys + TI_RD_OFF(ti_info.ti_stats); 2121 2122 /* Set up the standard receive ring. */ 2123 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2124 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2125 rcb->ti_max_len = TI_FRAMELEN; 2126 rcb->ti_flags = 0; 2127 if (sc->ti_ifp->if_hwassist) 2128 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2129 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2130 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2131 2132 /* Set up the jumbo receive ring. */ 2133 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2134 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2135 2136#ifdef TI_PRIVATE_JUMBOS 2137 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2138 rcb->ti_flags = 0; 2139#else 2140 rcb->ti_max_len = PAGE_SIZE; 2141 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2142#endif 2143 if (sc->ti_ifp->if_hwassist) 2144 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2145 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2146 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2147 2148 /* 2149 * Set up the mini ring. Only activated on the 2150 * Tigon 2 but the slot in the config block is 2151 * still there on the Tigon 1. 2152 */ 2153 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2154 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2155 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2156 if (sc->ti_hwrev == TI_HWREV_TIGON) 2157 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2158 else 2159 rcb->ti_flags = 0; 2160 if (sc->ti_ifp->if_hwassist) 2161 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2162 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2163 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2164 2165 /* 2166 * Set up the receive return ring. 2167 */ 2168 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2169 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2170 rcb->ti_flags = 0; 2171 rcb->ti_max_len = TI_RETURN_RING_CNT; 2172 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2173 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2174 2175 /* 2176 * Set up the tx ring. Note: for the Tigon 2, we have the option 2177 * of putting the transmit ring in the host's address space and 2178 * letting the chip DMA it instead of leaving the ring in the NIC's 2179 * memory and accessing it through the shared memory region. We 2180 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2181 * so we have to revert to the shared memory scheme if we detect 2182 * a Tigon 1 chip. 2183 */ 2184 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2185 bzero((char *)sc->ti_rdata->ti_tx_ring, 2186 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2187 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2188 if (sc->ti_hwrev == TI_HWREV_TIGON) 2189 rcb->ti_flags = 0; 2190 else 2191 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2192 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2193 if (sc->ti_ifp->if_hwassist) 2194 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2195 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2196 rcb->ti_max_len = TI_TX_RING_CNT; 2197 if (sc->ti_hwrev == TI_HWREV_TIGON) 2198 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2199 else 2200 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2201 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2202 rdphys + TI_RD_OFF(ti_tx_considx_r); 2203 2204 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2205 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2206 2207 /* Set up tuneables */ 2208#if 0 2209 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2210 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2211 (sc->ti_rx_coal_ticks / 10)); 2212 else 2213#endif 2214 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2215 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2216 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2217 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2218 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2219 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2220 2221 /* Turn interrupts on. */ 2222 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2223 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2224 2225 /* Start CPU. */ 2226 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2227 2228 return (0); 2229} 2230 2231static void 2232ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2233{ 2234 struct ti_softc *sc; 2235 2236 sc = arg; 2237 if (error || nseg != 1) 2238 return; 2239 2240 /* 2241 * All of the Tigon data structures need to live at <4GB. This 2242 * cast is fine since busdma was told about this constraint. 2243 */ 2244 sc->ti_rdata_phys = segs[0].ds_addr; 2245 return; 2246} 2247 2248/* 2249 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2250 * against our list and return its name if we find a match. 2251 */ 2252static int 2253ti_probe(dev) 2254 device_t dev; 2255{ 2256 struct ti_type *t; 2257 2258 t = ti_devs; 2259 2260 while (t->ti_name != NULL) { 2261 if ((pci_get_vendor(dev) == t->ti_vid) && 2262 (pci_get_device(dev) == t->ti_did)) { 2263 device_set_desc(dev, t->ti_name); 2264 return (BUS_PROBE_DEFAULT); 2265 } 2266 t++; 2267 } 2268 2269 return (ENXIO); 2270} 2271 2272static int 2273ti_attach(dev) 2274 device_t dev; 2275{ 2276 struct ifnet *ifp; 2277 struct ti_softc *sc; 2278 int error = 0, rid; 2279 u_char eaddr[6]; 2280 2281 sc = device_get_softc(dev); 2282 sc->ti_unit = device_get_unit(dev); 2283 sc->ti_dev = dev; 2284 2285 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2286 MTX_DEF); 2287 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2288 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2289 if (ifp == NULL) { 2290 device_printf(dev, "can not if_alloc()\n"); 2291 error = ENOSPC; 2292 goto fail; 2293 } 2294 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2295 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2296 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2297 2298 /* 2299 * Map control/status registers. 2300 */ 2301 pci_enable_busmaster(dev); 2302 2303 rid = TI_PCI_LOMEM; 2304 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2305 RF_ACTIVE|PCI_RF_DENSE); 2306 2307 if (sc->ti_res == NULL) { 2308 device_printf(dev, "couldn't map memory\n"); 2309 error = ENXIO; 2310 goto fail; 2311 } 2312 2313 sc->ti_btag = rman_get_bustag(sc->ti_res); 2314 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2315 2316 /* Allocate interrupt */ 2317 rid = 0; 2318 2319 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2320 RF_SHAREABLE | RF_ACTIVE); 2321 2322 if (sc->ti_irq == NULL) { 2323 device_printf(dev, "couldn't map interrupt\n"); 2324 error = ENXIO; 2325 goto fail; 2326 } 2327 2328 if (ti_chipinit(sc)) { 2329 device_printf(dev, "chip initialization failed\n"); 2330 error = ENXIO; 2331 goto fail; 2332 } 2333 2334 /* Zero out the NIC's on-board SRAM. */ 2335 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2336 2337 /* Init again -- zeroing memory may have clobbered some registers. */ 2338 if (ti_chipinit(sc)) { 2339 device_printf(dev, "chip initialization failed\n"); 2340 error = ENXIO; 2341 goto fail; 2342 } 2343 2344 /* 2345 * Get station address from the EEPROM. Note: the manual states 2346 * that the MAC address is at offset 0x8c, however the data is 2347 * stored as two longwords (since that's how it's loaded into 2348 * the NIC). This means the MAC address is actually preceded 2349 * by two zero bytes. We need to skip over those. 2350 */ 2351 if (ti_read_eeprom(sc, eaddr, 2352 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2353 device_printf(dev, "failed to read station address\n"); 2354 error = ENXIO; 2355 goto fail; 2356 } 2357 2358 /* Allocate the general information block and ring buffers. */ 2359 if (bus_dma_tag_create(NULL, /* parent */ 2360 1, 0, /* algnmnt, boundary */ 2361 BUS_SPACE_MAXADDR, /* lowaddr */ 2362 BUS_SPACE_MAXADDR, /* highaddr */ 2363 NULL, NULL, /* filter, filterarg */ 2364 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2365 0, /* nsegments */ 2366 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2367 0, /* flags */ 2368 NULL, NULL, /* lockfunc, lockarg */ 2369 &sc->ti_parent_dmat) != 0) { 2370 device_printf(dev, "Failed to allocate parent dmat\n"); 2371 error = ENOMEM; 2372 goto fail; 2373 } 2374 2375 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2376 PAGE_SIZE, 0, /* algnmnt, boundary */ 2377 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2378 BUS_SPACE_MAXADDR, /* highaddr */ 2379 NULL, NULL, /* filter, filterarg */ 2380 sizeof(struct ti_ring_data), /* maxsize */ 2381 1, /* nsegments */ 2382 sizeof(struct ti_ring_data), /* maxsegsize */ 2383 0, /* flags */ 2384 NULL, NULL, /* lockfunc, lockarg */ 2385 &sc->ti_rdata_dmat) != 0) { 2386 device_printf(dev, "Failed to allocate rdata dmat\n"); 2387 error = ENOMEM; 2388 goto fail; 2389 } 2390 2391 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2392 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2393 device_printf(dev, "Failed to allocate rdata memory\n"); 2394 error = ENOMEM; 2395 goto fail; 2396 } 2397 2398 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2399 sc->ti_rdata, sizeof(struct ti_ring_data), 2400 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2401 device_printf(dev, "Failed to load rdata segments\n"); 2402 error = ENOMEM; 2403 goto fail; 2404 } 2405 2406 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2407 2408 /* Try to allocate memory for jumbo buffers. */ 2409 if (ti_alloc_jumbo_mem(sc)) { 2410 device_printf(dev, "jumbo buffer allocation failed\n"); 2411 error = ENXIO; 2412 goto fail; 2413 } 2414 2415 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2416 1, 0, /* algnmnt, boundary */ 2417 BUS_SPACE_MAXADDR, /* lowaddr */ 2418 BUS_SPACE_MAXADDR, /* highaddr */ 2419 NULL, NULL, /* filter, filterarg */ 2420 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2421 TI_MAXTXSEGS, /* nsegments */ 2422 MCLBYTES, /* maxsegsize */ 2423 0, /* flags */ 2424 NULL, NULL, /* lockfunc, lockarg */ 2425 &sc->ti_mbuftx_dmat) != 0) { 2426 device_printf(dev, "Failed to allocate rdata dmat\n"); 2427 error = ENOMEM; 2428 goto fail; 2429 } 2430 2431 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2432 1, 0, /* algnmnt, boundary */ 2433 BUS_SPACE_MAXADDR, /* lowaddr */ 2434 BUS_SPACE_MAXADDR, /* highaddr */ 2435 NULL, NULL, /* filter, filterarg */ 2436 MCLBYTES, /* maxsize */ 2437 1, /* nsegments */ 2438 MCLBYTES, /* maxsegsize */ 2439 0, /* flags */ 2440 NULL, NULL, /* lockfunc, lockarg */ 2441 &sc->ti_mbufrx_dmat) != 0) { 2442 device_printf(dev, "Failed to allocate rdata dmat\n"); 2443 error = ENOMEM; 2444 goto fail; 2445 } 2446 2447 if (ti_alloc_dmamaps(sc)) { 2448 device_printf(dev, "dma map creation failed\n"); 2449 error = ENXIO; 2450 goto fail; 2451 } 2452 2453 /* 2454 * We really need a better way to tell a 1000baseTX card 2455 * from a 1000baseSX one, since in theory there could be 2456 * OEMed 1000baseTX cards from lame vendors who aren't 2457 * clever enough to change the PCI ID. For the moment 2458 * though, the AceNIC is the only copper card available. 2459 */ 2460 if (pci_get_vendor(dev) == ALT_VENDORID && 2461 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2462 sc->ti_copper = 1; 2463 /* Ok, it's not the only copper card available. */ 2464 if (pci_get_vendor(dev) == NG_VENDORID && 2465 pci_get_device(dev) == NG_DEVICEID_GA620T) 2466 sc->ti_copper = 1; 2467 2468 /* Set default tuneable values. */ 2469 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2470#if 0 2471 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2472#endif 2473 sc->ti_rx_coal_ticks = 170; 2474 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2475 sc->ti_rx_max_coal_bds = 64; 2476#if 0 2477 sc->ti_tx_max_coal_bds = 128; 2478#endif 2479 sc->ti_tx_max_coal_bds = 32; 2480 sc->ti_tx_buf_ratio = 21; 2481 2482 /* Set up ifnet structure */ 2483 ifp->if_softc = sc; 2484 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2486 ifp->if_ioctl = ti_ioctl; 2487 ifp->if_start = ti_start; 2488 ifp->if_watchdog = ti_watchdog; 2489 ifp->if_init = ti_init; 2490 ifp->if_mtu = ETHERMTU; 2491 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2492 2493 /* Set up ifmedia support. */ 2494 if (sc->ti_copper) { 2495 /* 2496 * Copper cards allow manual 10/100 mode selection, 2497 * but not manual 1000baseTX mode selection. Why? 2498 * Becuase currently there's no way to specify the 2499 * master/slave setting through the firmware interface, 2500 * so Alteon decided to just bag it and handle it 2501 * via autonegotiation. 2502 */ 2503 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2504 ifmedia_add(&sc->ifmedia, 2505 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2506 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2507 ifmedia_add(&sc->ifmedia, 2508 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2510 ifmedia_add(&sc->ifmedia, 2511 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2512 } else { 2513 /* Fiber cards don't support 10/100 modes. */ 2514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2515 ifmedia_add(&sc->ifmedia, 2516 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2517 } 2518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2519 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2520 2521 /* 2522 * We're assuming here that card initialization is a sequential 2523 * thing. If it isn't, multiple cards probing at the same time 2524 * could stomp on the list of softcs here. 2525 */ 2526 2527 /* Register the device */ 2528 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2529 0600, "ti%d", sc->ti_unit); 2530 sc->dev->si_drv1 = sc; 2531 2532 /* 2533 * Call MI attach routine. 2534 */ 2535 ether_ifattach(ifp, eaddr); 2536 2537 /* Hook interrupt last to avoid having to lock softc */ 2538 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2539 ti_intr, sc, &sc->ti_intrhand); 2540 2541 if (error) { 2542 device_printf(dev, "couldn't set up irq\n"); 2543 goto fail; 2544 } 2545 2546fail: 2547 if (error) 2548 ti_detach(dev); 2549 2550 return (error); 2551} 2552 2553/* 2554 * Shutdown hardware and free up resources. This can be called any 2555 * time after the mutex has been initialized. It is called in both 2556 * the error case in attach and the normal detach case so it needs 2557 * to be careful about only freeing resources that have actually been 2558 * allocated. 2559 */ 2560static int 2561ti_detach(dev) 2562 device_t dev; 2563{ 2564 struct ti_softc *sc; 2565 struct ifnet *ifp; 2566 int attached; 2567 2568 sc = device_get_softc(dev); 2569 if (sc->dev) 2570 destroy_dev(sc->dev); 2571 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2572 attached = device_is_attached(dev); 2573 TI_LOCK(sc); 2574 ifp = sc->ti_ifp; 2575 if (attached) 2576 ti_stop(sc); 2577 TI_UNLOCK(sc); 2578 if (attached) 2579 ether_ifdetach(ifp); 2580 2581 /* These should only be active if attach succeeded */ 2582 if (attached) 2583 bus_generic_detach(dev); 2584 ti_free_dmamaps(sc); 2585 ifmedia_removeall(&sc->ifmedia); 2586 2587#ifdef TI_PRIVATE_JUMBOS 2588 if (sc->ti_cdata.ti_jumbo_buf) 2589 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2590 sc->ti_jumbo_dmamap); 2591#endif 2592 if (sc->ti_jumbo_dmat) 2593 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2594 if (sc->ti_mbuftx_dmat) 2595 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2596 if (sc->ti_mbufrx_dmat) 2597 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2598 if (sc->ti_rdata) 2599 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2600 sc->ti_rdata_dmamap); 2601 if (sc->ti_rdata_dmat) 2602 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2603 if (sc->ti_parent_dmat) 2604 bus_dma_tag_destroy(sc->ti_parent_dmat); 2605 if (sc->ti_intrhand) 2606 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2607 if (sc->ti_irq) 2608 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2609 if (sc->ti_res) { 2610 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2611 sc->ti_res); 2612 } 2613 if (ifp) 2614 if_free(ifp); 2615 2616 mtx_destroy(&sc->ti_mtx); 2617 2618 return (0); 2619} 2620 2621#ifdef TI_JUMBO_HDRSPLIT 2622/* 2623 * If hdr_len is 0, that means that header splitting wasn't done on 2624 * this packet for some reason. The two most likely reasons are that 2625 * the protocol isn't a supported protocol for splitting, or this 2626 * packet had a fragment offset that wasn't 0. 2627 * 2628 * The header length, if it is non-zero, will always be the length of 2629 * the headers on the packet, but that length could be longer than the 2630 * first mbuf. So we take the minimum of the two as the actual 2631 * length. 2632 */ 2633static __inline void 2634ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2635{ 2636 int i = 0; 2637 int lengths[4] = {0, 0, 0, 0}; 2638 struct mbuf *m, *mp; 2639 2640 if (hdr_len != 0) 2641 top->m_len = min(hdr_len, top->m_len); 2642 pkt_len -= top->m_len; 2643 lengths[i++] = top->m_len; 2644 2645 mp = top; 2646 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2647 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2648 pkt_len -= m->m_len; 2649 lengths[i++] = m->m_len; 2650 mp = m; 2651 } 2652 2653#if 0 2654 if (hdr_len != 0) 2655 printf("got split packet: "); 2656 else 2657 printf("got non-split packet: "); 2658 2659 printf("%d,%d,%d,%d = %d\n", lengths[0], 2660 lengths[1], lengths[2], lengths[3], 2661 lengths[0] + lengths[1] + lengths[2] + 2662 lengths[3]); 2663#endif 2664 2665 if (pkt_len) 2666 panic("header splitting didn't"); 2667 2668 if (m) { 2669 m_freem(m); 2670 mp->m_next = NULL; 2671 2672 } 2673 if (mp->m_next != NULL) 2674 panic("ti_hdr_split: last mbuf in chain should be null"); 2675} 2676#endif /* TI_JUMBO_HDRSPLIT */ 2677 2678/* 2679 * Frame reception handling. This is called if there's a frame 2680 * on the receive return list. 2681 * 2682 * Note: we have to be able to handle three possibilities here: 2683 * 1) the frame is from the mini receive ring (can only happen) 2684 * on Tigon 2 boards) 2685 * 2) the frame is from the jumbo recieve ring 2686 * 3) the frame is from the standard receive ring 2687 */ 2688 2689static void 2690ti_rxeof(sc) 2691 struct ti_softc *sc; 2692{ 2693 bus_dmamap_t map; 2694 struct ifnet *ifp; 2695 struct ti_cmd_desc cmd; 2696 2697 TI_LOCK_ASSERT(sc); 2698 2699 ifp = sc->ti_ifp; 2700 2701 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2702 struct ti_rx_desc *cur_rx; 2703 u_int32_t rxidx; 2704 struct mbuf *m = NULL; 2705 u_int16_t vlan_tag = 0; 2706 int have_tag = 0; 2707 2708 cur_rx = 2709 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2710 rxidx = cur_rx->ti_idx; 2711 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2712 2713 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2714 have_tag = 1; 2715 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2716 } 2717 2718 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2719 2720 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2721 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2722 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2723 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2724 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2725 BUS_DMASYNC_POSTREAD); 2726 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2727 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2728 ifp->if_ierrors++; 2729 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2730 continue; 2731 } 2732 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2733 ifp->if_ierrors++; 2734 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2735 continue; 2736 } 2737#ifdef TI_PRIVATE_JUMBOS 2738 m->m_len = cur_rx->ti_len; 2739#else /* TI_PRIVATE_JUMBOS */ 2740#ifdef TI_JUMBO_HDRSPLIT 2741 if (sc->ti_hdrsplit) 2742 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2743 cur_rx->ti_len, rxidx); 2744 else 2745#endif /* TI_JUMBO_HDRSPLIT */ 2746 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2747#endif /* TI_PRIVATE_JUMBOS */ 2748 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2749 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2750 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2751 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2752 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2753 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2754 BUS_DMASYNC_POSTREAD); 2755 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2756 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2757 ifp->if_ierrors++; 2758 ti_newbuf_mini(sc, sc->ti_mini, m); 2759 continue; 2760 } 2761 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2762 ifp->if_ierrors++; 2763 ti_newbuf_mini(sc, sc->ti_mini, m); 2764 continue; 2765 } 2766 m->m_len = cur_rx->ti_len; 2767 } else { 2768 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2769 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2770 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2771 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2772 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2773 BUS_DMASYNC_POSTREAD); 2774 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2775 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2776 ifp->if_ierrors++; 2777 ti_newbuf_std(sc, sc->ti_std, m); 2778 continue; 2779 } 2780 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2781 ifp->if_ierrors++; 2782 ti_newbuf_std(sc, sc->ti_std, m); 2783 continue; 2784 } 2785 m->m_len = cur_rx->ti_len; 2786 } 2787 2788 m->m_pkthdr.len = cur_rx->ti_len; 2789 ifp->if_ipackets++; 2790 m->m_pkthdr.rcvif = ifp; 2791 2792 if (ifp->if_hwassist) { 2793 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2794 CSUM_DATA_VALID; 2795 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2796 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2797 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2798 } 2799 2800 /* 2801 * If we received a packet with a vlan tag, 2802 * tag it before passing the packet upward. 2803 */ 2804 if (have_tag) { 2805 VLAN_INPUT_TAG(ifp, m, vlan_tag); 2806 if (m == NULL) 2807 continue; 2808 } 2809 TI_UNLOCK(sc); 2810 (*ifp->if_input)(ifp, m); 2811 TI_LOCK(sc); 2812 } 2813 2814 /* Only necessary on the Tigon 1. */ 2815 if (sc->ti_hwrev == TI_HWREV_TIGON) 2816 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2817 sc->ti_rx_saved_considx); 2818 2819 TI_UPDATE_STDPROD(sc, sc->ti_std); 2820 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2821 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2822} 2823 2824static void 2825ti_txeof(sc) 2826 struct ti_softc *sc; 2827{ 2828 struct ti_tx_desc *cur_tx = NULL; 2829 struct ifnet *ifp; 2830 bus_dmamap_t map; 2831 2832 ifp = sc->ti_ifp; 2833 2834 /* 2835 * Go through our tx ring and free mbufs for those 2836 * frames that have been sent. 2837 */ 2838 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2839 u_int32_t idx = 0; 2840 struct ti_tx_desc txdesc; 2841 2842 idx = sc->ti_tx_saved_considx; 2843 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2844 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2845 sizeof(txdesc), &txdesc); 2846 cur_tx = &txdesc; 2847 } else 2848 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2849 if (cur_tx->ti_flags & TI_BDFLAG_END) 2850 ifp->if_opackets++; 2851 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2852 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2853 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2854 map = sc->ti_cdata.ti_tx_maps[idx]; 2855 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, 2856 BUS_DMASYNC_POSTWRITE); 2857 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 2858 } 2859 sc->ti_txcnt--; 2860 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2861 ifp->if_timer = 0; 2862 } 2863 2864 if (cur_tx != NULL) 2865 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2866} 2867 2868static void 2869ti_intr(xsc) 2870 void *xsc; 2871{ 2872 struct ti_softc *sc; 2873 struct ifnet *ifp; 2874 2875 sc = xsc; 2876 TI_LOCK(sc); 2877 ifp = sc->ti_ifp; 2878 2879/*#ifdef notdef*/ 2880 /* Avoid this for now -- checking this register is expensive. */ 2881 /* Make sure this is really our interrupt. */ 2882 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2883 TI_UNLOCK(sc); 2884 return; 2885 } 2886/*#endif*/ 2887 2888 /* Ack interrupt and stop others from occuring. */ 2889 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2890 2891 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2892 /* Check RX return ring producer/consumer */ 2893 ti_rxeof(sc); 2894 2895 /* Check TX ring producer/consumer */ 2896 ti_txeof(sc); 2897 } 2898 2899 ti_handle_events(sc); 2900 2901 /* Re-enable interrupts. */ 2902 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2903 2904 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2905 ifp->if_snd.ifq_head != NULL) 2906 ti_start_locked(ifp); 2907 2908 TI_UNLOCK(sc); 2909} 2910 2911static void 2912ti_stats_update(sc) 2913 struct ti_softc *sc; 2914{ 2915 struct ifnet *ifp; 2916 2917 ifp = sc->ti_ifp; 2918 2919 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2920 BUS_DMASYNC_POSTREAD); 2921 2922 ifp->if_collisions += 2923 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2924 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2925 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2926 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2927 ifp->if_collisions; 2928 2929 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2930 BUS_DMASYNC_PREREAD); 2931} 2932 2933struct ti_dmamap_arg { 2934 struct ti_softc *sc; 2935 struct m_tag *mtag; 2936 struct mbuf *m_head; 2937 u_int16_t csum_flags; 2938 int idx; 2939}; 2940 2941static void 2942ti_encap_cb(arg, segs, nseg, mapsize, error) 2943 void *arg; 2944 bus_dma_segment_t *segs; 2945 int nseg; 2946 bus_size_t mapsize; 2947 int error; 2948{ 2949 struct ti_softc *sc; 2950 struct ti_dmamap_arg *ctx; 2951 struct ti_tx_desc *f = NULL; 2952 struct ti_tx_desc txdesc; 2953 struct m_tag *mtag; 2954 u_int32_t frag, cur, cnt = 0; 2955 u_int16_t csum_flags; 2956 2957 if (error) 2958 return; 2959 2960 ctx = (struct ti_dmamap_arg *)arg; 2961 sc = ctx->sc; 2962 cur = frag = ctx->idx; 2963 mtag = ctx->mtag; 2964 csum_flags = ctx->csum_flags; 2965 2966 /* 2967 * Start packing the mbufs in this chain into 2968 * the fragment pointers. Stop when we run out 2969 * of fragments or hit the end of the mbuf chain. 2970 */ 2971 while (nseg-- > 0) { 2972 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2973 bzero(&txdesc, sizeof(txdesc)); 2974 f = &txdesc; 2975 } else 2976 f = &sc->ti_rdata->ti_tx_ring[frag]; 2977 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2978 break; 2979 ti_hostaddr64(&f->ti_addr, segs[cnt].ds_addr); 2980 f->ti_len = segs[cnt].ds_len; 2981 f->ti_flags = csum_flags; 2982 2983 if (mtag != NULL) { 2984 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2985 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2986 } else { 2987 f->ti_vlan_tag = 0; 2988 } 2989 2990 if (sc->ti_hwrev == TI_HWREV_TIGON) 2991 ti_mem_write(sc, TI_TX_RING_BASE + frag * 2992 sizeof(txdesc), sizeof(txdesc), &txdesc); 2993 cur = frag; 2994 TI_INC(frag, TI_TX_RING_CNT); 2995 cnt++; 2996 } 2997 2998 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2999 txdesc.ti_flags |= TI_BDFLAG_END; 3000 ti_mem_write(sc, TI_TX_RING_BASE + cur * sizeof(txdesc), 3001 sizeof(txdesc), &txdesc); 3002 } else 3003 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 3004 sc->ti_cdata.ti_tx_chain[cur] = ctx->m_head; 3005 sc->ti_txcnt += cnt; 3006 3007 ctx->idx = frag; 3008 3009} 3010 3011/* 3012 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3013 * pointers to descriptors. 3014 */ 3015static int 3016ti_encap(sc, m_head, txidx) 3017 struct ti_softc *sc; 3018 struct mbuf *m_head; 3019 u_int32_t *txidx; 3020{ 3021 bus_dmamap_t map; 3022 struct ti_dmamap_arg ctx; 3023 u_int32_t frag, cnt; 3024 u_int16_t csum_flags = 0; 3025 int error; 3026 3027 frag = *txidx; 3028 3029 if (m_head->m_pkthdr.csum_flags) { 3030 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3031 csum_flags |= TI_BDFLAG_IP_CKSUM; 3032 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3033 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3034 if (m_head->m_flags & M_LASTFRAG) 3035 csum_flags |= TI_BDFLAG_IP_FRAG_END; 3036 else if (m_head->m_flags & M_FRAG) 3037 csum_flags |= TI_BDFLAG_IP_FRAG; 3038 } 3039 3040 ctx.sc = sc; 3041 ctx.idx = frag; 3042 ctx.csum_flags = csum_flags; 3043 ctx.mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m_head); 3044 ctx.m_head = m_head; 3045 3046 map = sc->ti_cdata.ti_tx_maps[frag]; 3047 error = bus_dmamap_load_mbuf(sc->ti_mbuftx_dmat, map, m_head, 3048 ti_encap_cb, &ctx, 0); 3049 if (error) 3050 return (ENOBUFS); 3051 3052 cnt = ctx.idx - frag; 3053 frag = ctx.idx; 3054 3055 /* 3056 * Sanity check: avoid coming within 16 descriptors 3057 * of the end of the ring. 3058 */ 3059 if (((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) || 3060 (frag == sc->ti_tx_saved_considx)) { 3061 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 3062 return (ENOBUFS); 3063 } 3064 3065 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, BUS_DMASYNC_PREWRITE); 3066 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 3067 BUS_DMASYNC_PREWRITE); 3068 *txidx = frag; 3069 return (0); 3070} 3071 3072static void 3073ti_start(ifp) 3074 struct ifnet *ifp; 3075{ 3076 struct ti_softc *sc; 3077 3078 sc = ifp->if_softc; 3079 TI_LOCK(sc); 3080 ti_start_locked(ifp); 3081 TI_UNLOCK(sc); 3082} 3083 3084/* 3085 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3086 * to the mbuf data regions directly in the transmit descriptors. 3087 */ 3088static void 3089ti_start_locked(ifp) 3090 struct ifnet *ifp; 3091{ 3092 struct ti_softc *sc; 3093 struct mbuf *m_head = NULL; 3094 u_int32_t prodidx = 0; 3095 3096 sc = ifp->if_softc; 3097 3098 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 3099 3100 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 3101 IF_DEQUEUE(&ifp->if_snd, m_head); 3102 if (m_head == NULL) 3103 break; 3104 3105 /* 3106 * XXX 3107 * safety overkill. If this is a fragmented packet chain 3108 * with delayed TCP/UDP checksums, then only encapsulate 3109 * it if we have enough descriptors to handle the entire 3110 * chain at once. 3111 * (paranoia -- may not actually be needed) 3112 */ 3113 if (m_head->m_flags & M_FIRSTFRAG && 3114 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3115 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3116 m_head->m_pkthdr.csum_data + 16) { 3117 IF_PREPEND(&ifp->if_snd, m_head); 3118 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3119 break; 3120 } 3121 } 3122 3123 /* 3124 * Pack the data into the transmit ring. If we 3125 * don't have room, set the OACTIVE flag and wait 3126 * for the NIC to drain the ring. 3127 */ 3128 if (ti_encap(sc, m_head, &prodidx)) { 3129 IF_PREPEND(&ifp->if_snd, m_head); 3130 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3131 break; 3132 } 3133 3134 /* 3135 * If there's a BPF listener, bounce a copy of this frame 3136 * to him. 3137 */ 3138 BPF_MTAP(ifp, m_head); 3139 } 3140 3141 /* Transmit */ 3142 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 3143 3144 /* 3145 * Set a timeout in case the chip goes out to lunch. 3146 */ 3147 ifp->if_timer = 5; 3148} 3149 3150static void 3151ti_init(xsc) 3152 void *xsc; 3153{ 3154 struct ti_softc *sc; 3155 3156 sc = xsc; 3157 TI_LOCK(sc); 3158 ti_init_locked(sc); 3159 TI_UNLOCK(sc); 3160} 3161 3162static void 3163ti_init_locked(xsc) 3164 void *xsc; 3165{ 3166 struct ti_softc *sc = xsc; 3167 3168 /* Cancel pending I/O and flush buffers. */ 3169 ti_stop(sc); 3170 3171 /* Init the gen info block, ring control blocks and firmware. */ 3172 if (ti_gibinit(sc)) { 3173 if_printf(sc->ti_ifp, "initialization failure\n"); 3174 return; 3175 } 3176} 3177 3178static void ti_init2(sc) 3179 struct ti_softc *sc; 3180{ 3181 struct ti_cmd_desc cmd; 3182 struct ifnet *ifp; 3183 u_int8_t *ea; 3184 struct ifmedia *ifm; 3185 int tmp; 3186 3187 TI_LOCK_ASSERT(sc); 3188 3189 ifp = sc->ti_ifp; 3190 3191 /* Specify MTU and interface index. */ 3192 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 3193 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3194 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3195 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3196 3197 /* Load our MAC address. */ 3198 ea = IF_LLADDR(sc->ti_ifp); 3199 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3200 CSR_WRITE_4(sc, TI_GCR_PAR1, 3201 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3202 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3203 3204 /* Enable or disable promiscuous mode as needed. */ 3205 if (ifp->if_flags & IFF_PROMISC) { 3206 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3207 } else { 3208 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3209 } 3210 3211 /* Program multicast filter. */ 3212 ti_setmulti(sc); 3213 3214 /* 3215 * If this is a Tigon 1, we should tell the 3216 * firmware to use software packet filtering. 3217 */ 3218 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3219 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3220 } 3221 3222 /* Init RX ring. */ 3223 ti_init_rx_ring_std(sc); 3224 3225 /* Init jumbo RX ring. */ 3226 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3227 ti_init_rx_ring_jumbo(sc); 3228 3229 /* 3230 * If this is a Tigon 2, we can also configure the 3231 * mini ring. 3232 */ 3233 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 3234 ti_init_rx_ring_mini(sc); 3235 3236 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3237 sc->ti_rx_saved_considx = 0; 3238 3239 /* Init TX ring. */ 3240 ti_init_tx_ring(sc); 3241 3242 /* Tell firmware we're alive. */ 3243 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3244 3245 /* Enable host interrupts. */ 3246 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3247 3248 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3249 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3250 3251 /* 3252 * Make sure to set media properly. We have to do this 3253 * here since we have to issue commands in order to set 3254 * the link negotiation and we can't issue commands until 3255 * the firmware is running. 3256 */ 3257 ifm = &sc->ifmedia; 3258 tmp = ifm->ifm_media; 3259 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3260 ti_ifmedia_upd(ifp); 3261 ifm->ifm_media = tmp; 3262} 3263 3264/* 3265 * Set media options. 3266 */ 3267static int 3268ti_ifmedia_upd(ifp) 3269 struct ifnet *ifp; 3270{ 3271 struct ti_softc *sc; 3272 struct ifmedia *ifm; 3273 struct ti_cmd_desc cmd; 3274 u_int32_t flowctl; 3275 3276 sc = ifp->if_softc; 3277 ifm = &sc->ifmedia; 3278 3279 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3280 return (EINVAL); 3281 3282 flowctl = 0; 3283 3284 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3285 case IFM_AUTO: 3286 /* 3287 * Transmit flow control doesn't work on the Tigon 1. 3288 */ 3289 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3290 3291 /* 3292 * Transmit flow control can also cause problems on the 3293 * Tigon 2, apparantly with both the copper and fiber 3294 * boards. The symptom is that the interface will just 3295 * hang. This was reproduced with Alteon 180 switches. 3296 */ 3297#if 0 3298 if (sc->ti_hwrev != TI_HWREV_TIGON) 3299 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3300#endif 3301 3302 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3303 TI_GLNK_FULL_DUPLEX| flowctl | 3304 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3305 3306 flowctl = TI_LNK_RX_FLOWCTL_Y; 3307#if 0 3308 if (sc->ti_hwrev != TI_HWREV_TIGON) 3309 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3310#endif 3311 3312 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3313 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3314 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3315 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3316 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3317 break; 3318 case IFM_1000_SX: 3319 case IFM_1000_T: 3320 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3321#if 0 3322 if (sc->ti_hwrev != TI_HWREV_TIGON) 3323 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3324#endif 3325 3326 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3327 flowctl |TI_GLNK_ENB); 3328 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3329 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3330 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3331 } 3332 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3333 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3334 break; 3335 case IFM_100_FX: 3336 case IFM_10_FL: 3337 case IFM_100_TX: 3338 case IFM_10_T: 3339 flowctl = TI_LNK_RX_FLOWCTL_Y; 3340#if 0 3341 if (sc->ti_hwrev != TI_HWREV_TIGON) 3342 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3343#endif 3344 3345 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3346 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3347 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3348 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3349 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3350 } else { 3351 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3352 } 3353 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3354 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3355 } else { 3356 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3357 } 3358 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3359 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3360 break; 3361 } 3362 3363 return (0); 3364} 3365 3366/* 3367 * Report current media status. 3368 */ 3369static void 3370ti_ifmedia_sts(ifp, ifmr) 3371 struct ifnet *ifp; 3372 struct ifmediareq *ifmr; 3373{ 3374 struct ti_softc *sc; 3375 u_int32_t media = 0; 3376 3377 sc = ifp->if_softc; 3378 3379 ifmr->ifm_status = IFM_AVALID; 3380 ifmr->ifm_active = IFM_ETHER; 3381 3382 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3383 return; 3384 3385 ifmr->ifm_status |= IFM_ACTIVE; 3386 3387 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3388 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3389 if (sc->ti_copper) 3390 ifmr->ifm_active |= IFM_1000_T; 3391 else 3392 ifmr->ifm_active |= IFM_1000_SX; 3393 if (media & TI_GLNK_FULL_DUPLEX) 3394 ifmr->ifm_active |= IFM_FDX; 3395 else 3396 ifmr->ifm_active |= IFM_HDX; 3397 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3398 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3399 if (sc->ti_copper) { 3400 if (media & TI_LNK_100MB) 3401 ifmr->ifm_active |= IFM_100_TX; 3402 if (media & TI_LNK_10MB) 3403 ifmr->ifm_active |= IFM_10_T; 3404 } else { 3405 if (media & TI_LNK_100MB) 3406 ifmr->ifm_active |= IFM_100_FX; 3407 if (media & TI_LNK_10MB) 3408 ifmr->ifm_active |= IFM_10_FL; 3409 } 3410 if (media & TI_LNK_FULL_DUPLEX) 3411 ifmr->ifm_active |= IFM_FDX; 3412 if (media & TI_LNK_HALF_DUPLEX) 3413 ifmr->ifm_active |= IFM_HDX; 3414 } 3415} 3416 3417static int 3418ti_ioctl(ifp, command, data) 3419 struct ifnet *ifp; 3420 u_long command; 3421 caddr_t data; 3422{ 3423 struct ti_softc *sc = ifp->if_softc; 3424 struct ifreq *ifr = (struct ifreq *) data; 3425 int mask, error = 0; 3426 struct ti_cmd_desc cmd; 3427 3428 switch (command) { 3429 case SIOCSIFMTU: 3430 TI_LOCK(sc); 3431 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3432 error = EINVAL; 3433 else { 3434 ifp->if_mtu = ifr->ifr_mtu; 3435 ti_init_locked(sc); 3436 } 3437 TI_UNLOCK(sc); 3438 break; 3439 case SIOCSIFFLAGS: 3440 TI_LOCK(sc); 3441 if (ifp->if_flags & IFF_UP) { 3442 /* 3443 * If only the state of the PROMISC flag changed, 3444 * then just use the 'set promisc mode' command 3445 * instead of reinitializing the entire NIC. Doing 3446 * a full re-init means reloading the firmware and 3447 * waiting for it to start up, which may take a 3448 * second or two. 3449 */ 3450 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3451 ifp->if_flags & IFF_PROMISC && 3452 !(sc->ti_if_flags & IFF_PROMISC)) { 3453 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3454 TI_CMD_CODE_PROMISC_ENB, 0); 3455 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3456 !(ifp->if_flags & IFF_PROMISC) && 3457 sc->ti_if_flags & IFF_PROMISC) { 3458 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3459 TI_CMD_CODE_PROMISC_DIS, 0); 3460 } else 3461 ti_init_locked(sc); 3462 } else { 3463 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3464 ti_stop(sc); 3465 } 3466 } 3467 sc->ti_if_flags = ifp->if_flags; 3468 TI_UNLOCK(sc); 3469 break; 3470 case SIOCADDMULTI: 3471 case SIOCDELMULTI: 3472 TI_LOCK(sc); 3473 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3474 ti_setmulti(sc); 3475 TI_UNLOCK(sc); 3476 break; 3477 case SIOCSIFMEDIA: 3478 case SIOCGIFMEDIA: 3479 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3480 break; 3481 case SIOCSIFCAP: 3482 TI_LOCK(sc); 3483 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3484 if (mask & IFCAP_HWCSUM) { 3485 if (IFCAP_HWCSUM & ifp->if_capenable) 3486 ifp->if_capenable &= ~IFCAP_HWCSUM; 3487 else 3488 ifp->if_capenable |= IFCAP_HWCSUM; 3489 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3490 ti_init_locked(sc); 3491 } 3492 TI_UNLOCK(sc); 3493 break; 3494 default: 3495 error = ether_ioctl(ifp, command, data); 3496 break; 3497 } 3498 3499 return (error); 3500} 3501 3502static int 3503ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3504{ 3505 struct ti_softc *sc; 3506 3507 sc = dev->si_drv1; 3508 if (sc == NULL) 3509 return (ENODEV); 3510 3511 TI_LOCK(sc); 3512 sc->ti_flags |= TI_FLAG_DEBUGING; 3513 TI_UNLOCK(sc); 3514 3515 return (0); 3516} 3517 3518static int 3519ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3520{ 3521 struct ti_softc *sc; 3522 3523 sc = dev->si_drv1; 3524 if (sc == NULL) 3525 return (ENODEV); 3526 3527 TI_LOCK(sc); 3528 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3529 TI_UNLOCK(sc); 3530 3531 return (0); 3532} 3533 3534/* 3535 * This ioctl routine goes along with the Tigon character device. 3536 */ 3537static int 3538ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3539 struct thread *td) 3540{ 3541 int error; 3542 struct ti_softc *sc; 3543 3544 sc = dev->si_drv1; 3545 if (sc == NULL) 3546 return (ENODEV); 3547 3548 error = 0; 3549 3550 switch (cmd) { 3551 case TIIOCGETSTATS: 3552 { 3553 struct ti_stats *outstats; 3554 3555 outstats = (struct ti_stats *)addr; 3556 3557 TI_LOCK(sc); 3558 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3559 sizeof(struct ti_stats)); 3560 TI_UNLOCK(sc); 3561 break; 3562 } 3563 case TIIOCGETPARAMS: 3564 { 3565 struct ti_params *params; 3566 3567 params = (struct ti_params *)addr; 3568 3569 TI_LOCK(sc); 3570 params->ti_stat_ticks = sc->ti_stat_ticks; 3571 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3572 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3573 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3574 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3575 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3576 params->param_mask = TI_PARAM_ALL; 3577 TI_UNLOCK(sc); 3578 3579 error = 0; 3580 3581 break; 3582 } 3583 case TIIOCSETPARAMS: 3584 { 3585 struct ti_params *params; 3586 3587 params = (struct ti_params *)addr; 3588 3589 TI_LOCK(sc); 3590 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3591 sc->ti_stat_ticks = params->ti_stat_ticks; 3592 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3593 } 3594 3595 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3596 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3597 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3598 sc->ti_rx_coal_ticks); 3599 } 3600 3601 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3602 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3603 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3604 sc->ti_tx_coal_ticks); 3605 } 3606 3607 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3608 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3609 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3610 sc->ti_rx_max_coal_bds); 3611 } 3612 3613 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3614 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3615 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3616 sc->ti_tx_max_coal_bds); 3617 } 3618 3619 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3620 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3621 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3622 sc->ti_tx_buf_ratio); 3623 } 3624 TI_UNLOCK(sc); 3625 3626 error = 0; 3627 3628 break; 3629 } 3630 case TIIOCSETTRACE: { 3631 ti_trace_type trace_type; 3632 3633 trace_type = *(ti_trace_type *)addr; 3634 3635 /* 3636 * Set tracing to whatever the user asked for. Setting 3637 * this register to 0 should have the effect of disabling 3638 * tracing. 3639 */ 3640 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3641 3642 error = 0; 3643 3644 break; 3645 } 3646 case TIIOCGETTRACE: { 3647 struct ti_trace_buf *trace_buf; 3648 u_int32_t trace_start, cur_trace_ptr, trace_len; 3649 3650 trace_buf = (struct ti_trace_buf *)addr; 3651 3652 TI_LOCK(sc); 3653 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3654 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3655 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3656 3657#if 0 3658 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3659 "trace_len = %d\n", trace_start, 3660 cur_trace_ptr, trace_len); 3661 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3662 trace_buf->buf_len); 3663#endif 3664 3665 error = ti_copy_mem(sc, trace_start, min(trace_len, 3666 trace_buf->buf_len), 3667 (caddr_t)trace_buf->buf, 1, 1); 3668 3669 if (error == 0) { 3670 trace_buf->fill_len = min(trace_len, 3671 trace_buf->buf_len); 3672 if (cur_trace_ptr < trace_start) 3673 trace_buf->cur_trace_ptr = 3674 trace_start - cur_trace_ptr; 3675 else 3676 trace_buf->cur_trace_ptr = 3677 cur_trace_ptr - trace_start; 3678 } else 3679 trace_buf->fill_len = 0; 3680 TI_UNLOCK(sc); 3681 3682 break; 3683 } 3684 3685 /* 3686 * For debugging, five ioctls are needed: 3687 * ALT_ATTACH 3688 * ALT_READ_TG_REG 3689 * ALT_WRITE_TG_REG 3690 * ALT_READ_TG_MEM 3691 * ALT_WRITE_TG_MEM 3692 */ 3693 case ALT_ATTACH: 3694 /* 3695 * From what I can tell, Alteon's Solaris Tigon driver 3696 * only has one character device, so you have to attach 3697 * to the Tigon board you're interested in. This seems 3698 * like a not-so-good way to do things, since unless you 3699 * subsequently specify the unit number of the device 3700 * you're interested in in every ioctl, you'll only be 3701 * able to debug one board at a time. 3702 */ 3703 error = 0; 3704 break; 3705 case ALT_READ_TG_MEM: 3706 case ALT_WRITE_TG_MEM: 3707 { 3708 struct tg_mem *mem_param; 3709 u_int32_t sram_end, scratch_end; 3710 3711 mem_param = (struct tg_mem *)addr; 3712 3713 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3714 sram_end = TI_END_SRAM_I; 3715 scratch_end = TI_END_SCRATCH_I; 3716 } else { 3717 sram_end = TI_END_SRAM_II; 3718 scratch_end = TI_END_SCRATCH_II; 3719 } 3720 3721 /* 3722 * For now, we'll only handle accessing regular SRAM, 3723 * nothing else. 3724 */ 3725 TI_LOCK(sc); 3726 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3727 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3728 /* 3729 * In this instance, we always copy to/from user 3730 * space, so the user space argument is set to 1. 3731 */ 3732 error = ti_copy_mem(sc, mem_param->tgAddr, 3733 mem_param->len, 3734 mem_param->userAddr, 1, 3735 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3736 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3737 && (mem_param->tgAddr <= scratch_end)) { 3738 error = ti_copy_scratch(sc, mem_param->tgAddr, 3739 mem_param->len, 3740 mem_param->userAddr, 1, 3741 (cmd == ALT_READ_TG_MEM) ? 3742 1 : 0, TI_PROCESSOR_A); 3743 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3744 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3745 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3746 if_printf(sc->ti_ifp, 3747 "invalid memory range for Tigon I\n"); 3748 error = EINVAL; 3749 break; 3750 } 3751 error = ti_copy_scratch(sc, mem_param->tgAddr - 3752 TI_SCRATCH_DEBUG_OFF, 3753 mem_param->len, 3754 mem_param->userAddr, 1, 3755 (cmd == ALT_READ_TG_MEM) ? 3756 1 : 0, TI_PROCESSOR_B); 3757 } else { 3758 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3759 "out of supported range\n", 3760 mem_param->tgAddr, mem_param->len); 3761 error = EINVAL; 3762 } 3763 TI_UNLOCK(sc); 3764 3765 break; 3766 } 3767 case ALT_READ_TG_REG: 3768 case ALT_WRITE_TG_REG: 3769 { 3770 struct tg_reg *regs; 3771 u_int32_t tmpval; 3772 3773 regs = (struct tg_reg *)addr; 3774 3775 /* 3776 * Make sure the address in question isn't out of range. 3777 */ 3778 if (regs->addr > TI_REG_MAX) { 3779 error = EINVAL; 3780 break; 3781 } 3782 TI_LOCK(sc); 3783 if (cmd == ALT_READ_TG_REG) { 3784 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3785 regs->addr, &tmpval, 1); 3786 regs->data = ntohl(tmpval); 3787#if 0 3788 if ((regs->addr == TI_CPU_STATE) 3789 || (regs->addr == TI_CPU_CTL_B)) { 3790 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3791 regs->addr, tmpval); 3792 } 3793#endif 3794 } else { 3795 tmpval = htonl(regs->data); 3796 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3797 regs->addr, &tmpval, 1); 3798 } 3799 TI_UNLOCK(sc); 3800 3801 break; 3802 } 3803 default: 3804 error = ENOTTY; 3805 break; 3806 } 3807 return (error); 3808} 3809 3810static void 3811ti_watchdog(ifp) 3812 struct ifnet *ifp; 3813{ 3814 struct ti_softc *sc; 3815 3816 sc = ifp->if_softc; 3817 TI_LOCK(sc); 3818 3819 /* 3820 * When we're debugging, the chip is often stopped for long periods 3821 * of time, and that would normally cause the watchdog timer to fire. 3822 * Since that impedes debugging, we don't want to do that. 3823 */ 3824 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3825 TI_UNLOCK(sc); 3826 return; 3827 } 3828 3829 if_printf(ifp, "watchdog timeout -- resetting\n"); 3830 ti_stop(sc); 3831 ti_init_locked(sc); 3832 3833 ifp->if_oerrors++; 3834 TI_UNLOCK(sc); 3835} 3836 3837/* 3838 * Stop the adapter and free any mbufs allocated to the 3839 * RX and TX lists. 3840 */ 3841static void 3842ti_stop(sc) 3843 struct ti_softc *sc; 3844{ 3845 struct ifnet *ifp; 3846 struct ti_cmd_desc cmd; 3847 3848 TI_LOCK_ASSERT(sc); 3849 3850 ifp = sc->ti_ifp; 3851 3852 /* Disable host interrupts. */ 3853 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3854 /* 3855 * Tell firmware we're shutting down. 3856 */ 3857 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3858 3859 /* Halt and reinitialize. */ 3860 if (ti_chipinit(sc) != 0) 3861 return; 3862 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3863 if (ti_chipinit(sc) != 0) 3864 return; 3865 3866 /* Free the RX lists. */ 3867 ti_free_rx_ring_std(sc); 3868 3869 /* Free jumbo RX list. */ 3870 ti_free_rx_ring_jumbo(sc); 3871 3872 /* Free mini RX list. */ 3873 ti_free_rx_ring_mini(sc); 3874 3875 /* Free TX buffers. */ 3876 ti_free_tx_ring(sc); 3877 3878 sc->ti_ev_prodidx.ti_idx = 0; 3879 sc->ti_return_prodidx.ti_idx = 0; 3880 sc->ti_tx_considx.ti_idx = 0; 3881 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3882 3883 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3884} 3885 3886/* 3887 * Stop all chip I/O so that the kernel's probe routines don't 3888 * get confused by errant DMAs when rebooting. 3889 */ 3890static void 3891ti_shutdown(dev) 3892 device_t dev; 3893{ 3894 struct ti_softc *sc; 3895 3896 sc = device_get_softc(dev); 3897 TI_LOCK(sc); 3898 ti_chipinit(sc); 3899 TI_UNLOCK(sc); 3900} 3901