if_ti.c revision 153280
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 153280 2005-12-10 00:38:33Z scottl $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100#include <net/if_types.h> 101#include <net/if_vlan_var.h> 102 103#include <net/bpf.h> 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116/* #define TI_PRIVATE_JUMBOS */ 117 118#if !defined(TI_PRIVATE_JUMBOS) 119#include <sys/sockio.h> 120#include <sys/uio.h> 121#include <sys/lock.h> 122#include <sys/sf_buf.h> 123#include <vm/vm_extern.h> 124#include <vm/pmap.h> 125#include <vm/vm_map.h> 126#include <vm/vm_map.h> 127#include <vm/vm_param.h> 128#include <vm/vm_pageout.h> 129#include <sys/vmmeter.h> 130#include <vm/vm_page.h> 131#include <vm/vm_object.h> 132#include <vm/vm_kern.h> 133#include <sys/proc.h> 134#endif /* !TI_PRIVATE_JUMBOS */ 135 136#include <dev/pci/pcireg.h> 137#include <dev/pci/pcivar.h> 138 139#include <sys/tiio.h> 140#include <dev/ti/if_tireg.h> 141#include <dev/ti/ti_fw.h> 142#include <dev/ti/ti_fw2.h> 143 144#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145/* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153struct ti_softc *tis[8]; 154 155typedef enum { 156 TI_SWAP_HTON, 157 TI_SWAP_NTOH 158} ti_swap_type; 159 160 161/* 162 * Various supported device vendors/types and their names. 163 */ 164 165static struct ti_type ti_devs[] = { 166 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 167 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 168 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 169 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 170 { TC_VENDORID, TC_DEVICEID_3C985, 171 "3Com 3c985-SX Gigabit Ethernet" }, 172 { NG_VENDORID, NG_DEVICEID_GA620, 173 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 174 { NG_VENDORID, NG_DEVICEID_GA620T, 175 "Netgear GA620 1000baseT Gigabit Ethernet" }, 176 { SGI_VENDORID, SGI_DEVICEID_TIGON, 177 "Silicon Graphics Gigabit Ethernet" }, 178 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 179 "Farallon PN9000SX Gigabit Ethernet" }, 180 { 0, 0, NULL } 181}; 182 183 184static d_open_t ti_open; 185static d_close_t ti_close; 186static d_ioctl_t ti_ioctl2; 187 188static struct cdevsw ti_cdevsw = { 189 .d_version = D_VERSION, 190 .d_flags = D_NEEDGIANT, 191 .d_open = ti_open, 192 .d_close = ti_close, 193 .d_ioctl = ti_ioctl2, 194 .d_name = "ti", 195}; 196 197static int ti_probe(device_t); 198static int ti_attach(device_t); 199static int ti_detach(device_t); 200static void ti_txeof(struct ti_softc *); 201static void ti_rxeof(struct ti_softc *); 202 203static void ti_stats_update(struct ti_softc *); 204static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *); 205 206static void ti_intr(void *); 207static void ti_start(struct ifnet *); 208static int ti_ioctl(struct ifnet *, u_long, caddr_t); 209static void ti_init(void *); 210static void ti_init2(struct ti_softc *); 211static void ti_stop(struct ti_softc *); 212static void ti_watchdog(struct ifnet *); 213static void ti_shutdown(device_t); 214static int ti_ifmedia_upd(struct ifnet *); 215static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 218static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 219static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 220 221static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 222static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 223static void ti_setmulti(struct ti_softc *); 224 225static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t); 226static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 227static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 228 int, int, int); 229static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 230static void ti_loadfw(struct ti_softc *); 231static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 232static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 233static void ti_handle_events(struct ti_softc *); 234#ifdef TI_PRIVATE_JUMBOS 235static int ti_alloc_jumbo_mem(struct ti_softc *); 236static void *ti_jalloc(struct ti_softc *); 237static void ti_jfree(void *, void *); 238#endif /* TI_PRIVATE_JUMBOS */ 239static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 240static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 241static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 242static int ti_init_rx_ring_std(struct ti_softc *); 243static void ti_free_rx_ring_std(struct ti_softc *); 244static int ti_init_rx_ring_jumbo(struct ti_softc *); 245static void ti_free_rx_ring_jumbo(struct ti_softc *); 246static int ti_init_rx_ring_mini(struct ti_softc *); 247static void ti_free_rx_ring_mini(struct ti_softc *); 248static void ti_free_tx_ring(struct ti_softc *); 249static int ti_init_tx_ring(struct ti_softc *); 250 251static int ti_64bitslot_war(struct ti_softc *); 252static int ti_chipinit(struct ti_softc *); 253static int ti_gibinit(struct ti_softc *); 254 255#ifdef TI_JUMBO_HDRSPLIT 256static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 257 int pkt_len, int idx); 258#endif /* TI_JUMBO_HDRSPLIT */ 259 260static device_method_t ti_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, ti_probe), 263 DEVMETHOD(device_attach, ti_attach), 264 DEVMETHOD(device_detach, ti_detach), 265 DEVMETHOD(device_shutdown, ti_shutdown), 266 { 0, 0 } 267}; 268 269static driver_t ti_driver = { 270 "ti", 271 ti_methods, 272 sizeof(struct ti_softc) 273}; 274 275static devclass_t ti_devclass; 276 277DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 278MODULE_DEPEND(ti, pci, 1, 1, 1); 279MODULE_DEPEND(ti, ether, 1, 1, 1); 280 281/* 282 * Send an instruction or address to the EEPROM, check for ACK. 283 */ 284static u_int32_t ti_eeprom_putbyte(sc, byte) 285 struct ti_softc *sc; 286 int byte; 287{ 288 register int i, ack = 0; 289 290 /* 291 * Make sure we're in TX mode. 292 */ 293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 294 295 /* 296 * Feed in each bit and stobe the clock. 297 */ 298 for (i = 0x80; i; i >>= 1) { 299 if (byte & i) { 300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 301 } else { 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 303 } 304 DELAY(1); 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 DELAY(1); 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 } 309 310 /* 311 * Turn off TX mode. 312 */ 313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 314 315 /* 316 * Check for ack. 317 */ 318 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 319 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 321 322 return (ack); 323} 324 325/* 326 * Read a byte of data stored in the EEPROM at address 'addr.' 327 * We have to send two address bytes since the EEPROM can hold 328 * more than 256 bytes of data. 329 */ 330static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 331 struct ti_softc *sc; 332 int addr; 333 u_int8_t *dest; 334{ 335 register int i; 336 u_int8_t byte = 0; 337 338 EEPROM_START; 339 340 /* 341 * Send write control code to EEPROM. 342 */ 343 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 344 if_printf(sc->ti_ifp, 345 "failed to send write command, status: %x\n", 346 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 347 return (1); 348 } 349 350 /* 351 * Send first byte of address of byte we want to read. 352 */ 353 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 354 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 355 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 356 return (1); 357 } 358 /* 359 * Send second byte address of byte we want to read. 360 */ 361 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 362 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 363 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 364 return (1); 365 } 366 367 EEPROM_STOP; 368 EEPROM_START; 369 /* 370 * Send read control code to EEPROM. 371 */ 372 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 373 if_printf(sc->ti_ifp, 374 "failed to send read command, status: %x\n", 375 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 376 return (1); 377 } 378 379 /* 380 * Start reading bits from EEPROM. 381 */ 382 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 383 for (i = 0x80; i; i >>= 1) { 384 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 385 DELAY(1); 386 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 387 byte |= i; 388 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 389 DELAY(1); 390 } 391 392 EEPROM_STOP; 393 394 /* 395 * No ACK generated for read, so just return byte. 396 */ 397 398 *dest = byte; 399 400 return (0); 401} 402 403/* 404 * Read a sequence of bytes from the EEPROM. 405 */ 406static int 407ti_read_eeprom(sc, dest, off, cnt) 408 struct ti_softc *sc; 409 caddr_t dest; 410 int off; 411 int cnt; 412{ 413 int err = 0, i; 414 u_int8_t byte = 0; 415 416 for (i = 0; i < cnt; i++) { 417 err = ti_eeprom_getbyte(sc, off + i, &byte); 418 if (err) 419 break; 420 *(dest + i) = byte; 421 } 422 423 return (err ? 1 : 0); 424} 425 426/* 427 * NIC memory access function. Can be used to either clear a section 428 * of NIC local memory or (if buf is non-NULL) copy data into it. 429 */ 430static void 431ti_mem(sc, addr, len, buf) 432 struct ti_softc *sc; 433 u_int32_t addr, len; 434 caddr_t buf; 435{ 436 int segptr, segsize, cnt; 437 caddr_t ti_winbase, ptr; 438 439 segptr = addr; 440 cnt = len; 441 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 442 ptr = buf; 443 444 while (cnt) { 445 if (cnt < TI_WINLEN) 446 segsize = cnt; 447 else 448 segsize = TI_WINLEN - (segptr % TI_WINLEN); 449 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 450 if (buf == NULL) 451 bzero((char *)ti_winbase + (segptr & 452 (TI_WINLEN - 1)), segsize); 453 else { 454 bcopy((char *)ptr, (char *)ti_winbase + 455 (segptr & (TI_WINLEN - 1)), segsize); 456 ptr += segsize; 457 } 458 segptr += segsize; 459 cnt -= segsize; 460 } 461} 462 463static int 464ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 465 struct ti_softc *sc; 466 u_int32_t tigon_addr, len; 467 caddr_t buf; 468 int useraddr, readdata; 469{ 470 int segptr, segsize, cnt; 471 caddr_t ptr; 472 u_int32_t origwin; 473 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 474 int resid, segresid; 475 int first_pass; 476 477 /* 478 * At the moment, we don't handle non-aligned cases, we just bail. 479 * If this proves to be a problem, it will be fixed. 480 */ 481 if ((readdata == 0) 482 && (tigon_addr & 0x3)) { 483 if_printf(sc->ti_ifp, "ti_copy_mem: tigon address %#x isn't " 484 "word-aligned\n", tigon_addr); 485 if_printf(sc->ti_ifp, "ti_copy_mem: unaligned writes aren't " 486 "yet supported\n"); 487 return (EINVAL); 488 } 489 490 segptr = tigon_addr & ~0x3; 491 segresid = tigon_addr - segptr; 492 493 /* 494 * This is the non-aligned amount left over that we'll need to 495 * copy. 496 */ 497 resid = len & 0x3; 498 499 /* Add in the left over amount at the front of the buffer */ 500 resid += segresid; 501 502 cnt = len & ~0x3; 503 /* 504 * If resid + segresid is >= 4, add multiples of 4 to the count and 505 * decrease the residual by that much. 506 */ 507 cnt += resid & ~0x3; 508 resid -= resid & ~0x3; 509 510 ptr = buf; 511 512 first_pass = 1; 513 514 /* 515 * Make sure we aren't interrupted while we're changing the window 516 * pointer. 517 */ 518 TI_LOCK(sc); 519 520 /* 521 * Save the old window base value. 522 */ 523 origwin = CSR_READ_4(sc, TI_WINBASE); 524 525 while (cnt) { 526 bus_size_t ti_offset; 527 528 if (cnt < TI_WINLEN) 529 segsize = cnt; 530 else 531 segsize = TI_WINLEN - (segptr % TI_WINLEN); 532 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 533 534 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 535 536 if (readdata) { 537 538 bus_space_read_region_4(sc->ti_btag, 539 sc->ti_bhandle, ti_offset, 540 (u_int32_t *)tmparray, 541 segsize >> 2); 542 if (useraddr) { 543 /* 544 * Yeah, this is a little on the kludgy 545 * side, but at least this code is only 546 * used for debugging. 547 */ 548 ti_bcopy_swap(tmparray, tmparray2, segsize, 549 TI_SWAP_NTOH); 550 551 if (first_pass) { 552 copyout(&tmparray2[segresid], ptr, 553 segsize - segresid); 554 first_pass = 0; 555 } else 556 copyout(tmparray2, ptr, segsize); 557 } else { 558 if (first_pass) { 559 560 ti_bcopy_swap(tmparray, tmparray2, 561 segsize, TI_SWAP_NTOH); 562 bcopy(&tmparray2[segresid], ptr, 563 segsize - segresid); 564 first_pass = 0; 565 } else 566 ti_bcopy_swap(tmparray, ptr, segsize, 567 TI_SWAP_NTOH); 568 } 569 570 } else { 571 if (useraddr) { 572 copyin(ptr, tmparray2, segsize); 573 ti_bcopy_swap(tmparray2, tmparray, segsize, 574 TI_SWAP_HTON); 575 } else 576 ti_bcopy_swap(ptr, tmparray, segsize, 577 TI_SWAP_HTON); 578 579 bus_space_write_region_4(sc->ti_btag, 580 sc->ti_bhandle, ti_offset, 581 (u_int32_t *)tmparray, 582 segsize >> 2); 583 } 584 segptr += segsize; 585 ptr += segsize; 586 cnt -= segsize; 587 } 588 589 /* 590 * Handle leftover, non-word-aligned bytes. 591 */ 592 if (resid != 0) { 593 u_int32_t tmpval, tmpval2; 594 bus_size_t ti_offset; 595 596 /* 597 * Set the segment pointer. 598 */ 599 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 600 601 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 602 603 /* 604 * First, grab whatever is in our source/destination. 605 * We'll obviously need this for reads, but also for 606 * writes, since we'll be doing read/modify/write. 607 */ 608 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 609 ti_offset, &tmpval, 1); 610 611 /* 612 * Next, translate this from little-endian to big-endian 613 * (at least on i386 boxes). 614 */ 615 tmpval2 = ntohl(tmpval); 616 617 if (readdata) { 618 /* 619 * If we're reading, just copy the leftover number 620 * of bytes from the host byte order buffer to 621 * the user's buffer. 622 */ 623 if (useraddr) 624 copyout(&tmpval2, ptr, resid); 625 else 626 bcopy(&tmpval2, ptr, resid); 627 } else { 628 /* 629 * If we're writing, first copy the bytes to be 630 * written into the network byte order buffer, 631 * leaving the rest of the buffer with whatever was 632 * originally in there. Then, swap the bytes 633 * around into host order and write them out. 634 * 635 * XXX KDM the read side of this has been verified 636 * to work, but the write side of it has not been 637 * verified. So user beware. 638 */ 639 if (useraddr) 640 copyin(ptr, &tmpval2, resid); 641 else 642 bcopy(ptr, &tmpval2, resid); 643 644 tmpval = htonl(tmpval2); 645 646 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 647 ti_offset, &tmpval, 1); 648 } 649 } 650 651 CSR_WRITE_4(sc, TI_WINBASE, origwin); 652 653 TI_UNLOCK(sc); 654 655 return (0); 656} 657 658static int 659ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 660 struct ti_softc *sc; 661 u_int32_t tigon_addr, len; 662 caddr_t buf; 663 int useraddr, readdata; 664 int cpu; 665{ 666 u_int32_t segptr; 667 int cnt; 668 u_int32_t tmpval, tmpval2; 669 caddr_t ptr; 670 671 /* 672 * At the moment, we don't handle non-aligned cases, we just bail. 673 * If this proves to be a problem, it will be fixed. 674 */ 675 if (tigon_addr & 0x3) { 676 if_printf(sc->ti_ifp, "ti_copy_scratch: tigon address %#x " 677 "isn't word-aligned\n", tigon_addr); 678 return (EINVAL); 679 } 680 681 if (len & 0x3) { 682 if_printf(sc->ti_ifp, "ti_copy_scratch: transfer length %d " 683 "isn't word-aligned\n", len); 684 return (EINVAL); 685 } 686 687 segptr = tigon_addr; 688 cnt = len; 689 ptr = buf; 690 691 TI_LOCK(sc); 692 693 while (cnt) { 694 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 695 696 if (readdata) { 697 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 698 699 tmpval = ntohl(tmpval2); 700 701 /* 702 * Note: I've used this debugging interface 703 * extensively with Alteon's 12.3.15 firmware, 704 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 705 * 706 * When you compile the firmware without 707 * optimization, which is necessary sometimes in 708 * order to properly step through it, you sometimes 709 * read out a bogus value of 0xc0017c instead of 710 * whatever was supposed to be in that scratchpad 711 * location. That value is on the stack somewhere, 712 * but I've never been able to figure out what was 713 * causing the problem. 714 * 715 * The address seems to pop up in random places, 716 * often not in the same place on two subsequent 717 * reads. 718 * 719 * In any case, the underlying data doesn't seem 720 * to be affected, just the value read out. 721 * 722 * KDM, 3/7/2000 723 */ 724 725 if (tmpval2 == 0xc0017c) 726 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 727 "(tmpval2)\n", segptr); 728 729 if (tmpval == 0xc0017c) 730 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 731 "(tmpval)\n", segptr); 732 733 if (useraddr) 734 copyout(&tmpval, ptr, 4); 735 else 736 bcopy(&tmpval, ptr, 4); 737 } else { 738 if (useraddr) 739 copyin(ptr, &tmpval2, 4); 740 else 741 bcopy(ptr, &tmpval2, 4); 742 743 tmpval = htonl(tmpval2); 744 745 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 746 } 747 748 cnt -= 4; 749 segptr += 4; 750 ptr += 4; 751 } 752 753 TI_UNLOCK(sc); 754 755 return (0); 756} 757 758static int 759ti_bcopy_swap(src, dst, len, swap_type) 760 const void *src; 761 void *dst; 762 size_t len; 763 ti_swap_type swap_type; 764{ 765 const u_int8_t *tmpsrc; 766 u_int8_t *tmpdst; 767 size_t tmplen; 768 769 if (len & 0x3) { 770 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 771 len); 772 return (-1); 773 } 774 775 tmpsrc = src; 776 tmpdst = dst; 777 tmplen = len; 778 779 while (tmplen) { 780 if (swap_type == TI_SWAP_NTOH) 781 *(u_int32_t *)tmpdst = 782 ntohl(*(const u_int32_t *)tmpsrc); 783 else 784 *(u_int32_t *)tmpdst = 785 htonl(*(const u_int32_t *)tmpsrc); 786 787 tmpsrc += 4; 788 tmpdst += 4; 789 tmplen -= 4; 790 } 791 792 return (0); 793} 794 795/* 796 * Load firmware image into the NIC. Check that the firmware revision 797 * is acceptable and see if we want the firmware for the Tigon 1 or 798 * Tigon 2. 799 */ 800static void 801ti_loadfw(sc) 802 struct ti_softc *sc; 803{ 804 switch (sc->ti_hwrev) { 805 case TI_HWREV_TIGON: 806 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 807 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 808 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 809 if_printf(sc->ti_ifp, "firmware revision mismatch; " 810 "want %d.%d.%d, got %d.%d.%d\n", 811 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 812 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 813 tigonFwReleaseMinor, tigonFwReleaseFix); 814 return; 815 } 816 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 817 (caddr_t)tigonFwText); 818 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 819 (caddr_t)tigonFwData); 820 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 821 (caddr_t)tigonFwRodata); 822 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 823 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 824 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 825 break; 826 case TI_HWREV_TIGON_II: 827 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 828 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 829 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 830 if_printf(sc->ti_ifp, "firmware revision mismatch; " 831 "want %d.%d.%d, got %d.%d.%d\n", 832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 833 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 834 tigon2FwReleaseMinor, tigon2FwReleaseFix); 835 return; 836 } 837 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 838 (caddr_t)tigon2FwText); 839 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 840 (caddr_t)tigon2FwData); 841 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 842 (caddr_t)tigon2FwRodata); 843 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 844 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 845 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 846 break; 847 default: 848 if_printf(sc->ti_ifp, 849 "can't load firmware: unknown hardware rev\n"); 850 break; 851 } 852} 853 854/* 855 * Send the NIC a command via the command ring. 856 */ 857static void 858ti_cmd(sc, cmd) 859 struct ti_softc *sc; 860 struct ti_cmd_desc *cmd; 861{ 862 u_int32_t index; 863 864 if (sc->ti_rdata->ti_cmd_ring == NULL) 865 return; 866 867 index = sc->ti_cmd_saved_prodidx; 868 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 869 TI_INC(index, TI_CMD_RING_CNT); 870 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 871 sc->ti_cmd_saved_prodidx = index; 872} 873 874/* 875 * Send the NIC an extended command. The 'len' parameter specifies the 876 * number of command slots to include after the initial command. 877 */ 878static void 879ti_cmd_ext(sc, cmd, arg, len) 880 struct ti_softc *sc; 881 struct ti_cmd_desc *cmd; 882 caddr_t arg; 883 int len; 884{ 885 u_int32_t index; 886 register int i; 887 888 if (sc->ti_rdata->ti_cmd_ring == NULL) 889 return; 890 891 index = sc->ti_cmd_saved_prodidx; 892 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 893 TI_INC(index, TI_CMD_RING_CNT); 894 for (i = 0; i < len; i++) { 895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 896 *(u_int32_t *)(&arg[i * 4])); 897 TI_INC(index, TI_CMD_RING_CNT); 898 } 899 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 900 sc->ti_cmd_saved_prodidx = index; 901} 902 903/* 904 * Handle events that have triggered interrupts. 905 */ 906static void 907ti_handle_events(sc) 908 struct ti_softc *sc; 909{ 910 struct ti_event_desc *e; 911 912 if (sc->ti_rdata->ti_event_ring == NULL) 913 return; 914 915 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 916 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 917 switch (e->ti_event) { 918 case TI_EV_LINKSTAT_CHANGED: 919 sc->ti_linkstat = e->ti_code; 920 if (e->ti_code == TI_EV_CODE_LINK_UP) 921 if_printf(sc->ti_ifp, "10/100 link up\n"); 922 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 923 if_printf(sc->ti_ifp, "gigabit link up\n"); 924 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 925 if_printf(sc->ti_ifp, "link down\n"); 926 break; 927 case TI_EV_ERROR: 928 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 929 if_printf(sc->ti_ifp, "invalid command\n"); 930 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 931 if_printf(sc->ti_ifp, "unknown command\n"); 932 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 933 if_printf(sc->ti_ifp, "bad config data\n"); 934 break; 935 case TI_EV_FIRMWARE_UP: 936 ti_init2(sc); 937 break; 938 case TI_EV_STATS_UPDATED: 939 ti_stats_update(sc); 940 break; 941 case TI_EV_RESET_JUMBO_RING: 942 case TI_EV_MCAST_UPDATED: 943 /* Who cares. */ 944 break; 945 default: 946 if_printf(sc->ti_ifp, "unknown event: %d\n", 947 e->ti_event); 948 break; 949 } 950 /* Advance the consumer index. */ 951 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 952 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 953 } 954} 955 956#ifdef TI_PRIVATE_JUMBOS 957 958/* 959 * Memory management for the jumbo receive ring is a pain in the 960 * butt. We need to allocate at least 9018 bytes of space per frame, 961 * _and_ it has to be contiguous (unless you use the extended 962 * jumbo descriptor format). Using malloc() all the time won't 963 * work: malloc() allocates memory in powers of two, which means we 964 * would end up wasting a considerable amount of space by allocating 965 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 966 * to do our own memory management. 967 * 968 * The driver needs to allocate a contiguous chunk of memory at boot 969 * time. We then chop this up ourselves into 9K pieces and use them 970 * as external mbuf storage. 971 * 972 * One issue here is how much memory to allocate. The jumbo ring has 973 * 256 slots in it, but at 9K per slot than can consume over 2MB of 974 * RAM. This is a bit much, especially considering we also need 975 * RAM for the standard ring and mini ring (on the Tigon 2). To 976 * save space, we only actually allocate enough memory for 64 slots 977 * by default, which works out to between 500 and 600K. This can 978 * be tuned by changing a #define in if_tireg.h. 979 */ 980 981static int 982ti_alloc_jumbo_mem(sc) 983 struct ti_softc *sc; 984{ 985 caddr_t ptr; 986 register int i; 987 struct ti_jpool_entry *entry; 988 989 /* Grab a big chunk o' storage. */ 990 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 991 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 992 993 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 994 if_printf(sc->ti_ifp, "no memory for jumbo buffers!\n"); 995 return (ENOBUFS); 996 } 997 998 SLIST_INIT(&sc->ti_jfree_listhead); 999 SLIST_INIT(&sc->ti_jinuse_listhead); 1000 1001 /* 1002 * Now divide it up into 9K pieces and save the addresses 1003 * in an array. 1004 */ 1005 ptr = sc->ti_cdata.ti_jumbo_buf; 1006 for (i = 0; i < TI_JSLOTS; i++) { 1007 sc->ti_cdata.ti_jslots[i] = ptr; 1008 ptr += TI_JLEN; 1009 entry = malloc(sizeof(struct ti_jpool_entry), 1010 M_DEVBUF, M_NOWAIT); 1011 if (entry == NULL) { 1012 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1013 M_DEVBUF); 1014 sc->ti_cdata.ti_jumbo_buf = NULL; 1015 if_printf(sc->ti_ifp, "no memory for jumbo " 1016 "buffer queue!\n"); 1017 return (ENOBUFS); 1018 } 1019 entry->slot = i; 1020 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1021 } 1022 1023 return (0); 1024} 1025 1026/* 1027 * Allocate a jumbo buffer. 1028 */ 1029static void *ti_jalloc(sc) 1030 struct ti_softc *sc; 1031{ 1032 struct ti_jpool_entry *entry; 1033 1034 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1035 1036 if (entry == NULL) { 1037 if_printf(sc->ti_ifp, "no free jumbo buffers\n"); 1038 return (NULL); 1039 } 1040 1041 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1042 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1043 return (sc->ti_cdata.ti_jslots[entry->slot]); 1044} 1045 1046/* 1047 * Release a jumbo buffer. 1048 */ 1049static void 1050ti_jfree(buf, args) 1051 void *buf; 1052 void *args; 1053{ 1054 struct ti_softc *sc; 1055 int i; 1056 struct ti_jpool_entry *entry; 1057 1058 /* Extract the softc struct pointer. */ 1059 sc = (struct ti_softc *)args; 1060 1061 if (sc == NULL) 1062 panic("ti_jfree: didn't get softc pointer!"); 1063 1064 /* calculate the slot this buffer belongs to */ 1065 i = ((vm_offset_t)buf 1066 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1067 1068 if ((i < 0) || (i >= TI_JSLOTS)) 1069 panic("ti_jfree: asked to free buffer that we don't manage!"); 1070 1071 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1072 if (entry == NULL) 1073 panic("ti_jfree: buffer not in use!"); 1074 entry->slot = i; 1075 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1076 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1077} 1078 1079#endif /* TI_PRIVATE_JUMBOS */ 1080 1081/* 1082 * Intialize a standard receive ring descriptor. 1083 */ 1084static int 1085ti_newbuf_std(sc, i, m) 1086 struct ti_softc *sc; 1087 int i; 1088 struct mbuf *m; 1089{ 1090 struct mbuf *m_new = NULL; 1091 struct ti_rx_desc *r; 1092 1093 if (m == NULL) { 1094 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1095 if (m_new == NULL) 1096 return (ENOBUFS); 1097 1098 MCLGET(m_new, M_DONTWAIT); 1099 if (!(m_new->m_flags & M_EXT)) { 1100 m_freem(m_new); 1101 return (ENOBUFS); 1102 } 1103 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1104 } else { 1105 m_new = m; 1106 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1107 m_new->m_data = m_new->m_ext.ext_buf; 1108 } 1109 1110 m_adj(m_new, ETHER_ALIGN); 1111 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1112 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1113 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1114 r->ti_type = TI_BDTYPE_RECV_BD; 1115 r->ti_flags = 0; 1116 if (sc->ti_ifp->if_hwassist) 1117 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1118 r->ti_len = m_new->m_len; 1119 r->ti_idx = i; 1120 1121 return (0); 1122} 1123 1124/* 1125 * Intialize a mini receive ring descriptor. This only applies to 1126 * the Tigon 2. 1127 */ 1128static int 1129ti_newbuf_mini(sc, i, m) 1130 struct ti_softc *sc; 1131 int i; 1132 struct mbuf *m; 1133{ 1134 struct mbuf *m_new = NULL; 1135 struct ti_rx_desc *r; 1136 1137 if (m == NULL) { 1138 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1139 if (m_new == NULL) { 1140 return (ENOBUFS); 1141 } 1142 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1143 } else { 1144 m_new = m; 1145 m_new->m_data = m_new->m_pktdat; 1146 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1147 } 1148 1149 m_adj(m_new, ETHER_ALIGN); 1150 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1151 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1152 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1153 r->ti_type = TI_BDTYPE_RECV_BD; 1154 r->ti_flags = TI_BDFLAG_MINI_RING; 1155 if (sc->ti_ifp->if_hwassist) 1156 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1157 r->ti_len = m_new->m_len; 1158 r->ti_idx = i; 1159 1160 return (0); 1161} 1162 1163#ifdef TI_PRIVATE_JUMBOS 1164 1165/* 1166 * Initialize a jumbo receive ring descriptor. This allocates 1167 * a jumbo buffer from the pool managed internally by the driver. 1168 */ 1169static int 1170ti_newbuf_jumbo(sc, i, m) 1171 struct ti_softc *sc; 1172 int i; 1173 struct mbuf *m; 1174{ 1175 struct mbuf *m_new = NULL; 1176 struct ti_rx_desc *r; 1177 1178 if (m == NULL) { 1179 caddr_t *buf = NULL; 1180 1181 /* Allocate the mbuf. */ 1182 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1183 if (m_new == NULL) { 1184 return (ENOBUFS); 1185 } 1186 1187 /* Allocate the jumbo buffer */ 1188 buf = ti_jalloc(sc); 1189 if (buf == NULL) { 1190 m_freem(m_new); 1191 if_printf(sc->ti_ifp, "jumbo allocation failed " 1192 "-- packet dropped!\n"); 1193 return (ENOBUFS); 1194 } 1195 1196 /* Attach the buffer to the mbuf. */ 1197 m_new->m_data = (void *) buf; 1198 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1199 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1200 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1201 } else { 1202 m_new = m; 1203 m_new->m_data = m_new->m_ext.ext_buf; 1204 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1205 } 1206 1207 m_adj(m_new, ETHER_ALIGN); 1208 /* Set up the descriptor. */ 1209 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1210 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1211 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1212 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1213 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1214 if (sc->ti_ifp->if_hwassist) 1215 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1216 r->ti_len = m_new->m_len; 1217 r->ti_idx = i; 1218 1219 return (0); 1220} 1221 1222#else 1223#include <vm/vm_page.h> 1224 1225#if (PAGE_SIZE == 4096) 1226#define NPAYLOAD 2 1227#else 1228#define NPAYLOAD 1 1229#endif 1230 1231#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1232#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1233#define NFS_HDR_LEN (UDP_HDR_LEN) 1234static int HDR_LEN = TCP_HDR_LEN; 1235 1236 1237/* 1238 * Initialize a jumbo receive ring descriptor. This allocates 1239 * a jumbo buffer from the pool managed internally by the driver. 1240 */ 1241static int 1242ti_newbuf_jumbo(sc, idx, m_old) 1243 struct ti_softc *sc; 1244 int idx; 1245 struct mbuf *m_old; 1246{ 1247 struct mbuf *cur, *m_new = NULL; 1248 struct mbuf *m[3] = {NULL, NULL, NULL}; 1249 struct ti_rx_desc_ext *r; 1250 vm_page_t frame; 1251 static int color; 1252 /* 1 extra buf to make nobufs easy*/ 1253 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1254 int i; 1255 1256 if (m_old != NULL) { 1257 m_new = m_old; 1258 cur = m_old->m_next; 1259 for (i = 0; i <= NPAYLOAD; i++){ 1260 m[i] = cur; 1261 cur = cur->m_next; 1262 } 1263 } else { 1264 /* Allocate the mbufs. */ 1265 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1266 if (m_new == NULL) { 1267 if_printf(sc->ti_ifp, "mbuf allocation failed " 1268 "-- packet dropped!\n"); 1269 goto nobufs; 1270 } 1271 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1272 if (m[NPAYLOAD] == NULL) { 1273 if_printf(sc->ti_ifp, "cluster mbuf allocation failed " 1274 "-- packet dropped!\n"); 1275 goto nobufs; 1276 } 1277 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1278 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1279 if_printf(sc->ti_ifp, "mbuf allocation failed " 1280 "-- packet dropped!\n"); 1281 goto nobufs; 1282 } 1283 m[NPAYLOAD]->m_len = MCLBYTES; 1284 1285 for (i = 0; i < NPAYLOAD; i++){ 1286 MGET(m[i], M_DONTWAIT, MT_DATA); 1287 if (m[i] == NULL) { 1288 if_printf(sc->ti_ifp, "mbuf allocation failed " 1289 "-- packet dropped!\n"); 1290 goto nobufs; 1291 } 1292 frame = vm_page_alloc(NULL, color++, 1293 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1294 VM_ALLOC_WIRED); 1295 if (frame == NULL) { 1296 if_printf(sc->ti_ifp, "buffer allocation " 1297 "failed -- packet dropped!\n"); 1298 printf(" index %d page %d\n", idx, i); 1299 goto nobufs; 1300 } 1301 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1302 if (sf[i] == NULL) { 1303 vm_page_lock_queues(); 1304 vm_page_unwire(frame, 0); 1305 vm_page_free(frame); 1306 vm_page_unlock_queues(); 1307 if_printf(sc->ti_ifp, "buffer allocation " 1308 "failed -- packet dropped!\n"); 1309 printf(" index %d page %d\n", idx, i); 1310 goto nobufs; 1311 } 1312 } 1313 for (i = 0; i < NPAYLOAD; i++){ 1314 /* Attach the buffer to the mbuf. */ 1315 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1316 m[i]->m_len = PAGE_SIZE; 1317 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1318 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 1319 m[i]->m_next = m[i+1]; 1320 } 1321 /* link the buffers to the header */ 1322 m_new->m_next = m[0]; 1323 m_new->m_data += ETHER_ALIGN; 1324 if (sc->ti_hdrsplit) 1325 m_new->m_len = MHLEN - ETHER_ALIGN; 1326 else 1327 m_new->m_len = HDR_LEN; 1328 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1329 } 1330 1331 /* Set up the descriptor. */ 1332 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1333 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1334 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1335 r->ti_len0 = m_new->m_len; 1336 1337 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1338 r->ti_len1 = PAGE_SIZE; 1339 1340 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1341 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1342 1343 if (PAGE_SIZE == 4096) { 1344 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1345 r->ti_len3 = MCLBYTES; 1346 } else { 1347 r->ti_len3 = 0; 1348 } 1349 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1350 1351 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1352 1353 if (sc->ti_ifp->if_hwassist) 1354 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1355 1356 r->ti_idx = idx; 1357 1358 return (0); 1359 1360nobufs: 1361 1362 /* 1363 * Warning! : 1364 * This can only be called before the mbufs are strung together. 1365 * If the mbufs are strung together, m_freem() will free the chain, 1366 * so that the later mbufs will be freed multiple times. 1367 */ 1368 if (m_new) 1369 m_freem(m_new); 1370 1371 for (i = 0; i < 3; i++) { 1372 if (m[i]) 1373 m_freem(m[i]); 1374 if (sf[i]) 1375 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1376 } 1377 return (ENOBUFS); 1378} 1379#endif 1380 1381 1382 1383/* 1384 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1385 * that's 1MB or memory, which is a lot. For now, we fill only the first 1386 * 256 ring entries and hope that our CPU is fast enough to keep up with 1387 * the NIC. 1388 */ 1389static int 1390ti_init_rx_ring_std(sc) 1391 struct ti_softc *sc; 1392{ 1393 register int i; 1394 struct ti_cmd_desc cmd; 1395 1396 for (i = 0; i < TI_SSLOTS; i++) { 1397 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1398 return (ENOBUFS); 1399 }; 1400 1401 TI_UPDATE_STDPROD(sc, i - 1); 1402 sc->ti_std = i - 1; 1403 1404 return (0); 1405} 1406 1407static void 1408ti_free_rx_ring_std(sc) 1409 struct ti_softc *sc; 1410{ 1411 register int i; 1412 1413 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1414 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1415 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1416 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1417 } 1418 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1419 sizeof(struct ti_rx_desc)); 1420 } 1421} 1422 1423static int 1424ti_init_rx_ring_jumbo(sc) 1425 struct ti_softc *sc; 1426{ 1427 register int i; 1428 struct ti_cmd_desc cmd; 1429 1430 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1431 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1432 return (ENOBUFS); 1433 }; 1434 1435 TI_UPDATE_JUMBOPROD(sc, i - 1); 1436 sc->ti_jumbo = i - 1; 1437 1438 return (0); 1439} 1440 1441static void 1442ti_free_rx_ring_jumbo(sc) 1443 struct ti_softc *sc; 1444{ 1445 register int i; 1446 1447 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1448 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1449 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1450 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1451 } 1452 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1453 sizeof(struct ti_rx_desc)); 1454 } 1455} 1456 1457static int 1458ti_init_rx_ring_mini(sc) 1459 struct ti_softc *sc; 1460{ 1461 register int i; 1462 1463 for (i = 0; i < TI_MSLOTS; i++) { 1464 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1465 return (ENOBUFS); 1466 }; 1467 1468 TI_UPDATE_MINIPROD(sc, i - 1); 1469 sc->ti_mini = i - 1; 1470 1471 return (0); 1472} 1473 1474static void 1475ti_free_rx_ring_mini(sc) 1476 struct ti_softc *sc; 1477{ 1478 register int i; 1479 1480 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1481 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1482 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1483 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1484 } 1485 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1486 sizeof(struct ti_rx_desc)); 1487 } 1488} 1489 1490static void 1491ti_free_tx_ring(sc) 1492 struct ti_softc *sc; 1493{ 1494 register int i; 1495 1496 if (sc->ti_rdata->ti_tx_ring == NULL) 1497 return; 1498 1499 for (i = 0; i < TI_TX_RING_CNT; i++) { 1500 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1501 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1502 sc->ti_cdata.ti_tx_chain[i] = NULL; 1503 } 1504 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1505 sizeof(struct ti_tx_desc)); 1506 } 1507} 1508 1509static int 1510ti_init_tx_ring(sc) 1511 struct ti_softc *sc; 1512{ 1513 sc->ti_txcnt = 0; 1514 sc->ti_tx_saved_considx = 0; 1515 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1516 return (0); 1517} 1518 1519/* 1520 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1521 * but we have to support the old way too so that Tigon 1 cards will 1522 * work. 1523 */ 1524static void 1525ti_add_mcast(sc, addr) 1526 struct ti_softc *sc; 1527 struct ether_addr *addr; 1528{ 1529 struct ti_cmd_desc cmd; 1530 u_int16_t *m; 1531 u_int32_t ext[2] = {0, 0}; 1532 1533 m = (u_int16_t *)&addr->octet[0]; 1534 1535 switch (sc->ti_hwrev) { 1536 case TI_HWREV_TIGON: 1537 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1538 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1539 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1540 break; 1541 case TI_HWREV_TIGON_II: 1542 ext[0] = htons(m[0]); 1543 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1544 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1545 break; 1546 default: 1547 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1548 break; 1549 } 1550} 1551 1552static void 1553ti_del_mcast(sc, addr) 1554 struct ti_softc *sc; 1555 struct ether_addr *addr; 1556{ 1557 struct ti_cmd_desc cmd; 1558 u_int16_t *m; 1559 u_int32_t ext[2] = {0, 0}; 1560 1561 m = (u_int16_t *)&addr->octet[0]; 1562 1563 switch (sc->ti_hwrev) { 1564 case TI_HWREV_TIGON: 1565 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1566 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1567 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1568 break; 1569 case TI_HWREV_TIGON_II: 1570 ext[0] = htons(m[0]); 1571 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1572 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1573 break; 1574 default: 1575 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1576 break; 1577 } 1578} 1579 1580/* 1581 * Configure the Tigon's multicast address filter. 1582 * 1583 * The actual multicast table management is a bit of a pain, thanks to 1584 * slight brain damage on the part of both Alteon and us. With our 1585 * multicast code, we are only alerted when the multicast address table 1586 * changes and at that point we only have the current list of addresses: 1587 * we only know the current state, not the previous state, so we don't 1588 * actually know what addresses were removed or added. The firmware has 1589 * state, but we can't get our grubby mits on it, and there is no 'delete 1590 * all multicast addresses' command. Hence, we have to maintain our own 1591 * state so we know what addresses have been programmed into the NIC at 1592 * any given time. 1593 */ 1594static void 1595ti_setmulti(sc) 1596 struct ti_softc *sc; 1597{ 1598 struct ifnet *ifp; 1599 struct ifmultiaddr *ifma; 1600 struct ti_cmd_desc cmd; 1601 struct ti_mc_entry *mc; 1602 u_int32_t intrs; 1603 1604 ifp = sc->ti_ifp; 1605 1606 if (ifp->if_flags & IFF_ALLMULTI) { 1607 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1608 return; 1609 } else { 1610 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1611 } 1612 1613 /* Disable interrupts. */ 1614 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1615 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1616 1617 /* First, zot all the existing filters. */ 1618 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1619 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1620 ti_del_mcast(sc, &mc->mc_addr); 1621 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1622 free(mc, M_DEVBUF); 1623 } 1624 1625 /* Now program new ones. */ 1626 IF_ADDR_LOCK(ifp); 1627 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1628 if (ifma->ifma_addr->sa_family != AF_LINK) 1629 continue; 1630 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1631 if (mc == NULL) { 1632 if_printf(ifp, "no memory for mcast filter entry\n"); 1633 continue; 1634 } 1635 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1636 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1637 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1638 ti_add_mcast(sc, &mc->mc_addr); 1639 } 1640 IF_ADDR_UNLOCK(ifp); 1641 1642 /* Re-enable interrupts. */ 1643 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1644} 1645 1646/* 1647 * Check to see if the BIOS has configured us for a 64 bit slot when 1648 * we aren't actually in one. If we detect this condition, we can work 1649 * around it on the Tigon 2 by setting a bit in the PCI state register, 1650 * but for the Tigon 1 we must give up and abort the interface attach. 1651 */ 1652static int ti_64bitslot_war(sc) 1653 struct ti_softc *sc; 1654{ 1655 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1656 CSR_WRITE_4(sc, 0x600, 0); 1657 CSR_WRITE_4(sc, 0x604, 0); 1658 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1659 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1660 if (sc->ti_hwrev == TI_HWREV_TIGON) 1661 return (EINVAL); 1662 else { 1663 TI_SETBIT(sc, TI_PCI_STATE, 1664 TI_PCISTATE_32BIT_BUS); 1665 return (0); 1666 } 1667 } 1668 } 1669 1670 return (0); 1671} 1672 1673/* 1674 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1675 * self-test results. 1676 */ 1677static int 1678ti_chipinit(sc) 1679 struct ti_softc *sc; 1680{ 1681 u_int32_t cacheline; 1682 u_int32_t pci_writemax = 0; 1683 u_int32_t hdrsplit; 1684 1685 /* Initialize link to down state. */ 1686 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1687 1688 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1689 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1690 else 1691 sc->ti_ifp->if_hwassist = 0; 1692 1693 /* Set endianness before we access any non-PCI registers. */ 1694#if BYTE_ORDER == BIG_ENDIAN 1695 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1696 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1697#else 1698 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1699 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1700#endif 1701 1702 /* Check the ROM failed bit to see if self-tests passed. */ 1703 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1704 if_printf(sc->ti_ifp, "board self-diagnostics failed!\n"); 1705 return (ENODEV); 1706 } 1707 1708 /* Halt the CPU. */ 1709 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1710 1711 /* Figure out the hardware revision. */ 1712 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1713 case TI_REV_TIGON_I: 1714 sc->ti_hwrev = TI_HWREV_TIGON; 1715 break; 1716 case TI_REV_TIGON_II: 1717 sc->ti_hwrev = TI_HWREV_TIGON_II; 1718 break; 1719 default: 1720 if_printf(sc->ti_ifp, "unsupported chip revision\n"); 1721 return (ENODEV); 1722 } 1723 1724 /* Do special setup for Tigon 2. */ 1725 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1726 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1727 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1728 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1729 } 1730 1731 /* 1732 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1733 * can't do header splitting. 1734 */ 1735#ifdef TI_JUMBO_HDRSPLIT 1736 if (sc->ti_hwrev != TI_HWREV_TIGON) 1737 sc->ti_hdrsplit = 1; 1738 else 1739 if_printf(sc->ti_ifp, 1740 "can't do header splitting on a Tigon I board\n"); 1741#endif /* TI_JUMBO_HDRSPLIT */ 1742 1743 /* Set up the PCI state register. */ 1744 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1745 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1746 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1747 } 1748 1749 /* Clear the read/write max DMA parameters. */ 1750 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1751 TI_PCISTATE_READ_MAXDMA)); 1752 1753 /* Get cache line size. */ 1754 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1755 1756 /* 1757 * If the system has set enabled the PCI memory write 1758 * and invalidate command in the command register, set 1759 * the write max parameter accordingly. This is necessary 1760 * to use MWI with the Tigon 2. 1761 */ 1762 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1763 switch (cacheline) { 1764 case 1: 1765 case 4: 1766 case 8: 1767 case 16: 1768 case 32: 1769 case 64: 1770 break; 1771 default: 1772 /* Disable PCI memory write and invalidate. */ 1773 if (bootverbose) 1774 if_printf(sc->ti_ifp, "cache line size %d not " 1775 "supported; disabling PCI MWI\n", 1776 cacheline); 1777 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1778 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1779 break; 1780 } 1781 } 1782 1783#ifdef __brokenalpha__ 1784 /* 1785 * From the Alteon sample driver: 1786 * Must insure that we do not cross an 8K (bytes) boundary 1787 * for DMA reads. Our highest limit is 1K bytes. This is a 1788 * restriction on some ALPHA platforms with early revision 1789 * 21174 PCI chipsets, such as the AlphaPC 164lx 1790 */ 1791 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1792#else 1793 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1794#endif 1795 1796 /* This sets the min dma param all the way up (0xff). */ 1797 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1798 1799 if (sc->ti_hdrsplit) 1800 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1801 else 1802 hdrsplit = 0; 1803 1804 /* Configure DMA variables. */ 1805#if BYTE_ORDER == BIG_ENDIAN 1806 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1807 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1808 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1809 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1810#else /* BYTE_ORDER */ 1811 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1812 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1813 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1814#endif /* BYTE_ORDER */ 1815 1816 /* 1817 * Only allow 1 DMA channel to be active at a time. 1818 * I don't think this is a good idea, but without it 1819 * the firmware racks up lots of nicDmaReadRingFull 1820 * errors. This is not compatible with hardware checksums. 1821 */ 1822 if (sc->ti_ifp->if_hwassist == 0) 1823 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1824 1825 /* Recommended settings from Tigon manual. */ 1826 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1827 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1828 1829 if (ti_64bitslot_war(sc)) { 1830 if_printf(sc->ti_ifp, "bios thinks we're in a 64 bit slot, " 1831 "but we aren't"); 1832 return (EINVAL); 1833 } 1834 1835 return (0); 1836} 1837 1838#define TI_RD_OFF(x) offsetof(struct ti_ring_data, x) 1839 1840/* 1841 * Initialize the general information block and firmware, and 1842 * start the CPU(s) running. 1843 */ 1844static int 1845ti_gibinit(sc) 1846 struct ti_softc *sc; 1847{ 1848 struct ti_rcb *rcb; 1849 int i; 1850 struct ifnet *ifp; 1851 uint32_t rdphys; 1852 1853 ifp = sc->ti_ifp; 1854 rdphys = sc->ti_rdata_phys; 1855 1856 /* Disable interrupts for now. */ 1857 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1858 1859 /* 1860 * Tell the chip where to find the general information block. 1861 * While this struct could go into >4GB memory, we allocate it in a 1862 * single slab with the other descriptors, and those don't seem to 1863 * support being located in a 64-bit region. 1864 */ 1865 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1866 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 1867 1868 /* Load the firmware into SRAM. */ 1869 ti_loadfw(sc); 1870 1871 /* Set up the contents of the general info and ring control blocks. */ 1872 1873 /* Set up the event ring and producer pointer. */ 1874 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1875 1876 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 1877 rcb->ti_flags = 0; 1878 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1879 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 1880 sc->ti_ev_prodidx.ti_idx = 0; 1881 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1882 sc->ti_ev_saved_considx = 0; 1883 1884 /* Set up the command ring and producer mailbox. */ 1885 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1886 1887 sc->ti_rdata->ti_cmd_ring = 1888 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1889 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1890 rcb->ti_flags = 0; 1891 rcb->ti_max_len = 0; 1892 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1893 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1894 } 1895 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1896 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1897 sc->ti_cmd_saved_prodidx = 0; 1898 1899 /* 1900 * Assign the address of the stats refresh buffer. 1901 * We re-use the current stats buffer for this to 1902 * conserve memory. 1903 */ 1904 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1905 rdphys + TI_RD_OFF(ti_info.ti_stats); 1906 1907 /* Set up the standard receive ring. */ 1908 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1909 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 1910 rcb->ti_max_len = TI_FRAMELEN; 1911 rcb->ti_flags = 0; 1912 if (sc->ti_ifp->if_hwassist) 1913 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1914 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1915 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1916 1917 /* Set up the jumbo receive ring. */ 1918 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1919 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 1920 1921#ifdef TI_PRIVATE_JUMBOS 1922 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1923 rcb->ti_flags = 0; 1924#else 1925 rcb->ti_max_len = PAGE_SIZE; 1926 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1927#endif 1928 if (sc->ti_ifp->if_hwassist) 1929 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1930 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1931 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1932 1933 /* 1934 * Set up the mini ring. Only activated on the 1935 * Tigon 2 but the slot in the config block is 1936 * still there on the Tigon 1. 1937 */ 1938 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1939 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 1940 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1941 if (sc->ti_hwrev == TI_HWREV_TIGON) 1942 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1943 else 1944 rcb->ti_flags = 0; 1945 if (sc->ti_ifp->if_hwassist) 1946 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1947 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1948 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1949 1950 /* 1951 * Set up the receive return ring. 1952 */ 1953 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1954 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 1955 rcb->ti_flags = 0; 1956 rcb->ti_max_len = TI_RETURN_RING_CNT; 1957 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1958 rdphys + TI_RD_OFF(ti_return_prodidx_r); 1959 1960 /* 1961 * Set up the tx ring. Note: for the Tigon 2, we have the option 1962 * of putting the transmit ring in the host's address space and 1963 * letting the chip DMA it instead of leaving the ring in the NIC's 1964 * memory and accessing it through the shared memory region. We 1965 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1966 * so we have to revert to the shared memory scheme if we detect 1967 * a Tigon 1 chip. 1968 */ 1969 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1970 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1971 sc->ti_rdata->ti_tx_ring_nic = 1972 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1973 } 1974 bzero((char *)sc->ti_rdata->ti_tx_ring, 1975 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1976 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1977 if (sc->ti_hwrev == TI_HWREV_TIGON) 1978 rcb->ti_flags = 0; 1979 else 1980 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1981 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1982 if (sc->ti_ifp->if_hwassist) 1983 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1984 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1985 rcb->ti_max_len = TI_TX_RING_CNT; 1986 if (sc->ti_hwrev == TI_HWREV_TIGON) 1987 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1988 else 1989 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 1990 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1991 rdphys + TI_RD_OFF(ti_tx_considx_r); 1992 1993 /* Set up tuneables */ 1994#if 0 1995 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1996 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1997 (sc->ti_rx_coal_ticks / 10)); 1998 else 1999#endif 2000 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2001 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2002 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2003 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2004 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2005 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2006 2007 /* Turn interrupts on. */ 2008 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2009 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2010 2011 /* Start CPU. */ 2012 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2013 2014 return (0); 2015} 2016 2017static void 2018ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2019{ 2020 struct ti_softc *sc; 2021 2022 sc = arg; 2023 if (error || nseg != 1) 2024 return; 2025 2026 /* 2027 * All of the Tigon data structures need to live at <4GB. This 2028 * cast is fine since busdma was told about this constraint. 2029 */ 2030 sc->ti_rdata_phys = (uint32_t)segs[0].ds_addr; 2031 return; 2032} 2033 2034/* 2035 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2036 * against our list and return its name if we find a match. 2037 */ 2038static int 2039ti_probe(dev) 2040 device_t dev; 2041{ 2042 struct ti_type *t; 2043 2044 t = ti_devs; 2045 2046 while (t->ti_name != NULL) { 2047 if ((pci_get_vendor(dev) == t->ti_vid) && 2048 (pci_get_device(dev) == t->ti_did)) { 2049 device_set_desc(dev, t->ti_name); 2050 return (BUS_PROBE_DEFAULT); 2051 } 2052 t++; 2053 } 2054 2055 return (ENXIO); 2056} 2057 2058static int 2059ti_attach(dev) 2060 device_t dev; 2061{ 2062 struct ifnet *ifp; 2063 struct ti_softc *sc; 2064 int error = 0, rid; 2065 u_char eaddr[6]; 2066 2067 sc = device_get_softc(dev); 2068 sc->ti_unit = device_get_unit(dev); 2069 2070 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2071 MTX_DEF | MTX_RECURSE); 2072 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2073 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2074 if (ifp == NULL) { 2075 device_printf(dev, "can not if_alloc()\n"); 2076 error = ENOSPC; 2077 goto fail; 2078 } 2079 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2080 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2081 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2082 2083 /* 2084 * Map control/status registers. 2085 */ 2086 pci_enable_busmaster(dev); 2087 2088 rid = TI_PCI_LOMEM; 2089 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2090 RF_ACTIVE|PCI_RF_DENSE); 2091 2092 if (sc->ti_res == NULL) { 2093 device_printf(dev, "couldn't map memory\n"); 2094 error = ENXIO; 2095 goto fail; 2096 } 2097 2098 sc->ti_btag = rman_get_bustag(sc->ti_res); 2099 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2100 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2101 2102 /* Allocate interrupt */ 2103 rid = 0; 2104 2105 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2106 RF_SHAREABLE | RF_ACTIVE); 2107 2108 if (sc->ti_irq == NULL) { 2109 device_printf(dev, "couldn't map interrupt\n"); 2110 error = ENXIO; 2111 goto fail; 2112 } 2113 2114 if (ti_chipinit(sc)) { 2115 device_printf(dev, "chip initialization failed\n"); 2116 error = ENXIO; 2117 goto fail; 2118 } 2119 2120 /* Zero out the NIC's on-board SRAM. */ 2121 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2122 2123 /* Init again -- zeroing memory may have clobbered some registers. */ 2124 if (ti_chipinit(sc)) { 2125 device_printf(dev, "chip initialization failed\n"); 2126 error = ENXIO; 2127 goto fail; 2128 } 2129 2130 /* 2131 * Get station address from the EEPROM. Note: the manual states 2132 * that the MAC address is at offset 0x8c, however the data is 2133 * stored as two longwords (since that's how it's loaded into 2134 * the NIC). This means the MAC address is actually preceded 2135 * by two zero bytes. We need to skip over those. 2136 */ 2137 if (ti_read_eeprom(sc, eaddr, 2138 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2139 device_printf(dev, "failed to read station address\n"); 2140 error = ENXIO; 2141 goto fail; 2142 } 2143 2144 /* Allocate the general information block and ring buffers. */ 2145 if (bus_dma_tag_create(NULL, /* parent */ 2146 1, 0, /* algnmnt, boundary */ 2147 BUS_SPACE_MAXADDR, /* lowaddr */ 2148 BUS_SPACE_MAXADDR, /* highaddr */ 2149 NULL, NULL, /* filter, filterarg */ 2150 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2151 0, /* nsegments */ 2152 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2153 0, /* flags */ 2154 NULL, NULL, /* lockfunc, lockarg */ 2155 &sc->ti_parent_dmat) != 0) { 2156 device_printf(dev, "Failed to allocate parent dmat\n"); 2157 error = ENOMEM; 2158 goto fail; 2159 } 2160 2161 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2162 PAGE_SIZE, 0, /* algnmnt, boundary */ 2163 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2164 BUS_SPACE_MAXADDR, /* highaddr */ 2165 NULL, NULL, /* filter, filterarg */ 2166 sizeof(struct ti_ring_data), /* maxsize */ 2167 1, /* nsegments */ 2168 sizeof(struct ti_ring_data), /* maxsegsize */ 2169 0, /* flags */ 2170 NULL, NULL, /* lockfunc, lockarg */ 2171 &sc->ti_rdata_dmat) != 0) { 2172 device_printf(dev, "Failed to allocate rdata dmat\n"); 2173 error = ENOMEM; 2174 goto fail; 2175 } 2176 2177 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2178 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2179 device_printf(dev, "Failed to allocate rdata memory\n"); 2180 error = ENOMEM; 2181 goto fail; 2182 } 2183 2184 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2185 sc->ti_rdata, sizeof(struct ti_ring_data), 2186 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2187 device_printf(dev, "Failed to load rdata segments\n"); 2188 error = ENOMEM; 2189 goto fail; 2190 } 2191 2192 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2193 2194 /* Try to allocate memory for jumbo buffers. */ 2195#ifdef TI_PRIVATE_JUMBOS 2196 if (ti_alloc_jumbo_mem(sc)) { 2197 device_printf(dev, "jumbo buffer allocation failed\n"); 2198 error = ENXIO; 2199 goto fail; 2200 } 2201#endif 2202 2203 /* 2204 * We really need a better way to tell a 1000baseTX card 2205 * from a 1000baseSX one, since in theory there could be 2206 * OEMed 1000baseTX cards from lame vendors who aren't 2207 * clever enough to change the PCI ID. For the moment 2208 * though, the AceNIC is the only copper card available. 2209 */ 2210 if (pci_get_vendor(dev) == ALT_VENDORID && 2211 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2212 sc->ti_copper = 1; 2213 /* Ok, it's not the only copper card available. */ 2214 if (pci_get_vendor(dev) == NG_VENDORID && 2215 pci_get_device(dev) == NG_DEVICEID_GA620T) 2216 sc->ti_copper = 1; 2217 2218 /* Set default tuneable values. */ 2219 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2220#if 0 2221 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2222#endif 2223 sc->ti_rx_coal_ticks = 170; 2224 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2225 sc->ti_rx_max_coal_bds = 64; 2226#if 0 2227 sc->ti_tx_max_coal_bds = 128; 2228#endif 2229 sc->ti_tx_max_coal_bds = 32; 2230 sc->ti_tx_buf_ratio = 21; 2231 2232 /* Set up ifnet structure */ 2233 ifp->if_softc = sc; 2234 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 2236 IFF_NEEDSGIANT; 2237 tis[sc->ti_unit] = sc; 2238 ifp->if_ioctl = ti_ioctl; 2239 ifp->if_start = ti_start; 2240 ifp->if_watchdog = ti_watchdog; 2241 ifp->if_init = ti_init; 2242 ifp->if_mtu = ETHERMTU; 2243 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2244 2245 /* Set up ifmedia support. */ 2246 if (sc->ti_copper) { 2247 /* 2248 * Copper cards allow manual 10/100 mode selection, 2249 * but not manual 1000baseTX mode selection. Why? 2250 * Becuase currently there's no way to specify the 2251 * master/slave setting through the firmware interface, 2252 * so Alteon decided to just bag it and handle it 2253 * via autonegotiation. 2254 */ 2255 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2256 ifmedia_add(&sc->ifmedia, 2257 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2258 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2259 ifmedia_add(&sc->ifmedia, 2260 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2261 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2262 ifmedia_add(&sc->ifmedia, 2263 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2264 } else { 2265 /* Fiber cards don't support 10/100 modes. */ 2266 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2267 ifmedia_add(&sc->ifmedia, 2268 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2269 } 2270 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2271 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2272 2273 /* 2274 * We're assuming here that card initialization is a sequential 2275 * thing. If it isn't, multiple cards probing at the same time 2276 * could stomp on the list of softcs here. 2277 */ 2278 2279 /* Register the device */ 2280 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2281 0600, "ti%d", sc->ti_unit); 2282 sc->dev->si_drv1 = sc; 2283 2284 /* 2285 * Call MI attach routine. 2286 */ 2287 ether_ifattach(ifp, eaddr); 2288 2289 /* Hook interrupt last to avoid having to lock softc */ 2290 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2291 ti_intr, sc, &sc->ti_intrhand); 2292 2293 if (error) { 2294 device_printf(dev, "couldn't set up irq\n"); 2295 ether_ifdetach(ifp); 2296 goto fail; 2297 } 2298 2299fail: 2300 if (sc && error) 2301 ti_detach(dev); 2302 2303 return (error); 2304} 2305 2306/* 2307 * Shutdown hardware and free up resources. This can be called any 2308 * time after the mutex has been initialized. It is called in both 2309 * the error case in attach and the normal detach case so it needs 2310 * to be careful about only freeing resources that have actually been 2311 * allocated. 2312 */ 2313static int 2314ti_detach(dev) 2315 device_t dev; 2316{ 2317 struct ti_softc *sc; 2318 struct ifnet *ifp; 2319 2320 sc = device_get_softc(dev); 2321 if (sc->dev) 2322 destroy_dev(sc->dev); 2323 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2324 TI_LOCK(sc); 2325 ifp = sc->ti_ifp; 2326 2327 /* These should only be active if attach succeeded */ 2328 if (device_is_attached(dev)) { 2329 ti_stop(sc); 2330 ether_ifdetach(ifp); 2331 bus_generic_detach(dev); 2332 } 2333 ifmedia_removeall(&sc->ifmedia); 2334 2335 if (sc->ti_rdata) 2336 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2337 sc->ti_rdata_dmamap); 2338 if (sc->ti_rdata_dmat) 2339 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2340 if (sc->ti_parent_dmat) 2341 bus_dma_tag_destroy(sc->ti_parent_dmat); 2342 if (sc->ti_intrhand) 2343 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2344 if (sc->ti_irq) 2345 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2346 if (sc->ti_res) { 2347 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2348 sc->ti_res); 2349 } 2350 if (ifp) 2351 if_free(ifp); 2352 2353#ifdef TI_PRIVATE_JUMBOS 2354 if (sc->ti_cdata.ti_jumbo_buf) 2355 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2356#endif 2357 if (sc->ti_rdata) 2358 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2359 2360 TI_UNLOCK(sc); 2361 mtx_destroy(&sc->ti_mtx); 2362 2363 return (0); 2364} 2365 2366#ifdef TI_JUMBO_HDRSPLIT 2367/* 2368 * If hdr_len is 0, that means that header splitting wasn't done on 2369 * this packet for some reason. The two most likely reasons are that 2370 * the protocol isn't a supported protocol for splitting, or this 2371 * packet had a fragment offset that wasn't 0. 2372 * 2373 * The header length, if it is non-zero, will always be the length of 2374 * the headers on the packet, but that length could be longer than the 2375 * first mbuf. So we take the minimum of the two as the actual 2376 * length. 2377 */ 2378static __inline void 2379ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2380{ 2381 int i = 0; 2382 int lengths[4] = {0, 0, 0, 0}; 2383 struct mbuf *m, *mp; 2384 2385 if (hdr_len != 0) 2386 top->m_len = min(hdr_len, top->m_len); 2387 pkt_len -= top->m_len; 2388 lengths[i++] = top->m_len; 2389 2390 mp = top; 2391 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2392 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2393 pkt_len -= m->m_len; 2394 lengths[i++] = m->m_len; 2395 mp = m; 2396 } 2397 2398#if 0 2399 if (hdr_len != 0) 2400 printf("got split packet: "); 2401 else 2402 printf("got non-split packet: "); 2403 2404 printf("%d,%d,%d,%d = %d\n", lengths[0], 2405 lengths[1], lengths[2], lengths[3], 2406 lengths[0] + lengths[1] + lengths[2] + 2407 lengths[3]); 2408#endif 2409 2410 if (pkt_len) 2411 panic("header splitting didn't"); 2412 2413 if (m) { 2414 m_freem(m); 2415 mp->m_next = NULL; 2416 2417 } 2418 if (mp->m_next != NULL) 2419 panic("ti_hdr_split: last mbuf in chain should be null"); 2420} 2421#endif /* TI_JUMBO_HDRSPLIT */ 2422 2423/* 2424 * Frame reception handling. This is called if there's a frame 2425 * on the receive return list. 2426 * 2427 * Note: we have to be able to handle three possibilities here: 2428 * 1) the frame is from the mini receive ring (can only happen) 2429 * on Tigon 2 boards) 2430 * 2) the frame is from the jumbo recieve ring 2431 * 3) the frame is from the standard receive ring 2432 */ 2433 2434static void 2435ti_rxeof(sc) 2436 struct ti_softc *sc; 2437{ 2438 struct ifnet *ifp; 2439 struct ti_cmd_desc cmd; 2440 2441 TI_LOCK_ASSERT(sc); 2442 2443 ifp = sc->ti_ifp; 2444 2445 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2446 struct ti_rx_desc *cur_rx; 2447 u_int32_t rxidx; 2448 struct mbuf *m = NULL; 2449 u_int16_t vlan_tag = 0; 2450 int have_tag = 0; 2451 2452 cur_rx = 2453 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2454 rxidx = cur_rx->ti_idx; 2455 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2456 2457 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2458 have_tag = 1; 2459 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2460 } 2461 2462 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2463 2464 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2465 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2466 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2467 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2468 ifp->if_ierrors++; 2469 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2470 continue; 2471 } 2472 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2473 ifp->if_ierrors++; 2474 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2475 continue; 2476 } 2477#ifdef TI_PRIVATE_JUMBOS 2478 m->m_len = cur_rx->ti_len; 2479#else /* TI_PRIVATE_JUMBOS */ 2480#ifdef TI_JUMBO_HDRSPLIT 2481 if (sc->ti_hdrsplit) 2482 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2483 cur_rx->ti_len, rxidx); 2484 else 2485#endif /* TI_JUMBO_HDRSPLIT */ 2486 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2487#endif /* TI_PRIVATE_JUMBOS */ 2488 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2489 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2490 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2491 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2492 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2493 ifp->if_ierrors++; 2494 ti_newbuf_mini(sc, sc->ti_mini, m); 2495 continue; 2496 } 2497 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2498 ifp->if_ierrors++; 2499 ti_newbuf_mini(sc, sc->ti_mini, m); 2500 continue; 2501 } 2502 m->m_len = cur_rx->ti_len; 2503 } else { 2504 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2505 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2506 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2507 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2508 ifp->if_ierrors++; 2509 ti_newbuf_std(sc, sc->ti_std, m); 2510 continue; 2511 } 2512 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2513 ifp->if_ierrors++; 2514 ti_newbuf_std(sc, sc->ti_std, m); 2515 continue; 2516 } 2517 m->m_len = cur_rx->ti_len; 2518 } 2519 2520 m->m_pkthdr.len = cur_rx->ti_len; 2521 ifp->if_ipackets++; 2522 m->m_pkthdr.rcvif = ifp; 2523 2524 if (ifp->if_hwassist) { 2525 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2526 CSUM_DATA_VALID; 2527 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2528 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2529 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2530 } 2531 2532 /* 2533 * If we received a packet with a vlan tag, 2534 * tag it before passing the packet upward. 2535 */ 2536 if (have_tag) 2537 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2538 TI_UNLOCK(sc); 2539 (*ifp->if_input)(ifp, m); 2540 TI_LOCK(sc); 2541 } 2542 2543 /* Only necessary on the Tigon 1. */ 2544 if (sc->ti_hwrev == TI_HWREV_TIGON) 2545 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2546 sc->ti_rx_saved_considx); 2547 2548 TI_UPDATE_STDPROD(sc, sc->ti_std); 2549 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2550 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2551} 2552 2553static void 2554ti_txeof(sc) 2555 struct ti_softc *sc; 2556{ 2557 struct ti_tx_desc *cur_tx = NULL; 2558 struct ifnet *ifp; 2559 2560 ifp = sc->ti_ifp; 2561 2562 /* 2563 * Go through our tx ring and free mbufs for those 2564 * frames that have been sent. 2565 */ 2566 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2567 u_int32_t idx = 0; 2568 2569 idx = sc->ti_tx_saved_considx; 2570 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2571 if (idx > 383) 2572 CSR_WRITE_4(sc, TI_WINBASE, 2573 TI_TX_RING_BASE + 6144); 2574 else if (idx > 255) 2575 CSR_WRITE_4(sc, TI_WINBASE, 2576 TI_TX_RING_BASE + 4096); 2577 else if (idx > 127) 2578 CSR_WRITE_4(sc, TI_WINBASE, 2579 TI_TX_RING_BASE + 2048); 2580 else 2581 CSR_WRITE_4(sc, TI_WINBASE, 2582 TI_TX_RING_BASE); 2583 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2584 } else 2585 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2586 if (cur_tx->ti_flags & TI_BDFLAG_END) 2587 ifp->if_opackets++; 2588 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2589 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2590 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2591 } 2592 sc->ti_txcnt--; 2593 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2594 ifp->if_timer = 0; 2595 } 2596 2597 if (cur_tx != NULL) 2598 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2599} 2600 2601static void 2602ti_intr(xsc) 2603 void *xsc; 2604{ 2605 struct ti_softc *sc; 2606 struct ifnet *ifp; 2607 2608 sc = xsc; 2609 TI_LOCK(sc); 2610 ifp = sc->ti_ifp; 2611 2612/*#ifdef notdef*/ 2613 /* Avoid this for now -- checking this register is expensive. */ 2614 /* Make sure this is really our interrupt. */ 2615 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2616 TI_UNLOCK(sc); 2617 return; 2618 } 2619/*#endif*/ 2620 2621 /* Ack interrupt and stop others from occuring. */ 2622 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2623 2624 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2625 /* Check RX return ring producer/consumer */ 2626 ti_rxeof(sc); 2627 2628 /* Check TX ring producer/consumer */ 2629 ti_txeof(sc); 2630 } 2631 2632 ti_handle_events(sc); 2633 2634 /* Re-enable interrupts. */ 2635 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2636 2637 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2638 ifp->if_snd.ifq_head != NULL) 2639 ti_start(ifp); 2640 2641 TI_UNLOCK(sc); 2642} 2643 2644static void 2645ti_stats_update(sc) 2646 struct ti_softc *sc; 2647{ 2648 struct ifnet *ifp; 2649 2650 ifp = sc->ti_ifp; 2651 2652 ifp->if_collisions += 2653 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2654 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2655 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2656 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2657 ifp->if_collisions; 2658} 2659 2660/* 2661 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2662 * pointers to descriptors. 2663 */ 2664static int 2665ti_encap(sc, m_head, txidx) 2666 struct ti_softc *sc; 2667 struct mbuf *m_head; 2668 u_int32_t *txidx; 2669{ 2670 struct ti_tx_desc *f = NULL; 2671 struct mbuf *m; 2672 u_int32_t frag, cur, cnt = 0; 2673 u_int16_t csum_flags = 0; 2674 struct m_tag *mtag; 2675 2676 m = m_head; 2677 cur = frag = *txidx; 2678 2679 if (m_head->m_pkthdr.csum_flags) { 2680 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2681 csum_flags |= TI_BDFLAG_IP_CKSUM; 2682 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2683 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2684 if (m_head->m_flags & M_LASTFRAG) 2685 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2686 else if (m_head->m_flags & M_FRAG) 2687 csum_flags |= TI_BDFLAG_IP_FRAG; 2688 } 2689 2690 mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m); 2691 2692 /* 2693 * Start packing the mbufs in this chain into 2694 * the fragment pointers. Stop when we run out 2695 * of fragments or hit the end of the mbuf chain. 2696 */ 2697 for (m = m_head; m != NULL; m = m->m_next) { 2698 if (m->m_len != 0) { 2699 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2700 if (frag > 383) 2701 CSR_WRITE_4(sc, TI_WINBASE, 2702 TI_TX_RING_BASE + 6144); 2703 else if (frag > 255) 2704 CSR_WRITE_4(sc, TI_WINBASE, 2705 TI_TX_RING_BASE + 4096); 2706 else if (frag > 127) 2707 CSR_WRITE_4(sc, TI_WINBASE, 2708 TI_TX_RING_BASE + 2048); 2709 else 2710 CSR_WRITE_4(sc, TI_WINBASE, 2711 TI_TX_RING_BASE); 2712 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2713 } else 2714 f = &sc->ti_rdata->ti_tx_ring[frag]; 2715 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2716 break; 2717 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2718 f->ti_len = m->m_len; 2719 f->ti_flags = csum_flags; 2720 2721 if (mtag != NULL) { 2722 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2723 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2724 } else { 2725 f->ti_vlan_tag = 0; 2726 } 2727 2728 /* 2729 * Sanity check: avoid coming within 16 descriptors 2730 * of the end of the ring. 2731 */ 2732 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2733 return (ENOBUFS); 2734 cur = frag; 2735 TI_INC(frag, TI_TX_RING_CNT); 2736 cnt++; 2737 } 2738 } 2739 2740 if (m != NULL) 2741 return (ENOBUFS); 2742 2743 if (frag == sc->ti_tx_saved_considx) 2744 return (ENOBUFS); 2745 2746 if (sc->ti_hwrev == TI_HWREV_TIGON) 2747 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2748 TI_BDFLAG_END; 2749 else 2750 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2751 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2752 sc->ti_txcnt += cnt; 2753 2754 *txidx = frag; 2755 2756 return (0); 2757} 2758 2759/* 2760 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2761 * to the mbuf data regions directly in the transmit descriptors. 2762 */ 2763static void 2764ti_start(ifp) 2765 struct ifnet *ifp; 2766{ 2767 struct ti_softc *sc; 2768 struct mbuf *m_head = NULL; 2769 u_int32_t prodidx = 0; 2770 2771 sc = ifp->if_softc; 2772 TI_LOCK(sc); 2773 2774 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2775 2776 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2777 IF_DEQUEUE(&ifp->if_snd, m_head); 2778 if (m_head == NULL) 2779 break; 2780 2781 /* 2782 * XXX 2783 * safety overkill. If this is a fragmented packet chain 2784 * with delayed TCP/UDP checksums, then only encapsulate 2785 * it if we have enough descriptors to handle the entire 2786 * chain at once. 2787 * (paranoia -- may not actually be needed) 2788 */ 2789 if (m_head->m_flags & M_FIRSTFRAG && 2790 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2791 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2792 m_head->m_pkthdr.csum_data + 16) { 2793 IF_PREPEND(&ifp->if_snd, m_head); 2794 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2795 break; 2796 } 2797 } 2798 2799 /* 2800 * Pack the data into the transmit ring. If we 2801 * don't have room, set the OACTIVE flag and wait 2802 * for the NIC to drain the ring. 2803 */ 2804 if (ti_encap(sc, m_head, &prodidx)) { 2805 IF_PREPEND(&ifp->if_snd, m_head); 2806 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2807 break; 2808 } 2809 2810 /* 2811 * If there's a BPF listener, bounce a copy of this frame 2812 * to him. 2813 */ 2814 BPF_MTAP(ifp, m_head); 2815 } 2816 2817 /* Transmit */ 2818 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2819 2820 /* 2821 * Set a timeout in case the chip goes out to lunch. 2822 */ 2823 ifp->if_timer = 5; 2824 TI_UNLOCK(sc); 2825} 2826 2827static void 2828ti_init(xsc) 2829 void *xsc; 2830{ 2831 struct ti_softc *sc = xsc; 2832 2833 /* Cancel pending I/O and flush buffers. */ 2834 ti_stop(sc); 2835 2836 TI_LOCK(sc); 2837 /* Init the gen info block, ring control blocks and firmware. */ 2838 if (ti_gibinit(sc)) { 2839 if_printf(sc->ti_ifp, "initialization failure\n"); 2840 TI_UNLOCK(sc); 2841 return; 2842 } 2843 2844 TI_UNLOCK(sc); 2845} 2846 2847static void ti_init2(sc) 2848 struct ti_softc *sc; 2849{ 2850 struct ti_cmd_desc cmd; 2851 struct ifnet *ifp; 2852 u_int16_t *m; 2853 struct ifmedia *ifm; 2854 int tmp; 2855 2856 ifp = sc->ti_ifp; 2857 2858 /* Specify MTU and interface index. */ 2859 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 2860 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2861 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 2862 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2863 2864 /* Load our MAC address. */ 2865 m = (u_int16_t *)IF_LLADDR(sc->ti_ifp); 2866 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2867 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2868 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2869 2870 /* Enable or disable promiscuous mode as needed. */ 2871 if (ifp->if_flags & IFF_PROMISC) { 2872 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2873 } else { 2874 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2875 } 2876 2877 /* Program multicast filter. */ 2878 ti_setmulti(sc); 2879 2880 /* 2881 * If this is a Tigon 1, we should tell the 2882 * firmware to use software packet filtering. 2883 */ 2884 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2885 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2886 } 2887 2888 /* Init RX ring. */ 2889 ti_init_rx_ring_std(sc); 2890 2891 /* Init jumbo RX ring. */ 2892 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2893 ti_init_rx_ring_jumbo(sc); 2894 2895 /* 2896 * If this is a Tigon 2, we can also configure the 2897 * mini ring. 2898 */ 2899 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2900 ti_init_rx_ring_mini(sc); 2901 2902 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2903 sc->ti_rx_saved_considx = 0; 2904 2905 /* Init TX ring. */ 2906 ti_init_tx_ring(sc); 2907 2908 /* Tell firmware we're alive. */ 2909 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2910 2911 /* Enable host interrupts. */ 2912 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2913 2914 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2915 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2916 2917 /* 2918 * Make sure to set media properly. We have to do this 2919 * here since we have to issue commands in order to set 2920 * the link negotiation and we can't issue commands until 2921 * the firmware is running. 2922 */ 2923 ifm = &sc->ifmedia; 2924 tmp = ifm->ifm_media; 2925 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2926 ti_ifmedia_upd(ifp); 2927 ifm->ifm_media = tmp; 2928} 2929 2930/* 2931 * Set media options. 2932 */ 2933static int 2934ti_ifmedia_upd(ifp) 2935 struct ifnet *ifp; 2936{ 2937 struct ti_softc *sc; 2938 struct ifmedia *ifm; 2939 struct ti_cmd_desc cmd; 2940 u_int32_t flowctl; 2941 2942 sc = ifp->if_softc; 2943 ifm = &sc->ifmedia; 2944 2945 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2946 return (EINVAL); 2947 2948 flowctl = 0; 2949 2950 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2951 case IFM_AUTO: 2952 /* 2953 * Transmit flow control doesn't work on the Tigon 1. 2954 */ 2955 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2956 2957 /* 2958 * Transmit flow control can also cause problems on the 2959 * Tigon 2, apparantly with both the copper and fiber 2960 * boards. The symptom is that the interface will just 2961 * hang. This was reproduced with Alteon 180 switches. 2962 */ 2963#if 0 2964 if (sc->ti_hwrev != TI_HWREV_TIGON) 2965 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2966#endif 2967 2968 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2969 TI_GLNK_FULL_DUPLEX| flowctl | 2970 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2971 2972 flowctl = TI_LNK_RX_FLOWCTL_Y; 2973#if 0 2974 if (sc->ti_hwrev != TI_HWREV_TIGON) 2975 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2976#endif 2977 2978 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2979 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 2980 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2981 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2982 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2983 break; 2984 case IFM_1000_SX: 2985 case IFM_1000_T: 2986 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2987#if 0 2988 if (sc->ti_hwrev != TI_HWREV_TIGON) 2989 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2990#endif 2991 2992 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2993 flowctl |TI_GLNK_ENB); 2994 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2995 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2996 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2997 } 2998 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2999 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3000 break; 3001 case IFM_100_FX: 3002 case IFM_10_FL: 3003 case IFM_100_TX: 3004 case IFM_10_T: 3005 flowctl = TI_LNK_RX_FLOWCTL_Y; 3006#if 0 3007 if (sc->ti_hwrev != TI_HWREV_TIGON) 3008 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3009#endif 3010 3011 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3012 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3013 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3014 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3015 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3016 } else { 3017 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3018 } 3019 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3020 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3021 } else { 3022 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3023 } 3024 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3025 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3026 break; 3027 } 3028 3029 return (0); 3030} 3031 3032/* 3033 * Report current media status. 3034 */ 3035static void 3036ti_ifmedia_sts(ifp, ifmr) 3037 struct ifnet *ifp; 3038 struct ifmediareq *ifmr; 3039{ 3040 struct ti_softc *sc; 3041 u_int32_t media = 0; 3042 3043 sc = ifp->if_softc; 3044 3045 ifmr->ifm_status = IFM_AVALID; 3046 ifmr->ifm_active = IFM_ETHER; 3047 3048 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3049 return; 3050 3051 ifmr->ifm_status |= IFM_ACTIVE; 3052 3053 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3054 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3055 if (sc->ti_copper) 3056 ifmr->ifm_active |= IFM_1000_T; 3057 else 3058 ifmr->ifm_active |= IFM_1000_SX; 3059 if (media & TI_GLNK_FULL_DUPLEX) 3060 ifmr->ifm_active |= IFM_FDX; 3061 else 3062 ifmr->ifm_active |= IFM_HDX; 3063 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3064 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3065 if (sc->ti_copper) { 3066 if (media & TI_LNK_100MB) 3067 ifmr->ifm_active |= IFM_100_TX; 3068 if (media & TI_LNK_10MB) 3069 ifmr->ifm_active |= IFM_10_T; 3070 } else { 3071 if (media & TI_LNK_100MB) 3072 ifmr->ifm_active |= IFM_100_FX; 3073 if (media & TI_LNK_10MB) 3074 ifmr->ifm_active |= IFM_10_FL; 3075 } 3076 if (media & TI_LNK_FULL_DUPLEX) 3077 ifmr->ifm_active |= IFM_FDX; 3078 if (media & TI_LNK_HALF_DUPLEX) 3079 ifmr->ifm_active |= IFM_HDX; 3080 } 3081} 3082 3083static int 3084ti_ioctl(ifp, command, data) 3085 struct ifnet *ifp; 3086 u_long command; 3087 caddr_t data; 3088{ 3089 struct ti_softc *sc = ifp->if_softc; 3090 struct ifreq *ifr = (struct ifreq *) data; 3091 int mask, error = 0; 3092 struct ti_cmd_desc cmd; 3093 3094 TI_LOCK(sc); 3095 3096 switch (command) { 3097 case SIOCSIFMTU: 3098 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3099 error = EINVAL; 3100 else { 3101 ifp->if_mtu = ifr->ifr_mtu; 3102 ti_init(sc); 3103 } 3104 break; 3105 case SIOCSIFFLAGS: 3106 if (ifp->if_flags & IFF_UP) { 3107 /* 3108 * If only the state of the PROMISC flag changed, 3109 * then just use the 'set promisc mode' command 3110 * instead of reinitializing the entire NIC. Doing 3111 * a full re-init means reloading the firmware and 3112 * waiting for it to start up, which may take a 3113 * second or two. 3114 */ 3115 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3116 ifp->if_flags & IFF_PROMISC && 3117 !(sc->ti_if_flags & IFF_PROMISC)) { 3118 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3119 TI_CMD_CODE_PROMISC_ENB, 0); 3120 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3121 !(ifp->if_flags & IFF_PROMISC) && 3122 sc->ti_if_flags & IFF_PROMISC) { 3123 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3124 TI_CMD_CODE_PROMISC_DIS, 0); 3125 } else 3126 ti_init(sc); 3127 } else { 3128 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3129 ti_stop(sc); 3130 } 3131 } 3132 sc->ti_if_flags = ifp->if_flags; 3133 error = 0; 3134 break; 3135 case SIOCADDMULTI: 3136 case SIOCDELMULTI: 3137 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3138 ti_setmulti(sc); 3139 error = 0; 3140 } 3141 break; 3142 case SIOCSIFMEDIA: 3143 case SIOCGIFMEDIA: 3144 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3145 break; 3146 case SIOCSIFCAP: 3147 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3148 if (mask & IFCAP_HWCSUM) { 3149 if (IFCAP_HWCSUM & ifp->if_capenable) 3150 ifp->if_capenable &= ~IFCAP_HWCSUM; 3151 else 3152 ifp->if_capenable |= IFCAP_HWCSUM; 3153 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3154 ti_init(sc); 3155 } 3156 error = 0; 3157 break; 3158 default: 3159 error = ether_ioctl(ifp, command, data); 3160 break; 3161 } 3162 3163 TI_UNLOCK(sc); 3164 3165 return (error); 3166} 3167 3168static int 3169ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3170{ 3171 struct ti_softc *sc; 3172 3173 sc = dev->si_drv1; 3174 if (sc == NULL) 3175 return (ENODEV); 3176 3177 TI_LOCK(sc); 3178 sc->ti_flags |= TI_FLAG_DEBUGING; 3179 TI_UNLOCK(sc); 3180 3181 return (0); 3182} 3183 3184static int 3185ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3186{ 3187 struct ti_softc *sc; 3188 3189 sc = dev->si_drv1; 3190 if (sc == NULL) 3191 return (ENODEV); 3192 3193 TI_LOCK(sc); 3194 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3195 TI_UNLOCK(sc); 3196 3197 return (0); 3198} 3199 3200/* 3201 * This ioctl routine goes along with the Tigon character device. 3202 */ 3203static int 3204ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3205 struct thread *td) 3206{ 3207 int error; 3208 struct ti_softc *sc; 3209 3210 sc = dev->si_drv1; 3211 if (sc == NULL) 3212 return (ENODEV); 3213 3214 error = 0; 3215 3216 switch (cmd) { 3217 case TIIOCGETSTATS: 3218 { 3219 struct ti_stats *outstats; 3220 3221 outstats = (struct ti_stats *)addr; 3222 3223 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3224 sizeof(struct ti_stats)); 3225 break; 3226 } 3227 case TIIOCGETPARAMS: 3228 { 3229 struct ti_params *params; 3230 3231 params = (struct ti_params *)addr; 3232 3233 params->ti_stat_ticks = sc->ti_stat_ticks; 3234 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3235 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3236 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3237 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3238 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3239 params->param_mask = TI_PARAM_ALL; 3240 3241 error = 0; 3242 3243 break; 3244 } 3245 case TIIOCSETPARAMS: 3246 { 3247 struct ti_params *params; 3248 3249 params = (struct ti_params *)addr; 3250 3251 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3252 sc->ti_stat_ticks = params->ti_stat_ticks; 3253 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3254 } 3255 3256 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3257 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3258 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3259 sc->ti_rx_coal_ticks); 3260 } 3261 3262 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3263 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3264 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3265 sc->ti_tx_coal_ticks); 3266 } 3267 3268 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3269 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3270 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3271 sc->ti_rx_max_coal_bds); 3272 } 3273 3274 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3275 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3276 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3277 sc->ti_tx_max_coal_bds); 3278 } 3279 3280 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3281 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3282 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3283 sc->ti_tx_buf_ratio); 3284 } 3285 3286 error = 0; 3287 3288 break; 3289 } 3290 case TIIOCSETTRACE: { 3291 ti_trace_type trace_type; 3292 3293 trace_type = *(ti_trace_type *)addr; 3294 3295 /* 3296 * Set tracing to whatever the user asked for. Setting 3297 * this register to 0 should have the effect of disabling 3298 * tracing. 3299 */ 3300 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3301 3302 error = 0; 3303 3304 break; 3305 } 3306 case TIIOCGETTRACE: { 3307 struct ti_trace_buf *trace_buf; 3308 u_int32_t trace_start, cur_trace_ptr, trace_len; 3309 3310 trace_buf = (struct ti_trace_buf *)addr; 3311 3312 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3313 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3314 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3315 3316#if 0 3317 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3318 "trace_len = %d\n", trace_start, 3319 cur_trace_ptr, trace_len); 3320 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3321 trace_buf->buf_len); 3322#endif 3323 3324 error = ti_copy_mem(sc, trace_start, min(trace_len, 3325 trace_buf->buf_len), 3326 (caddr_t)trace_buf->buf, 1, 1); 3327 3328 if (error == 0) { 3329 trace_buf->fill_len = min(trace_len, 3330 trace_buf->buf_len); 3331 if (cur_trace_ptr < trace_start) 3332 trace_buf->cur_trace_ptr = 3333 trace_start - cur_trace_ptr; 3334 else 3335 trace_buf->cur_trace_ptr = 3336 cur_trace_ptr - trace_start; 3337 } else 3338 trace_buf->fill_len = 0; 3339 3340 break; 3341 } 3342 3343 /* 3344 * For debugging, five ioctls are needed: 3345 * ALT_ATTACH 3346 * ALT_READ_TG_REG 3347 * ALT_WRITE_TG_REG 3348 * ALT_READ_TG_MEM 3349 * ALT_WRITE_TG_MEM 3350 */ 3351 case ALT_ATTACH: 3352 /* 3353 * From what I can tell, Alteon's Solaris Tigon driver 3354 * only has one character device, so you have to attach 3355 * to the Tigon board you're interested in. This seems 3356 * like a not-so-good way to do things, since unless you 3357 * subsequently specify the unit number of the device 3358 * you're interested in in every ioctl, you'll only be 3359 * able to debug one board at a time. 3360 */ 3361 error = 0; 3362 break; 3363 case ALT_READ_TG_MEM: 3364 case ALT_WRITE_TG_MEM: 3365 { 3366 struct tg_mem *mem_param; 3367 u_int32_t sram_end, scratch_end; 3368 3369 mem_param = (struct tg_mem *)addr; 3370 3371 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3372 sram_end = TI_END_SRAM_I; 3373 scratch_end = TI_END_SCRATCH_I; 3374 } else { 3375 sram_end = TI_END_SRAM_II; 3376 scratch_end = TI_END_SCRATCH_II; 3377 } 3378 3379 /* 3380 * For now, we'll only handle accessing regular SRAM, 3381 * nothing else. 3382 */ 3383 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3384 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3385 /* 3386 * In this instance, we always copy to/from user 3387 * space, so the user space argument is set to 1. 3388 */ 3389 error = ti_copy_mem(sc, mem_param->tgAddr, 3390 mem_param->len, 3391 mem_param->userAddr, 1, 3392 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3393 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3394 && (mem_param->tgAddr <= scratch_end)) { 3395 error = ti_copy_scratch(sc, mem_param->tgAddr, 3396 mem_param->len, 3397 mem_param->userAddr, 1, 3398 (cmd == ALT_READ_TG_MEM) ? 3399 1 : 0, TI_PROCESSOR_A); 3400 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3401 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3402 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3403 if_printf(sc->ti_ifp, 3404 "invalid memory range for Tigon I\n"); 3405 error = EINVAL; 3406 break; 3407 } 3408 error = ti_copy_scratch(sc, mem_param->tgAddr - 3409 TI_SCRATCH_DEBUG_OFF, 3410 mem_param->len, 3411 mem_param->userAddr, 1, 3412 (cmd == ALT_READ_TG_MEM) ? 3413 1 : 0, TI_PROCESSOR_B); 3414 } else { 3415 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3416 "out of supported range\n", 3417 mem_param->tgAddr, mem_param->len); 3418 error = EINVAL; 3419 } 3420 3421 break; 3422 } 3423 case ALT_READ_TG_REG: 3424 case ALT_WRITE_TG_REG: 3425 { 3426 struct tg_reg *regs; 3427 u_int32_t tmpval; 3428 3429 regs = (struct tg_reg *)addr; 3430 3431 /* 3432 * Make sure the address in question isn't out of range. 3433 */ 3434 if (regs->addr > TI_REG_MAX) { 3435 error = EINVAL; 3436 break; 3437 } 3438 if (cmd == ALT_READ_TG_REG) { 3439 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3440 regs->addr, &tmpval, 1); 3441 regs->data = ntohl(tmpval); 3442#if 0 3443 if ((regs->addr == TI_CPU_STATE) 3444 || (regs->addr == TI_CPU_CTL_B)) { 3445 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3446 regs->addr, tmpval); 3447 } 3448#endif 3449 } else { 3450 tmpval = htonl(regs->data); 3451 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3452 regs->addr, &tmpval, 1); 3453 } 3454 3455 break; 3456 } 3457 default: 3458 error = ENOTTY; 3459 break; 3460 } 3461 return (error); 3462} 3463 3464static void 3465ti_watchdog(ifp) 3466 struct ifnet *ifp; 3467{ 3468 struct ti_softc *sc; 3469 3470 sc = ifp->if_softc; 3471 TI_LOCK(sc); 3472 3473 /* 3474 * When we're debugging, the chip is often stopped for long periods 3475 * of time, and that would normally cause the watchdog timer to fire. 3476 * Since that impedes debugging, we don't want to do that. 3477 */ 3478 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3479 TI_UNLOCK(sc); 3480 return; 3481 } 3482 3483 if_printf(ifp, "watchdog timeout -- resetting\n"); 3484 ti_stop(sc); 3485 ti_init(sc); 3486 3487 ifp->if_oerrors++; 3488 TI_UNLOCK(sc); 3489} 3490 3491/* 3492 * Stop the adapter and free any mbufs allocated to the 3493 * RX and TX lists. 3494 */ 3495static void 3496ti_stop(sc) 3497 struct ti_softc *sc; 3498{ 3499 struct ifnet *ifp; 3500 struct ti_cmd_desc cmd; 3501 3502 TI_LOCK(sc); 3503 3504 ifp = sc->ti_ifp; 3505 3506 /* Disable host interrupts. */ 3507 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3508 /* 3509 * Tell firmware we're shutting down. 3510 */ 3511 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3512 3513 /* Halt and reinitialize. */ 3514 ti_chipinit(sc); 3515 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3516 ti_chipinit(sc); 3517 3518 /* Free the RX lists. */ 3519 ti_free_rx_ring_std(sc); 3520 3521 /* Free jumbo RX list. */ 3522 ti_free_rx_ring_jumbo(sc); 3523 3524 /* Free mini RX list. */ 3525 ti_free_rx_ring_mini(sc); 3526 3527 /* Free TX buffers. */ 3528 ti_free_tx_ring(sc); 3529 3530 sc->ti_ev_prodidx.ti_idx = 0; 3531 sc->ti_return_prodidx.ti_idx = 0; 3532 sc->ti_tx_considx.ti_idx = 0; 3533 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3534 3535 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3536 TI_UNLOCK(sc); 3537} 3538 3539/* 3540 * Stop all chip I/O so that the kernel's probe routines don't 3541 * get confused by errant DMAs when rebooting. 3542 */ 3543static void 3544ti_shutdown(dev) 3545 device_t dev; 3546{ 3547 struct ti_softc *sc; 3548 3549 sc = device_get_softc(dev); 3550 TI_LOCK(sc); 3551 ti_chipinit(sc); 3552 TI_UNLOCK(sc); 3553} 3554