if_ti.c revision 126076
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 126076 2004-02-21 19:42:58Z phk $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/socket.h> 91#include <sys/queue.h> 92#include <sys/conf.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_types.h> 100#include <net/if_vlan_var.h> 101 102#include <net/bpf.h> 103 104#include <netinet/in_systm.h> 105#include <netinet/in.h> 106#include <netinet/ip.h> 107 108#include <vm/vm.h> /* for vtophys */ 109#include <vm/pmap.h> /* for vtophys */ 110#include <machine/bus_memio.h> 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116/* #define TI_PRIVATE_JUMBOS */ 117 118#if !defined(TI_PRIVATE_JUMBOS) 119#include <sys/sockio.h> 120#include <sys/uio.h> 121#include <sys/lock.h> 122#include <vm/vm_extern.h> 123#include <vm/pmap.h> 124#include <vm/vm_map.h> 125#include <vm/vm_map.h> 126#include <vm/vm_param.h> 127#include <vm/vm_pageout.h> 128#include <sys/vmmeter.h> 129#include <vm/vm_page.h> 130#include <vm/vm_object.h> 131#include <vm/vm_kern.h> 132#include <sys/proc.h> 133#include <sys/jumbo.h> 134#endif /* !TI_PRIVATE_JUMBOS */ 135 136#include <dev/pci/pcireg.h> 137#include <dev/pci/pcivar.h> 138 139#include <sys/tiio.h> 140#include <pci/if_tireg.h> 141#include <pci/ti_fw.h> 142#include <pci/ti_fw2.h> 143 144#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145/* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153struct ti_softc *tis[8]; 154 155typedef enum { 156 TI_SWAP_HTON, 157 TI_SWAP_NTOH 158} ti_swap_type; 159 160 161/* 162 * Various supported device vendors/types and their names. 163 */ 164 165static struct ti_type ti_devs[] = { 166 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 167 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 168 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 169 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 170 { TC_VENDORID, TC_DEVICEID_3C985, 171 "3Com 3c985-SX Gigabit Ethernet" }, 172 { NG_VENDORID, NG_DEVICEID_GA620, 173 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 174 { NG_VENDORID, NG_DEVICEID_GA620T, 175 "Netgear GA620 1000baseT Gigabit Ethernet" }, 176 { SGI_VENDORID, SGI_DEVICEID_TIGON, 177 "Silicon Graphics Gigabit Ethernet" }, 178 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 179 "Farallon PN9000SX Gigabit Ethernet" }, 180 { 0, 0, NULL } 181}; 182 183 184static d_open_t ti_open; 185static d_close_t ti_close; 186static d_ioctl_t ti_ioctl2; 187 188static struct cdevsw ti_cdevsw = { 189 .d_open = ti_open, 190 .d_close = ti_close, 191 .d_ioctl = ti_ioctl2, 192 .d_name = "ti", 193}; 194 195static int ti_probe (device_t); 196static int ti_attach (device_t); 197static int ti_detach (device_t); 198static void ti_txeof (struct ti_softc *); 199static void ti_rxeof (struct ti_softc *); 200 201static void ti_stats_update (struct ti_softc *); 202static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 203 204static void ti_intr (void *); 205static void ti_start (struct ifnet *); 206static int ti_ioctl (struct ifnet *, u_long, caddr_t); 207static void ti_init (void *); 208static void ti_init2 (struct ti_softc *); 209static void ti_stop (struct ti_softc *); 210static void ti_watchdog (struct ifnet *); 211static void ti_shutdown (device_t); 212static int ti_ifmedia_upd (struct ifnet *); 213static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 214 215static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 216static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 217static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 218 219static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 220static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 221static void ti_setmulti (struct ti_softc *); 222 223static void ti_mem (struct ti_softc *, u_int32_t, 224 u_int32_t, caddr_t); 225static int ti_copy_mem (struct ti_softc *, u_int32_t, 226 u_int32_t, caddr_t, int, int); 227static int ti_copy_scratch (struct ti_softc *, u_int32_t, 228 u_int32_t, caddr_t, int, int, int); 229static int ti_bcopy_swap (const void *, void *, size_t, 230 ti_swap_type); 231static void ti_loadfw (struct ti_softc *); 232static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 233static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 234 caddr_t, int); 235static void ti_handle_events (struct ti_softc *); 236#ifdef TI_PRIVATE_JUMBOS 237static int ti_alloc_jumbo_mem (struct ti_softc *); 238static void *ti_jalloc (struct ti_softc *); 239static void ti_jfree (void *, void *); 240#endif /* TI_PRIVATE_JUMBOS */ 241static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 242static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 243static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 244static int ti_init_rx_ring_std (struct ti_softc *); 245static void ti_free_rx_ring_std (struct ti_softc *); 246static int ti_init_rx_ring_jumbo (struct ti_softc *); 247static void ti_free_rx_ring_jumbo (struct ti_softc *); 248static int ti_init_rx_ring_mini (struct ti_softc *); 249static void ti_free_rx_ring_mini (struct ti_softc *); 250static void ti_free_tx_ring (struct ti_softc *); 251static int ti_init_tx_ring (struct ti_softc *); 252 253static int ti_64bitslot_war (struct ti_softc *); 254static int ti_chipinit (struct ti_softc *); 255static int ti_gibinit (struct ti_softc *); 256 257#ifdef TI_JUMBO_HDRSPLIT 258static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 259 int pkt_len, int idx); 260#endif /* TI_JUMBO_HDRSPLIT */ 261 262static device_method_t ti_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, ti_probe), 265 DEVMETHOD(device_attach, ti_attach), 266 DEVMETHOD(device_detach, ti_detach), 267 DEVMETHOD(device_shutdown, ti_shutdown), 268 { 0, 0 } 269}; 270 271static driver_t ti_driver = { 272 "ti", 273 ti_methods, 274 sizeof(struct ti_softc) 275}; 276 277static devclass_t ti_devclass; 278 279DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 280MODULE_DEPEND(ti, pci, 1, 1, 1); 281MODULE_DEPEND(ti, ether, 1, 1, 1); 282 283/* 284 * Send an instruction or address to the EEPROM, check for ACK. 285 */ 286static u_int32_t ti_eeprom_putbyte(sc, byte) 287 struct ti_softc *sc; 288 int byte; 289{ 290 register int i, ack = 0; 291 292 /* 293 * Make sure we're in TX mode. 294 */ 295 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 296 297 /* 298 * Feed in each bit and stobe the clock. 299 */ 300 for (i = 0x80; i; i >>= 1) { 301 if (byte & i) { 302 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 303 } else { 304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 305 } 306 DELAY(1); 307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 DELAY(1); 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 } 311 312 /* 313 * Turn off TX mode. 314 */ 315 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 316 317 /* 318 * Check for ack. 319 */ 320 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 321 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 322 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 324 return(ack); 325} 326 327/* 328 * Read a byte of data stored in the EEPROM at address 'addr.' 329 * We have to send two address bytes since the EEPROM can hold 330 * more than 256 bytes of data. 331 */ 332static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 333 struct ti_softc *sc; 334 int addr; 335 u_int8_t *dest; 336{ 337 register int i; 338 u_int8_t byte = 0; 339 340 EEPROM_START; 341 342 /* 343 * Send write control code to EEPROM. 344 */ 345 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 346 printf("ti%d: failed to send write command, status: %x\n", 347 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 348 return(1); 349 } 350 351 /* 352 * Send first byte of address of byte we want to read. 353 */ 354 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 355 printf("ti%d: failed to send address, status: %x\n", 356 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 357 return(1); 358 } 359 /* 360 * Send second byte address of byte we want to read. 361 */ 362 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 363 printf("ti%d: failed to send address, status: %x\n", 364 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 365 return(1); 366 } 367 368 EEPROM_STOP; 369 EEPROM_START; 370 /* 371 * Send read control code to EEPROM. 372 */ 373 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 374 printf("ti%d: failed to send read command, status: %x\n", 375 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 376 return(1); 377 } 378 379 /* 380 * Start reading bits from EEPROM. 381 */ 382 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 383 for (i = 0x80; i; i >>= 1) { 384 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 385 DELAY(1); 386 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 387 byte |= i; 388 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 389 DELAY(1); 390 } 391 392 EEPROM_STOP; 393 394 /* 395 * No ACK generated for read, so just return byte. 396 */ 397 398 *dest = byte; 399 400 return(0); 401} 402 403/* 404 * Read a sequence of bytes from the EEPROM. 405 */ 406static int 407ti_read_eeprom(sc, dest, off, cnt) 408 struct ti_softc *sc; 409 caddr_t dest; 410 int off; 411 int cnt; 412{ 413 int err = 0, i; 414 u_int8_t byte = 0; 415 416 for (i = 0; i < cnt; i++) { 417 err = ti_eeprom_getbyte(sc, off + i, &byte); 418 if (err) 419 break; 420 *(dest + i) = byte; 421 } 422 423 return(err ? 1 : 0); 424} 425 426/* 427 * NIC memory access function. Can be used to either clear a section 428 * of NIC local memory or (if buf is non-NULL) copy data into it. 429 */ 430static void 431ti_mem(sc, addr, len, buf) 432 struct ti_softc *sc; 433 u_int32_t addr, len; 434 caddr_t buf; 435{ 436 int segptr, segsize, cnt; 437 caddr_t ti_winbase, ptr; 438 439 segptr = addr; 440 cnt = len; 441 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 442 ptr = buf; 443 444 while(cnt) { 445 if (cnt < TI_WINLEN) 446 segsize = cnt; 447 else 448 segsize = TI_WINLEN - (segptr % TI_WINLEN); 449 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 450 if (buf == NULL) 451 bzero((char *)ti_winbase + (segptr & 452 (TI_WINLEN - 1)), segsize); 453 else { 454 bcopy((char *)ptr, (char *)ti_winbase + 455 (segptr & (TI_WINLEN - 1)), segsize); 456 ptr += segsize; 457 } 458 segptr += segsize; 459 cnt -= segsize; 460 } 461 462 return; 463} 464 465static int 466ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 467 struct ti_softc *sc; 468 u_int32_t tigon_addr, len; 469 caddr_t buf; 470 int useraddr, readdata; 471{ 472 int segptr, segsize, cnt; 473 caddr_t ptr; 474 u_int32_t origwin; 475 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 476 int resid, segresid; 477 int first_pass; 478 479 /* 480 * At the moment, we don't handle non-aligned cases, we just bail. 481 * If this proves to be a problem, it will be fixed. 482 */ 483 if ((readdata == 0) 484 && (tigon_addr & 0x3)) { 485 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 486 "word-aligned\n", sc->ti_unit, tigon_addr); 487 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 488 "supported\n", sc->ti_unit); 489 return(EINVAL); 490 } 491 492 segptr = tigon_addr & ~0x3; 493 segresid = tigon_addr - segptr; 494 495 /* 496 * This is the non-aligned amount left over that we'll need to 497 * copy. 498 */ 499 resid = len & 0x3; 500 501 /* Add in the left over amount at the front of the buffer */ 502 resid += segresid; 503 504 cnt = len & ~0x3; 505 /* 506 * If resid + segresid is >= 4, add multiples of 4 to the count and 507 * decrease the residual by that much. 508 */ 509 cnt += resid & ~0x3; 510 resid -= resid & ~0x3; 511 512 ptr = buf; 513 514 first_pass = 1; 515 516 /* 517 * Make sure we aren't interrupted while we're changing the window 518 * pointer. 519 */ 520 TI_LOCK(sc); 521 522 /* 523 * Save the old window base value. 524 */ 525 origwin = CSR_READ_4(sc, TI_WINBASE); 526 527 while(cnt) { 528 bus_size_t ti_offset; 529 530 if (cnt < TI_WINLEN) 531 segsize = cnt; 532 else 533 segsize = TI_WINLEN - (segptr % TI_WINLEN); 534 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 535 536 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 537 538 if (readdata) { 539 540 bus_space_read_region_4(sc->ti_btag, 541 sc->ti_bhandle, ti_offset, 542 (u_int32_t *)tmparray, 543 segsize >> 2); 544 if (useraddr) { 545 /* 546 * Yeah, this is a little on the kludgy 547 * side, but at least this code is only 548 * used for debugging. 549 */ 550 ti_bcopy_swap(tmparray, tmparray2, segsize, 551 TI_SWAP_NTOH); 552 553 if (first_pass) { 554 copyout(&tmparray2[segresid], ptr, 555 segsize - segresid); 556 first_pass = 0; 557 } else 558 copyout(tmparray2, ptr, segsize); 559 } else { 560 if (first_pass) { 561 562 ti_bcopy_swap(tmparray, tmparray2, 563 segsize, TI_SWAP_NTOH); 564 bcopy(&tmparray2[segresid], ptr, 565 segsize - segresid); 566 first_pass = 0; 567 } else 568 ti_bcopy_swap(tmparray, ptr, segsize, 569 TI_SWAP_NTOH); 570 } 571 572 } else { 573 if (useraddr) { 574 copyin(ptr, tmparray2, segsize); 575 ti_bcopy_swap(tmparray2, tmparray, segsize, 576 TI_SWAP_HTON); 577 } else 578 ti_bcopy_swap(ptr, tmparray, segsize, 579 TI_SWAP_HTON); 580 581 bus_space_write_region_4(sc->ti_btag, 582 sc->ti_bhandle, ti_offset, 583 (u_int32_t *)tmparray, 584 segsize >> 2); 585 } 586 segptr += segsize; 587 ptr += segsize; 588 cnt -= segsize; 589 } 590 591 /* 592 * Handle leftover, non-word-aligned bytes. 593 */ 594 if (resid != 0) { 595 u_int32_t tmpval, tmpval2; 596 bus_size_t ti_offset; 597 598 /* 599 * Set the segment pointer. 600 */ 601 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 602 603 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 604 605 /* 606 * First, grab whatever is in our source/destination. 607 * We'll obviously need this for reads, but also for 608 * writes, since we'll be doing read/modify/write. 609 */ 610 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 611 ti_offset, &tmpval, 1); 612 613 /* 614 * Next, translate this from little-endian to big-endian 615 * (at least on i386 boxes). 616 */ 617 tmpval2 = ntohl(tmpval); 618 619 if (readdata) { 620 /* 621 * If we're reading, just copy the leftover number 622 * of bytes from the host byte order buffer to 623 * the user's buffer. 624 */ 625 if (useraddr) 626 copyout(&tmpval2, ptr, resid); 627 else 628 bcopy(&tmpval2, ptr, resid); 629 } else { 630 /* 631 * If we're writing, first copy the bytes to be 632 * written into the network byte order buffer, 633 * leaving the rest of the buffer with whatever was 634 * originally in there. Then, swap the bytes 635 * around into host order and write them out. 636 * 637 * XXX KDM the read side of this has been verified 638 * to work, but the write side of it has not been 639 * verified. So user beware. 640 */ 641 if (useraddr) 642 copyin(ptr, &tmpval2, resid); 643 else 644 bcopy(ptr, &tmpval2, resid); 645 646 tmpval = htonl(tmpval2); 647 648 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 649 ti_offset, &tmpval, 1); 650 } 651 } 652 653 CSR_WRITE_4(sc, TI_WINBASE, origwin); 654 655 TI_UNLOCK(sc); 656 657 return(0); 658} 659 660static int 661ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 662 struct ti_softc *sc; 663 u_int32_t tigon_addr, len; 664 caddr_t buf; 665 int useraddr, readdata; 666 int cpu; 667{ 668 u_int32_t segptr; 669 int cnt; 670 u_int32_t tmpval, tmpval2; 671 caddr_t ptr; 672 673 /* 674 * At the moment, we don't handle non-aligned cases, we just bail. 675 * If this proves to be a problem, it will be fixed. 676 */ 677 if (tigon_addr & 0x3) { 678 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 679 "word-aligned\n", sc->ti_unit, tigon_addr); 680 return(EINVAL); 681 } 682 683 if (len & 0x3) { 684 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 685 "word-aligned\n", sc->ti_unit, len); 686 return(EINVAL); 687 } 688 689 segptr = tigon_addr; 690 cnt = len; 691 ptr = buf; 692 693 TI_LOCK(sc); 694 695 while (cnt) { 696 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 697 698 if (readdata) { 699 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 700 701 tmpval = ntohl(tmpval2); 702 703 /* 704 * Note: I've used this debugging interface 705 * extensively with Alteon's 12.3.15 firmware, 706 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 707 * 708 * When you compile the firmware without 709 * optimization, which is necessary sometimes in 710 * order to properly step through it, you sometimes 711 * read out a bogus value of 0xc0017c instead of 712 * whatever was supposed to be in that scratchpad 713 * location. That value is on the stack somewhere, 714 * but I've never been able to figure out what was 715 * causing the problem. 716 * 717 * The address seems to pop up in random places, 718 * often not in the same place on two subsequent 719 * reads. 720 * 721 * In any case, the underlying data doesn't seem 722 * to be affected, just the value read out. 723 * 724 * KDM, 3/7/2000 725 */ 726 727 if (tmpval2 == 0xc0017c) 728 printf("ti%d: found 0xc0017c at %#x " 729 "(tmpval2)\n", sc->ti_unit, segptr); 730 731 if (tmpval == 0xc0017c) 732 printf("ti%d: found 0xc0017c at %#x " 733 "(tmpval)\n", sc->ti_unit, segptr); 734 735 if (useraddr) 736 copyout(&tmpval, ptr, 4); 737 else 738 bcopy(&tmpval, ptr, 4); 739 } else { 740 if (useraddr) 741 copyin(ptr, &tmpval2, 4); 742 else 743 bcopy(ptr, &tmpval2, 4); 744 745 tmpval = htonl(tmpval2); 746 747 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 748 } 749 750 cnt -= 4; 751 segptr += 4; 752 ptr += 4; 753 } 754 755 TI_UNLOCK(sc); 756 757 return(0); 758} 759 760static int 761ti_bcopy_swap(src, dst, len, swap_type) 762 const void *src; 763 void *dst; 764 size_t len; 765 ti_swap_type swap_type; 766{ 767 const u_int8_t *tmpsrc; 768 u_int8_t *tmpdst; 769 size_t tmplen; 770 771 if (len & 0x3) { 772 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 773 len); 774 return(-1); 775 } 776 777 tmpsrc = src; 778 tmpdst = dst; 779 tmplen = len; 780 781 while (tmplen) { 782 if (swap_type == TI_SWAP_NTOH) 783 *(u_int32_t *)tmpdst = 784 ntohl(*(const u_int32_t *)tmpsrc); 785 else 786 *(u_int32_t *)tmpdst = 787 htonl(*(const u_int32_t *)tmpsrc); 788 789 tmpsrc += 4; 790 tmpdst += 4; 791 tmplen -= 4; 792 } 793 794 return(0); 795} 796 797/* 798 * Load firmware image into the NIC. Check that the firmware revision 799 * is acceptable and see if we want the firmware for the Tigon 1 or 800 * Tigon 2. 801 */ 802static void 803ti_loadfw(sc) 804 struct ti_softc *sc; 805{ 806 switch(sc->ti_hwrev) { 807 case TI_HWREV_TIGON: 808 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 809 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 810 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 811 printf("ti%d: firmware revision mismatch; want " 812 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 813 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 814 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 815 tigonFwReleaseMinor, tigonFwReleaseFix); 816 return; 817 } 818 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 819 (caddr_t)tigonFwText); 820 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 821 (caddr_t)tigonFwData); 822 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 823 (caddr_t)tigonFwRodata); 824 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 825 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 826 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 827 break; 828 case TI_HWREV_TIGON_II: 829 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 830 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 831 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 832 printf("ti%d: firmware revision mismatch; want " 833 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 834 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 835 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 836 tigon2FwReleaseMinor, tigon2FwReleaseFix); 837 return; 838 } 839 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 840 (caddr_t)tigon2FwText); 841 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 842 (caddr_t)tigon2FwData); 843 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 844 (caddr_t)tigon2FwRodata); 845 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 846 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 847 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 848 break; 849 default: 850 printf("ti%d: can't load firmware: unknown hardware rev\n", 851 sc->ti_unit); 852 break; 853 } 854 855 return; 856} 857 858/* 859 * Send the NIC a command via the command ring. 860 */ 861static void 862ti_cmd(sc, cmd) 863 struct ti_softc *sc; 864 struct ti_cmd_desc *cmd; 865{ 866 u_int32_t index; 867 868 if (sc->ti_rdata->ti_cmd_ring == NULL) 869 return; 870 871 index = sc->ti_cmd_saved_prodidx; 872 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 873 TI_INC(index, TI_CMD_RING_CNT); 874 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 875 sc->ti_cmd_saved_prodidx = index; 876 877 return; 878} 879 880/* 881 * Send the NIC an extended command. The 'len' parameter specifies the 882 * number of command slots to include after the initial command. 883 */ 884static void 885ti_cmd_ext(sc, cmd, arg, len) 886 struct ti_softc *sc; 887 struct ti_cmd_desc *cmd; 888 caddr_t arg; 889 int len; 890{ 891 u_int32_t index; 892 register int i; 893 894 if (sc->ti_rdata->ti_cmd_ring == NULL) 895 return; 896 897 index = sc->ti_cmd_saved_prodidx; 898 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 899 TI_INC(index, TI_CMD_RING_CNT); 900 for (i = 0; i < len; i++) { 901 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 902 *(u_int32_t *)(&arg[i * 4])); 903 TI_INC(index, TI_CMD_RING_CNT); 904 } 905 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 906 sc->ti_cmd_saved_prodidx = index; 907 908 return; 909} 910 911/* 912 * Handle events that have triggered interrupts. 913 */ 914static void 915ti_handle_events(sc) 916 struct ti_softc *sc; 917{ 918 struct ti_event_desc *e; 919 920 if (sc->ti_rdata->ti_event_ring == NULL) 921 return; 922 923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 924 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 925 switch(e->ti_event) { 926 case TI_EV_LINKSTAT_CHANGED: 927 sc->ti_linkstat = e->ti_code; 928 if (e->ti_code == TI_EV_CODE_LINK_UP) 929 printf("ti%d: 10/100 link up\n", sc->ti_unit); 930 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 931 printf("ti%d: gigabit link up\n", sc->ti_unit); 932 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 933 printf("ti%d: link down\n", sc->ti_unit); 934 break; 935 case TI_EV_ERROR: 936 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 937 printf("ti%d: invalid command\n", sc->ti_unit); 938 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 939 printf("ti%d: unknown command\n", sc->ti_unit); 940 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 941 printf("ti%d: bad config data\n", sc->ti_unit); 942 break; 943 case TI_EV_FIRMWARE_UP: 944 ti_init2(sc); 945 break; 946 case TI_EV_STATS_UPDATED: 947 ti_stats_update(sc); 948 break; 949 case TI_EV_RESET_JUMBO_RING: 950 case TI_EV_MCAST_UPDATED: 951 /* Who cares. */ 952 break; 953 default: 954 printf("ti%d: unknown event: %d\n", 955 sc->ti_unit, e->ti_event); 956 break; 957 } 958 /* Advance the consumer index. */ 959 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 960 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 961 } 962 963 return; 964} 965 966#ifdef TI_PRIVATE_JUMBOS 967 968/* 969 * Memory management for the jumbo receive ring is a pain in the 970 * butt. We need to allocate at least 9018 bytes of space per frame, 971 * _and_ it has to be contiguous (unless you use the extended 972 * jumbo descriptor format). Using malloc() all the time won't 973 * work: malloc() allocates memory in powers of two, which means we 974 * would end up wasting a considerable amount of space by allocating 975 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 976 * to do our own memory management. 977 * 978 * The driver needs to allocate a contiguous chunk of memory at boot 979 * time. We then chop this up ourselves into 9K pieces and use them 980 * as external mbuf storage. 981 * 982 * One issue here is how much memory to allocate. The jumbo ring has 983 * 256 slots in it, but at 9K per slot than can consume over 2MB of 984 * RAM. This is a bit much, especially considering we also need 985 * RAM for the standard ring and mini ring (on the Tigon 2). To 986 * save space, we only actually allocate enough memory for 64 slots 987 * by default, which works out to between 500 and 600K. This can 988 * be tuned by changing a #define in if_tireg.h. 989 */ 990 991static int 992ti_alloc_jumbo_mem(sc) 993 struct ti_softc *sc; 994{ 995 caddr_t ptr; 996 register int i; 997 struct ti_jpool_entry *entry; 998 999 /* Grab a big chunk o' storage. */ 1000 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1001 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1002 1003 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1004 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1005 return(ENOBUFS); 1006 } 1007 1008 SLIST_INIT(&sc->ti_jfree_listhead); 1009 SLIST_INIT(&sc->ti_jinuse_listhead); 1010 1011 /* 1012 * Now divide it up into 9K pieces and save the addresses 1013 * in an array. 1014 */ 1015 ptr = sc->ti_cdata.ti_jumbo_buf; 1016 for (i = 0; i < TI_JSLOTS; i++) { 1017 sc->ti_cdata.ti_jslots[i] = ptr; 1018 ptr += TI_JLEN; 1019 entry = malloc(sizeof(struct ti_jpool_entry), 1020 M_DEVBUF, M_NOWAIT); 1021 if (entry == NULL) { 1022 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1023 M_DEVBUF); 1024 sc->ti_cdata.ti_jumbo_buf = NULL; 1025 printf("ti%d: no memory for jumbo " 1026 "buffer queue!\n", sc->ti_unit); 1027 return(ENOBUFS); 1028 } 1029 entry->slot = i; 1030 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1031 } 1032 1033 return(0); 1034} 1035 1036/* 1037 * Allocate a jumbo buffer. 1038 */ 1039static void *ti_jalloc(sc) 1040 struct ti_softc *sc; 1041{ 1042 struct ti_jpool_entry *entry; 1043 1044 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1045 1046 if (entry == NULL) { 1047 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1048 return(NULL); 1049 } 1050 1051 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1052 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1053 return(sc->ti_cdata.ti_jslots[entry->slot]); 1054} 1055 1056/* 1057 * Release a jumbo buffer. 1058 */ 1059static void 1060ti_jfree(buf, args) 1061 void *buf; 1062 void *args; 1063{ 1064 struct ti_softc *sc; 1065 int i; 1066 struct ti_jpool_entry *entry; 1067 1068 /* Extract the softc struct pointer. */ 1069 sc = (struct ti_softc *)args; 1070 1071 if (sc == NULL) 1072 panic("ti_jfree: didn't get softc pointer!"); 1073 1074 /* calculate the slot this buffer belongs to */ 1075 i = ((vm_offset_t)buf 1076 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1077 1078 if ((i < 0) || (i >= TI_JSLOTS)) 1079 panic("ti_jfree: asked to free buffer that we don't manage!"); 1080 1081 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1082 if (entry == NULL) 1083 panic("ti_jfree: buffer not in use!"); 1084 entry->slot = i; 1085 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1086 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1087 1088 return; 1089} 1090 1091#endif /* TI_PRIVATE_JUMBOS */ 1092 1093/* 1094 * Intialize a standard receive ring descriptor. 1095 */ 1096static int 1097ti_newbuf_std(sc, i, m) 1098 struct ti_softc *sc; 1099 int i; 1100 struct mbuf *m; 1101{ 1102 struct mbuf *m_new = NULL; 1103 struct ti_rx_desc *r; 1104 1105 if (m == NULL) { 1106 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1107 if (m_new == NULL) 1108 return(ENOBUFS); 1109 1110 MCLGET(m_new, M_DONTWAIT); 1111 if (!(m_new->m_flags & M_EXT)) { 1112 m_freem(m_new); 1113 return(ENOBUFS); 1114 } 1115 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1116 } else { 1117 m_new = m; 1118 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1119 m_new->m_data = m_new->m_ext.ext_buf; 1120 } 1121 1122 m_adj(m_new, ETHER_ALIGN); 1123 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1124 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1125 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1126 r->ti_type = TI_BDTYPE_RECV_BD; 1127 r->ti_flags = 0; 1128 if (sc->arpcom.ac_if.if_hwassist) 1129 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1130 r->ti_len = m_new->m_len; 1131 r->ti_idx = i; 1132 1133 return(0); 1134} 1135 1136/* 1137 * Intialize a mini receive ring descriptor. This only applies to 1138 * the Tigon 2. 1139 */ 1140static int 1141ti_newbuf_mini(sc, i, m) 1142 struct ti_softc *sc; 1143 int i; 1144 struct mbuf *m; 1145{ 1146 struct mbuf *m_new = NULL; 1147 struct ti_rx_desc *r; 1148 1149 if (m == NULL) { 1150 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1151 if (m_new == NULL) { 1152 return(ENOBUFS); 1153 } 1154 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1155 } else { 1156 m_new = m; 1157 m_new->m_data = m_new->m_pktdat; 1158 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1159 } 1160 1161 m_adj(m_new, ETHER_ALIGN); 1162 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1163 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1164 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1165 r->ti_type = TI_BDTYPE_RECV_BD; 1166 r->ti_flags = TI_BDFLAG_MINI_RING; 1167 if (sc->arpcom.ac_if.if_hwassist) 1168 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1169 r->ti_len = m_new->m_len; 1170 r->ti_idx = i; 1171 1172 return(0); 1173} 1174 1175#ifdef TI_PRIVATE_JUMBOS 1176 1177/* 1178 * Initialize a jumbo receive ring descriptor. This allocates 1179 * a jumbo buffer from the pool managed internally by the driver. 1180 */ 1181static int 1182ti_newbuf_jumbo(sc, i, m) 1183 struct ti_softc *sc; 1184 int i; 1185 struct mbuf *m; 1186{ 1187 struct mbuf *m_new = NULL; 1188 struct ti_rx_desc *r; 1189 1190 if (m == NULL) { 1191 caddr_t *buf = NULL; 1192 1193 /* Allocate the mbuf. */ 1194 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1195 if (m_new == NULL) { 1196 return(ENOBUFS); 1197 } 1198 1199 /* Allocate the jumbo buffer */ 1200 buf = ti_jalloc(sc); 1201 if (buf == NULL) { 1202 m_freem(m_new); 1203 printf("ti%d: jumbo allocation failed " 1204 "-- packet dropped!\n", sc->ti_unit); 1205 return(ENOBUFS); 1206 } 1207 1208 /* Attach the buffer to the mbuf. */ 1209 m_new->m_data = (void *) buf; 1210 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1211 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1212 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1213 } else { 1214 m_new = m; 1215 m_new->m_data = m_new->m_ext.ext_buf; 1216 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1217 } 1218 1219 m_adj(m_new, ETHER_ALIGN); 1220 /* Set up the descriptor. */ 1221 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1222 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1223 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1224 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1225 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1226 if (sc->arpcom.ac_if.if_hwassist) 1227 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1228 r->ti_len = m_new->m_len; 1229 r->ti_idx = i; 1230 1231 return(0); 1232} 1233 1234#else 1235#include <vm/vm_page.h> 1236 1237#if (PAGE_SIZE == 4096) 1238#define NPAYLOAD 2 1239#else 1240#define NPAYLOAD 1 1241#endif 1242 1243#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1244#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1245#define NFS_HDR_LEN (UDP_HDR_LEN) 1246static int HDR_LEN = TCP_HDR_LEN; 1247 1248 1249 /* 1250 * Initialize a jumbo receive ring descriptor. This allocates 1251 * a jumbo buffer from the pool managed internally by the driver. 1252 */ 1253static int 1254ti_newbuf_jumbo(sc, idx, m_old) 1255 struct ti_softc *sc; 1256 int idx; 1257 struct mbuf *m_old; 1258{ 1259 struct mbuf *cur, *m_new = NULL; 1260 struct mbuf *m[3] = {NULL, NULL, NULL}; 1261 struct ti_rx_desc_ext *r; 1262 vm_page_t frame; 1263 /* 1 extra buf to make nobufs easy*/ 1264 caddr_t buf[3] = {NULL, NULL, NULL}; 1265 int i; 1266 1267 if (m_old != NULL) { 1268 m_new = m_old; 1269 cur = m_old->m_next; 1270 for (i = 0; i <= NPAYLOAD; i++){ 1271 m[i] = cur; 1272 cur = cur->m_next; 1273 } 1274 } else { 1275 /* Allocate the mbufs. */ 1276 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1277 if (m_new == NULL) { 1278 printf("ti%d: mbuf allocation failed " 1279 "-- packet dropped!\n", sc->ti_unit); 1280 goto nobufs; 1281 } 1282 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1283 if (m[NPAYLOAD] == NULL) { 1284 printf("ti%d: cluster mbuf allocation failed " 1285 "-- packet dropped!\n", sc->ti_unit); 1286 goto nobufs; 1287 } 1288 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1289 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1290 printf("ti%d: mbuf allocation failed " 1291 "-- packet dropped!\n", sc->ti_unit); 1292 goto nobufs; 1293 } 1294 m[NPAYLOAD]->m_len = MCLBYTES; 1295 1296 for (i = 0; i < NPAYLOAD; i++){ 1297 MGET(m[i], M_DONTWAIT, MT_DATA); 1298 if (m[i] == NULL) { 1299 printf("ti%d: mbuf allocation failed " 1300 "-- packet dropped!\n", sc->ti_unit); 1301 goto nobufs; 1302 } 1303 if (!(frame = jumbo_pg_alloc())){ 1304 printf("ti%d: buffer allocation failed " 1305 "-- packet dropped!\n", sc->ti_unit); 1306 printf(" index %d page %d\n", idx, i); 1307 goto nobufs; 1308 } 1309 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1310 } 1311 for (i = 0; i < NPAYLOAD; i++){ 1312 /* Attach the buffer to the mbuf. */ 1313 m[i]->m_data = (void *)buf[i]; 1314 m[i]->m_len = PAGE_SIZE; 1315 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1316 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1317 m[i]->m_next = m[i+1]; 1318 } 1319 /* link the buffers to the header */ 1320 m_new->m_next = m[0]; 1321 m_new->m_data += ETHER_ALIGN; 1322 if (sc->ti_hdrsplit) 1323 m_new->m_len = MHLEN - ETHER_ALIGN; 1324 else 1325 m_new->m_len = HDR_LEN; 1326 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1327 } 1328 1329 /* Set up the descriptor. */ 1330 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1331 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1332 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1333 r->ti_len0 = m_new->m_len; 1334 1335 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1336 r->ti_len1 = PAGE_SIZE; 1337 1338 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1339 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1340 1341 if (PAGE_SIZE == 4096) { 1342 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1343 r->ti_len3 = MCLBYTES; 1344 } else { 1345 r->ti_len3 = 0; 1346 } 1347 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1348 1349 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1350 1351 if (sc->arpcom.ac_if.if_hwassist) 1352 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1353 1354 r->ti_idx = idx; 1355 1356 return(0); 1357 1358 nobufs: 1359 1360 /* 1361 * Warning! : 1362 * This can only be called before the mbufs are strung together. 1363 * If the mbufs are strung together, m_freem() will free the chain, 1364 * so that the later mbufs will be freed multiple times. 1365 */ 1366 if (m_new) 1367 m_freem(m_new); 1368 1369 for(i = 0; i < 3; i++){ 1370 if (m[i]) 1371 m_freem(m[i]); 1372 if (buf[i]) 1373 jumbo_pg_free((vm_offset_t)buf[i]); 1374 } 1375 return ENOBUFS; 1376} 1377#endif 1378 1379 1380 1381/* 1382 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1383 * that's 1MB or memory, which is a lot. For now, we fill only the first 1384 * 256 ring entries and hope that our CPU is fast enough to keep up with 1385 * the NIC. 1386 */ 1387static int 1388ti_init_rx_ring_std(sc) 1389 struct ti_softc *sc; 1390{ 1391 register int i; 1392 struct ti_cmd_desc cmd; 1393 1394 for (i = 0; i < TI_SSLOTS; i++) { 1395 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1396 return(ENOBUFS); 1397 }; 1398 1399 TI_UPDATE_STDPROD(sc, i - 1); 1400 sc->ti_std = i - 1; 1401 1402 return(0); 1403} 1404 1405static void 1406ti_free_rx_ring_std(sc) 1407 struct ti_softc *sc; 1408{ 1409 register int i; 1410 1411 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1412 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1413 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1414 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1415 } 1416 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1417 sizeof(struct ti_rx_desc)); 1418 } 1419 1420 return; 1421} 1422 1423static int 1424ti_init_rx_ring_jumbo(sc) 1425 struct ti_softc *sc; 1426{ 1427 register int i; 1428 struct ti_cmd_desc cmd; 1429 1430 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1431 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1432 return(ENOBUFS); 1433 }; 1434 1435 TI_UPDATE_JUMBOPROD(sc, i - 1); 1436 sc->ti_jumbo = i - 1; 1437 1438 return(0); 1439} 1440 1441static void 1442ti_free_rx_ring_jumbo(sc) 1443 struct ti_softc *sc; 1444{ 1445 register int i; 1446 1447 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1448 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1449 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1450 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1451 } 1452 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1453 sizeof(struct ti_rx_desc)); 1454 } 1455 1456 return; 1457} 1458 1459static int 1460ti_init_rx_ring_mini(sc) 1461 struct ti_softc *sc; 1462{ 1463 register int i; 1464 1465 for (i = 0; i < TI_MSLOTS; i++) { 1466 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1467 return(ENOBUFS); 1468 }; 1469 1470 TI_UPDATE_MINIPROD(sc, i - 1); 1471 sc->ti_mini = i - 1; 1472 1473 return(0); 1474} 1475 1476static void 1477ti_free_rx_ring_mini(sc) 1478 struct ti_softc *sc; 1479{ 1480 register int i; 1481 1482 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1483 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1484 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1485 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1486 } 1487 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1488 sizeof(struct ti_rx_desc)); 1489 } 1490 1491 return; 1492} 1493 1494static void 1495ti_free_tx_ring(sc) 1496 struct ti_softc *sc; 1497{ 1498 register int i; 1499 1500 if (sc->ti_rdata->ti_tx_ring == NULL) 1501 return; 1502 1503 for (i = 0; i < TI_TX_RING_CNT; i++) { 1504 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1505 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1506 sc->ti_cdata.ti_tx_chain[i] = NULL; 1507 } 1508 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1509 sizeof(struct ti_tx_desc)); 1510 } 1511 1512 return; 1513} 1514 1515static int 1516ti_init_tx_ring(sc) 1517 struct ti_softc *sc; 1518{ 1519 sc->ti_txcnt = 0; 1520 sc->ti_tx_saved_considx = 0; 1521 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1522 return(0); 1523} 1524 1525/* 1526 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1527 * but we have to support the old way too so that Tigon 1 cards will 1528 * work. 1529 */ 1530static void 1531ti_add_mcast(sc, addr) 1532 struct ti_softc *sc; 1533 struct ether_addr *addr; 1534{ 1535 struct ti_cmd_desc cmd; 1536 u_int16_t *m; 1537 u_int32_t ext[2] = {0, 0}; 1538 1539 m = (u_int16_t *)&addr->octet[0]; 1540 1541 switch(sc->ti_hwrev) { 1542 case TI_HWREV_TIGON: 1543 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1544 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1545 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1546 break; 1547 case TI_HWREV_TIGON_II: 1548 ext[0] = htons(m[0]); 1549 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1550 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1551 break; 1552 default: 1553 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1554 break; 1555 } 1556 1557 return; 1558} 1559 1560static void 1561ti_del_mcast(sc, addr) 1562 struct ti_softc *sc; 1563 struct ether_addr *addr; 1564{ 1565 struct ti_cmd_desc cmd; 1566 u_int16_t *m; 1567 u_int32_t ext[2] = {0, 0}; 1568 1569 m = (u_int16_t *)&addr->octet[0]; 1570 1571 switch(sc->ti_hwrev) { 1572 case TI_HWREV_TIGON: 1573 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1574 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1575 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1576 break; 1577 case TI_HWREV_TIGON_II: 1578 ext[0] = htons(m[0]); 1579 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1580 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1581 break; 1582 default: 1583 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1584 break; 1585 } 1586 1587 return; 1588} 1589 1590/* 1591 * Configure the Tigon's multicast address filter. 1592 * 1593 * The actual multicast table management is a bit of a pain, thanks to 1594 * slight brain damage on the part of both Alteon and us. With our 1595 * multicast code, we are only alerted when the multicast address table 1596 * changes and at that point we only have the current list of addresses: 1597 * we only know the current state, not the previous state, so we don't 1598 * actually know what addresses were removed or added. The firmware has 1599 * state, but we can't get our grubby mits on it, and there is no 'delete 1600 * all multicast addresses' command. Hence, we have to maintain our own 1601 * state so we know what addresses have been programmed into the NIC at 1602 * any given time. 1603 */ 1604static void 1605ti_setmulti(sc) 1606 struct ti_softc *sc; 1607{ 1608 struct ifnet *ifp; 1609 struct ifmultiaddr *ifma; 1610 struct ti_cmd_desc cmd; 1611 struct ti_mc_entry *mc; 1612 u_int32_t intrs; 1613 1614 ifp = &sc->arpcom.ac_if; 1615 1616 if (ifp->if_flags & IFF_ALLMULTI) { 1617 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1618 return; 1619 } else { 1620 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1621 } 1622 1623 /* Disable interrupts. */ 1624 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1625 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1626 1627 /* First, zot all the existing filters. */ 1628 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1629 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1630 ti_del_mcast(sc, &mc->mc_addr); 1631 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1632 free(mc, M_DEVBUF); 1633 } 1634 1635 /* Now program new ones. */ 1636 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1637 if (ifma->ifma_addr->sa_family != AF_LINK) 1638 continue; 1639 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1640 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1641 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1642 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1643 ti_add_mcast(sc, &mc->mc_addr); 1644 } 1645 1646 /* Re-enable interrupts. */ 1647 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1648 1649 return; 1650} 1651 1652/* 1653 * Check to see if the BIOS has configured us for a 64 bit slot when 1654 * we aren't actually in one. If we detect this condition, we can work 1655 * around it on the Tigon 2 by setting a bit in the PCI state register, 1656 * but for the Tigon 1 we must give up and abort the interface attach. 1657 */ 1658static int ti_64bitslot_war(sc) 1659 struct ti_softc *sc; 1660{ 1661 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1662 CSR_WRITE_4(sc, 0x600, 0); 1663 CSR_WRITE_4(sc, 0x604, 0); 1664 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1665 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1666 if (sc->ti_hwrev == TI_HWREV_TIGON) 1667 return(EINVAL); 1668 else { 1669 TI_SETBIT(sc, TI_PCI_STATE, 1670 TI_PCISTATE_32BIT_BUS); 1671 return(0); 1672 } 1673 } 1674 } 1675 1676 return(0); 1677} 1678 1679/* 1680 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1681 * self-test results. 1682 */ 1683static int 1684ti_chipinit(sc) 1685 struct ti_softc *sc; 1686{ 1687 u_int32_t cacheline; 1688 u_int32_t pci_writemax = 0; 1689 u_int32_t hdrsplit; 1690 1691 /* Initialize link to down state. */ 1692 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1693 1694 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1695 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1696 else 1697 sc->arpcom.ac_if.if_hwassist = 0; 1698 1699 /* Set endianness before we access any non-PCI registers. */ 1700#if BYTE_ORDER == BIG_ENDIAN 1701 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1702 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1703#else 1704 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1705 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1706#endif 1707 1708 /* Check the ROM failed bit to see if self-tests passed. */ 1709 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1710 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1711 return(ENODEV); 1712 } 1713 1714 /* Halt the CPU. */ 1715 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1716 1717 /* Figure out the hardware revision. */ 1718 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1719 case TI_REV_TIGON_I: 1720 sc->ti_hwrev = TI_HWREV_TIGON; 1721 break; 1722 case TI_REV_TIGON_II: 1723 sc->ti_hwrev = TI_HWREV_TIGON_II; 1724 break; 1725 default: 1726 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1727 return(ENODEV); 1728 } 1729 1730 /* Do special setup for Tigon 2. */ 1731 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1732 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1733 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1734 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1735 } 1736 1737 /* 1738 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1739 * can't do header splitting. 1740 */ 1741#ifdef TI_JUMBO_HDRSPLIT 1742 if (sc->ti_hwrev != TI_HWREV_TIGON) 1743 sc->ti_hdrsplit = 1; 1744 else 1745 printf("ti%d: can't do header splitting on a Tigon I board\n", 1746 sc->ti_unit); 1747#endif /* TI_JUMBO_HDRSPLIT */ 1748 1749 /* Set up the PCI state register. */ 1750 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1751 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1752 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1753 } 1754 1755 /* Clear the read/write max DMA parameters. */ 1756 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1757 TI_PCISTATE_READ_MAXDMA)); 1758 1759 /* Get cache line size. */ 1760 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1761 1762 /* 1763 * If the system has set enabled the PCI memory write 1764 * and invalidate command in the command register, set 1765 * the write max parameter accordingly. This is necessary 1766 * to use MWI with the Tigon 2. 1767 */ 1768 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1769 switch(cacheline) { 1770 case 1: 1771 case 4: 1772 case 8: 1773 case 16: 1774 case 32: 1775 case 64: 1776 break; 1777 default: 1778 /* Disable PCI memory write and invalidate. */ 1779 if (bootverbose) 1780 printf("ti%d: cache line size %d not " 1781 "supported; disabling PCI MWI\n", 1782 sc->ti_unit, cacheline); 1783 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1784 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1785 break; 1786 } 1787 } 1788 1789#ifdef __brokenalpha__ 1790 /* 1791 * From the Alteon sample driver: 1792 * Must insure that we do not cross an 8K (bytes) boundary 1793 * for DMA reads. Our highest limit is 1K bytes. This is a 1794 * restriction on some ALPHA platforms with early revision 1795 * 21174 PCI chipsets, such as the AlphaPC 164lx 1796 */ 1797 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1798#else 1799 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1800#endif 1801 1802 /* This sets the min dma param all the way up (0xff). */ 1803 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1804 1805 if (sc->ti_hdrsplit) 1806 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1807 else 1808 hdrsplit = 0; 1809 1810 /* Configure DMA variables. */ 1811#if BYTE_ORDER == BIG_ENDIAN 1812 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1813 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1814 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1815 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1816#else /* BYTE_ORDER */ 1817 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1818 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1819 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1820#endif /* BYTE_ORDER */ 1821 1822 /* 1823 * Only allow 1 DMA channel to be active at a time. 1824 * I don't think this is a good idea, but without it 1825 * the firmware racks up lots of nicDmaReadRingFull 1826 * errors. This is not compatible with hardware checksums. 1827 */ 1828 if (sc->arpcom.ac_if.if_hwassist == 0) 1829 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1830 1831 /* Recommended settings from Tigon manual. */ 1832 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1833 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1834 1835 if (ti_64bitslot_war(sc)) { 1836 printf("ti%d: bios thinks we're in a 64 bit slot, " 1837 "but we aren't", sc->ti_unit); 1838 return(EINVAL); 1839 } 1840 1841 return(0); 1842} 1843 1844/* 1845 * Initialize the general information block and firmware, and 1846 * start the CPU(s) running. 1847 */ 1848static int 1849ti_gibinit(sc) 1850 struct ti_softc *sc; 1851{ 1852 struct ti_rcb *rcb; 1853 int i; 1854 struct ifnet *ifp; 1855 1856 ifp = &sc->arpcom.ac_if; 1857 1858 /* Disable interrupts for now. */ 1859 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1860 1861 /* Tell the chip where to find the general information block. */ 1862 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1863 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1864 1865 /* Load the firmware into SRAM. */ 1866 ti_loadfw(sc); 1867 1868 /* Set up the contents of the general info and ring control blocks. */ 1869 1870 /* Set up the event ring and producer pointer. */ 1871 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1872 1873 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1874 rcb->ti_flags = 0; 1875 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1876 vtophys(&sc->ti_ev_prodidx); 1877 sc->ti_ev_prodidx.ti_idx = 0; 1878 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1879 sc->ti_ev_saved_considx = 0; 1880 1881 /* Set up the command ring and producer mailbox. */ 1882 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1883 1884 sc->ti_rdata->ti_cmd_ring = 1885 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1886 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1887 rcb->ti_flags = 0; 1888 rcb->ti_max_len = 0; 1889 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1890 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1891 } 1892 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1893 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1894 sc->ti_cmd_saved_prodidx = 0; 1895 1896 /* 1897 * Assign the address of the stats refresh buffer. 1898 * We re-use the current stats buffer for this to 1899 * conserve memory. 1900 */ 1901 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1902 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1903 1904 /* Set up the standard receive ring. */ 1905 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1906 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1907 rcb->ti_max_len = TI_FRAMELEN; 1908 rcb->ti_flags = 0; 1909 if (sc->arpcom.ac_if.if_hwassist) 1910 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1911 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1912 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1913 1914 /* Set up the jumbo receive ring. */ 1915 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1916 TI_HOSTADDR(rcb->ti_hostaddr) = 1917 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1918 1919#ifdef TI_PRIVATE_JUMBOS 1920 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1921 rcb->ti_flags = 0; 1922#else 1923 rcb->ti_max_len = PAGE_SIZE; 1924 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1925#endif 1926 if (sc->arpcom.ac_if.if_hwassist) 1927 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1928 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1929 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1930 1931 /* 1932 * Set up the mini ring. Only activated on the 1933 * Tigon 2 but the slot in the config block is 1934 * still there on the Tigon 1. 1935 */ 1936 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1937 TI_HOSTADDR(rcb->ti_hostaddr) = 1938 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1939 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1940 if (sc->ti_hwrev == TI_HWREV_TIGON) 1941 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1942 else 1943 rcb->ti_flags = 0; 1944 if (sc->arpcom.ac_if.if_hwassist) 1945 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1946 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1947 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1948 1949 /* 1950 * Set up the receive return ring. 1951 */ 1952 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1953 TI_HOSTADDR(rcb->ti_hostaddr) = 1954 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1955 rcb->ti_flags = 0; 1956 rcb->ti_max_len = TI_RETURN_RING_CNT; 1957 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1958 vtophys(&sc->ti_return_prodidx); 1959 1960 /* 1961 * Set up the tx ring. Note: for the Tigon 2, we have the option 1962 * of putting the transmit ring in the host's address space and 1963 * letting the chip DMA it instead of leaving the ring in the NIC's 1964 * memory and accessing it through the shared memory region. We 1965 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1966 * so we have to revert to the shared memory scheme if we detect 1967 * a Tigon 1 chip. 1968 */ 1969 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1970 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1971 sc->ti_rdata->ti_tx_ring_nic = 1972 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1973 } 1974 bzero((char *)sc->ti_rdata->ti_tx_ring, 1975 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1976 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1977 if (sc->ti_hwrev == TI_HWREV_TIGON) 1978 rcb->ti_flags = 0; 1979 else 1980 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1981 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1982 if (sc->arpcom.ac_if.if_hwassist) 1983 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1984 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1985 rcb->ti_max_len = TI_TX_RING_CNT; 1986 if (sc->ti_hwrev == TI_HWREV_TIGON) 1987 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1988 else 1989 TI_HOSTADDR(rcb->ti_hostaddr) = 1990 vtophys(&sc->ti_rdata->ti_tx_ring); 1991 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1992 vtophys(&sc->ti_tx_considx); 1993 1994 /* Set up tuneables */ 1995#if 0 1996 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1997 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1998 (sc->ti_rx_coal_ticks / 10)); 1999 else 2000#endif 2001 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2002 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2003 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2004 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2005 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2006 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2007 2008 /* Turn interrupts on. */ 2009 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2010 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2011 2012 /* Start CPU. */ 2013 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2014 2015 return(0); 2016} 2017 2018/* 2019 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2020 * against our list and return its name if we find a match. 2021 */ 2022static int 2023ti_probe(dev) 2024 device_t dev; 2025{ 2026 struct ti_type *t; 2027 2028 t = ti_devs; 2029 2030 while(t->ti_name != NULL) { 2031 if ((pci_get_vendor(dev) == t->ti_vid) && 2032 (pci_get_device(dev) == t->ti_did)) { 2033 device_set_desc(dev, t->ti_name); 2034 return(0); 2035 } 2036 t++; 2037 } 2038 2039 return(ENXIO); 2040} 2041 2042static int 2043ti_attach(dev) 2044 device_t dev; 2045{ 2046 struct ifnet *ifp; 2047 struct ti_softc *sc; 2048 int unit, error = 0, rid; 2049 2050 sc = device_get_softc(dev); 2051 unit = device_get_unit(dev); 2052 2053 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2054 MTX_DEF | MTX_RECURSE); 2055 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2056 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | 2057 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2058 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2059 2060 /* 2061 * Map control/status registers. 2062 */ 2063 pci_enable_busmaster(dev); 2064 2065 rid = TI_PCI_LOMEM; 2066 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2067 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2068 2069 if (sc->ti_res == NULL) { 2070 printf ("ti%d: couldn't map memory\n", unit); 2071 error = ENXIO; 2072 goto fail; 2073 } 2074 2075 sc->ti_btag = rman_get_bustag(sc->ti_res); 2076 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2077 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2078 2079 /* Allocate interrupt */ 2080 rid = 0; 2081 2082 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2083 RF_SHAREABLE | RF_ACTIVE); 2084 2085 if (sc->ti_irq == NULL) { 2086 printf("ti%d: couldn't map interrupt\n", unit); 2087 error = ENXIO; 2088 goto fail; 2089 } 2090 2091 sc->ti_unit = unit; 2092 2093 if (ti_chipinit(sc)) { 2094 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2095 error = ENXIO; 2096 goto fail; 2097 } 2098 2099 /* Zero out the NIC's on-board SRAM. */ 2100 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2101 2102 /* Init again -- zeroing memory may have clobbered some registers. */ 2103 if (ti_chipinit(sc)) { 2104 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2105 error = ENXIO; 2106 goto fail; 2107 } 2108 2109 /* 2110 * Get station address from the EEPROM. Note: the manual states 2111 * that the MAC address is at offset 0x8c, however the data is 2112 * stored as two longwords (since that's how it's loaded into 2113 * the NIC). This means the MAC address is actually preceded 2114 * by two zero bytes. We need to skip over those. 2115 */ 2116 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2117 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2118 printf("ti%d: failed to read station address\n", unit); 2119 error = ENXIO; 2120 goto fail; 2121 } 2122 2123 /* 2124 * A Tigon chip was detected. Inform the world. 2125 */ 2126 printf("ti%d: Ethernet address: %6D\n", unit, 2127 sc->arpcom.ac_enaddr, ":"); 2128 2129 /* Allocate the general information block and ring buffers. */ 2130 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2131 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2132 2133 if (sc->ti_rdata == NULL) { 2134 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 2139 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2140 2141 /* Try to allocate memory for jumbo buffers. */ 2142#ifdef TI_PRIVATE_JUMBOS 2143 if (ti_alloc_jumbo_mem(sc)) { 2144 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2145 error = ENXIO; 2146 goto fail; 2147 } 2148#else 2149 if (!jumbo_vm_init()) { 2150 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2151 error = ENOMEM; 2152 goto fail; 2153 } 2154#endif 2155 2156 /* 2157 * We really need a better way to tell a 1000baseTX card 2158 * from a 1000baseSX one, since in theory there could be 2159 * OEMed 1000baseTX cards from lame vendors who aren't 2160 * clever enough to change the PCI ID. For the moment 2161 * though, the AceNIC is the only copper card available. 2162 */ 2163 if (pci_get_vendor(dev) == ALT_VENDORID && 2164 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2165 sc->ti_copper = 1; 2166 /* Ok, it's not the only copper card available. */ 2167 if (pci_get_vendor(dev) == NG_VENDORID && 2168 pci_get_device(dev) == NG_DEVICEID_GA620T) 2169 sc->ti_copper = 1; 2170 2171 /* Set default tuneable values. */ 2172 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2173#if 0 2174 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2175#endif 2176 sc->ti_rx_coal_ticks = 170; 2177 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2178 sc->ti_rx_max_coal_bds = 64; 2179#if 0 2180 sc->ti_tx_max_coal_bds = 128; 2181#endif 2182 sc->ti_tx_max_coal_bds = 32; 2183 sc->ti_tx_buf_ratio = 21; 2184 2185 /* Set up ifnet structure */ 2186 ifp = &sc->arpcom.ac_if; 2187 ifp->if_softc = sc; 2188 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2189 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2190 tis[unit] = sc; 2191 ifp->if_ioctl = ti_ioctl; 2192 ifp->if_output = ether_output; 2193 ifp->if_start = ti_start; 2194 ifp->if_watchdog = ti_watchdog; 2195 ifp->if_init = ti_init; 2196 ifp->if_mtu = ETHERMTU; 2197 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2198 2199 /* Set up ifmedia support. */ 2200 if (sc->ti_copper) { 2201 /* 2202 * Copper cards allow manual 10/100 mode selection, 2203 * but not manual 1000baseTX mode selection. Why? 2204 * Becuase currently there's no way to specify the 2205 * master/slave setting through the firmware interface, 2206 * so Alteon decided to just bag it and handle it 2207 * via autonegotiation. 2208 */ 2209 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2210 ifmedia_add(&sc->ifmedia, 2211 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2212 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2213 ifmedia_add(&sc->ifmedia, 2214 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2215 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2216 ifmedia_add(&sc->ifmedia, 2217 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2218 } else { 2219 /* Fiber cards don't support 10/100 modes. */ 2220 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2221 ifmedia_add(&sc->ifmedia, 2222 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2223 } 2224 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2225 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2226 2227 /* 2228 * We're assuming here that card initialization is a sequential 2229 * thing. If it isn't, multiple cards probing at the same time 2230 * could stomp on the list of softcs here. 2231 */ 2232 2233 /* Register the device */ 2234 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2235 0600, "ti%d", sc->ti_unit); 2236 sc->dev->si_drv1 = sc; 2237 2238 /* 2239 * Call MI attach routine. 2240 */ 2241 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2242 2243 /* Hook interrupt last to avoid having to lock softc */ 2244 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2245 ti_intr, sc, &sc->ti_intrhand); 2246 2247 if (error) { 2248 printf("ti%d: couldn't set up irq\n", unit); 2249 ether_ifdetach(ifp); 2250 goto fail; 2251 } 2252 2253fail: 2254 if (sc && error) 2255 ti_detach(dev); 2256 2257 return(error); 2258} 2259 2260/* 2261 * Shutdown hardware and free up resources. This can be called any 2262 * time after the mutex has been initialized. It is called in both 2263 * the error case in attach and the normal detach case so it needs 2264 * to be careful about only freeing resources that have actually been 2265 * allocated. 2266 */ 2267static int 2268ti_detach(dev) 2269 device_t dev; 2270{ 2271 struct ti_softc *sc; 2272 struct ifnet *ifp; 2273 2274 sc = device_get_softc(dev); 2275 destroy_dev(sc->dev); 2276 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2277 TI_LOCK(sc); 2278 ifp = &sc->arpcom.ac_if; 2279 2280 /* These should only be active if attach succeeded */ 2281 if (device_is_attached(dev)) { 2282 ti_stop(sc); 2283 ether_ifdetach(ifp); 2284 bus_generic_detach(dev); 2285 } 2286 ifmedia_removeall(&sc->ifmedia); 2287 2288 if (sc->ti_intrhand) 2289 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2290 if (sc->ti_irq) 2291 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2292 if (sc->ti_res) { 2293 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2294 sc->ti_res); 2295 } 2296 2297#ifdef TI_PRIVATE_JUMBOS 2298 if (sc->ti_cdata.ti_jumbo_buf) 2299 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2300#endif 2301 if (sc->ti_rdata) 2302 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2303 2304 TI_UNLOCK(sc); 2305 mtx_destroy(&sc->ti_mtx); 2306 2307 return(0); 2308} 2309 2310#ifdef TI_JUMBO_HDRSPLIT 2311/* 2312 * If hdr_len is 0, that means that header splitting wasn't done on 2313 * this packet for some reason. The two most likely reasons are that 2314 * the protocol isn't a supported protocol for splitting, or this 2315 * packet had a fragment offset that wasn't 0. 2316 * 2317 * The header length, if it is non-zero, will always be the length of 2318 * the headers on the packet, but that length could be longer than the 2319 * first mbuf. So we take the minimum of the two as the actual 2320 * length. 2321 */ 2322static __inline void 2323ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2324{ 2325 int i = 0; 2326 int lengths[4] = {0, 0, 0, 0}; 2327 struct mbuf *m, *mp; 2328 2329 if (hdr_len != 0) 2330 top->m_len = min(hdr_len, top->m_len); 2331 pkt_len -= top->m_len; 2332 lengths[i++] = top->m_len; 2333 2334 mp = top; 2335 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2336 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2337 pkt_len -= m->m_len; 2338 lengths[i++] = m->m_len; 2339 mp = m; 2340 } 2341 2342#if 0 2343 if (hdr_len != 0) 2344 printf("got split packet: "); 2345 else 2346 printf("got non-split packet: "); 2347 2348 printf("%d,%d,%d,%d = %d\n", lengths[0], 2349 lengths[1], lengths[2], lengths[3], 2350 lengths[0] + lengths[1] + lengths[2] + 2351 lengths[3]); 2352#endif 2353 2354 if (pkt_len) 2355 panic("header splitting didn't"); 2356 2357 if (m) { 2358 m_freem(m); 2359 mp->m_next = NULL; 2360 2361 } 2362 if (mp->m_next != NULL) 2363 panic("ti_hdr_split: last mbuf in chain should be null"); 2364} 2365#endif /* TI_JUMBO_HDRSPLIT */ 2366 2367/* 2368 * Frame reception handling. This is called if there's a frame 2369 * on the receive return list. 2370 * 2371 * Note: we have to be able to handle three possibilities here: 2372 * 1) the frame is from the mini receive ring (can only happen) 2373 * on Tigon 2 boards) 2374 * 2) the frame is from the jumbo recieve ring 2375 * 3) the frame is from the standard receive ring 2376 */ 2377 2378static void 2379ti_rxeof(sc) 2380 struct ti_softc *sc; 2381{ 2382 struct ifnet *ifp; 2383 struct ti_cmd_desc cmd; 2384 2385 TI_LOCK_ASSERT(sc); 2386 2387 ifp = &sc->arpcom.ac_if; 2388 2389 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2390 struct ti_rx_desc *cur_rx; 2391 u_int32_t rxidx; 2392 struct mbuf *m = NULL; 2393 u_int16_t vlan_tag = 0; 2394 int have_tag = 0; 2395 2396 cur_rx = 2397 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2398 rxidx = cur_rx->ti_idx; 2399 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2400 2401 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2402 have_tag = 1; 2403 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2404 } 2405 2406 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2407 2408 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2409 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2410 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2411 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2412 ifp->if_ierrors++; 2413 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2414 continue; 2415 } 2416 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2417 ifp->if_ierrors++; 2418 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2419 continue; 2420 } 2421#ifdef TI_PRIVATE_JUMBOS 2422 m->m_len = cur_rx->ti_len; 2423#else /* TI_PRIVATE_JUMBOS */ 2424#ifdef TI_JUMBO_HDRSPLIT 2425 if (sc->ti_hdrsplit) 2426 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2427 cur_rx->ti_len, rxidx); 2428 else 2429#endif /* TI_JUMBO_HDRSPLIT */ 2430 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2431#endif /* TI_PRIVATE_JUMBOS */ 2432 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2433 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2434 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2435 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2436 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2437 ifp->if_ierrors++; 2438 ti_newbuf_mini(sc, sc->ti_mini, m); 2439 continue; 2440 } 2441 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2442 ifp->if_ierrors++; 2443 ti_newbuf_mini(sc, sc->ti_mini, m); 2444 continue; 2445 } 2446 m->m_len = cur_rx->ti_len; 2447 } else { 2448 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2449 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2450 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2451 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2452 ifp->if_ierrors++; 2453 ti_newbuf_std(sc, sc->ti_std, m); 2454 continue; 2455 } 2456 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2457 ifp->if_ierrors++; 2458 ti_newbuf_std(sc, sc->ti_std, m); 2459 continue; 2460 } 2461 m->m_len = cur_rx->ti_len; 2462 } 2463 2464 m->m_pkthdr.len = cur_rx->ti_len; 2465 ifp->if_ipackets++; 2466 m->m_pkthdr.rcvif = ifp; 2467 2468 if (ifp->if_hwassist) { 2469 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2470 CSUM_DATA_VALID; 2471 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2472 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2473 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2474 } 2475 2476 /* 2477 * If we received a packet with a vlan tag, 2478 * tag it before passing the packet upward. 2479 */ 2480 if (have_tag) 2481 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2482 TI_UNLOCK(sc); 2483 (*ifp->if_input)(ifp, m); 2484 TI_LOCK(sc); 2485 } 2486 2487 /* Only necessary on the Tigon 1. */ 2488 if (sc->ti_hwrev == TI_HWREV_TIGON) 2489 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2490 sc->ti_rx_saved_considx); 2491 2492 TI_UPDATE_STDPROD(sc, sc->ti_std); 2493 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2494 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2495 2496 return; 2497} 2498 2499static void 2500ti_txeof(sc) 2501 struct ti_softc *sc; 2502{ 2503 struct ti_tx_desc *cur_tx = NULL; 2504 struct ifnet *ifp; 2505 2506 ifp = &sc->arpcom.ac_if; 2507 2508 /* 2509 * Go through our tx ring and free mbufs for those 2510 * frames that have been sent. 2511 */ 2512 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2513 u_int32_t idx = 0; 2514 2515 idx = sc->ti_tx_saved_considx; 2516 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2517 if (idx > 383) 2518 CSR_WRITE_4(sc, TI_WINBASE, 2519 TI_TX_RING_BASE + 6144); 2520 else if (idx > 255) 2521 CSR_WRITE_4(sc, TI_WINBASE, 2522 TI_TX_RING_BASE + 4096); 2523 else if (idx > 127) 2524 CSR_WRITE_4(sc, TI_WINBASE, 2525 TI_TX_RING_BASE + 2048); 2526 else 2527 CSR_WRITE_4(sc, TI_WINBASE, 2528 TI_TX_RING_BASE); 2529 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2530 } else 2531 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2532 if (cur_tx->ti_flags & TI_BDFLAG_END) 2533 ifp->if_opackets++; 2534 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2535 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2536 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2537 } 2538 sc->ti_txcnt--; 2539 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2540 ifp->if_timer = 0; 2541 } 2542 2543 if (cur_tx != NULL) 2544 ifp->if_flags &= ~IFF_OACTIVE; 2545 2546 return; 2547} 2548 2549static void 2550ti_intr(xsc) 2551 void *xsc; 2552{ 2553 struct ti_softc *sc; 2554 struct ifnet *ifp; 2555 2556 sc = xsc; 2557 TI_LOCK(sc); 2558 ifp = &sc->arpcom.ac_if; 2559 2560/*#ifdef notdef*/ 2561 /* Avoid this for now -- checking this register is expensive. */ 2562 /* Make sure this is really our interrupt. */ 2563 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2564 TI_UNLOCK(sc); 2565 return; 2566 } 2567/*#endif*/ 2568 2569 /* Ack interrupt and stop others from occuring. */ 2570 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2571 2572 if (ifp->if_flags & IFF_RUNNING) { 2573 /* Check RX return ring producer/consumer */ 2574 ti_rxeof(sc); 2575 2576 /* Check TX ring producer/consumer */ 2577 ti_txeof(sc); 2578 } 2579 2580 ti_handle_events(sc); 2581 2582 /* Re-enable interrupts. */ 2583 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2584 2585 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2586 ti_start(ifp); 2587 2588 TI_UNLOCK(sc); 2589 2590 return; 2591} 2592 2593static void 2594ti_stats_update(sc) 2595 struct ti_softc *sc; 2596{ 2597 struct ifnet *ifp; 2598 2599 ifp = &sc->arpcom.ac_if; 2600 2601 ifp->if_collisions += 2602 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2603 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2604 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2605 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2606 ifp->if_collisions; 2607 2608 return; 2609} 2610 2611/* 2612 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2613 * pointers to descriptors. 2614 */ 2615static int 2616ti_encap(sc, m_head, txidx) 2617 struct ti_softc *sc; 2618 struct mbuf *m_head; 2619 u_int32_t *txidx; 2620{ 2621 struct ti_tx_desc *f = NULL; 2622 struct mbuf *m; 2623 u_int32_t frag, cur, cnt = 0; 2624 u_int16_t csum_flags = 0; 2625 struct m_tag *mtag; 2626 2627 m = m_head; 2628 cur = frag = *txidx; 2629 2630 if (m_head->m_pkthdr.csum_flags) { 2631 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2632 csum_flags |= TI_BDFLAG_IP_CKSUM; 2633 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2634 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2635 if (m_head->m_flags & M_LASTFRAG) 2636 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2637 else if (m_head->m_flags & M_FRAG) 2638 csum_flags |= TI_BDFLAG_IP_FRAG; 2639 } 2640 2641 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2642 2643 /* 2644 * Start packing the mbufs in this chain into 2645 * the fragment pointers. Stop when we run out 2646 * of fragments or hit the end of the mbuf chain. 2647 */ 2648 for (m = m_head; m != NULL; m = m->m_next) { 2649 if (m->m_len != 0) { 2650 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2651 if (frag > 383) 2652 CSR_WRITE_4(sc, TI_WINBASE, 2653 TI_TX_RING_BASE + 6144); 2654 else if (frag > 255) 2655 CSR_WRITE_4(sc, TI_WINBASE, 2656 TI_TX_RING_BASE + 4096); 2657 else if (frag > 127) 2658 CSR_WRITE_4(sc, TI_WINBASE, 2659 TI_TX_RING_BASE + 2048); 2660 else 2661 CSR_WRITE_4(sc, TI_WINBASE, 2662 TI_TX_RING_BASE); 2663 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2664 } else 2665 f = &sc->ti_rdata->ti_tx_ring[frag]; 2666 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2667 break; 2668 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2669 f->ti_len = m->m_len; 2670 f->ti_flags = csum_flags; 2671 2672 if (mtag != NULL) { 2673 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2674 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2675 } else { 2676 f->ti_vlan_tag = 0; 2677 } 2678 2679 /* 2680 * Sanity check: avoid coming within 16 descriptors 2681 * of the end of the ring. 2682 */ 2683 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2684 return(ENOBUFS); 2685 cur = frag; 2686 TI_INC(frag, TI_TX_RING_CNT); 2687 cnt++; 2688 } 2689 } 2690 2691 if (m != NULL) 2692 return(ENOBUFS); 2693 2694 if (frag == sc->ti_tx_saved_considx) 2695 return(ENOBUFS); 2696 2697 if (sc->ti_hwrev == TI_HWREV_TIGON) 2698 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2699 TI_BDFLAG_END; 2700 else 2701 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2702 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2703 sc->ti_txcnt += cnt; 2704 2705 *txidx = frag; 2706 2707 return(0); 2708} 2709 2710/* 2711 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2712 * to the mbuf data regions directly in the transmit descriptors. 2713 */ 2714static void 2715ti_start(ifp) 2716 struct ifnet *ifp; 2717{ 2718 struct ti_softc *sc; 2719 struct mbuf *m_head = NULL; 2720 u_int32_t prodidx = 0; 2721 2722 sc = ifp->if_softc; 2723 TI_LOCK(sc); 2724 2725 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2726 2727 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2728 IF_DEQUEUE(&ifp->if_snd, m_head); 2729 if (m_head == NULL) 2730 break; 2731 2732 /* 2733 * XXX 2734 * safety overkill. If this is a fragmented packet chain 2735 * with delayed TCP/UDP checksums, then only encapsulate 2736 * it if we have enough descriptors to handle the entire 2737 * chain at once. 2738 * (paranoia -- may not actually be needed) 2739 */ 2740 if (m_head->m_flags & M_FIRSTFRAG && 2741 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2742 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2743 m_head->m_pkthdr.csum_data + 16) { 2744 IF_PREPEND(&ifp->if_snd, m_head); 2745 ifp->if_flags |= IFF_OACTIVE; 2746 break; 2747 } 2748 } 2749 2750 /* 2751 * Pack the data into the transmit ring. If we 2752 * don't have room, set the OACTIVE flag and wait 2753 * for the NIC to drain the ring. 2754 */ 2755 if (ti_encap(sc, m_head, &prodidx)) { 2756 IF_PREPEND(&ifp->if_snd, m_head); 2757 ifp->if_flags |= IFF_OACTIVE; 2758 break; 2759 } 2760 2761 /* 2762 * If there's a BPF listener, bounce a copy of this frame 2763 * to him. 2764 */ 2765 BPF_MTAP(ifp, m_head); 2766 } 2767 2768 /* Transmit */ 2769 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2770 2771 /* 2772 * Set a timeout in case the chip goes out to lunch. 2773 */ 2774 ifp->if_timer = 5; 2775 TI_UNLOCK(sc); 2776 2777 return; 2778} 2779 2780static void 2781ti_init(xsc) 2782 void *xsc; 2783{ 2784 struct ti_softc *sc = xsc; 2785 2786 /* Cancel pending I/O and flush buffers. */ 2787 ti_stop(sc); 2788 2789 TI_LOCK(sc); 2790 /* Init the gen info block, ring control blocks and firmware. */ 2791 if (ti_gibinit(sc)) { 2792 printf("ti%d: initialization failure\n", sc->ti_unit); 2793 TI_UNLOCK(sc); 2794 return; 2795 } 2796 2797 TI_UNLOCK(sc); 2798 2799 return; 2800} 2801 2802static void ti_init2(sc) 2803 struct ti_softc *sc; 2804{ 2805 struct ti_cmd_desc cmd; 2806 struct ifnet *ifp; 2807 u_int16_t *m; 2808 struct ifmedia *ifm; 2809 int tmp; 2810 2811 ifp = &sc->arpcom.ac_if; 2812 2813 /* Specify MTU and interface index. */ 2814 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 2815 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2816 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 2817 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2818 2819 /* Load our MAC address. */ 2820 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2821 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2822 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2823 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2824 2825 /* Enable or disable promiscuous mode as needed. */ 2826 if (ifp->if_flags & IFF_PROMISC) { 2827 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2828 } else { 2829 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2830 } 2831 2832 /* Program multicast filter. */ 2833 ti_setmulti(sc); 2834 2835 /* 2836 * If this is a Tigon 1, we should tell the 2837 * firmware to use software packet filtering. 2838 */ 2839 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2840 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2841 } 2842 2843 /* Init RX ring. */ 2844 ti_init_rx_ring_std(sc); 2845 2846 /* Init jumbo RX ring. */ 2847 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2848 ti_init_rx_ring_jumbo(sc); 2849 2850 /* 2851 * If this is a Tigon 2, we can also configure the 2852 * mini ring. 2853 */ 2854 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2855 ti_init_rx_ring_mini(sc); 2856 2857 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2858 sc->ti_rx_saved_considx = 0; 2859 2860 /* Init TX ring. */ 2861 ti_init_tx_ring(sc); 2862 2863 /* Tell firmware we're alive. */ 2864 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2865 2866 /* Enable host interrupts. */ 2867 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2868 2869 ifp->if_flags |= IFF_RUNNING; 2870 ifp->if_flags &= ~IFF_OACTIVE; 2871 2872 /* 2873 * Make sure to set media properly. We have to do this 2874 * here since we have to issue commands in order to set 2875 * the link negotiation and we can't issue commands until 2876 * the firmware is running. 2877 */ 2878 ifm = &sc->ifmedia; 2879 tmp = ifm->ifm_media; 2880 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2881 ti_ifmedia_upd(ifp); 2882 ifm->ifm_media = tmp; 2883 2884 return; 2885} 2886 2887/* 2888 * Set media options. 2889 */ 2890static int 2891ti_ifmedia_upd(ifp) 2892 struct ifnet *ifp; 2893{ 2894 struct ti_softc *sc; 2895 struct ifmedia *ifm; 2896 struct ti_cmd_desc cmd; 2897 u_int32_t flowctl; 2898 2899 sc = ifp->if_softc; 2900 ifm = &sc->ifmedia; 2901 2902 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2903 return(EINVAL); 2904 2905 flowctl = 0; 2906 2907 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2908 case IFM_AUTO: 2909 /* 2910 * Transmit flow control doesn't work on the Tigon 1. 2911 */ 2912 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2913 2914 /* 2915 * Transmit flow control can also cause problems on the 2916 * Tigon 2, apparantly with both the copper and fiber 2917 * boards. The symptom is that the interface will just 2918 * hang. This was reproduced with Alteon 180 switches. 2919 */ 2920#if 0 2921 if (sc->ti_hwrev != TI_HWREV_TIGON) 2922 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2923#endif 2924 2925 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2926 TI_GLNK_FULL_DUPLEX| flowctl | 2927 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2928 2929 flowctl = TI_LNK_RX_FLOWCTL_Y; 2930#if 0 2931 if (sc->ti_hwrev != TI_HWREV_TIGON) 2932 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2933#endif 2934 2935 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2936 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 2937 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2938 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2939 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2940 break; 2941 case IFM_1000_SX: 2942 case IFM_1000_T: 2943 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2944#if 0 2945 if (sc->ti_hwrev != TI_HWREV_TIGON) 2946 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2947#endif 2948 2949 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2950 flowctl |TI_GLNK_ENB); 2951 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2952 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2953 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2954 } 2955 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2956 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2957 break; 2958 case IFM_100_FX: 2959 case IFM_10_FL: 2960 case IFM_100_TX: 2961 case IFM_10_T: 2962 flowctl = TI_LNK_RX_FLOWCTL_Y; 2963#if 0 2964 if (sc->ti_hwrev != TI_HWREV_TIGON) 2965 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2966#endif 2967 2968 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2969 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 2970 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2971 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2972 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2973 } else { 2974 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2975 } 2976 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2977 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2978 } else { 2979 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2980 } 2981 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2982 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2983 break; 2984 } 2985 2986 return(0); 2987} 2988 2989/* 2990 * Report current media status. 2991 */ 2992static void 2993ti_ifmedia_sts(ifp, ifmr) 2994 struct ifnet *ifp; 2995 struct ifmediareq *ifmr; 2996{ 2997 struct ti_softc *sc; 2998 u_int32_t media = 0; 2999 3000 sc = ifp->if_softc; 3001 3002 ifmr->ifm_status = IFM_AVALID; 3003 ifmr->ifm_active = IFM_ETHER; 3004 3005 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3006 return; 3007 3008 ifmr->ifm_status |= IFM_ACTIVE; 3009 3010 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3011 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3012 if (sc->ti_copper) 3013 ifmr->ifm_active |= IFM_1000_T; 3014 else 3015 ifmr->ifm_active |= IFM_1000_SX; 3016 if (media & TI_GLNK_FULL_DUPLEX) 3017 ifmr->ifm_active |= IFM_FDX; 3018 else 3019 ifmr->ifm_active |= IFM_HDX; 3020 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3021 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3022 if (sc->ti_copper) { 3023 if (media & TI_LNK_100MB) 3024 ifmr->ifm_active |= IFM_100_TX; 3025 if (media & TI_LNK_10MB) 3026 ifmr->ifm_active |= IFM_10_T; 3027 } else { 3028 if (media & TI_LNK_100MB) 3029 ifmr->ifm_active |= IFM_100_FX; 3030 if (media & TI_LNK_10MB) 3031 ifmr->ifm_active |= IFM_10_FL; 3032 } 3033 if (media & TI_LNK_FULL_DUPLEX) 3034 ifmr->ifm_active |= IFM_FDX; 3035 if (media & TI_LNK_HALF_DUPLEX) 3036 ifmr->ifm_active |= IFM_HDX; 3037 } 3038 3039 return; 3040} 3041 3042static int 3043ti_ioctl(ifp, command, data) 3044 struct ifnet *ifp; 3045 u_long command; 3046 caddr_t data; 3047{ 3048 struct ti_softc *sc = ifp->if_softc; 3049 struct ifreq *ifr = (struct ifreq *) data; 3050 int mask, error = 0; 3051 struct ti_cmd_desc cmd; 3052 3053 TI_LOCK(sc); 3054 3055 switch(command) { 3056 case SIOCSIFMTU: 3057 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3058 error = EINVAL; 3059 else { 3060 ifp->if_mtu = ifr->ifr_mtu; 3061 ti_init(sc); 3062 } 3063 break; 3064 case SIOCSIFFLAGS: 3065 if (ifp->if_flags & IFF_UP) { 3066 /* 3067 * If only the state of the PROMISC flag changed, 3068 * then just use the 'set promisc mode' command 3069 * instead of reinitializing the entire NIC. Doing 3070 * a full re-init means reloading the firmware and 3071 * waiting for it to start up, which may take a 3072 * second or two. 3073 */ 3074 if (ifp->if_flags & IFF_RUNNING && 3075 ifp->if_flags & IFF_PROMISC && 3076 !(sc->ti_if_flags & IFF_PROMISC)) { 3077 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3078 TI_CMD_CODE_PROMISC_ENB, 0); 3079 } else if (ifp->if_flags & IFF_RUNNING && 3080 !(ifp->if_flags & IFF_PROMISC) && 3081 sc->ti_if_flags & IFF_PROMISC) { 3082 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3083 TI_CMD_CODE_PROMISC_DIS, 0); 3084 } else 3085 ti_init(sc); 3086 } else { 3087 if (ifp->if_flags & IFF_RUNNING) { 3088 ti_stop(sc); 3089 } 3090 } 3091 sc->ti_if_flags = ifp->if_flags; 3092 error = 0; 3093 break; 3094 case SIOCADDMULTI: 3095 case SIOCDELMULTI: 3096 if (ifp->if_flags & IFF_RUNNING) { 3097 ti_setmulti(sc); 3098 error = 0; 3099 } 3100 break; 3101 case SIOCSIFMEDIA: 3102 case SIOCGIFMEDIA: 3103 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3104 break; 3105 case SIOCSIFCAP: 3106 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3107 if (mask & IFCAP_HWCSUM) { 3108 if (IFCAP_HWCSUM & ifp->if_capenable) 3109 ifp->if_capenable &= ~IFCAP_HWCSUM; 3110 else 3111 ifp->if_capenable |= IFCAP_HWCSUM; 3112 if (ifp->if_flags & IFF_RUNNING) 3113 ti_init(sc); 3114 } 3115 error = 0; 3116 break; 3117 default: 3118 error = ether_ioctl(ifp, command, data); 3119 break; 3120 } 3121 3122 TI_UNLOCK(sc); 3123 3124 return(error); 3125} 3126 3127static int 3128ti_open(dev_t dev, int flags, int fmt, struct thread *td) 3129{ 3130 struct ti_softc *sc; 3131 3132 sc = dev->si_drv1; 3133 if (sc == NULL) 3134 return(ENODEV); 3135 3136 TI_LOCK(sc); 3137 sc->ti_flags |= TI_FLAG_DEBUGING; 3138 TI_UNLOCK(sc); 3139 3140 return(0); 3141} 3142 3143static int 3144ti_close(dev_t dev, int flag, int fmt, struct thread *td) 3145{ 3146 struct ti_softc *sc; 3147 3148 sc = dev->si_drv1; 3149 if (sc == NULL) 3150 return(ENODEV); 3151 3152 TI_LOCK(sc); 3153 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3154 TI_UNLOCK(sc); 3155 3156 return(0); 3157} 3158 3159/* 3160 * This ioctl routine goes along with the Tigon character device. 3161 */ 3162static int 3163ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3164{ 3165 int error; 3166 struct ti_softc *sc; 3167 3168 sc = dev->si_drv1; 3169 if (sc == NULL) 3170 return(ENODEV); 3171 3172 error = 0; 3173 3174 switch(cmd) { 3175 case TIIOCGETSTATS: 3176 { 3177 struct ti_stats *outstats; 3178 3179 outstats = (struct ti_stats *)addr; 3180 3181 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3182 sizeof(struct ti_stats)); 3183 break; 3184 } 3185 case TIIOCGETPARAMS: 3186 { 3187 struct ti_params *params; 3188 3189 params = (struct ti_params *)addr; 3190 3191 params->ti_stat_ticks = sc->ti_stat_ticks; 3192 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3193 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3194 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3195 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3196 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3197 params->param_mask = TI_PARAM_ALL; 3198 3199 error = 0; 3200 3201 break; 3202 } 3203 case TIIOCSETPARAMS: 3204 { 3205 struct ti_params *params; 3206 3207 params = (struct ti_params *)addr; 3208 3209 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3210 sc->ti_stat_ticks = params->ti_stat_ticks; 3211 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3212 } 3213 3214 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3215 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3216 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3217 sc->ti_rx_coal_ticks); 3218 } 3219 3220 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3221 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3222 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3223 sc->ti_tx_coal_ticks); 3224 } 3225 3226 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3227 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3228 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3229 sc->ti_rx_max_coal_bds); 3230 } 3231 3232 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3233 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3234 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3235 sc->ti_tx_max_coal_bds); 3236 } 3237 3238 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3239 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3240 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3241 sc->ti_tx_buf_ratio); 3242 } 3243 3244 error = 0; 3245 3246 break; 3247 } 3248 case TIIOCSETTRACE: { 3249 ti_trace_type trace_type; 3250 3251 trace_type = *(ti_trace_type *)addr; 3252 3253 /* 3254 * Set tracing to whatever the user asked for. Setting 3255 * this register to 0 should have the effect of disabling 3256 * tracing. 3257 */ 3258 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3259 3260 error = 0; 3261 3262 break; 3263 } 3264 case TIIOCGETTRACE: { 3265 struct ti_trace_buf *trace_buf; 3266 u_int32_t trace_start, cur_trace_ptr, trace_len; 3267 3268 trace_buf = (struct ti_trace_buf *)addr; 3269 3270 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3271 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3272 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3273 3274#if 0 3275 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3276 "trace_len = %d\n", sc->ti_unit, trace_start, 3277 cur_trace_ptr, trace_len); 3278 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3279 trace_buf->buf_len); 3280#endif 3281 3282 error = ti_copy_mem(sc, trace_start, min(trace_len, 3283 trace_buf->buf_len), 3284 (caddr_t)trace_buf->buf, 1, 1); 3285 3286 if (error == 0) { 3287 trace_buf->fill_len = min(trace_len, 3288 trace_buf->buf_len); 3289 if (cur_trace_ptr < trace_start) 3290 trace_buf->cur_trace_ptr = 3291 trace_start - cur_trace_ptr; 3292 else 3293 trace_buf->cur_trace_ptr = 3294 cur_trace_ptr - trace_start; 3295 } else 3296 trace_buf->fill_len = 0; 3297 3298 3299 break; 3300 } 3301 3302 /* 3303 * For debugging, five ioctls are needed: 3304 * ALT_ATTACH 3305 * ALT_READ_TG_REG 3306 * ALT_WRITE_TG_REG 3307 * ALT_READ_TG_MEM 3308 * ALT_WRITE_TG_MEM 3309 */ 3310 case ALT_ATTACH: 3311 /* 3312 * From what I can tell, Alteon's Solaris Tigon driver 3313 * only has one character device, so you have to attach 3314 * to the Tigon board you're interested in. This seems 3315 * like a not-so-good way to do things, since unless you 3316 * subsequently specify the unit number of the device 3317 * you're interested in in every ioctl, you'll only be 3318 * able to debug one board at a time. 3319 */ 3320 error = 0; 3321 break; 3322 case ALT_READ_TG_MEM: 3323 case ALT_WRITE_TG_MEM: 3324 { 3325 struct tg_mem *mem_param; 3326 u_int32_t sram_end, scratch_end; 3327 3328 mem_param = (struct tg_mem *)addr; 3329 3330 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3331 sram_end = TI_END_SRAM_I; 3332 scratch_end = TI_END_SCRATCH_I; 3333 } else { 3334 sram_end = TI_END_SRAM_II; 3335 scratch_end = TI_END_SCRATCH_II; 3336 } 3337 3338 /* 3339 * For now, we'll only handle accessing regular SRAM, 3340 * nothing else. 3341 */ 3342 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3343 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3344 /* 3345 * In this instance, we always copy to/from user 3346 * space, so the user space argument is set to 1. 3347 */ 3348 error = ti_copy_mem(sc, mem_param->tgAddr, 3349 mem_param->len, 3350 mem_param->userAddr, 1, 3351 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3352 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3353 && (mem_param->tgAddr <= scratch_end)) { 3354 error = ti_copy_scratch(sc, mem_param->tgAddr, 3355 mem_param->len, 3356 mem_param->userAddr, 1, 3357 (cmd == ALT_READ_TG_MEM) ? 3358 1 : 0, TI_PROCESSOR_A); 3359 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3360 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3361 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3362 printf("ti%d: invalid memory range for " 3363 "Tigon I\n", sc->ti_unit); 3364 error = EINVAL; 3365 break; 3366 } 3367 error = ti_copy_scratch(sc, mem_param->tgAddr - 3368 TI_SCRATCH_DEBUG_OFF, 3369 mem_param->len, 3370 mem_param->userAddr, 1, 3371 (cmd == ALT_READ_TG_MEM) ? 3372 1 : 0, TI_PROCESSOR_B); 3373 } else { 3374 printf("ti%d: memory address %#x len %d is out of " 3375 "supported range\n", sc->ti_unit, 3376 mem_param->tgAddr, mem_param->len); 3377 error = EINVAL; 3378 } 3379 3380 break; 3381 } 3382 case ALT_READ_TG_REG: 3383 case ALT_WRITE_TG_REG: 3384 { 3385 struct tg_reg *regs; 3386 u_int32_t tmpval; 3387 3388 regs = (struct tg_reg *)addr; 3389 3390 /* 3391 * Make sure the address in question isn't out of range. 3392 */ 3393 if (regs->addr > TI_REG_MAX) { 3394 error = EINVAL; 3395 break; 3396 } 3397 if (cmd == ALT_READ_TG_REG) { 3398 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3399 regs->addr, &tmpval, 1); 3400 regs->data = ntohl(tmpval); 3401#if 0 3402 if ((regs->addr == TI_CPU_STATE) 3403 || (regs->addr == TI_CPU_CTL_B)) { 3404 printf("ti%d: register %#x = %#x\n", 3405 sc->ti_unit, regs->addr, tmpval); 3406 } 3407#endif 3408 } else { 3409 tmpval = htonl(regs->data); 3410 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3411 regs->addr, &tmpval, 1); 3412 } 3413 3414 break; 3415 } 3416 default: 3417 error = ENOTTY; 3418 break; 3419 } 3420 return(error); 3421} 3422 3423static void 3424ti_watchdog(ifp) 3425 struct ifnet *ifp; 3426{ 3427 struct ti_softc *sc; 3428 3429 sc = ifp->if_softc; 3430 TI_LOCK(sc); 3431 3432 /* 3433 * When we're debugging, the chip is often stopped for long periods 3434 * of time, and that would normally cause the watchdog timer to fire. 3435 * Since that impedes debugging, we don't want to do that. 3436 */ 3437 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3438 TI_UNLOCK(sc); 3439 return; 3440 } 3441 3442 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3443 ti_stop(sc); 3444 ti_init(sc); 3445 3446 ifp->if_oerrors++; 3447 TI_UNLOCK(sc); 3448 3449 return; 3450} 3451 3452/* 3453 * Stop the adapter and free any mbufs allocated to the 3454 * RX and TX lists. 3455 */ 3456static void 3457ti_stop(sc) 3458 struct ti_softc *sc; 3459{ 3460 struct ifnet *ifp; 3461 struct ti_cmd_desc cmd; 3462 3463 TI_LOCK(sc); 3464 3465 ifp = &sc->arpcom.ac_if; 3466 3467 /* Disable host interrupts. */ 3468 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3469 /* 3470 * Tell firmware we're shutting down. 3471 */ 3472 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3473 3474 /* Halt and reinitialize. */ 3475 ti_chipinit(sc); 3476 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3477 ti_chipinit(sc); 3478 3479 /* Free the RX lists. */ 3480 ti_free_rx_ring_std(sc); 3481 3482 /* Free jumbo RX list. */ 3483 ti_free_rx_ring_jumbo(sc); 3484 3485 /* Free mini RX list. */ 3486 ti_free_rx_ring_mini(sc); 3487 3488 /* Free TX buffers. */ 3489 ti_free_tx_ring(sc); 3490 3491 sc->ti_ev_prodidx.ti_idx = 0; 3492 sc->ti_return_prodidx.ti_idx = 0; 3493 sc->ti_tx_considx.ti_idx = 0; 3494 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3495 3496 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3497 TI_UNLOCK(sc); 3498 3499 return; 3500} 3501 3502/* 3503 * Stop all chip I/O so that the kernel's probe routines don't 3504 * get confused by errant DMAs when rebooting. 3505 */ 3506static void 3507ti_shutdown(dev) 3508 device_t dev; 3509{ 3510 struct ti_softc *sc; 3511 3512 sc = device_get_softc(dev); 3513 TI_LOCK(sc); 3514 ti_chipinit(sc); 3515 TI_UNLOCK(sc); 3516 3517 return; 3518} 3519