if_ti.c revision 111815
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 111815 2003-03-03 12:15:54Z phk $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "opt_ti.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90#include <sys/queue.h> 91#include <sys/conf.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98#include <net/if_types.h> 99#include <net/if_vlan_var.h> 100 101#include <net/bpf.h> 102 103#include <netinet/in_systm.h> 104#include <netinet/in.h> 105#include <netinet/ip.h> 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/bus_memio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116 117#if !defined(TI_PRIVATE_JUMBOS) 118#include <sys/sockio.h> 119#include <sys/uio.h> 120#include <sys/lock.h> 121#include <vm/vm_extern.h> 122#include <vm/pmap.h> 123#include <vm/vm_map.h> 124#include <vm/vm_map.h> 125#include <vm/vm_param.h> 126#include <vm/vm_pageout.h> 127#include <sys/vmmeter.h> 128#include <vm/vm_page.h> 129#include <vm/vm_object.h> 130#include <vm/vm_kern.h> 131#include <sys/proc.h> 132#include <sys/jumbo.h> 133#endif /* !TI_PRIVATE_JUMBOS */ 134#include <sys/vnode.h> /* for vfindev, vgone */ 135 136#include <pci/pcireg.h> 137#include <pci/pcivar.h> 138 139#include <sys/tiio.h> 140#include <pci/if_tireg.h> 141#include <pci/ti_fw.h> 142#include <pci/ti_fw2.h> 143 144#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145/* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153#if !defined(lint) 154static const char rcsid[] = 155 "$FreeBSD: head/sys/dev/ti/if_ti.c 111815 2003-03-03 12:15:54Z phk $"; 156#endif 157 158struct ti_softc *tis[8]; 159 160typedef enum { 161 TI_SWAP_HTON, 162 TI_SWAP_NTOH 163} ti_swap_type; 164 165 166/* 167 * Various supported device vendors/types and their names. 168 */ 169 170static struct ti_type ti_devs[] = { 171 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 172 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 173 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 174 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 175 { TC_VENDORID, TC_DEVICEID_3C985, 176 "3Com 3c985-SX Gigabit Ethernet" }, 177 { NG_VENDORID, NG_DEVICEID_GA620, 178 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 179 { NG_VENDORID, NG_DEVICEID_GA620T, 180 "Netgear GA620 1000baseT Gigabit Ethernet" }, 181 { SGI_VENDORID, SGI_DEVICEID_TIGON, 182 "Silicon Graphics Gigabit Ethernet" }, 183 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 184 "Farallon PN9000SX Gigabit Ethernet" }, 185 { 0, 0, NULL } 186}; 187 188#define TI_CDEV_MAJOR 153 189 190static d_open_t ti_open; 191static d_close_t ti_close; 192static d_ioctl_t ti_ioctl2; 193 194static struct cdevsw ti_cdevsw = { 195 .d_open = ti_open, 196 .d_close = ti_close, 197 .d_ioctl = ti_ioctl2, 198 .d_name = "ti", 199 .d_maj = TI_CDEV_MAJOR, 200}; 201 202static int ti_probe (device_t); 203static int ti_attach (device_t); 204static int ti_detach (device_t); 205static void ti_txeof (struct ti_softc *); 206static void ti_rxeof (struct ti_softc *); 207 208static void ti_stats_update (struct ti_softc *); 209static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 210 211static void ti_intr (void *); 212static void ti_start (struct ifnet *); 213static int ti_ioctl (struct ifnet *, u_long, caddr_t); 214static void ti_init (void *); 215static void ti_init2 (struct ti_softc *); 216static void ti_stop (struct ti_softc *); 217static void ti_watchdog (struct ifnet *); 218static void ti_shutdown (device_t); 219static int ti_ifmedia_upd (struct ifnet *); 220static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 221 222static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 223static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 224static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 225 226static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 227static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 228static void ti_setmulti (struct ti_softc *); 229 230static void ti_mem (struct ti_softc *, u_int32_t, 231 u_int32_t, caddr_t); 232static int ti_copy_mem (struct ti_softc *, u_int32_t, 233 u_int32_t, caddr_t, int, int); 234static int ti_copy_scratch (struct ti_softc *, u_int32_t, 235 u_int32_t, caddr_t, int, int, int); 236static int ti_bcopy_swap (const void *, void *, size_t, 237 ti_swap_type); 238static void ti_loadfw (struct ti_softc *); 239static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 240static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 241 caddr_t, int); 242static void ti_handle_events (struct ti_softc *); 243#ifdef TI_PRIVATE_JUMBOS 244static int ti_alloc_jumbo_mem (struct ti_softc *); 245static void *ti_jalloc (struct ti_softc *); 246static void ti_jfree (void *, void *); 247#endif /* TI_PRIVATE_JUMBOS */ 248static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 249static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 250static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 251static int ti_init_rx_ring_std (struct ti_softc *); 252static void ti_free_rx_ring_std (struct ti_softc *); 253static int ti_init_rx_ring_jumbo (struct ti_softc *); 254static void ti_free_rx_ring_jumbo (struct ti_softc *); 255static int ti_init_rx_ring_mini (struct ti_softc *); 256static void ti_free_rx_ring_mini (struct ti_softc *); 257static void ti_free_tx_ring (struct ti_softc *); 258static int ti_init_tx_ring (struct ti_softc *); 259 260static int ti_64bitslot_war (struct ti_softc *); 261static int ti_chipinit (struct ti_softc *); 262static int ti_gibinit (struct ti_softc *); 263 264#ifdef TI_JUMBO_HDRSPLIT 265static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 266 int pkt_len, int idx); 267#endif /* TI_JUMBO_HDRSPLIT */ 268 269static device_method_t ti_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, ti_probe), 272 DEVMETHOD(device_attach, ti_attach), 273 DEVMETHOD(device_detach, ti_detach), 274 DEVMETHOD(device_shutdown, ti_shutdown), 275 { 0, 0 } 276}; 277 278static driver_t ti_driver = { 279 "ti", 280 ti_methods, 281 sizeof(struct ti_softc) 282}; 283 284static devclass_t ti_devclass; 285 286DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 287 288/* List of Tigon softcs */ 289static STAILQ_HEAD(ti_softc_list, ti_softc) ti_sc_list; 290 291static struct ti_softc * 292ti_lookup_softc(int unit) 293{ 294 struct ti_softc *sc; 295 for (sc = STAILQ_FIRST(&ti_sc_list); sc != NULL; 296 sc = STAILQ_NEXT(sc, ti_links)) 297 if (sc->ti_unit == unit) 298 return(sc); 299 return(NULL); 300} 301 302/* 303 * Send an instruction or address to the EEPROM, check for ACK. 304 */ 305static u_int32_t ti_eeprom_putbyte(sc, byte) 306 struct ti_softc *sc; 307 int byte; 308{ 309 register int i, ack = 0; 310 311 /* 312 * Make sure we're in TX mode. 313 */ 314 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 315 316 /* 317 * Feed in each bit and stobe the clock. 318 */ 319 for (i = 0x80; i; i >>= 1) { 320 if (byte & i) { 321 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 322 } else { 323 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 324 } 325 DELAY(1); 326 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 327 DELAY(1); 328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 329 } 330 331 /* 332 * Turn off TX mode. 333 */ 334 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 335 336 /* 337 * Check for ack. 338 */ 339 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 340 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 341 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 342 343 return(ack); 344} 345 346/* 347 * Read a byte of data stored in the EEPROM at address 'addr.' 348 * We have to send two address bytes since the EEPROM can hold 349 * more than 256 bytes of data. 350 */ 351static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 352 struct ti_softc *sc; 353 int addr; 354 u_int8_t *dest; 355{ 356 register int i; 357 u_int8_t byte = 0; 358 359 EEPROM_START; 360 361 /* 362 * Send write control code to EEPROM. 363 */ 364 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 365 printf("ti%d: failed to send write command, status: %x\n", 366 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 367 return(1); 368 } 369 370 /* 371 * Send first byte of address of byte we want to read. 372 */ 373 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 374 printf("ti%d: failed to send address, status: %x\n", 375 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 376 return(1); 377 } 378 /* 379 * Send second byte address of byte we want to read. 380 */ 381 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 382 printf("ti%d: failed to send address, status: %x\n", 383 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 384 return(1); 385 } 386 387 EEPROM_STOP; 388 EEPROM_START; 389 /* 390 * Send read control code to EEPROM. 391 */ 392 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 393 printf("ti%d: failed to send read command, status: %x\n", 394 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 395 return(1); 396 } 397 398 /* 399 * Start reading bits from EEPROM. 400 */ 401 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 402 for (i = 0x80; i; i >>= 1) { 403 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 404 DELAY(1); 405 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 406 byte |= i; 407 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 408 DELAY(1); 409 } 410 411 EEPROM_STOP; 412 413 /* 414 * No ACK generated for read, so just return byte. 415 */ 416 417 *dest = byte; 418 419 return(0); 420} 421 422/* 423 * Read a sequence of bytes from the EEPROM. 424 */ 425static int 426ti_read_eeprom(sc, dest, off, cnt) 427 struct ti_softc *sc; 428 caddr_t dest; 429 int off; 430 int cnt; 431{ 432 int err = 0, i; 433 u_int8_t byte = 0; 434 435 for (i = 0; i < cnt; i++) { 436 err = ti_eeprom_getbyte(sc, off + i, &byte); 437 if (err) 438 break; 439 *(dest + i) = byte; 440 } 441 442 return(err ? 1 : 0); 443} 444 445/* 446 * NIC memory access function. Can be used to either clear a section 447 * of NIC local memory or (if buf is non-NULL) copy data into it. 448 */ 449static void 450ti_mem(sc, addr, len, buf) 451 struct ti_softc *sc; 452 u_int32_t addr, len; 453 caddr_t buf; 454{ 455 int segptr, segsize, cnt; 456 caddr_t ti_winbase, ptr; 457 458 segptr = addr; 459 cnt = len; 460 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 461 ptr = buf; 462 463 while(cnt) { 464 if (cnt < TI_WINLEN) 465 segsize = cnt; 466 else 467 segsize = TI_WINLEN - (segptr % TI_WINLEN); 468 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 469 if (buf == NULL) 470 bzero((char *)ti_winbase + (segptr & 471 (TI_WINLEN - 1)), segsize); 472 else { 473 bcopy((char *)ptr, (char *)ti_winbase + 474 (segptr & (TI_WINLEN - 1)), segsize); 475 ptr += segsize; 476 } 477 segptr += segsize; 478 cnt -= segsize; 479 } 480 481 return; 482} 483 484static int 485ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 486 struct ti_softc *sc; 487 u_int32_t tigon_addr, len; 488 caddr_t buf; 489 int useraddr, readdata; 490{ 491 int segptr, segsize, cnt; 492 caddr_t ptr; 493 u_int32_t origwin; 494 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 495 int resid, segresid; 496 int first_pass; 497 498 /* 499 * At the moment, we don't handle non-aligned cases, we just bail. 500 * If this proves to be a problem, it will be fixed. 501 */ 502 if ((readdata == 0) 503 && (tigon_addr & 0x3)) { 504 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 505 "word-aligned\n", sc->ti_unit, tigon_addr); 506 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 507 "supported\n", sc->ti_unit); 508 return(EINVAL); 509 } 510 511 segptr = tigon_addr & ~0x3; 512 segresid = tigon_addr - segptr; 513 514 /* 515 * This is the non-aligned amount left over that we'll need to 516 * copy. 517 */ 518 resid = len & 0x3; 519 520 /* Add in the left over amount at the front of the buffer */ 521 resid += segresid; 522 523 cnt = len & ~0x3; 524 /* 525 * If resid + segresid is >= 4, add multiples of 4 to the count and 526 * decrease the residual by that much. 527 */ 528 cnt += resid & ~0x3; 529 resid -= resid & ~0x3; 530 531 ptr = buf; 532 533 first_pass = 1; 534 535 /* 536 * Make sure we aren't interrupted while we're changing the window 537 * pointer. 538 */ 539 TI_LOCK(sc); 540 541 /* 542 * Save the old window base value. 543 */ 544 origwin = CSR_READ_4(sc, TI_WINBASE); 545 546 while(cnt) { 547 bus_size_t ti_offset; 548 549 if (cnt < TI_WINLEN) 550 segsize = cnt; 551 else 552 segsize = TI_WINLEN - (segptr % TI_WINLEN); 553 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 554 555 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 556 557 if (readdata) { 558 559 bus_space_read_region_4(sc->ti_btag, 560 sc->ti_bhandle, ti_offset, 561 (u_int32_t *)tmparray, 562 segsize >> 2); 563 if (useraddr) { 564 /* 565 * Yeah, this is a little on the kludgy 566 * side, but at least this code is only 567 * used for debugging. 568 */ 569 ti_bcopy_swap(tmparray, tmparray2, segsize, 570 TI_SWAP_NTOH); 571 572 if (first_pass) { 573 copyout(&tmparray2[segresid], ptr, 574 segsize - segresid); 575 first_pass = 0; 576 } else 577 copyout(tmparray2, ptr, segsize); 578 } else { 579 if (first_pass) { 580 581 ti_bcopy_swap(tmparray, tmparray2, 582 segsize, TI_SWAP_NTOH); 583 bcopy(&tmparray2[segresid], ptr, 584 segsize - segresid); 585 first_pass = 0; 586 } else 587 ti_bcopy_swap(tmparray, ptr, segsize, 588 TI_SWAP_NTOH); 589 } 590 591 } else { 592 if (useraddr) { 593 copyin(ptr, tmparray2, segsize); 594 ti_bcopy_swap(tmparray2, tmparray, segsize, 595 TI_SWAP_HTON); 596 } else 597 ti_bcopy_swap(ptr, tmparray, segsize, 598 TI_SWAP_HTON); 599 600 bus_space_write_region_4(sc->ti_btag, 601 sc->ti_bhandle, ti_offset, 602 (u_int32_t *)tmparray, 603 segsize >> 2); 604 } 605 segptr += segsize; 606 ptr += segsize; 607 cnt -= segsize; 608 } 609 610 /* 611 * Handle leftover, non-word-aligned bytes. 612 */ 613 if (resid != 0) { 614 u_int32_t tmpval, tmpval2; 615 bus_size_t ti_offset; 616 617 /* 618 * Set the segment pointer. 619 */ 620 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 621 622 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 623 624 /* 625 * First, grab whatever is in our source/destination. 626 * We'll obviously need this for reads, but also for 627 * writes, since we'll be doing read/modify/write. 628 */ 629 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 630 ti_offset, &tmpval, 1); 631 632 /* 633 * Next, translate this from little-endian to big-endian 634 * (at least on i386 boxes). 635 */ 636 tmpval2 = ntohl(tmpval); 637 638 if (readdata) { 639 /* 640 * If we're reading, just copy the leftover number 641 * of bytes from the host byte order buffer to 642 * the user's buffer. 643 */ 644 if (useraddr) 645 copyout(&tmpval2, ptr, resid); 646 else 647 bcopy(&tmpval2, ptr, resid); 648 } else { 649 /* 650 * If we're writing, first copy the bytes to be 651 * written into the network byte order buffer, 652 * leaving the rest of the buffer with whatever was 653 * originally in there. Then, swap the bytes 654 * around into host order and write them out. 655 * 656 * XXX KDM the read side of this has been verified 657 * to work, but the write side of it has not been 658 * verified. So user beware. 659 */ 660 if (useraddr) 661 copyin(ptr, &tmpval2, resid); 662 else 663 bcopy(ptr, &tmpval2, resid); 664 665 tmpval = htonl(tmpval2); 666 667 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 668 ti_offset, &tmpval, 1); 669 } 670 } 671 672 CSR_WRITE_4(sc, TI_WINBASE, origwin); 673 674 TI_UNLOCK(sc); 675 676 return(0); 677} 678 679static int 680ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 681 struct ti_softc *sc; 682 u_int32_t tigon_addr, len; 683 caddr_t buf; 684 int useraddr, readdata; 685 int cpu; 686{ 687 u_int32_t segptr; 688 int cnt; 689 u_int32_t tmpval, tmpval2; 690 caddr_t ptr; 691 692 /* 693 * At the moment, we don't handle non-aligned cases, we just bail. 694 * If this proves to be a problem, it will be fixed. 695 */ 696 if (tigon_addr & 0x3) { 697 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 698 "word-aligned\n", sc->ti_unit, tigon_addr); 699 return(EINVAL); 700 } 701 702 if (len & 0x3) { 703 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 704 "word-aligned\n", sc->ti_unit, len); 705 return(EINVAL); 706 } 707 708 segptr = tigon_addr; 709 cnt = len; 710 ptr = buf; 711 712 TI_LOCK(sc); 713 714 while (cnt) { 715 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 716 717 if (readdata) { 718 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 719 720 tmpval = ntohl(tmpval2); 721 722 /* 723 * Note: I've used this debugging interface 724 * extensively with Alteon's 12.3.15 firmware, 725 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 726 * 727 * When you compile the firmware without 728 * optimization, which is necessary sometimes in 729 * order to properly step through it, you sometimes 730 * read out a bogus value of 0xc0017c instead of 731 * whatever was supposed to be in that scratchpad 732 * location. That value is on the stack somewhere, 733 * but I've never been able to figure out what was 734 * causing the problem. 735 * 736 * The address seems to pop up in random places, 737 * often not in the same place on two subsequent 738 * reads. 739 * 740 * In any case, the underlying data doesn't seem 741 * to be affected, just the value read out. 742 * 743 * KDM, 3/7/2000 744 */ 745 746 if (tmpval2 == 0xc0017c) 747 printf("ti%d: found 0xc0017c at %#x " 748 "(tmpval2)\n", sc->ti_unit, segptr); 749 750 if (tmpval == 0xc0017c) 751 printf("ti%d: found 0xc0017c at %#x " 752 "(tmpval)\n", sc->ti_unit, segptr); 753 754 if (useraddr) 755 copyout(&tmpval, ptr, 4); 756 else 757 bcopy(&tmpval, ptr, 4); 758 } else { 759 if (useraddr) 760 copyin(ptr, &tmpval2, 4); 761 else 762 bcopy(ptr, &tmpval2, 4); 763 764 tmpval = htonl(tmpval2); 765 766 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 767 } 768 769 cnt -= 4; 770 segptr += 4; 771 ptr += 4; 772 } 773 774 TI_UNLOCK(sc); 775 776 return(0); 777} 778 779static int 780ti_bcopy_swap(src, dst, len, swap_type) 781 const void *src; 782 void *dst; 783 size_t len; 784 ti_swap_type swap_type; 785{ 786 const u_int8_t *tmpsrc; 787 u_int8_t *tmpdst; 788 size_t tmplen; 789 790 if (len & 0x3) { 791 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 792 len); 793 return(-1); 794 } 795 796 tmpsrc = src; 797 tmpdst = dst; 798 tmplen = len; 799 800 while (tmplen) { 801 if (swap_type == TI_SWAP_NTOH) 802 *(u_int32_t *)tmpdst = 803 ntohl(*(const u_int32_t *)tmpsrc); 804 else 805 *(u_int32_t *)tmpdst = 806 htonl(*(const u_int32_t *)tmpsrc); 807 808 tmpsrc += 4; 809 tmpdst += 4; 810 tmplen -= 4; 811 } 812 813 return(0); 814} 815 816/* 817 * Load firmware image into the NIC. Check that the firmware revision 818 * is acceptable and see if we want the firmware for the Tigon 1 or 819 * Tigon 2. 820 */ 821static void 822ti_loadfw(sc) 823 struct ti_softc *sc; 824{ 825 switch(sc->ti_hwrev) { 826 case TI_HWREV_TIGON: 827 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 828 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 829 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 830 printf("ti%d: firmware revision mismatch; want " 831 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 833 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 834 tigonFwReleaseMinor, tigonFwReleaseFix); 835 return; 836 } 837 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 838 (caddr_t)tigonFwText); 839 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 840 (caddr_t)tigonFwData); 841 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 842 (caddr_t)tigonFwRodata); 843 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 844 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 845 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 846 break; 847 case TI_HWREV_TIGON_II: 848 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 849 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 850 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 851 printf("ti%d: firmware revision mismatch; want " 852 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 853 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 854 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 855 tigon2FwReleaseMinor, tigon2FwReleaseFix); 856 return; 857 } 858 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 859 (caddr_t)tigon2FwText); 860 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 861 (caddr_t)tigon2FwData); 862 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 863 (caddr_t)tigon2FwRodata); 864 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 865 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 866 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 867 break; 868 default: 869 printf("ti%d: can't load firmware: unknown hardware rev\n", 870 sc->ti_unit); 871 break; 872 } 873 874 return; 875} 876 877/* 878 * Send the NIC a command via the command ring. 879 */ 880static void 881ti_cmd(sc, cmd) 882 struct ti_softc *sc; 883 struct ti_cmd_desc *cmd; 884{ 885 u_int32_t index; 886 887 if (sc->ti_rdata->ti_cmd_ring == NULL) 888 return; 889 890 index = sc->ti_cmd_saved_prodidx; 891 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 892 TI_INC(index, TI_CMD_RING_CNT); 893 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 894 sc->ti_cmd_saved_prodidx = index; 895 896 return; 897} 898 899/* 900 * Send the NIC an extended command. The 'len' parameter specifies the 901 * number of command slots to include after the initial command. 902 */ 903static void 904ti_cmd_ext(sc, cmd, arg, len) 905 struct ti_softc *sc; 906 struct ti_cmd_desc *cmd; 907 caddr_t arg; 908 int len; 909{ 910 u_int32_t index; 911 register int i; 912 913 if (sc->ti_rdata->ti_cmd_ring == NULL) 914 return; 915 916 index = sc->ti_cmd_saved_prodidx; 917 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 918 TI_INC(index, TI_CMD_RING_CNT); 919 for (i = 0; i < len; i++) { 920 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 921 *(u_int32_t *)(&arg[i * 4])); 922 TI_INC(index, TI_CMD_RING_CNT); 923 } 924 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 925 sc->ti_cmd_saved_prodidx = index; 926 927 return; 928} 929 930/* 931 * Handle events that have triggered interrupts. 932 */ 933static void 934ti_handle_events(sc) 935 struct ti_softc *sc; 936{ 937 struct ti_event_desc *e; 938 939 if (sc->ti_rdata->ti_event_ring == NULL) 940 return; 941 942 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 943 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 944 switch(e->ti_event) { 945 case TI_EV_LINKSTAT_CHANGED: 946 sc->ti_linkstat = e->ti_code; 947 if (e->ti_code == TI_EV_CODE_LINK_UP) 948 printf("ti%d: 10/100 link up\n", sc->ti_unit); 949 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 950 printf("ti%d: gigabit link up\n", sc->ti_unit); 951 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 952 printf("ti%d: link down\n", sc->ti_unit); 953 break; 954 case TI_EV_ERROR: 955 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 956 printf("ti%d: invalid command\n", sc->ti_unit); 957 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 958 printf("ti%d: unknown command\n", sc->ti_unit); 959 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 960 printf("ti%d: bad config data\n", sc->ti_unit); 961 break; 962 case TI_EV_FIRMWARE_UP: 963 ti_init2(sc); 964 break; 965 case TI_EV_STATS_UPDATED: 966 ti_stats_update(sc); 967 break; 968 case TI_EV_RESET_JUMBO_RING: 969 case TI_EV_MCAST_UPDATED: 970 /* Who cares. */ 971 break; 972 default: 973 printf("ti%d: unknown event: %d\n", 974 sc->ti_unit, e->ti_event); 975 break; 976 } 977 /* Advance the consumer index. */ 978 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 979 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 980 } 981 982 return; 983} 984 985#ifdef TI_PRIVATE_JUMBOS 986 987/* 988 * Memory management for the jumbo receive ring is a pain in the 989 * butt. We need to allocate at least 9018 bytes of space per frame, 990 * _and_ it has to be contiguous (unless you use the extended 991 * jumbo descriptor format). Using malloc() all the time won't 992 * work: malloc() allocates memory in powers of two, which means we 993 * would end up wasting a considerable amount of space by allocating 994 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 995 * to do our own memory management. 996 * 997 * The driver needs to allocate a contiguous chunk of memory at boot 998 * time. We then chop this up ourselves into 9K pieces and use them 999 * as external mbuf storage. 1000 * 1001 * One issue here is how much memory to allocate. The jumbo ring has 1002 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1003 * RAM. This is a bit much, especially considering we also need 1004 * RAM for the standard ring and mini ring (on the Tigon 2). To 1005 * save space, we only actually allocate enough memory for 64 slots 1006 * by default, which works out to between 500 and 600K. This can 1007 * be tuned by changing a #define in if_tireg.h. 1008 */ 1009 1010static int 1011ti_alloc_jumbo_mem(sc) 1012 struct ti_softc *sc; 1013{ 1014 caddr_t ptr; 1015 register int i; 1016 struct ti_jpool_entry *entry; 1017 1018 /* Grab a big chunk o' storage. */ 1019 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1020 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1021 1022 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1023 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1024 return(ENOBUFS); 1025 } 1026 1027 SLIST_INIT(&sc->ti_jfree_listhead); 1028 SLIST_INIT(&sc->ti_jinuse_listhead); 1029 1030 /* 1031 * Now divide it up into 9K pieces and save the addresses 1032 * in an array. 1033 */ 1034 ptr = sc->ti_cdata.ti_jumbo_buf; 1035 for (i = 0; i < TI_JSLOTS; i++) { 1036 sc->ti_cdata.ti_jslots[i] = ptr; 1037 ptr += TI_JLEN; 1038 entry = malloc(sizeof(struct ti_jpool_entry), 1039 M_DEVBUF, M_NOWAIT); 1040 if (entry == NULL) { 1041 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1042 M_DEVBUF); 1043 sc->ti_cdata.ti_jumbo_buf = NULL; 1044 printf("ti%d: no memory for jumbo " 1045 "buffer queue!\n", sc->ti_unit); 1046 return(ENOBUFS); 1047 } 1048 entry->slot = i; 1049 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1050 } 1051 1052 return(0); 1053} 1054 1055/* 1056 * Allocate a jumbo buffer. 1057 */ 1058static void *ti_jalloc(sc) 1059 struct ti_softc *sc; 1060{ 1061 struct ti_jpool_entry *entry; 1062 1063 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1064 1065 if (entry == NULL) { 1066 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1067 return(NULL); 1068 } 1069 1070 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1071 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1072 return(sc->ti_cdata.ti_jslots[entry->slot]); 1073} 1074 1075/* 1076 * Release a jumbo buffer. 1077 */ 1078static void 1079ti_jfree(buf, args) 1080 void *buf; 1081 void *args; 1082{ 1083 struct ti_softc *sc; 1084 int i; 1085 struct ti_jpool_entry *entry; 1086 1087 /* Extract the softc struct pointer. */ 1088 sc = (struct ti_softc *)args; 1089 1090 if (sc == NULL) 1091 panic("ti_jfree: didn't get softc pointer!"); 1092 1093 /* calculate the slot this buffer belongs to */ 1094 i = ((vm_offset_t)buf 1095 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1096 1097 if ((i < 0) || (i >= TI_JSLOTS)) 1098 panic("ti_jfree: asked to free buffer that we don't manage!"); 1099 1100 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1101 if (entry == NULL) 1102 panic("ti_jfree: buffer not in use!"); 1103 entry->slot = i; 1104 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1105 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1106 1107 return; 1108} 1109 1110#endif /* TI_PRIVATE_JUMBOS */ 1111 1112/* 1113 * Intialize a standard receive ring descriptor. 1114 */ 1115static int 1116ti_newbuf_std(sc, i, m) 1117 struct ti_softc *sc; 1118 int i; 1119 struct mbuf *m; 1120{ 1121 struct mbuf *m_new = NULL; 1122 struct ti_rx_desc *r; 1123 1124 if (m == NULL) { 1125 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1126 if (m_new == NULL) 1127 return(ENOBUFS); 1128 1129 MCLGET(m_new, M_DONTWAIT); 1130 if (!(m_new->m_flags & M_EXT)) { 1131 m_freem(m_new); 1132 return(ENOBUFS); 1133 } 1134 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1135 } else { 1136 m_new = m; 1137 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1138 m_new->m_data = m_new->m_ext.ext_buf; 1139 } 1140 1141 m_adj(m_new, ETHER_ALIGN); 1142 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1143 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1144 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1145 r->ti_type = TI_BDTYPE_RECV_BD; 1146 r->ti_flags = 0; 1147 if (sc->arpcom.ac_if.if_hwassist) 1148 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1149 r->ti_len = m_new->m_len; 1150 r->ti_idx = i; 1151 1152 return(0); 1153} 1154 1155/* 1156 * Intialize a mini receive ring descriptor. This only applies to 1157 * the Tigon 2. 1158 */ 1159static int 1160ti_newbuf_mini(sc, i, m) 1161 struct ti_softc *sc; 1162 int i; 1163 struct mbuf *m; 1164{ 1165 struct mbuf *m_new = NULL; 1166 struct ti_rx_desc *r; 1167 1168 if (m == NULL) { 1169 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1170 if (m_new == NULL) { 1171 return(ENOBUFS); 1172 } 1173 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1174 } else { 1175 m_new = m; 1176 m_new->m_data = m_new->m_pktdat; 1177 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1178 } 1179 1180 m_adj(m_new, ETHER_ALIGN); 1181 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1182 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1183 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1184 r->ti_type = TI_BDTYPE_RECV_BD; 1185 r->ti_flags = TI_BDFLAG_MINI_RING; 1186 if (sc->arpcom.ac_if.if_hwassist) 1187 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1188 r->ti_len = m_new->m_len; 1189 r->ti_idx = i; 1190 1191 return(0); 1192} 1193 1194#ifdef TI_PRIVATE_JUMBOS 1195 1196/* 1197 * Initialize a jumbo receive ring descriptor. This allocates 1198 * a jumbo buffer from the pool managed internally by the driver. 1199 */ 1200static int 1201ti_newbuf_jumbo(sc, i, m) 1202 struct ti_softc *sc; 1203 int i; 1204 struct mbuf *m; 1205{ 1206 struct mbuf *m_new = NULL; 1207 struct ti_rx_desc *r; 1208 1209 if (m == NULL) { 1210 caddr_t *buf = NULL; 1211 1212 /* Allocate the mbuf. */ 1213 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1214 if (m_new == NULL) { 1215 return(ENOBUFS); 1216 } 1217 1218 /* Allocate the jumbo buffer */ 1219 buf = ti_jalloc(sc); 1220 if (buf == NULL) { 1221 m_freem(m_new); 1222 printf("ti%d: jumbo allocation failed " 1223 "-- packet dropped!\n", sc->ti_unit); 1224 return(ENOBUFS); 1225 } 1226 1227 /* Attach the buffer to the mbuf. */ 1228 m_new->m_data = (void *) buf; 1229 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1230 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1231 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1232 } else { 1233 m_new = m; 1234 m_new->m_data = m_new->m_ext.ext_buf; 1235 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1236 } 1237 1238 m_adj(m_new, ETHER_ALIGN); 1239 /* Set up the descriptor. */ 1240 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1241 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1242 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1243 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1244 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1245 if (sc->arpcom.ac_if.if_hwassist) 1246 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1247 r->ti_len = m_new->m_len; 1248 r->ti_idx = i; 1249 1250 return(0); 1251} 1252 1253#else 1254#include <vm/vm_page.h> 1255 1256#if (PAGE_SIZE == 4096) 1257#define NPAYLOAD 2 1258#else 1259#define NPAYLOAD 1 1260#endif 1261 1262#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1263#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1264#define NFS_HDR_LEN (UDP_HDR_LEN) 1265static int HDR_LEN = TCP_HDR_LEN; 1266 1267 1268 /* 1269 * Initialize a jumbo receive ring descriptor. This allocates 1270 * a jumbo buffer from the pool managed internally by the driver. 1271 */ 1272static int 1273ti_newbuf_jumbo(sc, idx, m_old) 1274 struct ti_softc *sc; 1275 int idx; 1276 struct mbuf *m_old; 1277{ 1278 struct mbuf *cur, *m_new = NULL; 1279 struct mbuf *m[3] = {NULL, NULL, NULL}; 1280 struct ti_rx_desc_ext *r; 1281 vm_page_t frame; 1282 /* 1 extra buf to make nobufs easy*/ 1283 caddr_t buf[3] = {NULL, NULL, NULL}; 1284 int i; 1285 1286 if (m_old != NULL) { 1287 m_new = m_old; 1288 cur = m_old->m_next; 1289 for (i = 0; i <= NPAYLOAD; i++){ 1290 m[i] = cur; 1291 cur = cur->m_next; 1292 } 1293 } else { 1294 /* Allocate the mbufs. */ 1295 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1296 if (m_new == NULL) { 1297 printf("ti%d: mbuf allocation failed " 1298 "-- packet dropped!\n", sc->ti_unit); 1299 goto nobufs; 1300 } 1301 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1302 if (m[NPAYLOAD] == NULL) { 1303 printf("ti%d: cluster mbuf allocation failed " 1304 "-- packet dropped!\n", sc->ti_unit); 1305 goto nobufs; 1306 } 1307 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1308 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1309 printf("ti%d: mbuf allocation failed " 1310 "-- packet dropped!\n", sc->ti_unit); 1311 goto nobufs; 1312 } 1313 m[NPAYLOAD]->m_len = MCLBYTES; 1314 1315 for (i = 0; i < NPAYLOAD; i++){ 1316 MGET(m[i], M_DONTWAIT, MT_DATA); 1317 if (m[i] == NULL) { 1318 printf("ti%d: mbuf allocation failed " 1319 "-- packet dropped!\n", sc->ti_unit); 1320 goto nobufs; 1321 } 1322 if (!(frame = jumbo_pg_alloc())){ 1323 printf("ti%d: buffer allocation failed " 1324 "-- packet dropped!\n", sc->ti_unit); 1325 printf(" index %d page %d\n", idx, i); 1326 goto nobufs; 1327 } 1328 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1329 } 1330 for (i = 0; i < NPAYLOAD; i++){ 1331 /* Attach the buffer to the mbuf. */ 1332 m[i]->m_data = (void *)buf[i]; 1333 m[i]->m_len = PAGE_SIZE; 1334 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1335 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1336 m[i]->m_next = m[i+1]; 1337 } 1338 /* link the buffers to the header */ 1339 m_new->m_next = m[0]; 1340 m_new->m_data += ETHER_ALIGN; 1341 if (sc->ti_hdrsplit) 1342 m_new->m_len = MHLEN - ETHER_ALIGN; 1343 else 1344 m_new->m_len = HDR_LEN; 1345 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1346 } 1347 1348 /* Set up the descriptor. */ 1349 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1350 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1351 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1352 r->ti_len0 = m_new->m_len; 1353 1354 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1355 r->ti_len1 = PAGE_SIZE; 1356 1357 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1358 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1359 1360 if (PAGE_SIZE == 4096) { 1361 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1362 r->ti_len3 = MCLBYTES; 1363 } else { 1364 r->ti_len3 = 0; 1365 } 1366 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1367 1368 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1369 1370 if (sc->arpcom.ac_if.if_hwassist) 1371 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1372 1373 r->ti_idx = idx; 1374 1375 return(0); 1376 1377 nobufs: 1378 1379 /* 1380 * Warning! : 1381 * This can only be called before the mbufs are strung together. 1382 * If the mbufs are strung together, m_freem() will free the chain, 1383 * so that the later mbufs will be freed multiple times. 1384 */ 1385 if (m_new) 1386 m_freem(m_new); 1387 1388 for(i = 0; i < 3; i++){ 1389 if (m[i]) 1390 m_freem(m[i]); 1391 if (buf[i]) 1392 jumbo_pg_free((vm_offset_t)buf[i]); 1393 } 1394 return ENOBUFS; 1395} 1396#endif 1397 1398 1399 1400/* 1401 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1402 * that's 1MB or memory, which is a lot. For now, we fill only the first 1403 * 256 ring entries and hope that our CPU is fast enough to keep up with 1404 * the NIC. 1405 */ 1406static int 1407ti_init_rx_ring_std(sc) 1408 struct ti_softc *sc; 1409{ 1410 register int i; 1411 struct ti_cmd_desc cmd; 1412 1413 for (i = 0; i < TI_SSLOTS; i++) { 1414 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1415 return(ENOBUFS); 1416 }; 1417 1418 TI_UPDATE_STDPROD(sc, i - 1); 1419 sc->ti_std = i - 1; 1420 1421 return(0); 1422} 1423 1424static void 1425ti_free_rx_ring_std(sc) 1426 struct ti_softc *sc; 1427{ 1428 register int i; 1429 1430 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1431 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1432 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1433 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1434 } 1435 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1436 sizeof(struct ti_rx_desc)); 1437 } 1438 1439 return; 1440} 1441 1442static int 1443ti_init_rx_ring_jumbo(sc) 1444 struct ti_softc *sc; 1445{ 1446 register int i; 1447 struct ti_cmd_desc cmd; 1448 1449 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1450 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1451 return(ENOBUFS); 1452 }; 1453 1454 TI_UPDATE_JUMBOPROD(sc, i - 1); 1455 sc->ti_jumbo = i - 1; 1456 1457 return(0); 1458} 1459 1460static void 1461ti_free_rx_ring_jumbo(sc) 1462 struct ti_softc *sc; 1463{ 1464 register int i; 1465 1466 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1467 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1468 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1469 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1470 } 1471 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1472 sizeof(struct ti_rx_desc)); 1473 } 1474 1475 return; 1476} 1477 1478static int 1479ti_init_rx_ring_mini(sc) 1480 struct ti_softc *sc; 1481{ 1482 register int i; 1483 1484 for (i = 0; i < TI_MSLOTS; i++) { 1485 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1486 return(ENOBUFS); 1487 }; 1488 1489 TI_UPDATE_MINIPROD(sc, i - 1); 1490 sc->ti_mini = i - 1; 1491 1492 return(0); 1493} 1494 1495static void 1496ti_free_rx_ring_mini(sc) 1497 struct ti_softc *sc; 1498{ 1499 register int i; 1500 1501 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1502 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1503 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1504 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1505 } 1506 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1507 sizeof(struct ti_rx_desc)); 1508 } 1509 1510 return; 1511} 1512 1513static void 1514ti_free_tx_ring(sc) 1515 struct ti_softc *sc; 1516{ 1517 register int i; 1518 1519 if (sc->ti_rdata->ti_tx_ring == NULL) 1520 return; 1521 1522 for (i = 0; i < TI_TX_RING_CNT; i++) { 1523 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1524 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1525 sc->ti_cdata.ti_tx_chain[i] = NULL; 1526 } 1527 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1528 sizeof(struct ti_tx_desc)); 1529 } 1530 1531 return; 1532} 1533 1534static int 1535ti_init_tx_ring(sc) 1536 struct ti_softc *sc; 1537{ 1538 sc->ti_txcnt = 0; 1539 sc->ti_tx_saved_considx = 0; 1540 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1541 return(0); 1542} 1543 1544/* 1545 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1546 * but we have to support the old way too so that Tigon 1 cards will 1547 * work. 1548 */ 1549static void 1550ti_add_mcast(sc, addr) 1551 struct ti_softc *sc; 1552 struct ether_addr *addr; 1553{ 1554 struct ti_cmd_desc cmd; 1555 u_int16_t *m; 1556 u_int32_t ext[2] = {0, 0}; 1557 1558 m = (u_int16_t *)&addr->octet[0]; 1559 1560 switch(sc->ti_hwrev) { 1561 case TI_HWREV_TIGON: 1562 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1563 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1564 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1565 break; 1566 case TI_HWREV_TIGON_II: 1567 ext[0] = htons(m[0]); 1568 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1569 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1570 break; 1571 default: 1572 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1573 break; 1574 } 1575 1576 return; 1577} 1578 1579static void 1580ti_del_mcast(sc, addr) 1581 struct ti_softc *sc; 1582 struct ether_addr *addr; 1583{ 1584 struct ti_cmd_desc cmd; 1585 u_int16_t *m; 1586 u_int32_t ext[2] = {0, 0}; 1587 1588 m = (u_int16_t *)&addr->octet[0]; 1589 1590 switch(sc->ti_hwrev) { 1591 case TI_HWREV_TIGON: 1592 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1593 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1594 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1595 break; 1596 case TI_HWREV_TIGON_II: 1597 ext[0] = htons(m[0]); 1598 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1599 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1600 break; 1601 default: 1602 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1603 break; 1604 } 1605 1606 return; 1607} 1608 1609/* 1610 * Configure the Tigon's multicast address filter. 1611 * 1612 * The actual multicast table management is a bit of a pain, thanks to 1613 * slight brain damage on the part of both Alteon and us. With our 1614 * multicast code, we are only alerted when the multicast address table 1615 * changes and at that point we only have the current list of addresses: 1616 * we only know the current state, not the previous state, so we don't 1617 * actually know what addresses were removed or added. The firmware has 1618 * state, but we can't get our grubby mits on it, and there is no 'delete 1619 * all multicast addresses' command. Hence, we have to maintain our own 1620 * state so we know what addresses have been programmed into the NIC at 1621 * any given time. 1622 */ 1623static void 1624ti_setmulti(sc) 1625 struct ti_softc *sc; 1626{ 1627 struct ifnet *ifp; 1628 struct ifmultiaddr *ifma; 1629 struct ti_cmd_desc cmd; 1630 struct ti_mc_entry *mc; 1631 u_int32_t intrs; 1632 1633 ifp = &sc->arpcom.ac_if; 1634 1635 if (ifp->if_flags & IFF_ALLMULTI) { 1636 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1637 return; 1638 } else { 1639 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1640 } 1641 1642 /* Disable interrupts. */ 1643 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1644 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1645 1646 /* First, zot all the existing filters. */ 1647 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1648 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1649 ti_del_mcast(sc, &mc->mc_addr); 1650 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1651 free(mc, M_DEVBUF); 1652 } 1653 1654 /* Now program new ones. */ 1655 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1656 if (ifma->ifma_addr->sa_family != AF_LINK) 1657 continue; 1658 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1659 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1660 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1661 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1662 ti_add_mcast(sc, &mc->mc_addr); 1663 } 1664 1665 /* Re-enable interrupts. */ 1666 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1667 1668 return; 1669} 1670 1671/* 1672 * Check to see if the BIOS has configured us for a 64 bit slot when 1673 * we aren't actually in one. If we detect this condition, we can work 1674 * around it on the Tigon 2 by setting a bit in the PCI state register, 1675 * but for the Tigon 1 we must give up and abort the interface attach. 1676 */ 1677static int ti_64bitslot_war(sc) 1678 struct ti_softc *sc; 1679{ 1680 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1681 CSR_WRITE_4(sc, 0x600, 0); 1682 CSR_WRITE_4(sc, 0x604, 0); 1683 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1684 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1685 if (sc->ti_hwrev == TI_HWREV_TIGON) 1686 return(EINVAL); 1687 else { 1688 TI_SETBIT(sc, TI_PCI_STATE, 1689 TI_PCISTATE_32BIT_BUS); 1690 return(0); 1691 } 1692 } 1693 } 1694 1695 return(0); 1696} 1697 1698/* 1699 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1700 * self-test results. 1701 */ 1702static int 1703ti_chipinit(sc) 1704 struct ti_softc *sc; 1705{ 1706 u_int32_t cacheline; 1707 u_int32_t pci_writemax = 0; 1708 u_int32_t hdrsplit; 1709 1710 /* Initialize link to down state. */ 1711 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1712 1713 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1714 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1715 else 1716 sc->arpcom.ac_if.if_hwassist = 0; 1717 1718 /* Set endianness before we access any non-PCI registers. */ 1719#if BYTE_ORDER == BIG_ENDIAN 1720 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1721 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1722#else 1723 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1724 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1725#endif 1726 1727 /* Check the ROM failed bit to see if self-tests passed. */ 1728 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1729 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1730 return(ENODEV); 1731 } 1732 1733 /* Halt the CPU. */ 1734 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1735 1736 /* Figure out the hardware revision. */ 1737 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1738 case TI_REV_TIGON_I: 1739 sc->ti_hwrev = TI_HWREV_TIGON; 1740 break; 1741 case TI_REV_TIGON_II: 1742 sc->ti_hwrev = TI_HWREV_TIGON_II; 1743 break; 1744 default: 1745 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1746 return(ENODEV); 1747 } 1748 1749 /* Do special setup for Tigon 2. */ 1750 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1751 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1752 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1753 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1754 } 1755 1756 /* 1757 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1758 * can't do header splitting. 1759 */ 1760#ifdef TI_JUMBO_HDRSPLIT 1761 if (sc->ti_hwrev != TI_HWREV_TIGON) 1762 sc->ti_hdrsplit = 1; 1763 else 1764 printf("ti%d: can't do header splitting on a Tigon I board\n", 1765 sc->ti_unit); 1766#endif /* TI_JUMBO_HDRSPLIT */ 1767 1768 /* Set up the PCI state register. */ 1769 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1770 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1771 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1772 } 1773 1774 /* Clear the read/write max DMA parameters. */ 1775 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1776 TI_PCISTATE_READ_MAXDMA)); 1777 1778 /* Get cache line size. */ 1779 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1780 1781 /* 1782 * If the system has set enabled the PCI memory write 1783 * and invalidate command in the command register, set 1784 * the write max parameter accordingly. This is necessary 1785 * to use MWI with the Tigon 2. 1786 */ 1787 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1788 switch(cacheline) { 1789 case 1: 1790 case 4: 1791 case 8: 1792 case 16: 1793 case 32: 1794 case 64: 1795 break; 1796 default: 1797 /* Disable PCI memory write and invalidate. */ 1798 if (bootverbose) 1799 printf("ti%d: cache line size %d not " 1800 "supported; disabling PCI MWI\n", 1801 sc->ti_unit, cacheline); 1802 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1803 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1804 break; 1805 } 1806 } 1807 1808#ifdef __brokenalpha__ 1809 /* 1810 * From the Alteon sample driver: 1811 * Must insure that we do not cross an 8K (bytes) boundary 1812 * for DMA reads. Our highest limit is 1K bytes. This is a 1813 * restriction on some ALPHA platforms with early revision 1814 * 21174 PCI chipsets, such as the AlphaPC 164lx 1815 */ 1816 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1817#else 1818 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1819#endif 1820 1821 /* This sets the min dma param all the way up (0xff). */ 1822 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1823 1824 if (sc->ti_hdrsplit) 1825 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1826 else 1827 hdrsplit = 0; 1828 1829 /* Configure DMA variables. */ 1830#if BYTE_ORDER == BIG_ENDIAN 1831 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1832 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1833 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1834 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1835#else /* BYTE_ORDER */ 1836 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1837 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1838 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1839#endif /* BYTE_ORDER */ 1840 1841 /* 1842 * Only allow 1 DMA channel to be active at a time. 1843 * I don't think this is a good idea, but without it 1844 * the firmware racks up lots of nicDmaReadRingFull 1845 * errors. This is not compatible with hardware checksums. 1846 */ 1847 if (sc->arpcom.ac_if.if_hwassist == 0) 1848 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1849 1850 /* Recommended settings from Tigon manual. */ 1851 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1852 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1853 1854 if (ti_64bitslot_war(sc)) { 1855 printf("ti%d: bios thinks we're in a 64 bit slot, " 1856 "but we aren't", sc->ti_unit); 1857 return(EINVAL); 1858 } 1859 1860 return(0); 1861} 1862 1863/* 1864 * Initialize the general information block and firmware, and 1865 * start the CPU(s) running. 1866 */ 1867static int 1868ti_gibinit(sc) 1869 struct ti_softc *sc; 1870{ 1871 struct ti_rcb *rcb; 1872 int i; 1873 struct ifnet *ifp; 1874 1875 ifp = &sc->arpcom.ac_if; 1876 1877 /* Disable interrupts for now. */ 1878 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1879 1880 /* Tell the chip where to find the general information block. */ 1881 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1882 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1883 1884 /* Load the firmware into SRAM. */ 1885 ti_loadfw(sc); 1886 1887 /* Set up the contents of the general info and ring control blocks. */ 1888 1889 /* Set up the event ring and producer pointer. */ 1890 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1891 1892 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1893 rcb->ti_flags = 0; 1894 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1895 vtophys(&sc->ti_ev_prodidx); 1896 sc->ti_ev_prodidx.ti_idx = 0; 1897 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1898 sc->ti_ev_saved_considx = 0; 1899 1900 /* Set up the command ring and producer mailbox. */ 1901 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1902 1903 sc->ti_rdata->ti_cmd_ring = 1904 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1905 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1906 rcb->ti_flags = 0; 1907 rcb->ti_max_len = 0; 1908 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1909 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1910 } 1911 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1912 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1913 sc->ti_cmd_saved_prodidx = 0; 1914 1915 /* 1916 * Assign the address of the stats refresh buffer. 1917 * We re-use the current stats buffer for this to 1918 * conserve memory. 1919 */ 1920 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1921 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1922 1923 /* Set up the standard receive ring. */ 1924 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1925 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1926 rcb->ti_max_len = TI_FRAMELEN; 1927 rcb->ti_flags = 0; 1928 if (sc->arpcom.ac_if.if_hwassist) 1929 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1930 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1931 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1932 1933 /* Set up the jumbo receive ring. */ 1934 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1935 TI_HOSTADDR(rcb->ti_hostaddr) = 1936 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1937 1938#ifdef TI_PRIVATE_JUMBOS 1939 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1940 rcb->ti_flags = 0; 1941#else 1942 rcb->ti_max_len = PAGE_SIZE; 1943 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1944#endif 1945 if (sc->arpcom.ac_if.if_hwassist) 1946 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1947 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1948 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1949 1950 /* 1951 * Set up the mini ring. Only activated on the 1952 * Tigon 2 but the slot in the config block is 1953 * still there on the Tigon 1. 1954 */ 1955 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1956 TI_HOSTADDR(rcb->ti_hostaddr) = 1957 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1958 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1959 if (sc->ti_hwrev == TI_HWREV_TIGON) 1960 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1961 else 1962 rcb->ti_flags = 0; 1963 if (sc->arpcom.ac_if.if_hwassist) 1964 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1965 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1966 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1967 1968 /* 1969 * Set up the receive return ring. 1970 */ 1971 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1972 TI_HOSTADDR(rcb->ti_hostaddr) = 1973 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1974 rcb->ti_flags = 0; 1975 rcb->ti_max_len = TI_RETURN_RING_CNT; 1976 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1977 vtophys(&sc->ti_return_prodidx); 1978 1979 /* 1980 * Set up the tx ring. Note: for the Tigon 2, we have the option 1981 * of putting the transmit ring in the host's address space and 1982 * letting the chip DMA it instead of leaving the ring in the NIC's 1983 * memory and accessing it through the shared memory region. We 1984 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1985 * so we have to revert to the shared memory scheme if we detect 1986 * a Tigon 1 chip. 1987 */ 1988 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1989 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1990 sc->ti_rdata->ti_tx_ring_nic = 1991 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1992 } 1993 bzero((char *)sc->ti_rdata->ti_tx_ring, 1994 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1995 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1996 if (sc->ti_hwrev == TI_HWREV_TIGON) 1997 rcb->ti_flags = 0; 1998 else 1999 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2000 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2001 if (sc->arpcom.ac_if.if_hwassist) 2002 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2003 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2004 rcb->ti_max_len = TI_TX_RING_CNT; 2005 if (sc->ti_hwrev == TI_HWREV_TIGON) 2006 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2007 else 2008 TI_HOSTADDR(rcb->ti_hostaddr) = 2009 vtophys(&sc->ti_rdata->ti_tx_ring); 2010 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2011 vtophys(&sc->ti_tx_considx); 2012 2013 /* Set up tuneables */ 2014#if 0 2015 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2016 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2017 (sc->ti_rx_coal_ticks / 10)); 2018 else 2019#endif 2020 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2021 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2022 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2023 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2024 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2025 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2026 2027 /* Turn interrupts on. */ 2028 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2029 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2030 2031 /* Start CPU. */ 2032 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2033 2034 return(0); 2035} 2036 2037/* 2038 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2039 * against our list and return its name if we find a match. 2040 */ 2041static int 2042ti_probe(dev) 2043 device_t dev; 2044{ 2045 struct ti_type *t; 2046 2047 t = ti_devs; 2048 2049 while(t->ti_name != NULL) { 2050 if ((pci_get_vendor(dev) == t->ti_vid) && 2051 (pci_get_device(dev) == t->ti_did)) { 2052 device_set_desc(dev, t->ti_name); 2053 return(0); 2054 } 2055 t++; 2056 } 2057 2058 return(ENXIO); 2059} 2060 2061#ifdef KLD_MODULE 2062static int 2063log2rndup(int len) 2064{ 2065 int log2size = 0, t = len; 2066 while (t > 1) { 2067 log2size++; 2068 t >>= 1; 2069 } 2070 if (len != (1 << log2size)) 2071 log2size++; 2072 return log2size; 2073} 2074 2075static int 2076ti_mbuf_sanity(device_t dev) 2077{ 2078 if ((mbstat.m_msize != MSIZE) || mbstat.m_mclbytes != MCLBYTES){ 2079 device_printf(dev, "\n"); 2080 device_printf(dev, "This module was compiled with " 2081 "-DMCLSHIFT=%d -DMSIZE=%d\n", MCLSHIFT, 2082 MSIZE); 2083 device_printf(dev, "The kernel was compiled with MCLSHIFT=%d," 2084 " MSIZE=%d\n", log2rndup(mbstat.m_mclbytes), 2085 (int)mbstat.m_msize); 2086 return(EINVAL); 2087 } 2088 return(0); 2089} 2090#endif 2091 2092 2093static int 2094ti_attach(dev) 2095 device_t dev; 2096{ 2097 u_int32_t command; 2098 struct ifnet *ifp; 2099 struct ti_softc *sc; 2100 int unit, error = 0, rid; 2101 2102 sc = NULL; 2103 2104#ifdef KLD_MODULE 2105 if (ti_mbuf_sanity(dev)){ 2106 device_printf(dev, "Module mbuf constants do not match " 2107 "kernel constants!\n"); 2108 device_printf(dev, "Rebuild the module or the kernel so " 2109 "they match\n"); 2110 device_printf(dev, "\n"); 2111 error = EINVAL; 2112 goto fail; 2113 } 2114#endif 2115 2116 sc = device_get_softc(dev); 2117 unit = device_get_unit(dev); 2118 bzero(sc, sizeof(struct ti_softc)); 2119 2120 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2121 MTX_DEF | MTX_RECURSE); 2122 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 2123 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2124 2125 /* 2126 * Map control/status registers. 2127 */ 2128 pci_enable_busmaster(dev); 2129 pci_enable_io(dev, SYS_RES_MEMORY); 2130 command = pci_read_config(dev, PCIR_COMMAND, 4); 2131 2132 if (!(command & PCIM_CMD_MEMEN)) { 2133 printf("ti%d: failed to enable memory mapping!\n", unit); 2134 error = ENXIO; 2135 goto fail; 2136 } 2137 2138 rid = TI_PCI_LOMEM; 2139 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2140 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2141 2142 if (sc->ti_res == NULL) { 2143 printf ("ti%d: couldn't map memory\n", unit); 2144 error = ENXIO; 2145 goto fail; 2146 } 2147 2148 sc->ti_btag = rman_get_bustag(sc->ti_res); 2149 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2150 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2151 2152 /* Allocate interrupt */ 2153 rid = 0; 2154 2155 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2156 RF_SHAREABLE | RF_ACTIVE); 2157 2158 if (sc->ti_irq == NULL) { 2159 printf("ti%d: couldn't map interrupt\n", unit); 2160 error = ENXIO; 2161 goto fail; 2162 } 2163 2164 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2165 ti_intr, sc, &sc->ti_intrhand); 2166 2167 if (error) { 2168 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2169 bus_release_resource(dev, SYS_RES_MEMORY, 2170 TI_PCI_LOMEM, sc->ti_res); 2171 printf("ti%d: couldn't set up irq\n", unit); 2172 goto fail; 2173 } 2174 2175 sc->ti_unit = unit; 2176 2177 if (ti_chipinit(sc)) { 2178 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2179 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2180 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2181 bus_release_resource(dev, SYS_RES_MEMORY, 2182 TI_PCI_LOMEM, sc->ti_res); 2183 error = ENXIO; 2184 goto fail; 2185 } 2186 2187 /* Zero out the NIC's on-board SRAM. */ 2188 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2189 2190 /* Init again -- zeroing memory may have clobbered some registers. */ 2191 if (ti_chipinit(sc)) { 2192 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2193 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2194 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2195 bus_release_resource(dev, SYS_RES_MEMORY, 2196 TI_PCI_LOMEM, sc->ti_res); 2197 error = ENXIO; 2198 goto fail; 2199 } 2200 2201 /* 2202 * Get station address from the EEPROM. Note: the manual states 2203 * that the MAC address is at offset 0x8c, however the data is 2204 * stored as two longwords (since that's how it's loaded into 2205 * the NIC). This means the MAC address is actually preceded 2206 * by two zero bytes. We need to skip over those. 2207 */ 2208 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2209 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2210 printf("ti%d: failed to read station address\n", unit); 2211 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2213 bus_release_resource(dev, SYS_RES_MEMORY, 2214 TI_PCI_LOMEM, sc->ti_res); 2215 error = ENXIO; 2216 goto fail; 2217 } 2218 2219 /* 2220 * A Tigon chip was detected. Inform the world. 2221 */ 2222 printf("ti%d: Ethernet address: %6D\n", unit, 2223 sc->arpcom.ac_enaddr, ":"); 2224 2225 /* Allocate the general information block and ring buffers. */ 2226 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2227 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2228 2229 if (sc->ti_rdata == NULL) { 2230 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2231 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2232 bus_release_resource(dev, SYS_RES_MEMORY, 2233 TI_PCI_LOMEM, sc->ti_res); 2234 error = ENXIO; 2235 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2236 goto fail; 2237 } 2238 2239 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2240 2241 /* Try to allocate memory for jumbo buffers. */ 2242#ifdef TI_PRIVATE_JUMBOS 2243 if (ti_alloc_jumbo_mem(sc)) { 2244 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2245 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2246 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2247 bus_release_resource(dev, SYS_RES_MEMORY, 2248 TI_PCI_LOMEM, sc->ti_res); 2249 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 2250 M_DEVBUF); 2251 error = ENXIO; 2252 goto fail; 2253 } 2254#else 2255 if (!jumbo_vm_init()) { 2256 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2257 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2258 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2259 bus_release_resource(dev, SYS_RES_MEMORY, 2260 TI_PCI_LOMEM, sc->ti_res); 2261 free(sc->ti_rdata, M_DEVBUF); 2262 error = ENOMEM; 2263 goto fail; 2264 } 2265#endif 2266 2267 /* 2268 * We really need a better way to tell a 1000baseTX card 2269 * from a 1000baseSX one, since in theory there could be 2270 * OEMed 1000baseTX cards from lame vendors who aren't 2271 * clever enough to change the PCI ID. For the moment 2272 * though, the AceNIC is the only copper card available. 2273 */ 2274 if (pci_get_vendor(dev) == ALT_VENDORID && 2275 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2276 sc->ti_copper = 1; 2277 /* Ok, it's not the only copper card available. */ 2278 if (pci_get_vendor(dev) == NG_VENDORID && 2279 pci_get_device(dev) == NG_DEVICEID_GA620T) 2280 sc->ti_copper = 1; 2281 2282 /* Set default tuneable values. */ 2283 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2284#if 0 2285 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2286#endif 2287 sc->ti_rx_coal_ticks = 170; 2288 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2289 sc->ti_rx_max_coal_bds = 64; 2290#if 0 2291 sc->ti_tx_max_coal_bds = 128; 2292#endif 2293 sc->ti_tx_max_coal_bds = 32; 2294 sc->ti_tx_buf_ratio = 21; 2295 2296 /* Set up ifnet structure */ 2297 ifp = &sc->arpcom.ac_if; 2298 ifp->if_softc = sc; 2299 ifp->if_unit = sc->ti_unit; 2300 ifp->if_name = "ti"; 2301 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2302 tis[unit] = sc; 2303 ifp->if_ioctl = ti_ioctl; 2304 ifp->if_output = ether_output; 2305 ifp->if_start = ti_start; 2306 ifp->if_watchdog = ti_watchdog; 2307 ifp->if_init = ti_init; 2308 ifp->if_mtu = ETHERMTU; 2309 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2310 2311 /* Set up ifmedia support. */ 2312 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2313 if (sc->ti_copper) { 2314 /* 2315 * Copper cards allow manual 10/100 mode selection, 2316 * but not manual 1000baseTX mode selection. Why? 2317 * Becuase currently there's no way to specify the 2318 * master/slave setting through the firmware interface, 2319 * so Alteon decided to just bag it and handle it 2320 * via autonegotiation. 2321 */ 2322 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2323 ifmedia_add(&sc->ifmedia, 2324 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2325 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2326 ifmedia_add(&sc->ifmedia, 2327 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2328 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2329 ifmedia_add(&sc->ifmedia, 2330 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2331 } else { 2332 /* Fiber cards don't support 10/100 modes. */ 2333 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2334 ifmedia_add(&sc->ifmedia, 2335 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2336 } 2337 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2338 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2339 2340 /* 2341 * We're assuming here that card initialization is a sequential 2342 * thing. If it isn't, multiple cards probing at the same time 2343 * could stomp on the list of softcs here. 2344 */ 2345 /* 2346 * If this is the first card to be initialized, initialize the 2347 * softc queue. 2348 */ 2349 if (unit == 0) 2350 STAILQ_INIT(&ti_sc_list); 2351 2352 STAILQ_INSERT_TAIL(&ti_sc_list, sc, ti_links); 2353 2354 /* Register the device */ 2355 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2356 0600, "ti%d", sc->ti_unit); 2357 2358 /* 2359 * Call MI attach routine. 2360 */ 2361 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2362 return(0); 2363 2364fail: 2365 mtx_destroy(&sc->ti_mtx); 2366 return(error); 2367} 2368 2369/* 2370 * Verify that our character special device is not currently 2371 * open. Also track down any cached vnodes & kill them before 2372 * the module is unloaded 2373 */ 2374static int 2375ti_unref_special(device_t dev) 2376{ 2377 struct vnode *ti_vn; 2378 int count; 2379 struct ti_softc *sc = sc = device_get_softc(dev); 2380 2381 if (!vfinddev(sc->dev, VCHR, &ti_vn)) { 2382 return 0; 2383 } 2384 2385 if ((count = vcount(ti_vn))) { 2386 device_printf(dev, "%d refs to special device, " 2387 "denying unload\n", count); 2388 return count; 2389 } 2390 /* now we know that there's a vnode in the cache. We hunt it 2391 down and kill it now, before unloading */ 2392 vgone(ti_vn); 2393 return(0); 2394} 2395 2396 2397static int 2398ti_detach(dev) 2399 device_t dev; 2400{ 2401 struct ti_softc *sc; 2402 struct ifnet *ifp; 2403 2404 if (ti_unref_special(dev)) 2405 return EBUSY; 2406 2407 sc = device_get_softc(dev); 2408 TI_LOCK(sc); 2409 ifp = &sc->arpcom.ac_if; 2410 2411 ether_ifdetach(ifp); 2412 ti_stop(sc); 2413 2414 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2415 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2416 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 2417 2418#ifdef TI_PRIVATE_JUMBOS 2419 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2420#endif 2421 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2422 ifmedia_removeall(&sc->ifmedia); 2423 2424 TI_UNLOCK(sc); 2425 mtx_destroy(&sc->ti_mtx); 2426 2427 return(0); 2428} 2429 2430#ifdef TI_JUMBO_HDRSPLIT 2431/* 2432 * If hdr_len is 0, that means that header splitting wasn't done on 2433 * this packet for some reason. The two most likely reasons are that 2434 * the protocol isn't a supported protocol for splitting, or this 2435 * packet had a fragment offset that wasn't 0. 2436 * 2437 * The header length, if it is non-zero, will always be the length of 2438 * the headers on the packet, but that length could be longer than the 2439 * first mbuf. So we take the minimum of the two as the actual 2440 * length. 2441 */ 2442static __inline void 2443ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2444{ 2445 int i = 0; 2446 int lengths[4] = {0, 0, 0, 0}; 2447 struct mbuf *m, *mp; 2448 2449 if (hdr_len != 0) 2450 top->m_len = min(hdr_len, top->m_len); 2451 pkt_len -= top->m_len; 2452 lengths[i++] = top->m_len; 2453 2454 mp = top; 2455 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2456 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2457 pkt_len -= m->m_len; 2458 lengths[i++] = m->m_len; 2459 mp = m; 2460 } 2461 2462#if 0 2463 if (hdr_len != 0) 2464 printf("got split packet: "); 2465 else 2466 printf("got non-split packet: "); 2467 2468 printf("%d,%d,%d,%d = %d\n", lengths[0], 2469 lengths[1], lengths[2], lengths[3], 2470 lengths[0] + lengths[1] + lengths[2] + 2471 lengths[3]); 2472#endif 2473 2474 if (pkt_len) 2475 panic("header splitting didn't"); 2476 2477 if (m) { 2478 m_freem(m); 2479 mp->m_next = NULL; 2480 2481 } 2482 if (mp->m_next != NULL) 2483 panic("ti_hdr_split: last mbuf in chain should be null"); 2484} 2485#endif /* TI_JUMBO_HDRSPLIT */ 2486 2487/* 2488 * Frame reception handling. This is called if there's a frame 2489 * on the receive return list. 2490 * 2491 * Note: we have to be able to handle three possibilities here: 2492 * 1) the frame is from the mini receive ring (can only happen) 2493 * on Tigon 2 boards) 2494 * 2) the frame is from the jumbo recieve ring 2495 * 3) the frame is from the standard receive ring 2496 */ 2497 2498static void 2499ti_rxeof(sc) 2500 struct ti_softc *sc; 2501{ 2502 struct ifnet *ifp; 2503 struct ti_cmd_desc cmd; 2504 2505 ifp = &sc->arpcom.ac_if; 2506 2507 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2508 struct ti_rx_desc *cur_rx; 2509 u_int32_t rxidx; 2510 struct ether_header *eh; 2511 struct mbuf *m = NULL; 2512 u_int16_t vlan_tag = 0; 2513 int have_tag = 0; 2514 2515 cur_rx = 2516 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2517 rxidx = cur_rx->ti_idx; 2518 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2519 2520 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2521 have_tag = 1; 2522 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2523 } 2524 2525 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2526 2527 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2528 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2529 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2530 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2531 ifp->if_ierrors++; 2532 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2533 continue; 2534 } 2535 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2536 ifp->if_ierrors++; 2537 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2538 continue; 2539 } 2540#ifdef TI_PRIVATE_JUMBOS 2541 m->m_len = cur_rx->ti_len; 2542#else /* TI_PRIVATE_JUMBOS */ 2543#ifdef TI_JUMBO_HDRSPLIT 2544 if (sc->ti_hdrsplit) 2545 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2546 cur_rx->ti_len, rxidx); 2547 else 2548#endif /* TI_JUMBO_HDRSPLIT */ 2549 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2550#endif /* TI_PRIVATE_JUMBOS */ 2551 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2552 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2553 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2554 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2555 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2556 ifp->if_ierrors++; 2557 ti_newbuf_mini(sc, sc->ti_mini, m); 2558 continue; 2559 } 2560 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2561 ifp->if_ierrors++; 2562 ti_newbuf_mini(sc, sc->ti_mini, m); 2563 continue; 2564 } 2565 m->m_len = cur_rx->ti_len; 2566 } else { 2567 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2568 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2569 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2570 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2571 ifp->if_ierrors++; 2572 ti_newbuf_std(sc, sc->ti_std, m); 2573 continue; 2574 } 2575 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2576 ifp->if_ierrors++; 2577 ti_newbuf_std(sc, sc->ti_std, m); 2578 continue; 2579 } 2580 m->m_len = cur_rx->ti_len; 2581 } 2582 2583 m->m_pkthdr.len = cur_rx->ti_len; 2584 ifp->if_ipackets++; 2585 eh = mtod(m, struct ether_header *); 2586 m->m_pkthdr.rcvif = ifp; 2587 2588 if (ifp->if_hwassist) { 2589 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2590 CSUM_DATA_VALID; 2591 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2592 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2593 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2594 } 2595 2596 /* 2597 * If we received a packet with a vlan tag, 2598 * tag it before passing the packet upward. 2599 */ 2600 if (have_tag) 2601 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2602 (*ifp->if_input)(ifp, m); 2603 } 2604 2605 /* Only necessary on the Tigon 1. */ 2606 if (sc->ti_hwrev == TI_HWREV_TIGON) 2607 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2608 sc->ti_rx_saved_considx); 2609 2610 TI_UPDATE_STDPROD(sc, sc->ti_std); 2611 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2612 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2613 2614 return; 2615} 2616 2617static void 2618ti_txeof(sc) 2619 struct ti_softc *sc; 2620{ 2621 struct ti_tx_desc *cur_tx = NULL; 2622 struct ifnet *ifp; 2623 2624 ifp = &sc->arpcom.ac_if; 2625 2626 /* 2627 * Go through our tx ring and free mbufs for those 2628 * frames that have been sent. 2629 */ 2630 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2631 u_int32_t idx = 0; 2632 2633 idx = sc->ti_tx_saved_considx; 2634 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2635 if (idx > 383) 2636 CSR_WRITE_4(sc, TI_WINBASE, 2637 TI_TX_RING_BASE + 6144); 2638 else if (idx > 255) 2639 CSR_WRITE_4(sc, TI_WINBASE, 2640 TI_TX_RING_BASE + 4096); 2641 else if (idx > 127) 2642 CSR_WRITE_4(sc, TI_WINBASE, 2643 TI_TX_RING_BASE + 2048); 2644 else 2645 CSR_WRITE_4(sc, TI_WINBASE, 2646 TI_TX_RING_BASE); 2647 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2648 } else 2649 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2650 if (cur_tx->ti_flags & TI_BDFLAG_END) 2651 ifp->if_opackets++; 2652 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2653 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2654 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2655 } 2656 sc->ti_txcnt--; 2657 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2658 ifp->if_timer = 0; 2659 } 2660 2661 if (cur_tx != NULL) 2662 ifp->if_flags &= ~IFF_OACTIVE; 2663 2664 return; 2665} 2666 2667static void 2668ti_intr(xsc) 2669 void *xsc; 2670{ 2671 struct ti_softc *sc; 2672 struct ifnet *ifp; 2673 2674 sc = xsc; 2675 TI_LOCK(sc); 2676 ifp = &sc->arpcom.ac_if; 2677 2678/*#ifdef notdef*/ 2679 /* Avoid this for now -- checking this register is expensive. */ 2680 /* Make sure this is really our interrupt. */ 2681 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2682 TI_UNLOCK(sc); 2683 return; 2684 } 2685/*#endif*/ 2686 2687 /* Ack interrupt and stop others from occuring. */ 2688 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2689 2690 if (ifp->if_flags & IFF_RUNNING) { 2691 /* Check RX return ring producer/consumer */ 2692 ti_rxeof(sc); 2693 2694 /* Check TX ring producer/consumer */ 2695 ti_txeof(sc); 2696 } 2697 2698 ti_handle_events(sc); 2699 2700 /* Re-enable interrupts. */ 2701 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2702 2703 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2704 ti_start(ifp); 2705 2706 TI_UNLOCK(sc); 2707 2708 return; 2709} 2710 2711static void 2712ti_stats_update(sc) 2713 struct ti_softc *sc; 2714{ 2715 struct ifnet *ifp; 2716 2717 ifp = &sc->arpcom.ac_if; 2718 2719 ifp->if_collisions += 2720 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2721 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2722 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2723 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2724 ifp->if_collisions; 2725 2726 return; 2727} 2728 2729/* 2730 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2731 * pointers to descriptors. 2732 */ 2733static int 2734ti_encap(sc, m_head, txidx) 2735 struct ti_softc *sc; 2736 struct mbuf *m_head; 2737 u_int32_t *txidx; 2738{ 2739 struct ti_tx_desc *f = NULL; 2740 struct mbuf *m; 2741 u_int32_t frag, cur, cnt = 0; 2742 u_int16_t csum_flags = 0; 2743 struct m_tag *mtag; 2744 2745 m = m_head; 2746 cur = frag = *txidx; 2747 2748 if (m_head->m_pkthdr.csum_flags) { 2749 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2750 csum_flags |= TI_BDFLAG_IP_CKSUM; 2751 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2752 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2753 if (m_head->m_flags & M_LASTFRAG) 2754 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2755 else if (m_head->m_flags & M_FRAG) 2756 csum_flags |= TI_BDFLAG_IP_FRAG; 2757 } 2758 2759 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2760 2761 /* 2762 * Start packing the mbufs in this chain into 2763 * the fragment pointers. Stop when we run out 2764 * of fragments or hit the end of the mbuf chain. 2765 */ 2766 for (m = m_head; m != NULL; m = m->m_next) { 2767 if (m->m_len != 0) { 2768 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2769 if (frag > 383) 2770 CSR_WRITE_4(sc, TI_WINBASE, 2771 TI_TX_RING_BASE + 6144); 2772 else if (frag > 255) 2773 CSR_WRITE_4(sc, TI_WINBASE, 2774 TI_TX_RING_BASE + 4096); 2775 else if (frag > 127) 2776 CSR_WRITE_4(sc, TI_WINBASE, 2777 TI_TX_RING_BASE + 2048); 2778 else 2779 CSR_WRITE_4(sc, TI_WINBASE, 2780 TI_TX_RING_BASE); 2781 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2782 } else 2783 f = &sc->ti_rdata->ti_tx_ring[frag]; 2784 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2785 break; 2786 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2787 f->ti_len = m->m_len; 2788 f->ti_flags = csum_flags; 2789 2790 if (mtag != NULL) { 2791 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2792 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2793 } else { 2794 f->ti_vlan_tag = 0; 2795 } 2796 2797 /* 2798 * Sanity check: avoid coming within 16 descriptors 2799 * of the end of the ring. 2800 */ 2801 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2802 return(ENOBUFS); 2803 cur = frag; 2804 TI_INC(frag, TI_TX_RING_CNT); 2805 cnt++; 2806 } 2807 } 2808 2809 if (m != NULL) 2810 return(ENOBUFS); 2811 2812 if (frag == sc->ti_tx_saved_considx) 2813 return(ENOBUFS); 2814 2815 if (sc->ti_hwrev == TI_HWREV_TIGON) 2816 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2817 TI_BDFLAG_END; 2818 else 2819 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2820 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2821 sc->ti_txcnt += cnt; 2822 2823 *txidx = frag; 2824 2825 return(0); 2826} 2827 2828/* 2829 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2830 * to the mbuf data regions directly in the transmit descriptors. 2831 */ 2832static void 2833ti_start(ifp) 2834 struct ifnet *ifp; 2835{ 2836 struct ti_softc *sc; 2837 struct mbuf *m_head = NULL; 2838 u_int32_t prodidx = 0; 2839 2840 sc = ifp->if_softc; 2841 TI_LOCK(sc); 2842 2843 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2844 2845 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2846 IF_DEQUEUE(&ifp->if_snd, m_head); 2847 if (m_head == NULL) 2848 break; 2849 2850 /* 2851 * XXX 2852 * safety overkill. If this is a fragmented packet chain 2853 * with delayed TCP/UDP checksums, then only encapsulate 2854 * it if we have enough descriptors to handle the entire 2855 * chain at once. 2856 * (paranoia -- may not actually be needed) 2857 */ 2858 if (m_head->m_flags & M_FIRSTFRAG && 2859 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2860 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2861 m_head->m_pkthdr.csum_data + 16) { 2862 IF_PREPEND(&ifp->if_snd, m_head); 2863 ifp->if_flags |= IFF_OACTIVE; 2864 break; 2865 } 2866 } 2867 2868 /* 2869 * Pack the data into the transmit ring. If we 2870 * don't have room, set the OACTIVE flag and wait 2871 * for the NIC to drain the ring. 2872 */ 2873 if (ti_encap(sc, m_head, &prodidx)) { 2874 IF_PREPEND(&ifp->if_snd, m_head); 2875 ifp->if_flags |= IFF_OACTIVE; 2876 break; 2877 } 2878 2879 /* 2880 * If there's a BPF listener, bounce a copy of this frame 2881 * to him. 2882 */ 2883 BPF_MTAP(ifp, m_head); 2884 } 2885 2886 /* Transmit */ 2887 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2888 2889 /* 2890 * Set a timeout in case the chip goes out to lunch. 2891 */ 2892 ifp->if_timer = 5; 2893 TI_UNLOCK(sc); 2894 2895 return; 2896} 2897 2898static void 2899ti_init(xsc) 2900 void *xsc; 2901{ 2902 struct ti_softc *sc = xsc; 2903 2904 /* Cancel pending I/O and flush buffers. */ 2905 ti_stop(sc); 2906 2907 TI_LOCK(sc); 2908 /* Init the gen info block, ring control blocks and firmware. */ 2909 if (ti_gibinit(sc)) { 2910 printf("ti%d: initialization failure\n", sc->ti_unit); 2911 TI_UNLOCK(sc); 2912 return; 2913 } 2914 2915 TI_UNLOCK(sc); 2916 2917 return; 2918} 2919 2920static void ti_init2(sc) 2921 struct ti_softc *sc; 2922{ 2923 struct ti_cmd_desc cmd; 2924 struct ifnet *ifp; 2925 u_int16_t *m; 2926 struct ifmedia *ifm; 2927 int tmp; 2928 2929 ifp = &sc->arpcom.ac_if; 2930 2931 /* Specify MTU and interface index. */ 2932 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2933 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2934 ETHER_HDR_LEN + ETHER_CRC_LEN); 2935 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2936 2937 /* Load our MAC address. */ 2938 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2939 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2940 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2941 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2942 2943 /* Enable or disable promiscuous mode as needed. */ 2944 if (ifp->if_flags & IFF_PROMISC) { 2945 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2946 } else { 2947 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2948 } 2949 2950 /* Program multicast filter. */ 2951 ti_setmulti(sc); 2952 2953 /* 2954 * If this is a Tigon 1, we should tell the 2955 * firmware to use software packet filtering. 2956 */ 2957 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2958 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2959 } 2960 2961 /* Init RX ring. */ 2962 ti_init_rx_ring_std(sc); 2963 2964 /* Init jumbo RX ring. */ 2965 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2966 ti_init_rx_ring_jumbo(sc); 2967 2968 /* 2969 * If this is a Tigon 2, we can also configure the 2970 * mini ring. 2971 */ 2972 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2973 ti_init_rx_ring_mini(sc); 2974 2975 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2976 sc->ti_rx_saved_considx = 0; 2977 2978 /* Init TX ring. */ 2979 ti_init_tx_ring(sc); 2980 2981 /* Tell firmware we're alive. */ 2982 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2983 2984 /* Enable host interrupts. */ 2985 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2986 2987 ifp->if_flags |= IFF_RUNNING; 2988 ifp->if_flags &= ~IFF_OACTIVE; 2989 2990 /* 2991 * Make sure to set media properly. We have to do this 2992 * here since we have to issue commands in order to set 2993 * the link negotiation and we can't issue commands until 2994 * the firmware is running. 2995 */ 2996 ifm = &sc->ifmedia; 2997 tmp = ifm->ifm_media; 2998 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2999 ti_ifmedia_upd(ifp); 3000 ifm->ifm_media = tmp; 3001 3002 return; 3003} 3004 3005/* 3006 * Set media options. 3007 */ 3008static int 3009ti_ifmedia_upd(ifp) 3010 struct ifnet *ifp; 3011{ 3012 struct ti_softc *sc; 3013 struct ifmedia *ifm; 3014 struct ti_cmd_desc cmd; 3015 u_int32_t flowctl; 3016 3017 sc = ifp->if_softc; 3018 ifm = &sc->ifmedia; 3019 3020 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3021 return(EINVAL); 3022 3023 flowctl = 0; 3024 3025 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3026 case IFM_AUTO: 3027 /* 3028 * Transmit flow control doesn't work on the Tigon 1. 3029 */ 3030 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3031 3032 /* 3033 * Transmit flow control can also cause problems on the 3034 * Tigon 2, apparantly with both the copper and fiber 3035 * boards. The symptom is that the interface will just 3036 * hang. This was reproduced with Alteon 180 switches. 3037 */ 3038#if 0 3039 if (sc->ti_hwrev != TI_HWREV_TIGON) 3040 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3041#endif 3042 3043 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3044 TI_GLNK_FULL_DUPLEX| flowctl | 3045 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3046 3047 flowctl = TI_LNK_RX_FLOWCTL_Y; 3048#if 0 3049 if (sc->ti_hwrev != TI_HWREV_TIGON) 3050 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3051#endif 3052 3053 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3054 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3055 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3056 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3057 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3058 break; 3059 case IFM_1000_SX: 3060 case IFM_1000_T: 3061 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3062#if 0 3063 if (sc->ti_hwrev != TI_HWREV_TIGON) 3064 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3065#endif 3066 3067 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3068 flowctl |TI_GLNK_ENB); 3069 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3070 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3071 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3072 } 3073 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3074 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3075 break; 3076 case IFM_100_FX: 3077 case IFM_10_FL: 3078 case IFM_100_TX: 3079 case IFM_10_T: 3080 flowctl = TI_LNK_RX_FLOWCTL_Y; 3081#if 0 3082 if (sc->ti_hwrev != TI_HWREV_TIGON) 3083 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3084#endif 3085 3086 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3087 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3088 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3089 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3090 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3091 } else { 3092 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3093 } 3094 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3095 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3096 } else { 3097 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3098 } 3099 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3100 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3101 break; 3102 } 3103 3104 return(0); 3105} 3106 3107/* 3108 * Report current media status. 3109 */ 3110static void 3111ti_ifmedia_sts(ifp, ifmr) 3112 struct ifnet *ifp; 3113 struct ifmediareq *ifmr; 3114{ 3115 struct ti_softc *sc; 3116 u_int32_t media = 0; 3117 3118 sc = ifp->if_softc; 3119 3120 ifmr->ifm_status = IFM_AVALID; 3121 ifmr->ifm_active = IFM_ETHER; 3122 3123 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3124 return; 3125 3126 ifmr->ifm_status |= IFM_ACTIVE; 3127 3128 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3129 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3130 if (sc->ti_copper) 3131 ifmr->ifm_active |= IFM_1000_T; 3132 else 3133 ifmr->ifm_active |= IFM_1000_SX; 3134 if (media & TI_GLNK_FULL_DUPLEX) 3135 ifmr->ifm_active |= IFM_FDX; 3136 else 3137 ifmr->ifm_active |= IFM_HDX; 3138 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3139 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3140 if (sc->ti_copper) { 3141 if (media & TI_LNK_100MB) 3142 ifmr->ifm_active |= IFM_100_TX; 3143 if (media & TI_LNK_10MB) 3144 ifmr->ifm_active |= IFM_10_T; 3145 } else { 3146 if (media & TI_LNK_100MB) 3147 ifmr->ifm_active |= IFM_100_FX; 3148 if (media & TI_LNK_10MB) 3149 ifmr->ifm_active |= IFM_10_FL; 3150 } 3151 if (media & TI_LNK_FULL_DUPLEX) 3152 ifmr->ifm_active |= IFM_FDX; 3153 if (media & TI_LNK_HALF_DUPLEX) 3154 ifmr->ifm_active |= IFM_HDX; 3155 } 3156 3157 return; 3158} 3159 3160static int 3161ti_ioctl(ifp, command, data) 3162 struct ifnet *ifp; 3163 u_long command; 3164 caddr_t data; 3165{ 3166 struct ti_softc *sc = ifp->if_softc; 3167 struct ifreq *ifr = (struct ifreq *) data; 3168 int mask, error = 0; 3169 struct ti_cmd_desc cmd; 3170 3171 TI_LOCK(sc); 3172 3173 switch(command) { 3174 case SIOCSIFMTU: 3175 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3176 error = EINVAL; 3177 else { 3178 ifp->if_mtu = ifr->ifr_mtu; 3179 ti_init(sc); 3180 } 3181 break; 3182 case SIOCSIFFLAGS: 3183 if (ifp->if_flags & IFF_UP) { 3184 /* 3185 * If only the state of the PROMISC flag changed, 3186 * then just use the 'set promisc mode' command 3187 * instead of reinitializing the entire NIC. Doing 3188 * a full re-init means reloading the firmware and 3189 * waiting for it to start up, which may take a 3190 * second or two. 3191 */ 3192 if (ifp->if_flags & IFF_RUNNING && 3193 ifp->if_flags & IFF_PROMISC && 3194 !(sc->ti_if_flags & IFF_PROMISC)) { 3195 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3196 TI_CMD_CODE_PROMISC_ENB, 0); 3197 } else if (ifp->if_flags & IFF_RUNNING && 3198 !(ifp->if_flags & IFF_PROMISC) && 3199 sc->ti_if_flags & IFF_PROMISC) { 3200 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3201 TI_CMD_CODE_PROMISC_DIS, 0); 3202 } else 3203 ti_init(sc); 3204 } else { 3205 if (ifp->if_flags & IFF_RUNNING) { 3206 ti_stop(sc); 3207 } 3208 } 3209 sc->ti_if_flags = ifp->if_flags; 3210 error = 0; 3211 break; 3212 case SIOCADDMULTI: 3213 case SIOCDELMULTI: 3214 if (ifp->if_flags & IFF_RUNNING) { 3215 ti_setmulti(sc); 3216 error = 0; 3217 } 3218 break; 3219 case SIOCSIFMEDIA: 3220 case SIOCGIFMEDIA: 3221 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3222 break; 3223 case SIOCSIFCAP: 3224 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3225 if (mask & IFCAP_HWCSUM) { 3226 if (IFCAP_HWCSUM & ifp->if_capenable) 3227 ifp->if_capenable &= ~IFCAP_HWCSUM; 3228 else 3229 ifp->if_capenable |= IFCAP_HWCSUM; 3230 if (ifp->if_flags & IFF_RUNNING) 3231 ti_init(sc); 3232 } 3233 error = 0; 3234 break; 3235 default: 3236 error = ether_ioctl(ifp, command, data); 3237 break; 3238 } 3239 3240 TI_UNLOCK(sc); 3241 3242 return(error); 3243} 3244 3245static int 3246ti_open(dev_t dev, int flags, int fmt, struct thread *td) 3247{ 3248 int unit; 3249 struct ti_softc *sc; 3250 3251 unit = minor(dev) & 0xff; 3252 3253 sc = ti_lookup_softc(unit); 3254 3255 if (sc == NULL) 3256 return(ENODEV); 3257 3258 TI_LOCK(sc); 3259 sc->ti_flags |= TI_FLAG_DEBUGING; 3260 TI_UNLOCK(sc); 3261 3262 return(0); 3263} 3264 3265static int 3266ti_close(dev_t dev, int flag, int fmt, struct thread *td) 3267{ 3268 int unit; 3269 struct ti_softc *sc; 3270 3271 unit = minor(dev) & 0xff; 3272 3273 sc = ti_lookup_softc(unit); 3274 3275 if (sc == NULL) 3276 return(ENODEV); 3277 3278 TI_LOCK(sc); 3279 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3280 TI_UNLOCK(sc); 3281 3282 return(0); 3283} 3284 3285/* 3286 * This ioctl routine goes along with the Tigon character device. 3287 */ 3288static int 3289ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3290{ 3291 int unit, error; 3292 struct ti_softc *sc; 3293 3294 unit = minor(dev) & 0xff; 3295 3296 sc = ti_lookup_softc(unit); 3297 3298 if (sc == NULL) 3299 return(ENODEV); 3300 3301 error = 0; 3302 3303 switch(cmd) { 3304 case TIIOCGETSTATS: 3305 { 3306 struct ti_stats *outstats; 3307 3308 outstats = (struct ti_stats *)addr; 3309 3310 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3311 sizeof(struct ti_stats)); 3312 break; 3313 } 3314 case TIIOCGETPARAMS: 3315 { 3316 struct ti_params *params; 3317 3318 params = (struct ti_params *)addr; 3319 3320 params->ti_stat_ticks = sc->ti_stat_ticks; 3321 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3322 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3323 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3324 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3325 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3326 params->param_mask = TI_PARAM_ALL; 3327 3328 error = 0; 3329 3330 break; 3331 } 3332 case TIIOCSETPARAMS: 3333 { 3334 struct ti_params *params; 3335 3336 params = (struct ti_params *)addr; 3337 3338 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3339 sc->ti_stat_ticks = params->ti_stat_ticks; 3340 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3341 } 3342 3343 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3344 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3345 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3346 sc->ti_rx_coal_ticks); 3347 } 3348 3349 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3350 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3351 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3352 sc->ti_tx_coal_ticks); 3353 } 3354 3355 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3356 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3357 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3358 sc->ti_rx_max_coal_bds); 3359 } 3360 3361 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3362 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3363 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3364 sc->ti_tx_max_coal_bds); 3365 } 3366 3367 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3368 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3369 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3370 sc->ti_tx_buf_ratio); 3371 } 3372 3373 error = 0; 3374 3375 break; 3376 } 3377 case TIIOCSETTRACE: { 3378 ti_trace_type trace_type; 3379 3380 trace_type = *(ti_trace_type *)addr; 3381 3382 /* 3383 * Set tracing to whatever the user asked for. Setting 3384 * this register to 0 should have the effect of disabling 3385 * tracing. 3386 */ 3387 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3388 3389 error = 0; 3390 3391 break; 3392 } 3393 case TIIOCGETTRACE: { 3394 struct ti_trace_buf *trace_buf; 3395 u_int32_t trace_start, cur_trace_ptr, trace_len; 3396 3397 trace_buf = (struct ti_trace_buf *)addr; 3398 3399 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3400 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3401 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3402 3403#if 0 3404 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3405 "trace_len = %d\n", sc->ti_unit, trace_start, 3406 cur_trace_ptr, trace_len); 3407 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3408 trace_buf->buf_len); 3409#endif 3410 3411 error = ti_copy_mem(sc, trace_start, min(trace_len, 3412 trace_buf->buf_len), 3413 (caddr_t)trace_buf->buf, 1, 1); 3414 3415 if (error == 0) { 3416 trace_buf->fill_len = min(trace_len, 3417 trace_buf->buf_len); 3418 if (cur_trace_ptr < trace_start) 3419 trace_buf->cur_trace_ptr = 3420 trace_start - cur_trace_ptr; 3421 else 3422 trace_buf->cur_trace_ptr = 3423 cur_trace_ptr - trace_start; 3424 } else 3425 trace_buf->fill_len = 0; 3426 3427 3428 break; 3429 } 3430 3431 /* 3432 * For debugging, five ioctls are needed: 3433 * ALT_ATTACH 3434 * ALT_READ_TG_REG 3435 * ALT_WRITE_TG_REG 3436 * ALT_READ_TG_MEM 3437 * ALT_WRITE_TG_MEM 3438 */ 3439 case ALT_ATTACH: 3440 /* 3441 * From what I can tell, Alteon's Solaris Tigon driver 3442 * only has one character device, so you have to attach 3443 * to the Tigon board you're interested in. This seems 3444 * like a not-so-good way to do things, since unless you 3445 * subsequently specify the unit number of the device 3446 * you're interested in in every ioctl, you'll only be 3447 * able to debug one board at a time. 3448 */ 3449 error = 0; 3450 break; 3451 case ALT_READ_TG_MEM: 3452 case ALT_WRITE_TG_MEM: 3453 { 3454 struct tg_mem *mem_param; 3455 u_int32_t sram_end, scratch_end; 3456 3457 mem_param = (struct tg_mem *)addr; 3458 3459 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3460 sram_end = TI_END_SRAM_I; 3461 scratch_end = TI_END_SCRATCH_I; 3462 } else { 3463 sram_end = TI_END_SRAM_II; 3464 scratch_end = TI_END_SCRATCH_II; 3465 } 3466 3467 /* 3468 * For now, we'll only handle accessing regular SRAM, 3469 * nothing else. 3470 */ 3471 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3472 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3473 /* 3474 * In this instance, we always copy to/from user 3475 * space, so the user space argument is set to 1. 3476 */ 3477 error = ti_copy_mem(sc, mem_param->tgAddr, 3478 mem_param->len, 3479 mem_param->userAddr, 1, 3480 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3481 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3482 && (mem_param->tgAddr <= scratch_end)) { 3483 error = ti_copy_scratch(sc, mem_param->tgAddr, 3484 mem_param->len, 3485 mem_param->userAddr, 1, 3486 (cmd == ALT_READ_TG_MEM) ? 3487 1 : 0, TI_PROCESSOR_A); 3488 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3489 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3490 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3491 printf("ti%d: invalid memory range for " 3492 "Tigon I\n", sc->ti_unit); 3493 error = EINVAL; 3494 break; 3495 } 3496 error = ti_copy_scratch(sc, mem_param->tgAddr - 3497 TI_SCRATCH_DEBUG_OFF, 3498 mem_param->len, 3499 mem_param->userAddr, 1, 3500 (cmd == ALT_READ_TG_MEM) ? 3501 1 : 0, TI_PROCESSOR_B); 3502 } else { 3503 printf("ti%d: memory address %#x len %d is out of " 3504 "supported range\n", sc->ti_unit, 3505 mem_param->tgAddr, mem_param->len); 3506 error = EINVAL; 3507 } 3508 3509 break; 3510 } 3511 case ALT_READ_TG_REG: 3512 case ALT_WRITE_TG_REG: 3513 { 3514 struct tg_reg *regs; 3515 u_int32_t tmpval; 3516 3517 regs = (struct tg_reg *)addr; 3518 3519 /* 3520 * Make sure the address in question isn't out of range. 3521 */ 3522 if (regs->addr > TI_REG_MAX) { 3523 error = EINVAL; 3524 break; 3525 } 3526 if (cmd == ALT_READ_TG_REG) { 3527 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3528 regs->addr, &tmpval, 1); 3529 regs->data = ntohl(tmpval); 3530#if 0 3531 if ((regs->addr == TI_CPU_STATE) 3532 || (regs->addr == TI_CPU_CTL_B)) { 3533 printf("ti%d: register %#x = %#x\n", 3534 sc->ti_unit, regs->addr, tmpval); 3535 } 3536#endif 3537 } else { 3538 tmpval = htonl(regs->data); 3539 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3540 regs->addr, &tmpval, 1); 3541 } 3542 3543 break; 3544 } 3545 default: 3546 error = ENOTTY; 3547 break; 3548 } 3549 return(error); 3550} 3551 3552static void 3553ti_watchdog(ifp) 3554 struct ifnet *ifp; 3555{ 3556 struct ti_softc *sc; 3557 3558 sc = ifp->if_softc; 3559 TI_LOCK(sc); 3560 3561 /* 3562 * When we're debugging, the chip is often stopped for long periods 3563 * of time, and that would normally cause the watchdog timer to fire. 3564 * Since that impedes debugging, we don't want to do that. 3565 */ 3566 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3567 TI_UNLOCK(sc); 3568 return; 3569 } 3570 3571 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3572 ti_stop(sc); 3573 ti_init(sc); 3574 3575 ifp->if_oerrors++; 3576 TI_UNLOCK(sc); 3577 3578 return; 3579} 3580 3581/* 3582 * Stop the adapter and free any mbufs allocated to the 3583 * RX and TX lists. 3584 */ 3585static void 3586ti_stop(sc) 3587 struct ti_softc *sc; 3588{ 3589 struct ifnet *ifp; 3590 struct ti_cmd_desc cmd; 3591 3592 TI_LOCK(sc); 3593 3594 ifp = &sc->arpcom.ac_if; 3595 3596 /* Disable host interrupts. */ 3597 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3598 /* 3599 * Tell firmware we're shutting down. 3600 */ 3601 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3602 3603 /* Halt and reinitialize. */ 3604 ti_chipinit(sc); 3605 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3606 ti_chipinit(sc); 3607 3608 /* Free the RX lists. */ 3609 ti_free_rx_ring_std(sc); 3610 3611 /* Free jumbo RX list. */ 3612 ti_free_rx_ring_jumbo(sc); 3613 3614 /* Free mini RX list. */ 3615 ti_free_rx_ring_mini(sc); 3616 3617 /* Free TX buffers. */ 3618 ti_free_tx_ring(sc); 3619 3620 sc->ti_ev_prodidx.ti_idx = 0; 3621 sc->ti_return_prodidx.ti_idx = 0; 3622 sc->ti_tx_considx.ti_idx = 0; 3623 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3624 3625 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3626 TI_UNLOCK(sc); 3627 3628 return; 3629} 3630 3631/* 3632 * Stop all chip I/O so that the kernel's probe routines don't 3633 * get confused by errant DMAs when rebooting. 3634 */ 3635static void 3636ti_shutdown(dev) 3637 device_t dev; 3638{ 3639 struct ti_softc *sc; 3640 3641 sc = device_get_softc(dev); 3642 TI_LOCK(sc); 3643 ti_chipinit(sc); 3644 TI_UNLOCK(sc); 3645 3646 return; 3647} 3648