if_ti.c revision 99013
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 99013 2002-06-29 02:32:34Z peter $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "opt_ti.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90#include <sys/queue.h> 91#include <sys/conf.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98#include <net/if_types.h> 99#include <net/if_vlan_var.h> 100 101#include <net/bpf.h> 102 103#include <netinet/in_systm.h> 104#include <netinet/in.h> 105#include <netinet/ip.h> 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/bus_memio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116 117#if !defined(TI_PRIVATE_JUMBOS) 118#include <sys/sockio.h> 119#include <sys/uio.h> 120#include <sys/lock.h> 121#include <vm/vm_extern.h> 122#include <vm/pmap.h> 123#include <vm/vm_map.h> 124#include <vm/vm_map.h> 125#include <vm/vm_param.h> 126#include <vm/vm_pageout.h> 127#include <sys/vmmeter.h> 128#include <vm/vm_page.h> 129#include <vm/vm_object.h> 130#include <vm/vm_kern.h> 131#include <sys/proc.h> 132#include <sys/jumbo.h> 133#endif /* !TI_PRIVATE_JUMBOS */ 134#include <sys/vnode.h> /* for vfindev, vgone */ 135 136#include <pci/pcireg.h> 137#include <pci/pcivar.h> 138 139#include <sys/tiio.h> 140#include <pci/if_tireg.h> 141#include <pci/ti_fw.h> 142#include <pci/ti_fw2.h> 143 144#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145/* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153#if !defined(lint) 154static const char rcsid[] = 155 "$FreeBSD: head/sys/dev/ti/if_ti.c 99013 2002-06-29 02:32:34Z peter $"; 156#endif 157 158struct ti_softc *tis[8]; 159 160typedef enum { 161 TI_SWAP_HTON, 162 TI_SWAP_NTOH 163} ti_swap_type; 164 165 166/* 167 * Various supported device vendors/types and their names. 168 */ 169 170static struct ti_type ti_devs[] = { 171 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 172 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 173 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 174 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 175 { TC_VENDORID, TC_DEVICEID_3C985, 176 "3Com 3c985-SX Gigabit Ethernet" }, 177 { NG_VENDORID, NG_DEVICEID_GA620, 178 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 179 { NG_VENDORID, NG_DEVICEID_GA620T, 180 "Netgear GA620 1000baseT Gigabit Ethernet" }, 181 { SGI_VENDORID, SGI_DEVICEID_TIGON, 182 "Silicon Graphics Gigabit Ethernet" }, 183 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 184 "Farallon PN9000SX Gigabit Ethernet" }, 185 { 0, 0, NULL } 186}; 187 188#define TI_CDEV_MAJOR 153 189 190static d_open_t ti_open; 191static d_close_t ti_close; 192static d_ioctl_t ti_ioctl2; 193 194static struct cdevsw ti_cdevsw = { 195 /* open */ ti_open, 196 /* close */ ti_close, 197 /* read */ NULL, 198 /* write */ NULL, 199 /* ioctl */ ti_ioctl2, 200 /* poll */ seltrue, 201 /* mmap */ nommap, 202 /* strategy */ nostrategy, 203 /* name */ "ti", 204 /* maj */ TI_CDEV_MAJOR, 205 /* dump */ nodump, 206 /* psize */ nopsize, 207 /* flags */ 0, 208}; 209 210static int ti_probe (device_t); 211static int ti_attach (device_t); 212static int ti_detach (device_t); 213static void ti_txeof (struct ti_softc *); 214static void ti_rxeof (struct ti_softc *); 215 216static void ti_stats_update (struct ti_softc *); 217static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 218 219static void ti_intr (void *); 220static void ti_start (struct ifnet *); 221static int ti_ioctl (struct ifnet *, u_long, caddr_t); 222static void ti_init (void *); 223static void ti_init2 (struct ti_softc *); 224static void ti_stop (struct ti_softc *); 225static void ti_watchdog (struct ifnet *); 226static void ti_shutdown (device_t); 227static int ti_ifmedia_upd (struct ifnet *); 228static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 231static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 232static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 233 234static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 235static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 236static void ti_setmulti (struct ti_softc *); 237 238static void ti_mem (struct ti_softc *, u_int32_t, 239 u_int32_t, caddr_t); 240static int ti_copy_mem (struct ti_softc *, u_int32_t, 241 u_int32_t, caddr_t, int, int); 242static int ti_copy_scratch (struct ti_softc *, u_int32_t, 243 u_int32_t, caddr_t, int, int, int); 244static int ti_bcopy_swap (const void *, void *, size_t, 245 ti_swap_type); 246static void ti_loadfw (struct ti_softc *); 247static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 248static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 249 caddr_t, int); 250static void ti_handle_events (struct ti_softc *); 251#ifdef TI_PRIVATE_JUMBOS 252static int ti_alloc_jumbo_mem (struct ti_softc *); 253static void *ti_jalloc (struct ti_softc *); 254static void ti_jfree (caddr_t, void *); 255#endif /* TI_PRIVATE_JUMBOS */ 256static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 257static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 258static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 259static int ti_init_rx_ring_std (struct ti_softc *); 260static void ti_free_rx_ring_std (struct ti_softc *); 261static int ti_init_rx_ring_jumbo (struct ti_softc *); 262static void ti_free_rx_ring_jumbo (struct ti_softc *); 263static int ti_init_rx_ring_mini (struct ti_softc *); 264static void ti_free_rx_ring_mini (struct ti_softc *); 265static void ti_free_tx_ring (struct ti_softc *); 266static int ti_init_tx_ring (struct ti_softc *); 267 268static int ti_64bitslot_war (struct ti_softc *); 269static int ti_chipinit (struct ti_softc *); 270static int ti_gibinit (struct ti_softc *); 271 272#ifdef TI_JUMBO_HDRSPLIT 273static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 274 int pkt_len, int idx); 275#endif /* TI_JUMBO_HDRSPLIT */ 276 277static device_method_t ti_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, ti_probe), 280 DEVMETHOD(device_attach, ti_attach), 281 DEVMETHOD(device_detach, ti_detach), 282 DEVMETHOD(device_shutdown, ti_shutdown), 283 { 0, 0 } 284}; 285 286static driver_t ti_driver = { 287 "ti", 288 ti_methods, 289 sizeof(struct ti_softc) 290}; 291 292static devclass_t ti_devclass; 293 294DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 295 296/* List of Tigon softcs */ 297static STAILQ_HEAD(ti_softc_list, ti_softc) ti_sc_list; 298 299static struct ti_softc * 300ti_lookup_softc(int unit) 301{ 302 struct ti_softc *sc; 303 for (sc = STAILQ_FIRST(&ti_sc_list); sc != NULL; 304 sc = STAILQ_NEXT(sc, ti_links)) 305 if (sc->ti_unit == unit) 306 return(sc); 307 return(NULL); 308} 309 310/* 311 * Send an instruction or address to the EEPROM, check for ACK. 312 */ 313static u_int32_t ti_eeprom_putbyte(sc, byte) 314 struct ti_softc *sc; 315 int byte; 316{ 317 register int i, ack = 0; 318 319 /* 320 * Make sure we're in TX mode. 321 */ 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 323 324 /* 325 * Feed in each bit and stobe the clock. 326 */ 327 for (i = 0x80; i; i >>= 1) { 328 if (byte & i) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 330 } else { 331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 332 } 333 DELAY(1); 334 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 335 DELAY(1); 336 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 337 } 338 339 /* 340 * Turn off TX mode. 341 */ 342 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 343 344 /* 345 * Check for ack. 346 */ 347 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 348 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 349 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 350 351 return(ack); 352} 353 354/* 355 * Read a byte of data stored in the EEPROM at address 'addr.' 356 * We have to send two address bytes since the EEPROM can hold 357 * more than 256 bytes of data. 358 */ 359static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 360 struct ti_softc *sc; 361 int addr; 362 u_int8_t *dest; 363{ 364 register int i; 365 u_int8_t byte = 0; 366 367 EEPROM_START; 368 369 /* 370 * Send write control code to EEPROM. 371 */ 372 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 373 printf("ti%d: failed to send write command, status: %x\n", 374 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 375 return(1); 376 } 377 378 /* 379 * Send first byte of address of byte we want to read. 380 */ 381 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 382 printf("ti%d: failed to send address, status: %x\n", 383 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 384 return(1); 385 } 386 /* 387 * Send second byte address of byte we want to read. 388 */ 389 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 390 printf("ti%d: failed to send address, status: %x\n", 391 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 392 return(1); 393 } 394 395 EEPROM_STOP; 396 EEPROM_START; 397 /* 398 * Send read control code to EEPROM. 399 */ 400 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 401 printf("ti%d: failed to send read command, status: %x\n", 402 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 403 return(1); 404 } 405 406 /* 407 * Start reading bits from EEPROM. 408 */ 409 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 410 for (i = 0x80; i; i >>= 1) { 411 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 412 DELAY(1); 413 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 414 byte |= i; 415 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 416 DELAY(1); 417 } 418 419 EEPROM_STOP; 420 421 /* 422 * No ACK generated for read, so just return byte. 423 */ 424 425 *dest = byte; 426 427 return(0); 428} 429 430/* 431 * Read a sequence of bytes from the EEPROM. 432 */ 433static int ti_read_eeprom(sc, dest, off, cnt) 434 struct ti_softc *sc; 435 caddr_t dest; 436 int off; 437 int cnt; 438{ 439 int err = 0, i; 440 u_int8_t byte = 0; 441 442 for (i = 0; i < cnt; i++) { 443 err = ti_eeprom_getbyte(sc, off + i, &byte); 444 if (err) 445 break; 446 *(dest + i) = byte; 447 } 448 449 return(err ? 1 : 0); 450} 451 452/* 453 * NIC memory access function. Can be used to either clear a section 454 * of NIC local memory or (if buf is non-NULL) copy data into it. 455 */ 456static void ti_mem(sc, addr, len, buf) 457 struct ti_softc *sc; 458 u_int32_t addr, len; 459 caddr_t buf; 460{ 461 int segptr, segsize, cnt; 462 caddr_t ti_winbase, ptr; 463 464 segptr = addr; 465 cnt = len; 466 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 467 ptr = buf; 468 469 while(cnt) { 470 if (cnt < TI_WINLEN) 471 segsize = cnt; 472 else 473 segsize = TI_WINLEN - (segptr % TI_WINLEN); 474 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 475 if (buf == NULL) 476 bzero((char *)ti_winbase + (segptr & 477 (TI_WINLEN - 1)), segsize); 478 else { 479 bcopy((char *)ptr, (char *)ti_winbase + 480 (segptr & (TI_WINLEN - 1)), segsize); 481 ptr += segsize; 482 } 483 segptr += segsize; 484 cnt -= segsize; 485 } 486 487 return; 488} 489 490static int 491ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 492 struct ti_softc *sc; 493 u_int32_t tigon_addr, len; 494 caddr_t buf; 495 int useraddr, readdata; 496{ 497 int segptr, segsize, cnt; 498 caddr_t ptr; 499 u_int32_t origwin; 500 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 501 int resid, segresid; 502 int first_pass; 503 504 /* 505 * At the moment, we don't handle non-aligned cases, we just bail. 506 * If this proves to be a problem, it will be fixed. 507 */ 508 if ((readdata == 0) 509 && (tigon_addr & 0x3)) { 510 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 511 "word-aligned\n", sc->ti_unit, tigon_addr); 512 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 513 "supported\n", sc->ti_unit); 514 return(EINVAL); 515 } 516 517 segptr = tigon_addr & ~0x3; 518 segresid = tigon_addr - segptr; 519 520 /* 521 * This is the non-aligned amount left over that we'll need to 522 * copy. 523 */ 524 resid = len & 0x3; 525 526 /* Add in the left over amount at the front of the buffer */ 527 resid += segresid; 528 529 cnt = len & ~0x3; 530 /* 531 * If resid + segresid is >= 4, add multiples of 4 to the count and 532 * decrease the residual by that much. 533 */ 534 cnt += resid & ~0x3; 535 resid -= resid & ~0x3; 536 537 ptr = buf; 538 539 first_pass = 1; 540 541 /* 542 * Make sure we aren't interrupted while we're changing the window 543 * pointer. 544 */ 545 TI_LOCK(sc); 546 547 /* 548 * Save the old window base value. 549 */ 550 origwin = CSR_READ_4(sc, TI_WINBASE); 551 552 while(cnt) { 553 bus_size_t ti_offset; 554 555 if (cnt < TI_WINLEN) 556 segsize = cnt; 557 else 558 segsize = TI_WINLEN - (segptr % TI_WINLEN); 559 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 560 561 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 562 563 if (readdata) { 564 565 bus_space_read_region_4(sc->ti_btag, 566 sc->ti_bhandle, ti_offset, 567 (u_int32_t *)tmparray, 568 segsize >> 2); 569 if (useraddr) { 570 /* 571 * Yeah, this is a little on the kludgy 572 * side, but at least this code is only 573 * used for debugging. 574 */ 575 ti_bcopy_swap(tmparray, tmparray2, segsize, 576 TI_SWAP_NTOH); 577 578 if (first_pass) { 579 copyout(&tmparray2[segresid], ptr, 580 segsize - segresid); 581 first_pass = 0; 582 } else 583 copyout(tmparray2, ptr, segsize); 584 } else { 585 if (first_pass) { 586 587 ti_bcopy_swap(tmparray, tmparray2, 588 segsize, TI_SWAP_NTOH); 589 bcopy(&tmparray2[segresid], ptr, 590 segsize - segresid); 591 first_pass = 0; 592 } else 593 ti_bcopy_swap(tmparray, ptr, segsize, 594 TI_SWAP_NTOH); 595 } 596 597 } else { 598 if (useraddr) { 599 copyin(ptr, tmparray2, segsize); 600 ti_bcopy_swap(tmparray2, tmparray, segsize, 601 TI_SWAP_HTON); 602 } else 603 ti_bcopy_swap(ptr, tmparray, segsize, 604 TI_SWAP_HTON); 605 606 bus_space_write_region_4(sc->ti_btag, 607 sc->ti_bhandle, ti_offset, 608 (u_int32_t *)tmparray, 609 segsize >> 2); 610 } 611 segptr += segsize; 612 ptr += segsize; 613 cnt -= segsize; 614 } 615 616 /* 617 * Handle leftover, non-word-aligned bytes. 618 */ 619 if (resid != 0) { 620 u_int32_t tmpval, tmpval2; 621 bus_size_t ti_offset; 622 623 /* 624 * Set the segment pointer. 625 */ 626 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 627 628 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 629 630 /* 631 * First, grab whatever is in our source/destination. 632 * We'll obviously need this for reads, but also for 633 * writes, since we'll be doing read/modify/write. 634 */ 635 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 636 ti_offset, &tmpval, 1); 637 638 /* 639 * Next, translate this from little-endian to big-endian 640 * (at least on i386 boxes). 641 */ 642 tmpval2 = ntohl(tmpval); 643 644 if (readdata) { 645 /* 646 * If we're reading, just copy the leftover number 647 * of bytes from the host byte order buffer to 648 * the user's buffer. 649 */ 650 if (useraddr) 651 copyout(&tmpval2, ptr, resid); 652 else 653 bcopy(&tmpval2, ptr, resid); 654 } else { 655 /* 656 * If we're writing, first copy the bytes to be 657 * written into the network byte order buffer, 658 * leaving the rest of the buffer with whatever was 659 * originally in there. Then, swap the bytes 660 * around into host order and write them out. 661 * 662 * XXX KDM the read side of this has been verified 663 * to work, but the write side of it has not been 664 * verified. So user beware. 665 */ 666 if (useraddr) 667 copyin(ptr, &tmpval2, resid); 668 else 669 bcopy(ptr, &tmpval2, resid); 670 671 tmpval = htonl(tmpval2); 672 673 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 674 ti_offset, &tmpval, 1); 675 } 676 } 677 678 CSR_WRITE_4(sc, TI_WINBASE, origwin); 679 680 TI_UNLOCK(sc); 681 682 return(0); 683} 684 685static int 686ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 687 struct ti_softc *sc; 688 u_int32_t tigon_addr, len; 689 caddr_t buf; 690 int useraddr, readdata; 691 int cpu; 692{ 693 u_int32_t segptr; 694 int cnt; 695 u_int32_t tmpval, tmpval2; 696 caddr_t ptr; 697 698 /* 699 * At the moment, we don't handle non-aligned cases, we just bail. 700 * If this proves to be a problem, it will be fixed. 701 */ 702 if (tigon_addr & 0x3) { 703 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 704 "word-aligned\n", sc->ti_unit, tigon_addr); 705 return(EINVAL); 706 } 707 708 if (len & 0x3) { 709 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 710 "word-aligned\n", sc->ti_unit, len); 711 return(EINVAL); 712 } 713 714 segptr = tigon_addr; 715 cnt = len; 716 ptr = buf; 717 718 TI_LOCK(sc); 719 720 while (cnt) { 721 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 722 723 if (readdata) { 724 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 725 726 tmpval = ntohl(tmpval2); 727 728 /* 729 * Note: I've used this debugging interface 730 * extensively with Alteon's 12.3.15 firmware, 731 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 732 * 733 * When you compile the firmware without 734 * optimization, which is necessary sometimes in 735 * order to properly step through it, you sometimes 736 * read out a bogus value of 0xc0017c instead of 737 * whatever was supposed to be in that scratchpad 738 * location. That value is on the stack somewhere, 739 * but I've never been able to figure out what was 740 * causing the problem. 741 * 742 * The address seems to pop up in random places, 743 * often not in the same place on two subsequent 744 * reads. 745 * 746 * In any case, the underlying data doesn't seem 747 * to be affected, just the value read out. 748 * 749 * KDM, 3/7/2000 750 */ 751 752 if (tmpval2 == 0xc0017c) 753 printf("ti%d: found 0xc0017c at %#x " 754 "(tmpval2)\n", sc->ti_unit, segptr); 755 756 if (tmpval == 0xc0017c) 757 printf("ti%d: found 0xc0017c at %#x " 758 "(tmpval)\n", sc->ti_unit, segptr); 759 760 if (useraddr) 761 copyout(&tmpval, ptr, 4); 762 else 763 bcopy(&tmpval, ptr, 4); 764 } else { 765 if (useraddr) 766 copyin(ptr, &tmpval2, 4); 767 else 768 bcopy(ptr, &tmpval2, 4); 769 770 tmpval = htonl(tmpval2); 771 772 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 773 } 774 775 cnt -= 4; 776 segptr += 4; 777 ptr += 4; 778 } 779 780 TI_UNLOCK(sc); 781 782 return(0); 783} 784 785static int 786ti_bcopy_swap(src, dst, len, swap_type) 787 const void *src; 788 void *dst; 789 size_t len; 790 ti_swap_type swap_type; 791{ 792 const u_int8_t *tmpsrc; 793 u_int8_t *tmpdst; 794 size_t tmplen; 795 796 if (len & 0x3) { 797 printf("ti_bcopy_swap: length %d isn't 32-bit aligned\n", 798 len); 799 return(-1); 800 } 801 802 tmpsrc = src; 803 tmpdst = dst; 804 tmplen = len; 805 806 while (tmplen) { 807 if (swap_type == TI_SWAP_NTOH) 808 *(u_int32_t *)tmpdst = 809 ntohl(*(const u_int32_t *)tmpsrc); 810 else 811 *(u_int32_t *)tmpdst = 812 htonl(*(const u_int32_t *)tmpsrc); 813 814 tmpsrc += 4; 815 tmpdst += 4; 816 tmplen -= 4; 817 } 818 819 return(0); 820} 821 822/* 823 * Load firmware image into the NIC. Check that the firmware revision 824 * is acceptable and see if we want the firmware for the Tigon 1 or 825 * Tigon 2. 826 */ 827static void ti_loadfw(sc) 828 struct ti_softc *sc; 829{ 830 switch(sc->ti_hwrev) { 831 case TI_HWREV_TIGON: 832 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 833 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 834 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 835 printf("ti%d: firmware revision mismatch; want " 836 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 837 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 838 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 839 tigonFwReleaseMinor, tigonFwReleaseFix); 840 return; 841 } 842 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 843 (caddr_t)tigonFwText); 844 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 845 (caddr_t)tigonFwData); 846 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 847 (caddr_t)tigonFwRodata); 848 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 849 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 850 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 851 break; 852 case TI_HWREV_TIGON_II: 853 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 854 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 855 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 856 printf("ti%d: firmware revision mismatch; want " 857 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 858 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 859 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 860 tigon2FwReleaseMinor, tigon2FwReleaseFix); 861 return; 862 } 863 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 864 (caddr_t)tigon2FwText); 865 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 866 (caddr_t)tigon2FwData); 867 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 868 (caddr_t)tigon2FwRodata); 869 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 870 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 871 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 872 break; 873 default: 874 printf("ti%d: can't load firmware: unknown hardware rev\n", 875 sc->ti_unit); 876 break; 877 } 878 879 return; 880} 881 882/* 883 * Send the NIC a command via the command ring. 884 */ 885static void ti_cmd(sc, cmd) 886 struct ti_softc *sc; 887 struct ti_cmd_desc *cmd; 888{ 889 u_int32_t index; 890 891 if (sc->ti_rdata->ti_cmd_ring == NULL) 892 return; 893 894 index = sc->ti_cmd_saved_prodidx; 895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 896 TI_INC(index, TI_CMD_RING_CNT); 897 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 898 sc->ti_cmd_saved_prodidx = index; 899 900 return; 901} 902 903/* 904 * Send the NIC an extended command. The 'len' parameter specifies the 905 * number of command slots to include after the initial command. 906 */ 907static void ti_cmd_ext(sc, cmd, arg, len) 908 struct ti_softc *sc; 909 struct ti_cmd_desc *cmd; 910 caddr_t arg; 911 int len; 912{ 913 u_int32_t index; 914 register int i; 915 916 if (sc->ti_rdata->ti_cmd_ring == NULL) 917 return; 918 919 index = sc->ti_cmd_saved_prodidx; 920 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 921 TI_INC(index, TI_CMD_RING_CNT); 922 for (i = 0; i < len; i++) { 923 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 924 *(u_int32_t *)(&arg[i * 4])); 925 TI_INC(index, TI_CMD_RING_CNT); 926 } 927 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 928 sc->ti_cmd_saved_prodidx = index; 929 930 return; 931} 932 933/* 934 * Handle events that have triggered interrupts. 935 */ 936static void ti_handle_events(sc) 937 struct ti_softc *sc; 938{ 939 struct ti_event_desc *e; 940 941 if (sc->ti_rdata->ti_event_ring == NULL) 942 return; 943 944 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 945 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 946 switch(e->ti_event) { 947 case TI_EV_LINKSTAT_CHANGED: 948 sc->ti_linkstat = e->ti_code; 949 if (e->ti_code == TI_EV_CODE_LINK_UP) 950 printf("ti%d: 10/100 link up\n", sc->ti_unit); 951 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 952 printf("ti%d: gigabit link up\n", sc->ti_unit); 953 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 954 printf("ti%d: link down\n", sc->ti_unit); 955 break; 956 case TI_EV_ERROR: 957 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 958 printf("ti%d: invalid command\n", sc->ti_unit); 959 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 960 printf("ti%d: unknown command\n", sc->ti_unit); 961 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 962 printf("ti%d: bad config data\n", sc->ti_unit); 963 break; 964 case TI_EV_FIRMWARE_UP: 965 ti_init2(sc); 966 break; 967 case TI_EV_STATS_UPDATED: 968 ti_stats_update(sc); 969 break; 970 case TI_EV_RESET_JUMBO_RING: 971 case TI_EV_MCAST_UPDATED: 972 /* Who cares. */ 973 break; 974 default: 975 printf("ti%d: unknown event: %d\n", 976 sc->ti_unit, e->ti_event); 977 break; 978 } 979 /* Advance the consumer index. */ 980 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 981 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 982 } 983 984 return; 985} 986 987#ifdef TI_PRIVATE_JUMBOS 988 989/* 990 * Memory management for the jumbo receive ring is a pain in the 991 * butt. We need to allocate at least 9018 bytes of space per frame, 992 * _and_ it has to be contiguous (unless you use the extended 993 * jumbo descriptor format). Using malloc() all the time won't 994 * work: malloc() allocates memory in powers of two, which means we 995 * would end up wasting a considerable amount of space by allocating 996 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 997 * to do our own memory management. 998 * 999 * The driver needs to allocate a contiguous chunk of memory at boot 1000 * time. We then chop this up ourselves into 9K pieces and use them 1001 * as external mbuf storage. 1002 * 1003 * One issue here is how much memory to allocate. The jumbo ring has 1004 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1005 * RAM. This is a bit much, especially considering we also need 1006 * RAM for the standard ring and mini ring (on the Tigon 2). To 1007 * save space, we only actually allocate enough memory for 64 slots 1008 * by default, which works out to between 500 and 600K. This can 1009 * be tuned by changing a #define in if_tireg.h. 1010 */ 1011 1012static int ti_alloc_jumbo_mem(sc) 1013 struct ti_softc *sc; 1014{ 1015 caddr_t ptr; 1016 register int i; 1017 struct ti_jpool_entry *entry; 1018 1019 /* Grab a big chunk o' storage. */ 1020 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1021 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1022 1023 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1024 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1025 return(ENOBUFS); 1026 } 1027 1028 SLIST_INIT(&sc->ti_jfree_listhead); 1029 SLIST_INIT(&sc->ti_jinuse_listhead); 1030 1031 /* 1032 * Now divide it up into 9K pieces and save the addresses 1033 * in an array. 1034 */ 1035 ptr = sc->ti_cdata.ti_jumbo_buf; 1036 for (i = 0; i < TI_JSLOTS; i++) { 1037 sc->ti_cdata.ti_jslots[i] = ptr; 1038 ptr += TI_JLEN; 1039 entry = malloc(sizeof(struct ti_jpool_entry), 1040 M_DEVBUF, M_NOWAIT); 1041 if (entry == NULL) { 1042 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1043 M_DEVBUF); 1044 sc->ti_cdata.ti_jumbo_buf = NULL; 1045 printf("ti%d: no memory for jumbo " 1046 "buffer queue!\n", sc->ti_unit); 1047 return(ENOBUFS); 1048 } 1049 entry->slot = i; 1050 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1051 } 1052 1053 return(0); 1054} 1055 1056/* 1057 * Allocate a jumbo buffer. 1058 */ 1059static void *ti_jalloc(sc) 1060 struct ti_softc *sc; 1061{ 1062 struct ti_jpool_entry *entry; 1063 1064 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1065 1066 if (entry == NULL) { 1067 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1068 return(NULL); 1069 } 1070 1071 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1072 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1073 return(sc->ti_cdata.ti_jslots[entry->slot]); 1074} 1075 1076/* 1077 * Release a jumbo buffer. 1078 */ 1079static void ti_jfree(buf, args) 1080 caddr_t buf; 1081 void *args; 1082{ 1083 struct ti_softc *sc; 1084 int i; 1085 struct ti_jpool_entry *entry; 1086 1087 /* Extract the softc struct pointer. */ 1088 sc = (struct ti_softc *)args; 1089 1090 if (sc == NULL) 1091 panic("ti_jfree: didn't get softc pointer!"); 1092 1093 /* calculate the slot this buffer belongs to */ 1094 i = ((vm_offset_t)buf 1095 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1096 1097 if ((i < 0) || (i >= TI_JSLOTS)) 1098 panic("ti_jfree: asked to free buffer that we don't manage!"); 1099 1100 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1101 if (entry == NULL) 1102 panic("ti_jfree: buffer not in use!"); 1103 entry->slot = i; 1104 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1105 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1106 1107 return; 1108} 1109 1110#endif /* TI_PRIVATE_JUMBOS */ 1111 1112/* 1113 * Intialize a standard receive ring descriptor. 1114 */ 1115static int ti_newbuf_std(sc, i, m) 1116 struct ti_softc *sc; 1117 int i; 1118 struct mbuf *m; 1119{ 1120 struct mbuf *m_new = NULL; 1121 struct ti_rx_desc *r; 1122 1123 if (m == NULL) { 1124 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1125 if (m_new == NULL) 1126 return(ENOBUFS); 1127 1128 MCLGET(m_new, M_DONTWAIT); 1129 if (!(m_new->m_flags & M_EXT)) { 1130 m_freem(m_new); 1131 return(ENOBUFS); 1132 } 1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1134 } else { 1135 m_new = m; 1136 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1137 m_new->m_data = m_new->m_ext.ext_buf; 1138 } 1139 1140 m_adj(m_new, ETHER_ALIGN); 1141 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1142 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1143 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1144 r->ti_type = TI_BDTYPE_RECV_BD; 1145 r->ti_flags = 0; 1146 if (sc->arpcom.ac_if.if_hwassist) 1147 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1148 r->ti_len = m_new->m_len; 1149 r->ti_idx = i; 1150 1151 return(0); 1152} 1153 1154/* 1155 * Intialize a mini receive ring descriptor. This only applies to 1156 * the Tigon 2. 1157 */ 1158static int ti_newbuf_mini(sc, i, m) 1159 struct ti_softc *sc; 1160 int i; 1161 struct mbuf *m; 1162{ 1163 struct mbuf *m_new = NULL; 1164 struct ti_rx_desc *r; 1165 1166 if (m == NULL) { 1167 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1168 if (m_new == NULL) { 1169 return(ENOBUFS); 1170 } 1171 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1172 } else { 1173 m_new = m; 1174 m_new->m_data = m_new->m_pktdat; 1175 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1176 } 1177 1178 m_adj(m_new, ETHER_ALIGN); 1179 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1180 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1181 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1182 r->ti_type = TI_BDTYPE_RECV_BD; 1183 r->ti_flags = TI_BDFLAG_MINI_RING; 1184 if (sc->arpcom.ac_if.if_hwassist) 1185 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1186 r->ti_len = m_new->m_len; 1187 r->ti_idx = i; 1188 1189 return(0); 1190} 1191 1192#ifdef TI_PRIVATE_JUMBOS 1193 1194/* 1195 * Initialize a jumbo receive ring descriptor. This allocates 1196 * a jumbo buffer from the pool managed internally by the driver. 1197 */ 1198static int ti_newbuf_jumbo(sc, i, m) 1199 struct ti_softc *sc; 1200 int i; 1201 struct mbuf *m; 1202{ 1203 struct mbuf *m_new = NULL; 1204 struct ti_rx_desc *r; 1205 1206 if (m == NULL) { 1207 caddr_t *buf = NULL; 1208 1209 /* Allocate the mbuf. */ 1210 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1211 if (m_new == NULL) { 1212 return(ENOBUFS); 1213 } 1214 1215 /* Allocate the jumbo buffer */ 1216 buf = ti_jalloc(sc); 1217 if (buf == NULL) { 1218 m_freem(m_new); 1219 printf("ti%d: jumbo allocation failed " 1220 "-- packet dropped!\n", sc->ti_unit); 1221 return(ENOBUFS); 1222 } 1223 1224 /* Attach the buffer to the mbuf. */ 1225 m_new->m_data = (void *) buf; 1226 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1227 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1228 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1229 } else { 1230 m_new = m; 1231 m_new->m_data = m_new->m_ext.ext_buf; 1232 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1233 } 1234 1235 m_adj(m_new, ETHER_ALIGN); 1236 /* Set up the descriptor. */ 1237 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1238 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1239 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1240 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1241 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1242 if (sc->arpcom.ac_if.if_hwassist) 1243 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1244 r->ti_len = m_new->m_len; 1245 r->ti_idx = i; 1246 1247 return(0); 1248} 1249 1250#else 1251#include <vm/vm_page.h> 1252 1253#if (PAGE_SIZE == 4096) 1254#define NPAYLOAD 2 1255#else 1256#define NPAYLOAD 1 1257#endif 1258 1259#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1260#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1261#define NFS_HDR_LEN (UDP_HDR_LEN) 1262int HDR_LEN = TCP_HDR_LEN; 1263 1264 1265 /* 1266 * Initialize a jumbo receive ring descriptor. This allocates 1267 * a jumbo buffer from the pool managed internally by the driver. 1268 */ 1269static int 1270ti_newbuf_jumbo(sc, idx, m_old) 1271 struct ti_softc *sc; 1272 int idx; 1273 struct mbuf *m_old; 1274{ 1275 struct mbuf *cur, *m_new = NULL; 1276 struct mbuf *m[3] = {NULL, NULL, NULL}; 1277 struct ti_rx_desc_ext *r; 1278 vm_page_t frame; 1279 /* 1 extra buf to make nobufs easy*/ 1280 caddr_t buf[3] = {NULL, NULL, NULL}; 1281 int i; 1282 1283 if (m_old != NULL) { 1284 m_new = m_old; 1285 cur = m_old->m_next; 1286 for (i = 0; i <= NPAYLOAD; i++){ 1287 m[i] = cur; 1288 cur = cur->m_next; 1289 } 1290 } else { 1291 /* Allocate the mbufs. */ 1292 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1293 if (m_new == NULL) { 1294 printf("ti%d: mbuf allocation failed " 1295 "-- packet dropped!\n", sc->ti_unit); 1296 goto nobufs; 1297 } 1298 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1299 if (m[NPAYLOAD] == NULL) { 1300 printf("ti%d: cluster mbuf allocation failed " 1301 "-- packet dropped!\n", sc->ti_unit); 1302 goto nobufs; 1303 } 1304 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1305 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1306 printf("ti%d: mbuf allocation failed " 1307 "-- packet dropped!\n", sc->ti_unit); 1308 goto nobufs; 1309 } 1310 m[NPAYLOAD]->m_len = MCLBYTES; 1311 1312 for (i = 0; i < NPAYLOAD; i++){ 1313 MGET(m[i], M_DONTWAIT, MT_DATA); 1314 if (m[i] == NULL) { 1315 printf("ti%d: mbuf allocation failed " 1316 "-- packet dropped!\n", sc->ti_unit); 1317 goto nobufs; 1318 } 1319 if (!(frame = jumbo_pg_alloc())){ 1320 printf("ti%d: buffer allocation failed " 1321 "-- packet dropped!\n", sc->ti_unit); 1322 printf(" index %d page %d\n", idx, i); 1323 goto nobufs; 1324 } 1325 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1326 } 1327 for (i = 0; i < NPAYLOAD; i++){ 1328 /* Attach the buffer to the mbuf. */ 1329 m[i]->m_data = (void *)buf[i]; 1330 m[i]->m_len = PAGE_SIZE; 1331 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1332 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1333 m[i]->m_next = m[i+1]; 1334 } 1335 /* link the buffers to the header */ 1336 m_new->m_next = m[0]; 1337 m_new->m_data += ETHER_ALIGN; 1338 if (sc->ti_hdrsplit) 1339 m_new->m_len = MHLEN - ETHER_ALIGN; 1340 else 1341 m_new->m_len = HDR_LEN; 1342 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1343 } 1344 1345 /* Set up the descriptor. */ 1346 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1347 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1348 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1349 r->ti_len0 = m_new->m_len; 1350 1351 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1352 r->ti_len1 = PAGE_SIZE; 1353 1354 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1355 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1356 1357 if (PAGE_SIZE == 4096) { 1358 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1359 r->ti_len3 = MCLBYTES; 1360 } else { 1361 r->ti_len3 = 0; 1362 } 1363 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1364 1365 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1366 1367 if (sc->arpcom.ac_if.if_hwassist) 1368 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1369 1370 r->ti_idx = idx; 1371 1372 return(0); 1373 1374 nobufs: 1375 1376 /* 1377 * Warning! : 1378 * This can only be called before the mbufs are strung together. 1379 * If the mbufs are strung together, m_freem() will free the chain, 1380 * so that the later mbufs will be freed multiple times. 1381 */ 1382 if (m_new) 1383 m_freem(m_new); 1384 1385 for(i = 0; i < 3; i++){ 1386 if (m[i]) 1387 m_freem(m[i]); 1388 if (buf[i]) 1389 jumbo_pg_free((vm_offset_t)buf[i]); 1390 } 1391 return ENOBUFS; 1392} 1393#endif 1394 1395 1396 1397/* 1398 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1399 * that's 1MB or memory, which is a lot. For now, we fill only the first 1400 * 256 ring entries and hope that our CPU is fast enough to keep up with 1401 * the NIC. 1402 */ 1403static int ti_init_rx_ring_std(sc) 1404 struct ti_softc *sc; 1405{ 1406 register int i; 1407 struct ti_cmd_desc cmd; 1408 1409 for (i = 0; i < TI_SSLOTS; i++) { 1410 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1411 return(ENOBUFS); 1412 }; 1413 1414 TI_UPDATE_STDPROD(sc, i - 1); 1415 sc->ti_std = i - 1; 1416 1417 return(0); 1418} 1419 1420static void ti_free_rx_ring_std(sc) 1421 struct ti_softc *sc; 1422{ 1423 register int i; 1424 1425 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1426 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1427 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1428 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1429 } 1430 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1431 sizeof(struct ti_rx_desc)); 1432 } 1433 1434 return; 1435} 1436 1437static int ti_init_rx_ring_jumbo(sc) 1438 struct ti_softc *sc; 1439{ 1440 register int i; 1441 struct ti_cmd_desc cmd; 1442 1443 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1444 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1445 return(ENOBUFS); 1446 }; 1447 1448 TI_UPDATE_JUMBOPROD(sc, i - 1); 1449 sc->ti_jumbo = i - 1; 1450 1451 return(0); 1452} 1453 1454static void ti_free_rx_ring_jumbo(sc) 1455 struct ti_softc *sc; 1456{ 1457 register int i; 1458 1459 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1460 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1461 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1462 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1463 } 1464 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1465 sizeof(struct ti_rx_desc)); 1466 } 1467 1468 return; 1469} 1470 1471static int ti_init_rx_ring_mini(sc) 1472 struct ti_softc *sc; 1473{ 1474 register int i; 1475 1476 for (i = 0; i < TI_MSLOTS; i++) { 1477 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1478 return(ENOBUFS); 1479 }; 1480 1481 TI_UPDATE_MINIPROD(sc, i - 1); 1482 sc->ti_mini = i - 1; 1483 1484 return(0); 1485} 1486 1487static void ti_free_rx_ring_mini(sc) 1488 struct ti_softc *sc; 1489{ 1490 register int i; 1491 1492 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1493 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1494 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1495 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1496 } 1497 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1498 sizeof(struct ti_rx_desc)); 1499 } 1500 1501 return; 1502} 1503 1504static void ti_free_tx_ring(sc) 1505 struct ti_softc *sc; 1506{ 1507 register int i; 1508 1509 if (sc->ti_rdata->ti_tx_ring == NULL) 1510 return; 1511 1512 for (i = 0; i < TI_TX_RING_CNT; i++) { 1513 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1514 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1515 sc->ti_cdata.ti_tx_chain[i] = NULL; 1516 } 1517 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1518 sizeof(struct ti_tx_desc)); 1519 } 1520 1521 return; 1522} 1523 1524static int ti_init_tx_ring(sc) 1525 struct ti_softc *sc; 1526{ 1527 sc->ti_txcnt = 0; 1528 sc->ti_tx_saved_considx = 0; 1529 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1530 return(0); 1531} 1532 1533/* 1534 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1535 * but we have to support the old way too so that Tigon 1 cards will 1536 * work. 1537 */ 1538void ti_add_mcast(sc, addr) 1539 struct ti_softc *sc; 1540 struct ether_addr *addr; 1541{ 1542 struct ti_cmd_desc cmd; 1543 u_int16_t *m; 1544 u_int32_t ext[2] = {0, 0}; 1545 1546 m = (u_int16_t *)&addr->octet[0]; 1547 1548 switch(sc->ti_hwrev) { 1549 case TI_HWREV_TIGON: 1550 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1551 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1552 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1553 break; 1554 case TI_HWREV_TIGON_II: 1555 ext[0] = htons(m[0]); 1556 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1557 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1558 break; 1559 default: 1560 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1561 break; 1562 } 1563 1564 return; 1565} 1566 1567void ti_del_mcast(sc, addr) 1568 struct ti_softc *sc; 1569 struct ether_addr *addr; 1570{ 1571 struct ti_cmd_desc cmd; 1572 u_int16_t *m; 1573 u_int32_t ext[2] = {0, 0}; 1574 1575 m = (u_int16_t *)&addr->octet[0]; 1576 1577 switch(sc->ti_hwrev) { 1578 case TI_HWREV_TIGON: 1579 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1580 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1581 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1582 break; 1583 case TI_HWREV_TIGON_II: 1584 ext[0] = htons(m[0]); 1585 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1586 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1587 break; 1588 default: 1589 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1590 break; 1591 } 1592 1593 return; 1594} 1595 1596/* 1597 * Configure the Tigon's multicast address filter. 1598 * 1599 * The actual multicast table management is a bit of a pain, thanks to 1600 * slight brain damage on the part of both Alteon and us. With our 1601 * multicast code, we are only alerted when the multicast address table 1602 * changes and at that point we only have the current list of addresses: 1603 * we only know the current state, not the previous state, so we don't 1604 * actually know what addresses were removed or added. The firmware has 1605 * state, but we can't get our grubby mits on it, and there is no 'delete 1606 * all multicast addresses' command. Hence, we have to maintain our own 1607 * state so we know what addresses have been programmed into the NIC at 1608 * any given time. 1609 */ 1610static void ti_setmulti(sc) 1611 struct ti_softc *sc; 1612{ 1613 struct ifnet *ifp; 1614 struct ifmultiaddr *ifma; 1615 struct ti_cmd_desc cmd; 1616 struct ti_mc_entry *mc; 1617 u_int32_t intrs; 1618 1619 ifp = &sc->arpcom.ac_if; 1620 1621 if (ifp->if_flags & IFF_ALLMULTI) { 1622 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1623 return; 1624 } else { 1625 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1626 } 1627 1628 /* Disable interrupts. */ 1629 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1630 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1631 1632 /* First, zot all the existing filters. */ 1633 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1634 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1635 ti_del_mcast(sc, &mc->mc_addr); 1636 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1637 free(mc, M_DEVBUF); 1638 } 1639 1640 /* Now program new ones. */ 1641 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1642 if (ifma->ifma_addr->sa_family != AF_LINK) 1643 continue; 1644 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1645 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1646 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1647 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1648 ti_add_mcast(sc, &mc->mc_addr); 1649 } 1650 1651 /* Re-enable interrupts. */ 1652 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1653 1654 return; 1655} 1656 1657/* 1658 * Check to see if the BIOS has configured us for a 64 bit slot when 1659 * we aren't actually in one. If we detect this condition, we can work 1660 * around it on the Tigon 2 by setting a bit in the PCI state register, 1661 * but for the Tigon 1 we must give up and abort the interface attach. 1662 */ 1663static int ti_64bitslot_war(sc) 1664 struct ti_softc *sc; 1665{ 1666 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1667 CSR_WRITE_4(sc, 0x600, 0); 1668 CSR_WRITE_4(sc, 0x604, 0); 1669 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1670 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1671 if (sc->ti_hwrev == TI_HWREV_TIGON) 1672 return(EINVAL); 1673 else { 1674 TI_SETBIT(sc, TI_PCI_STATE, 1675 TI_PCISTATE_32BIT_BUS); 1676 return(0); 1677 } 1678 } 1679 } 1680 1681 return(0); 1682} 1683 1684/* 1685 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1686 * self-test results. 1687 */ 1688static int ti_chipinit(sc) 1689 struct ti_softc *sc; 1690{ 1691 u_int32_t cacheline; 1692 u_int32_t pci_writemax = 0; 1693 u_int32_t hdrsplit; 1694 1695 /* Initialize link to down state. */ 1696 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1697 1698 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1699 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1700 else 1701 sc->arpcom.ac_if.if_hwassist = 0; 1702 1703 /* Set endianness before we access any non-PCI registers. */ 1704#if BYTE_ORDER == BIG_ENDIAN 1705 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1706 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1707#else 1708 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1709 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1710#endif 1711 1712 /* Check the ROM failed bit to see if self-tests passed. */ 1713 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1714 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1715 return(ENODEV); 1716 } 1717 1718 /* Halt the CPU. */ 1719 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1720 1721 /* Figure out the hardware revision. */ 1722 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1723 case TI_REV_TIGON_I: 1724 sc->ti_hwrev = TI_HWREV_TIGON; 1725 break; 1726 case TI_REV_TIGON_II: 1727 sc->ti_hwrev = TI_HWREV_TIGON_II; 1728 break; 1729 default: 1730 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1731 return(ENODEV); 1732 } 1733 1734 /* Do special setup for Tigon 2. */ 1735 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1736 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1737 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1738 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1739 } 1740 1741 /* 1742 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1743 * can't do header splitting. 1744 */ 1745#ifdef TI_JUMBO_HDRSPLIT 1746 if (sc->ti_hwrev != TI_HWREV_TIGON) 1747 sc->ti_hdrsplit = 1; 1748 else 1749 printf("ti%d: can't do header splitting on a Tigon I board\n", 1750 sc->ti_unit); 1751#endif /* TI_JUMBO_HDRSPLIT */ 1752 1753 /* Set up the PCI state register. */ 1754 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1755 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1756 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1757 } 1758 1759 /* Clear the read/write max DMA parameters. */ 1760 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1761 TI_PCISTATE_READ_MAXDMA)); 1762 1763 /* Get cache line size. */ 1764 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1765 1766 /* 1767 * If the system has set enabled the PCI memory write 1768 * and invalidate command in the command register, set 1769 * the write max parameter accordingly. This is necessary 1770 * to use MWI with the Tigon 2. 1771 */ 1772 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1773 switch(cacheline) { 1774 case 1: 1775 case 4: 1776 case 8: 1777 case 16: 1778 case 32: 1779 case 64: 1780 break; 1781 default: 1782 /* Disable PCI memory write and invalidate. */ 1783 if (bootverbose) 1784 printf("ti%d: cache line size %d not " 1785 "supported; disabling PCI MWI\n", 1786 sc->ti_unit, cacheline); 1787 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1788 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1789 break; 1790 } 1791 } 1792 1793#ifdef __brokenalpha__ 1794 /* 1795 * From the Alteon sample driver: 1796 * Must insure that we do not cross an 8K (bytes) boundary 1797 * for DMA reads. Our highest limit is 1K bytes. This is a 1798 * restriction on some ALPHA platforms with early revision 1799 * 21174 PCI chipsets, such as the AlphaPC 164lx 1800 */ 1801 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1802#else 1803 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1804#endif 1805 1806 /* This sets the min dma param all the way up (0xff). */ 1807 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1808 1809 if (sc->ti_hdrsplit) 1810 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1811 else 1812 hdrsplit = 0; 1813 1814 /* Configure DMA variables. */ 1815#if BYTE_ORDER == BIG_ENDIAN 1816 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1817 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1818 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1819 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1820#else /* BYTE_ORDER */ 1821 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1822 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1823 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1824#endif /* BYTE_ORDER */ 1825 1826 /* 1827 * Only allow 1 DMA channel to be active at a time. 1828 * I don't think this is a good idea, but without it 1829 * the firmware racks up lots of nicDmaReadRingFull 1830 * errors. This is not compatible with hardware checksums. 1831 */ 1832 if (sc->arpcom.ac_if.if_hwassist == 0) 1833 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1834 1835 /* Recommended settings from Tigon manual. */ 1836 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1837 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1838 1839 if (ti_64bitslot_war(sc)) { 1840 printf("ti%d: bios thinks we're in a 64 bit slot, " 1841 "but we aren't", sc->ti_unit); 1842 return(EINVAL); 1843 } 1844 1845 return(0); 1846} 1847 1848/* 1849 * Initialize the general information block and firmware, and 1850 * start the CPU(s) running. 1851 */ 1852static int ti_gibinit(sc) 1853 struct ti_softc *sc; 1854{ 1855 struct ti_rcb *rcb; 1856 int i; 1857 struct ifnet *ifp; 1858 1859 ifp = &sc->arpcom.ac_if; 1860 1861 /* Disable interrupts for now. */ 1862 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1863 1864 /* Tell the chip where to find the general information block. */ 1865 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1866 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1867 1868 /* Load the firmware into SRAM. */ 1869 ti_loadfw(sc); 1870 1871 /* Set up the contents of the general info and ring control blocks. */ 1872 1873 /* Set up the event ring and producer pointer. */ 1874 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1875 1876 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1877 rcb->ti_flags = 0; 1878 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1879 vtophys(&sc->ti_ev_prodidx); 1880 sc->ti_ev_prodidx.ti_idx = 0; 1881 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1882 sc->ti_ev_saved_considx = 0; 1883 1884 /* Set up the command ring and producer mailbox. */ 1885 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1886 1887 sc->ti_rdata->ti_cmd_ring = 1888 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1889 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1890 rcb->ti_flags = 0; 1891 rcb->ti_max_len = 0; 1892 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1893 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1894 } 1895 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1896 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1897 sc->ti_cmd_saved_prodidx = 0; 1898 1899 /* 1900 * Assign the address of the stats refresh buffer. 1901 * We re-use the current stats buffer for this to 1902 * conserve memory. 1903 */ 1904 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1905 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1906 1907 /* Set up the standard receive ring. */ 1908 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1909 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1910 rcb->ti_max_len = TI_FRAMELEN; 1911 rcb->ti_flags = 0; 1912 if (sc->arpcom.ac_if.if_hwassist) 1913 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1914 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1915 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1916 1917 /* Set up the jumbo receive ring. */ 1918 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1919 TI_HOSTADDR(rcb->ti_hostaddr) = 1920 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1921 1922#ifdef TI_PRIVATE_JUMBOS 1923 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1924 rcb->ti_flags = 0; 1925#else 1926 rcb->ti_max_len = PAGE_SIZE; 1927 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1928#endif 1929 if (sc->arpcom.ac_if.if_hwassist) 1930 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1931 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1932 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1933 1934 /* 1935 * Set up the mini ring. Only activated on the 1936 * Tigon 2 but the slot in the config block is 1937 * still there on the Tigon 1. 1938 */ 1939 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1940 TI_HOSTADDR(rcb->ti_hostaddr) = 1941 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1942 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1943 if (sc->ti_hwrev == TI_HWREV_TIGON) 1944 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1945 else 1946 rcb->ti_flags = 0; 1947 if (sc->arpcom.ac_if.if_hwassist) 1948 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1949 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1950 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1951 1952 /* 1953 * Set up the receive return ring. 1954 */ 1955 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1956 TI_HOSTADDR(rcb->ti_hostaddr) = 1957 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1958 rcb->ti_flags = 0; 1959 rcb->ti_max_len = TI_RETURN_RING_CNT; 1960 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1961 vtophys(&sc->ti_return_prodidx); 1962 1963 /* 1964 * Set up the tx ring. Note: for the Tigon 2, we have the option 1965 * of putting the transmit ring in the host's address space and 1966 * letting the chip DMA it instead of leaving the ring in the NIC's 1967 * memory and accessing it through the shared memory region. We 1968 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1969 * so we have to revert to the shared memory scheme if we detect 1970 * a Tigon 1 chip. 1971 */ 1972 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1973 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1974 sc->ti_rdata->ti_tx_ring_nic = 1975 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1976 } 1977 bzero((char *)sc->ti_rdata->ti_tx_ring, 1978 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1979 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1980 if (sc->ti_hwrev == TI_HWREV_TIGON) 1981 rcb->ti_flags = 0; 1982 else 1983 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1984 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1985 if (sc->arpcom.ac_if.if_hwassist) 1986 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1987 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1988 rcb->ti_max_len = TI_TX_RING_CNT; 1989 if (sc->ti_hwrev == TI_HWREV_TIGON) 1990 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1991 else 1992 TI_HOSTADDR(rcb->ti_hostaddr) = 1993 vtophys(&sc->ti_rdata->ti_tx_ring); 1994 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1995 vtophys(&sc->ti_tx_considx); 1996 1997 /* Set up tuneables */ 1998#if 0 1999 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2000 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2001 (sc->ti_rx_coal_ticks / 10)); 2002 else 2003#endif 2004 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2005 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2006 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2007 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2008 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2009 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2010 2011 /* Turn interrupts on. */ 2012 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2013 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2014 2015 /* Start CPU. */ 2016 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2017 2018 return(0); 2019} 2020 2021/* 2022 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2023 * against our list and return its name if we find a match. 2024 */ 2025static int ti_probe(dev) 2026 device_t dev; 2027{ 2028 struct ti_type *t; 2029 2030 t = ti_devs; 2031 2032 while(t->ti_name != NULL) { 2033 if ((pci_get_vendor(dev) == t->ti_vid) && 2034 (pci_get_device(dev) == t->ti_did)) { 2035 device_set_desc(dev, t->ti_name); 2036 return(0); 2037 } 2038 t++; 2039 } 2040 2041 return(ENXIO); 2042} 2043 2044#ifdef KLD_MODULE 2045static int 2046log2rndup(int len) 2047{ 2048 int log2size = 0, t = len; 2049 while (t > 1) { 2050 log2size++; 2051 t >>= 1; 2052 } 2053 if (len != (1 << log2size)) 2054 log2size++; 2055 return log2size; 2056} 2057 2058static int 2059ti_mbuf_sanity(device_t dev) 2060{ 2061 if ((mbstat.m_msize != MSIZE) || mbstat.m_mclbytes != MCLBYTES){ 2062 device_printf(dev, "\n"); 2063 device_printf(dev, "This module was compiled with " 2064 "-DMCLSHIFT=%d -DMSIZE=%d\n", MCLSHIFT, 2065 MSIZE); 2066 device_printf(dev, "The kernel was compiled with MCLSHIFT=%d," 2067 " MSIZE=%d\n", log2rndup(mbstat.m_mclbytes), 2068 (int)mbstat.m_msize); 2069 return(EINVAL); 2070 } 2071 return(0); 2072} 2073#endif 2074 2075 2076static int ti_attach(dev) 2077 device_t dev; 2078{ 2079 u_int32_t command; 2080 struct ifnet *ifp; 2081 struct ti_softc *sc; 2082 int unit, error = 0, rid; 2083 2084 sc = NULL; 2085 2086#ifdef KLD_MODULE 2087 if (ti_mbuf_sanity(dev)){ 2088 device_printf(dev, "Module mbuf constants do not match " 2089 "kernel constants!\n"); 2090 device_printf(dev, "Rebuild the module or the kernel so " 2091 "they match\n"); 2092 device_printf(dev, "\n"); 2093 error = EINVAL; 2094 goto fail; 2095 } 2096#endif 2097 2098 sc = device_get_softc(dev); 2099 unit = device_get_unit(dev); 2100 bzero(sc, sizeof(struct ti_softc)); 2101 2102 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2103 MTX_DEF | MTX_RECURSE); 2104 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 2105 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2106 2107 /* 2108 * Map control/status registers. 2109 */ 2110 pci_enable_busmaster(dev); 2111 pci_enable_io(dev, SYS_RES_MEMORY); 2112 command = pci_read_config(dev, PCIR_COMMAND, 4); 2113 2114 if (!(command & PCIM_CMD_MEMEN)) { 2115 printf("ti%d: failed to enable memory mapping!\n", unit); 2116 error = ENXIO; 2117 goto fail; 2118 } 2119 2120 rid = TI_PCI_LOMEM; 2121 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2122 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2123 2124 if (sc->ti_res == NULL) { 2125 printf ("ti%d: couldn't map memory\n", unit); 2126 error = ENXIO; 2127 goto fail; 2128 } 2129 2130 sc->ti_btag = rman_get_bustag(sc->ti_res); 2131 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2132 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2133 2134 /* Allocate interrupt */ 2135 rid = 0; 2136 2137 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2138 RF_SHAREABLE | RF_ACTIVE); 2139 2140 if (sc->ti_irq == NULL) { 2141 printf("ti%d: couldn't map interrupt\n", unit); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 2146 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2147 ti_intr, sc, &sc->ti_intrhand); 2148 2149 if (error) { 2150 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2151 bus_release_resource(dev, SYS_RES_MEMORY, 2152 TI_PCI_LOMEM, sc->ti_res); 2153 printf("ti%d: couldn't set up irq\n", unit); 2154 goto fail; 2155 } 2156 2157 sc->ti_unit = unit; 2158 2159 if (ti_chipinit(sc)) { 2160 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2161 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2162 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2163 bus_release_resource(dev, SYS_RES_MEMORY, 2164 TI_PCI_LOMEM, sc->ti_res); 2165 error = ENXIO; 2166 goto fail; 2167 } 2168 2169 /* Zero out the NIC's on-board SRAM. */ 2170 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2171 2172 /* Init again -- zeroing memory may have clobbered some registers. */ 2173 if (ti_chipinit(sc)) { 2174 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2175 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2176 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2177 bus_release_resource(dev, SYS_RES_MEMORY, 2178 TI_PCI_LOMEM, sc->ti_res); 2179 error = ENXIO; 2180 goto fail; 2181 } 2182 2183 /* 2184 * Get station address from the EEPROM. Note: the manual states 2185 * that the MAC address is at offset 0x8c, however the data is 2186 * stored as two longwords (since that's how it's loaded into 2187 * the NIC). This means the MAC address is actually preceded 2188 * by two zero bytes. We need to skip over those. 2189 */ 2190 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2191 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2192 printf("ti%d: failed to read station address\n", unit); 2193 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2194 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2195 bus_release_resource(dev, SYS_RES_MEMORY, 2196 TI_PCI_LOMEM, sc->ti_res); 2197 error = ENXIO; 2198 goto fail; 2199 } 2200 2201 /* 2202 * A Tigon chip was detected. Inform the world. 2203 */ 2204 printf("ti%d: Ethernet address: %6D\n", unit, 2205 sc->arpcom.ac_enaddr, ":"); 2206 2207 /* Allocate the general information block and ring buffers. */ 2208 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2209 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2210 2211 if (sc->ti_rdata == NULL) { 2212 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2213 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2214 bus_release_resource(dev, SYS_RES_MEMORY, 2215 TI_PCI_LOMEM, sc->ti_res); 2216 error = ENXIO; 2217 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2218 goto fail; 2219 } 2220 2221 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2222 2223 /* Try to allocate memory for jumbo buffers. */ 2224#ifdef TI_PRIVATE_JUMBOS 2225 if (ti_alloc_jumbo_mem(sc)) { 2226 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2227 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2228 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2229 bus_release_resource(dev, SYS_RES_MEMORY, 2230 TI_PCI_LOMEM, sc->ti_res); 2231 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 2232 M_DEVBUF); 2233 error = ENXIO; 2234 goto fail; 2235 } 2236#else 2237 if (!jumbo_vm_init()) { 2238 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2239 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2240 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2241 bus_release_resource(dev, SYS_RES_MEMORY, 2242 TI_PCI_LOMEM, sc->ti_res); 2243 free(sc->ti_rdata, M_DEVBUF); 2244 error = ENOMEM; 2245 goto fail; 2246 } 2247#endif 2248 2249 /* 2250 * We really need a better way to tell a 1000baseTX card 2251 * from a 1000baseSX one, since in theory there could be 2252 * OEMed 1000baseTX cards from lame vendors who aren't 2253 * clever enough to change the PCI ID. For the moment 2254 * though, the AceNIC is the only copper card available. 2255 */ 2256 if (pci_get_vendor(dev) == ALT_VENDORID && 2257 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2258 sc->ti_copper = 1; 2259 /* Ok, it's not the only copper card available. */ 2260 if (pci_get_vendor(dev) == NG_VENDORID && 2261 pci_get_device(dev) == NG_DEVICEID_GA620T) 2262 sc->ti_copper = 1; 2263 2264 /* Set default tuneable values. */ 2265 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2266#if 0 2267 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2268#endif 2269 sc->ti_rx_coal_ticks = 170; 2270 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2271 sc->ti_rx_max_coal_bds = 64; 2272#if 0 2273 sc->ti_tx_max_coal_bds = 128; 2274#endif 2275 sc->ti_tx_max_coal_bds = 32; 2276 sc->ti_tx_buf_ratio = 21; 2277 2278 /* Set up ifnet structure */ 2279 ifp = &sc->arpcom.ac_if; 2280 ifp->if_softc = sc; 2281 ifp->if_unit = sc->ti_unit; 2282 ifp->if_name = "ti"; 2283 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2284 tis[unit] = sc; 2285 ifp->if_ioctl = ti_ioctl; 2286 ifp->if_output = ether_output; 2287 ifp->if_start = ti_start; 2288 ifp->if_watchdog = ti_watchdog; 2289 ifp->if_init = ti_init; 2290 ifp->if_mtu = ETHERMTU; 2291 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2292 2293 /* Set up ifmedia support. */ 2294 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2295 if (sc->ti_copper) { 2296 /* 2297 * Copper cards allow manual 10/100 mode selection, 2298 * but not manual 1000baseTX mode selection. Why? 2299 * Becuase currently there's no way to specify the 2300 * master/slave setting through the firmware interface, 2301 * so Alteon decided to just bag it and handle it 2302 * via autonegotiation. 2303 */ 2304 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2305 ifmedia_add(&sc->ifmedia, 2306 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2307 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2308 ifmedia_add(&sc->ifmedia, 2309 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2310 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2311 ifmedia_add(&sc->ifmedia, 2312 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2313 } else { 2314 /* Fiber cards don't support 10/100 modes. */ 2315 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2316 ifmedia_add(&sc->ifmedia, 2317 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2318 } 2319 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2320 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2321 2322 /* 2323 * We're assuming here that card initialization is a sequential 2324 * thing. If it isn't, multiple cards probing at the same time 2325 * could stomp on the list of softcs here. 2326 */ 2327 /* 2328 * If this is the first card to be initialized, initialize the 2329 * softc queue. 2330 */ 2331 if (unit == 0) 2332 STAILQ_INIT(&ti_sc_list); 2333 2334 STAILQ_INSERT_TAIL(&ti_sc_list, sc, ti_links); 2335 2336 /* Register the device */ 2337 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2338 0600, "ti%d", sc->ti_unit); 2339 2340 /* 2341 * Call MI attach routine. 2342 */ 2343 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2344 return(0); 2345 2346fail: 2347 mtx_destroy(&sc->ti_mtx); 2348 return(error); 2349} 2350 2351/* 2352 * Verify that our character special device is not currently 2353 * open. Also track down any cached vnodes & kill them before 2354 * the module is unloaded 2355 */ 2356static int 2357ti_unref_special(device_t dev) 2358{ 2359 struct vnode *ti_vn; 2360 int count; 2361 struct ti_softc *sc = sc = device_get_softc(dev); 2362 2363 if (!vfinddev(sc->dev, VCHR, &ti_vn)) { 2364 return 0; 2365 } 2366 2367 if ((count = vcount(ti_vn))) { 2368 device_printf(dev, "%d refs to special device, " 2369 "denying unload\n", count); 2370 return count; 2371 } 2372 /* now we know that there's a vnode in the cache. We hunt it 2373 down and kill it now, before unloading */ 2374 vgone(ti_vn); 2375 return(0); 2376} 2377 2378 2379static int ti_detach(dev) 2380 device_t dev; 2381{ 2382 struct ti_softc *sc; 2383 struct ifnet *ifp; 2384 2385 if (ti_unref_special(dev)) 2386 return EBUSY; 2387 2388 sc = device_get_softc(dev); 2389 TI_LOCK(sc); 2390 ifp = &sc->arpcom.ac_if; 2391 2392 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2393 ti_stop(sc); 2394 2395 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2396 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2397 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 2398 2399#ifdef TI_PRIVATE_JUMBOS 2400 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2401#endif 2402 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2403 ifmedia_removeall(&sc->ifmedia); 2404 2405 TI_UNLOCK(sc); 2406 mtx_destroy(&sc->ti_mtx); 2407 2408 return(0); 2409} 2410 2411#ifdef TI_JUMBO_HDRSPLIT 2412/* 2413 * If hdr_len is 0, that means that header splitting wasn't done on 2414 * this packet for some reason. The two most likely reasons are that 2415 * the protocol isn't a supported protocol for splitting, or this 2416 * packet had a fragment offset that wasn't 0. 2417 * 2418 * The header length, if it is non-zero, will always be the length of 2419 * the headers on the packet, but that length could be longer than the 2420 * first mbuf. So we take the minimum of the two as the actual 2421 * length. 2422 */ 2423static __inline void 2424ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2425{ 2426 int i = 0; 2427 int lengths[4] = {0, 0, 0, 0}; 2428 struct mbuf *m, *mp; 2429 2430 if (hdr_len != 0) 2431 top->m_len = min(hdr_len, top->m_len); 2432 pkt_len -= top->m_len; 2433 lengths[i++] = top->m_len; 2434 2435 mp = top; 2436 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2437 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2438 pkt_len -= m->m_len; 2439 lengths[i++] = m->m_len; 2440 mp = m; 2441 } 2442 2443#if 0 2444 if (hdr_len != 0) 2445 printf("got split packet: "); 2446 else 2447 printf("got non-split packet: "); 2448 2449 printf("%d,%d,%d,%d = %d\n", lengths[0], 2450 lengths[1], lengths[2], lengths[3], 2451 lengths[0] + lengths[1] + lengths[2] + 2452 lengths[3]); 2453#endif 2454 2455 if (pkt_len) 2456 panic("header splitting didn't"); 2457 2458 if (m) { 2459 m_freem(m); 2460 mp->m_next = NULL; 2461 2462 } 2463 if (mp->m_next != NULL) 2464 panic("ti_hdr_split: last mbuf in chain should be null"); 2465} 2466#endif /* TI_JUMBO_HDRSPLIT */ 2467 2468/* 2469 * Frame reception handling. This is called if there's a frame 2470 * on the receive return list. 2471 * 2472 * Note: we have to be able to handle three possibilities here: 2473 * 1) the frame is from the mini receive ring (can only happen) 2474 * on Tigon 2 boards) 2475 * 2) the frame is from the jumbo recieve ring 2476 * 3) the frame is from the standard receive ring 2477 */ 2478 2479static void ti_rxeof(sc) 2480 struct ti_softc *sc; 2481{ 2482 struct ifnet *ifp; 2483 struct ti_cmd_desc cmd; 2484 2485 ifp = &sc->arpcom.ac_if; 2486 2487 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2488 struct ti_rx_desc *cur_rx; 2489 u_int32_t rxidx; 2490 struct ether_header *eh; 2491 struct mbuf *m = NULL; 2492 u_int16_t vlan_tag = 0; 2493 int have_tag = 0; 2494 2495 cur_rx = 2496 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2497 rxidx = cur_rx->ti_idx; 2498 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2499 2500 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2501 have_tag = 1; 2502 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2503 } 2504 2505 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2506 2507 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2508 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2509 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2510 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2511 ifp->if_ierrors++; 2512 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2513 continue; 2514 } 2515 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2516 ifp->if_ierrors++; 2517 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2518 continue; 2519 } 2520#ifdef TI_PRIVATE_JUMBOS 2521 m->m_len = cur_rx->ti_len; 2522#else /* TI_PRIVATE_JUMBOS */ 2523#ifdef TI_JUMBO_HDRSPLIT 2524 if (sc->ti_hdrsplit) 2525 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2526 cur_rx->ti_len, rxidx); 2527 else 2528#endif /* TI_JUMBO_HDRSPLIT */ 2529 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2530#endif /* TI_PRIVATE_JUMBOS */ 2531 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2532 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2533 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2534 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2535 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2536 ifp->if_ierrors++; 2537 ti_newbuf_mini(sc, sc->ti_mini, m); 2538 continue; 2539 } 2540 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2541 ifp->if_ierrors++; 2542 ti_newbuf_mini(sc, sc->ti_mini, m); 2543 continue; 2544 } 2545 m->m_len = cur_rx->ti_len; 2546 } else { 2547 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2548 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2549 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2550 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2551 ifp->if_ierrors++; 2552 ti_newbuf_std(sc, sc->ti_std, m); 2553 continue; 2554 } 2555 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2556 ifp->if_ierrors++; 2557 ti_newbuf_std(sc, sc->ti_std, m); 2558 continue; 2559 } 2560 m->m_len = cur_rx->ti_len; 2561 } 2562 2563 m->m_pkthdr.len = cur_rx->ti_len; 2564 ifp->if_ipackets++; 2565 eh = mtod(m, struct ether_header *); 2566 m->m_pkthdr.rcvif = ifp; 2567 2568 /* Remove header from mbuf and pass it on. */ 2569 m_adj(m, sizeof(struct ether_header)); 2570 2571 if (ifp->if_hwassist) { 2572 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2573 CSUM_DATA_VALID; 2574 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2575 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2576 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2577 } 2578 2579 /* 2580 * If we received a packet with a vlan tag, pass it 2581 * to vlan_input() instead of ether_input(). 2582 */ 2583 if (have_tag) { 2584 VLAN_INPUT_TAG(eh, m, vlan_tag); 2585 have_tag = vlan_tag = 0; 2586 continue; 2587 } 2588 ether_input(ifp, eh, m); 2589 } 2590 2591 /* Only necessary on the Tigon 1. */ 2592 if (sc->ti_hwrev == TI_HWREV_TIGON) 2593 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2594 sc->ti_rx_saved_considx); 2595 2596 TI_UPDATE_STDPROD(sc, sc->ti_std); 2597 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2598 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2599 2600 return; 2601} 2602 2603static void ti_txeof(sc) 2604 struct ti_softc *sc; 2605{ 2606 struct ti_tx_desc *cur_tx = NULL; 2607 struct ifnet *ifp; 2608 2609 ifp = &sc->arpcom.ac_if; 2610 2611 /* 2612 * Go through our tx ring and free mbufs for those 2613 * frames that have been sent. 2614 */ 2615 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2616 u_int32_t idx = 0; 2617 2618 idx = sc->ti_tx_saved_considx; 2619 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2620 if (idx > 383) 2621 CSR_WRITE_4(sc, TI_WINBASE, 2622 TI_TX_RING_BASE + 6144); 2623 else if (idx > 255) 2624 CSR_WRITE_4(sc, TI_WINBASE, 2625 TI_TX_RING_BASE + 4096); 2626 else if (idx > 127) 2627 CSR_WRITE_4(sc, TI_WINBASE, 2628 TI_TX_RING_BASE + 2048); 2629 else 2630 CSR_WRITE_4(sc, TI_WINBASE, 2631 TI_TX_RING_BASE); 2632 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2633 } else 2634 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2635 if (cur_tx->ti_flags & TI_BDFLAG_END) 2636 ifp->if_opackets++; 2637 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2638 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2639 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2640 } 2641 sc->ti_txcnt--; 2642 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2643 ifp->if_timer = 0; 2644 } 2645 2646 if (cur_tx != NULL) 2647 ifp->if_flags &= ~IFF_OACTIVE; 2648 2649 return; 2650} 2651 2652static void ti_intr(xsc) 2653 void *xsc; 2654{ 2655 struct ti_softc *sc; 2656 struct ifnet *ifp; 2657 2658 sc = xsc; 2659 TI_LOCK(sc); 2660 ifp = &sc->arpcom.ac_if; 2661 2662/*#ifdef notdef*/ 2663 /* Avoid this for now -- checking this register is expensive. */ 2664 /* Make sure this is really our interrupt. */ 2665 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2666 TI_UNLOCK(sc); 2667 return; 2668 } 2669/*#endif*/ 2670 2671 /* Ack interrupt and stop others from occuring. */ 2672 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2673 2674 if (ifp->if_flags & IFF_RUNNING) { 2675 /* Check RX return ring producer/consumer */ 2676 ti_rxeof(sc); 2677 2678 /* Check TX ring producer/consumer */ 2679 ti_txeof(sc); 2680 } 2681 2682 ti_handle_events(sc); 2683 2684 /* Re-enable interrupts. */ 2685 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2686 2687 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2688 ti_start(ifp); 2689 2690 TI_UNLOCK(sc); 2691 2692 return; 2693} 2694 2695static void ti_stats_update(sc) 2696 struct ti_softc *sc; 2697{ 2698 struct ifnet *ifp; 2699 2700 ifp = &sc->arpcom.ac_if; 2701 2702 ifp->if_collisions += 2703 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2704 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2705 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2706 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2707 ifp->if_collisions; 2708 2709 return; 2710} 2711 2712/* 2713 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2714 * pointers to descriptors. 2715 */ 2716static int ti_encap(sc, m_head, txidx) 2717 struct ti_softc *sc; 2718 struct mbuf *m_head; 2719 u_int32_t *txidx; 2720{ 2721 struct ti_tx_desc *f = NULL; 2722 struct mbuf *m; 2723 u_int32_t frag, cur, cnt = 0; 2724 u_int16_t csum_flags = 0; 2725 struct ifvlan *ifv = NULL; 2726 2727 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2728 m_head->m_pkthdr.rcvif != NULL && 2729 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2730 ifv = m_head->m_pkthdr.rcvif->if_softc; 2731 2732 m = m_head; 2733 cur = frag = *txidx; 2734 2735 if (m_head->m_pkthdr.csum_flags) { 2736 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2737 csum_flags |= TI_BDFLAG_IP_CKSUM; 2738 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2739 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2740 if (m_head->m_flags & M_LASTFRAG) 2741 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2742 else if (m_head->m_flags & M_FRAG) 2743 csum_flags |= TI_BDFLAG_IP_FRAG; 2744 } 2745 /* 2746 * Start packing the mbufs in this chain into 2747 * the fragment pointers. Stop when we run out 2748 * of fragments or hit the end of the mbuf chain. 2749 */ 2750 for (m = m_head; m != NULL; m = m->m_next) { 2751 if (m->m_len != 0) { 2752 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2753 if (frag > 383) 2754 CSR_WRITE_4(sc, TI_WINBASE, 2755 TI_TX_RING_BASE + 6144); 2756 else if (frag > 255) 2757 CSR_WRITE_4(sc, TI_WINBASE, 2758 TI_TX_RING_BASE + 4096); 2759 else if (frag > 127) 2760 CSR_WRITE_4(sc, TI_WINBASE, 2761 TI_TX_RING_BASE + 2048); 2762 else 2763 CSR_WRITE_4(sc, TI_WINBASE, 2764 TI_TX_RING_BASE); 2765 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2766 } else 2767 f = &sc->ti_rdata->ti_tx_ring[frag]; 2768 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2769 break; 2770 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2771 f->ti_len = m->m_len; 2772 f->ti_flags = csum_flags; 2773 2774 if (ifv != NULL) { 2775 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2776 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 2777 } else { 2778 f->ti_vlan_tag = 0; 2779 } 2780 2781 /* 2782 * Sanity check: avoid coming within 16 descriptors 2783 * of the end of the ring. 2784 */ 2785 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2786 return(ENOBUFS); 2787 cur = frag; 2788 TI_INC(frag, TI_TX_RING_CNT); 2789 cnt++; 2790 } 2791 } 2792 2793 if (m != NULL) 2794 return(ENOBUFS); 2795 2796 if (frag == sc->ti_tx_saved_considx) 2797 return(ENOBUFS); 2798 2799 if (sc->ti_hwrev == TI_HWREV_TIGON) 2800 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2801 TI_BDFLAG_END; 2802 else 2803 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2804 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2805 sc->ti_txcnt += cnt; 2806 2807 *txidx = frag; 2808 2809 return(0); 2810} 2811 2812/* 2813 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2814 * to the mbuf data regions directly in the transmit descriptors. 2815 */ 2816static void ti_start(ifp) 2817 struct ifnet *ifp; 2818{ 2819 struct ti_softc *sc; 2820 struct mbuf *m_head = NULL; 2821 u_int32_t prodidx = 0; 2822 2823 sc = ifp->if_softc; 2824 TI_LOCK(sc); 2825 2826 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2827 2828 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2829 IF_DEQUEUE(&ifp->if_snd, m_head); 2830 if (m_head == NULL) 2831 break; 2832 2833 /* 2834 * XXX 2835 * safety overkill. If this is a fragmented packet chain 2836 * with delayed TCP/UDP checksums, then only encapsulate 2837 * it if we have enough descriptors to handle the entire 2838 * chain at once. 2839 * (paranoia -- may not actually be needed) 2840 */ 2841 if (m_head->m_flags & M_FIRSTFRAG && 2842 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2843 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2844 m_head->m_pkthdr.csum_data + 16) { 2845 IF_PREPEND(&ifp->if_snd, m_head); 2846 ifp->if_flags |= IFF_OACTIVE; 2847 break; 2848 } 2849 } 2850 2851 /* 2852 * Pack the data into the transmit ring. If we 2853 * don't have room, set the OACTIVE flag and wait 2854 * for the NIC to drain the ring. 2855 */ 2856 if (ti_encap(sc, m_head, &prodidx)) { 2857 IF_PREPEND(&ifp->if_snd, m_head); 2858 ifp->if_flags |= IFF_OACTIVE; 2859 break; 2860 } 2861 2862 /* 2863 * If there's a BPF listener, bounce a copy of this frame 2864 * to him. 2865 */ 2866 if (ifp->if_bpf) 2867 bpf_mtap(ifp, m_head); 2868 } 2869 2870 /* Transmit */ 2871 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2872 2873 /* 2874 * Set a timeout in case the chip goes out to lunch. 2875 */ 2876 ifp->if_timer = 5; 2877 TI_UNLOCK(sc); 2878 2879 return; 2880} 2881 2882static void ti_init(xsc) 2883 void *xsc; 2884{ 2885 struct ti_softc *sc = xsc; 2886 2887 /* Cancel pending I/O and flush buffers. */ 2888 ti_stop(sc); 2889 2890 TI_LOCK(sc); 2891 /* Init the gen info block, ring control blocks and firmware. */ 2892 if (ti_gibinit(sc)) { 2893 printf("ti%d: initialization failure\n", sc->ti_unit); 2894 TI_UNLOCK(sc); 2895 return; 2896 } 2897 2898 TI_UNLOCK(sc); 2899 2900 return; 2901} 2902 2903static void ti_init2(sc) 2904 struct ti_softc *sc; 2905{ 2906 struct ti_cmd_desc cmd; 2907 struct ifnet *ifp; 2908 u_int16_t *m; 2909 struct ifmedia *ifm; 2910 int tmp; 2911 2912 ifp = &sc->arpcom.ac_if; 2913 2914 /* Specify MTU and interface index. */ 2915 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2916 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2917 ETHER_HDR_LEN + ETHER_CRC_LEN); 2918 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2919 2920 /* Load our MAC address. */ 2921 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2922 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2923 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2924 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2925 2926 /* Enable or disable promiscuous mode as needed. */ 2927 if (ifp->if_flags & IFF_PROMISC) { 2928 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2929 } else { 2930 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2931 } 2932 2933 /* Program multicast filter. */ 2934 ti_setmulti(sc); 2935 2936 /* 2937 * If this is a Tigon 1, we should tell the 2938 * firmware to use software packet filtering. 2939 */ 2940 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2941 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2942 } 2943 2944 /* Init RX ring. */ 2945 ti_init_rx_ring_std(sc); 2946 2947 /* Init jumbo RX ring. */ 2948 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2949 ti_init_rx_ring_jumbo(sc); 2950 2951 /* 2952 * If this is a Tigon 2, we can also configure the 2953 * mini ring. 2954 */ 2955 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2956 ti_init_rx_ring_mini(sc); 2957 2958 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2959 sc->ti_rx_saved_considx = 0; 2960 2961 /* Init TX ring. */ 2962 ti_init_tx_ring(sc); 2963 2964 /* Tell firmware we're alive. */ 2965 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2966 2967 /* Enable host interrupts. */ 2968 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2969 2970 ifp->if_flags |= IFF_RUNNING; 2971 ifp->if_flags &= ~IFF_OACTIVE; 2972 2973 /* 2974 * Make sure to set media properly. We have to do this 2975 * here since we have to issue commands in order to set 2976 * the link negotiation and we can't issue commands until 2977 * the firmware is running. 2978 */ 2979 ifm = &sc->ifmedia; 2980 tmp = ifm->ifm_media; 2981 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2982 ti_ifmedia_upd(ifp); 2983 ifm->ifm_media = tmp; 2984 2985 return; 2986} 2987 2988/* 2989 * Set media options. 2990 */ 2991static int ti_ifmedia_upd(ifp) 2992 struct ifnet *ifp; 2993{ 2994 struct ti_softc *sc; 2995 struct ifmedia *ifm; 2996 struct ti_cmd_desc cmd; 2997 u_int32_t flowctl; 2998 2999 sc = ifp->if_softc; 3000 ifm = &sc->ifmedia; 3001 3002 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3003 return(EINVAL); 3004 3005 flowctl = 0; 3006 3007 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3008 case IFM_AUTO: 3009 /* 3010 * Transmit flow control doesn't work on the Tigon 1. 3011 */ 3012 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3013 3014 /* 3015 * Transmit flow control can also cause problems on the 3016 * Tigon 2, apparantly with both the copper and fiber 3017 * boards. The symptom is that the interface will just 3018 * hang. This was reproduced with Alteon 180 switches. 3019 */ 3020#if 0 3021 if (sc->ti_hwrev != TI_HWREV_TIGON) 3022 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3023#endif 3024 3025 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3026 TI_GLNK_FULL_DUPLEX| flowctl | 3027 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3028 3029 flowctl = TI_LNK_RX_FLOWCTL_Y; 3030#if 0 3031 if (sc->ti_hwrev != TI_HWREV_TIGON) 3032 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3033#endif 3034 3035 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3036 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3037 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3038 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3039 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3040 break; 3041 case IFM_1000_SX: 3042 case IFM_1000_T: 3043 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3044#if 0 3045 if (sc->ti_hwrev != TI_HWREV_TIGON) 3046 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3047#endif 3048 3049 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3050 flowctl |TI_GLNK_ENB); 3051 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3052 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3053 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3054 } 3055 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3056 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3057 break; 3058 case IFM_100_FX: 3059 case IFM_10_FL: 3060 case IFM_100_TX: 3061 case IFM_10_T: 3062 flowctl = TI_LNK_RX_FLOWCTL_Y; 3063#if 0 3064 if (sc->ti_hwrev != TI_HWREV_TIGON) 3065 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3066#endif 3067 3068 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3069 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3070 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3071 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3072 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3073 } else { 3074 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3075 } 3076 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3077 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3078 } else { 3079 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3080 } 3081 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3082 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3083 break; 3084 } 3085 3086 return(0); 3087} 3088 3089/* 3090 * Report current media status. 3091 */ 3092static void ti_ifmedia_sts(ifp, ifmr) 3093 struct ifnet *ifp; 3094 struct ifmediareq *ifmr; 3095{ 3096 struct ti_softc *sc; 3097 u_int32_t media = 0; 3098 3099 sc = ifp->if_softc; 3100 3101 ifmr->ifm_status = IFM_AVALID; 3102 ifmr->ifm_active = IFM_ETHER; 3103 3104 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3105 return; 3106 3107 ifmr->ifm_status |= IFM_ACTIVE; 3108 3109 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3110 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3111 if (sc->ti_copper) 3112 ifmr->ifm_active |= IFM_1000_T; 3113 else 3114 ifmr->ifm_active |= IFM_1000_SX; 3115 if (media & TI_GLNK_FULL_DUPLEX) 3116 ifmr->ifm_active |= IFM_FDX; 3117 else 3118 ifmr->ifm_active |= IFM_HDX; 3119 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3120 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3121 if (sc->ti_copper) { 3122 if (media & TI_LNK_100MB) 3123 ifmr->ifm_active |= IFM_100_TX; 3124 if (media & TI_LNK_10MB) 3125 ifmr->ifm_active |= IFM_10_T; 3126 } else { 3127 if (media & TI_LNK_100MB) 3128 ifmr->ifm_active |= IFM_100_FX; 3129 if (media & TI_LNK_10MB) 3130 ifmr->ifm_active |= IFM_10_FL; 3131 } 3132 if (media & TI_LNK_FULL_DUPLEX) 3133 ifmr->ifm_active |= IFM_FDX; 3134 if (media & TI_LNK_HALF_DUPLEX) 3135 ifmr->ifm_active |= IFM_HDX; 3136 } 3137 3138 return; 3139} 3140 3141static int ti_ioctl(ifp, command, data) 3142 struct ifnet *ifp; 3143 u_long command; 3144 caddr_t data; 3145{ 3146 struct ti_softc *sc = ifp->if_softc; 3147 struct ifreq *ifr = (struct ifreq *) data; 3148 int mask, error = 0; 3149 struct ti_cmd_desc cmd; 3150 3151 TI_LOCK(sc); 3152 3153 switch(command) { 3154 case SIOCSIFADDR: 3155 case SIOCGIFADDR: 3156 error = ether_ioctl(ifp, command, data); 3157 break; 3158 case SIOCSIFMTU: 3159 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3160 error = EINVAL; 3161 else { 3162 ifp->if_mtu = ifr->ifr_mtu; 3163 ti_init(sc); 3164 } 3165 break; 3166 case SIOCSIFFLAGS: 3167 if (ifp->if_flags & IFF_UP) { 3168 /* 3169 * If only the state of the PROMISC flag changed, 3170 * then just use the 'set promisc mode' command 3171 * instead of reinitializing the entire NIC. Doing 3172 * a full re-init means reloading the firmware and 3173 * waiting for it to start up, which may take a 3174 * second or two. 3175 */ 3176 if (ifp->if_flags & IFF_RUNNING && 3177 ifp->if_flags & IFF_PROMISC && 3178 !(sc->ti_if_flags & IFF_PROMISC)) { 3179 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3180 TI_CMD_CODE_PROMISC_ENB, 0); 3181 } else if (ifp->if_flags & IFF_RUNNING && 3182 !(ifp->if_flags & IFF_PROMISC) && 3183 sc->ti_if_flags & IFF_PROMISC) { 3184 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3185 TI_CMD_CODE_PROMISC_DIS, 0); 3186 } else 3187 ti_init(sc); 3188 } else { 3189 if (ifp->if_flags & IFF_RUNNING) { 3190 ti_stop(sc); 3191 } 3192 } 3193 sc->ti_if_flags = ifp->if_flags; 3194 error = 0; 3195 break; 3196 case SIOCADDMULTI: 3197 case SIOCDELMULTI: 3198 if (ifp->if_flags & IFF_RUNNING) { 3199 ti_setmulti(sc); 3200 error = 0; 3201 } 3202 break; 3203 case SIOCSIFMEDIA: 3204 case SIOCGIFMEDIA: 3205 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3206 break; 3207 case SIOCSIFCAP: 3208 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3209 if (mask & IFCAP_HWCSUM) { 3210 if (IFCAP_HWCSUM & ifp->if_capenable) 3211 ifp->if_capenable &= ~IFCAP_HWCSUM; 3212 else 3213 ifp->if_capenable |= IFCAP_HWCSUM; 3214 if (ifp->if_flags & IFF_RUNNING) 3215 ti_init(sc); 3216 } 3217 error = 0; 3218 break; 3219 default: 3220 error = EINVAL; 3221 break; 3222 } 3223 3224 TI_UNLOCK(sc); 3225 3226 return(error); 3227} 3228 3229static int 3230ti_open(dev_t dev, int flags, int fmt, struct thread *td) 3231{ 3232 int unit; 3233 struct ti_softc *sc; 3234 3235 unit = minor(dev) & 0xff; 3236 3237 sc = ti_lookup_softc(unit); 3238 3239 if (sc == NULL) 3240 return(ENODEV); 3241 3242 TI_LOCK(sc); 3243 sc->ti_flags |= TI_FLAG_DEBUGING; 3244 TI_UNLOCK(sc); 3245 3246 return(0); 3247} 3248 3249static int 3250ti_close(dev_t dev, int flag, int fmt, struct thread *td) 3251{ 3252 int unit; 3253 struct ti_softc *sc; 3254 3255 unit = minor(dev) & 0xff; 3256 3257 sc = ti_lookup_softc(unit); 3258 3259 if (sc == NULL) 3260 return(ENODEV); 3261 3262 TI_LOCK(sc); 3263 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3264 TI_UNLOCK(sc); 3265 3266 return(0); 3267} 3268 3269/* 3270 * This ioctl routine goes along with the Tigon character device. 3271 */ 3272static int 3273ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3274{ 3275 int unit, error; 3276 struct ti_softc *sc; 3277 3278 unit = minor(dev) & 0xff; 3279 3280 sc = ti_lookup_softc(unit); 3281 3282 if (sc == NULL) 3283 return(ENODEV); 3284 3285 error = 0; 3286 3287 switch(cmd) { 3288 case TIIOCGETSTATS: 3289 { 3290 struct ti_stats *outstats; 3291 3292 outstats = (struct ti_stats *)addr; 3293 3294 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3295 sizeof(struct ti_stats)); 3296 break; 3297 } 3298 case TIIOCGETPARAMS: 3299 { 3300 struct ti_params *params; 3301 3302 params = (struct ti_params *)addr; 3303 3304 params->ti_stat_ticks = sc->ti_stat_ticks; 3305 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3306 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3307 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3308 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3309 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3310 params->param_mask = TI_PARAM_ALL; 3311 3312 error = 0; 3313 3314 break; 3315 } 3316 case TIIOCSETPARAMS: 3317 { 3318 struct ti_params *params; 3319 3320 params = (struct ti_params *)addr; 3321 3322 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3323 sc->ti_stat_ticks = params->ti_stat_ticks; 3324 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3325 } 3326 3327 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3328 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3329 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3330 sc->ti_rx_coal_ticks); 3331 } 3332 3333 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3334 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3335 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3336 sc->ti_tx_coal_ticks); 3337 } 3338 3339 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3340 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3341 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3342 sc->ti_rx_max_coal_bds); 3343 } 3344 3345 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3346 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3347 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3348 sc->ti_tx_max_coal_bds); 3349 } 3350 3351 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3352 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3353 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3354 sc->ti_tx_buf_ratio); 3355 } 3356 3357 error = 0; 3358 3359 break; 3360 } 3361 case TIIOCSETTRACE: { 3362 ti_trace_type trace_type; 3363 3364 trace_type = *(ti_trace_type *)addr; 3365 3366 /* 3367 * Set tracing to whatever the user asked for. Setting 3368 * this register to 0 should have the effect of disabling 3369 * tracing. 3370 */ 3371 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3372 3373 error = 0; 3374 3375 break; 3376 } 3377 case TIIOCGETTRACE: { 3378 struct ti_trace_buf *trace_buf; 3379 u_int32_t trace_start, cur_trace_ptr, trace_len; 3380 3381 trace_buf = (struct ti_trace_buf *)addr; 3382 3383 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3384 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3385 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3386 3387#if 0 3388 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3389 "trace_len = %d\n", sc->ti_unit, trace_start, 3390 cur_trace_ptr, trace_len); 3391 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3392 trace_buf->buf_len); 3393#endif 3394 3395 error = ti_copy_mem(sc, trace_start, min(trace_len, 3396 trace_buf->buf_len), 3397 (caddr_t)trace_buf->buf, 1, 1); 3398 3399 if (error == 0) { 3400 trace_buf->fill_len = min(trace_len, 3401 trace_buf->buf_len); 3402 if (cur_trace_ptr < trace_start) 3403 trace_buf->cur_trace_ptr = 3404 trace_start - cur_trace_ptr; 3405 else 3406 trace_buf->cur_trace_ptr = 3407 cur_trace_ptr - trace_start; 3408 } else 3409 trace_buf->fill_len = 0; 3410 3411 3412 break; 3413 } 3414 3415 /* 3416 * For debugging, five ioctls are needed: 3417 * ALT_ATTACH 3418 * ALT_READ_TG_REG 3419 * ALT_WRITE_TG_REG 3420 * ALT_READ_TG_MEM 3421 * ALT_WRITE_TG_MEM 3422 */ 3423 case ALT_ATTACH: 3424 /* 3425 * From what I can tell, Alteon's Solaris Tigon driver 3426 * only has one character device, so you have to attach 3427 * to the Tigon board you're interested in. This seems 3428 * like a not-so-good way to do things, since unless you 3429 * subsequently specify the unit number of the device 3430 * you're interested in in every ioctl, you'll only be 3431 * able to debug one board at a time. 3432 */ 3433 error = 0; 3434 break; 3435 case ALT_READ_TG_MEM: 3436 case ALT_WRITE_TG_MEM: 3437 { 3438 struct tg_mem *mem_param; 3439 u_int32_t sram_end, scratch_end; 3440 3441 mem_param = (struct tg_mem *)addr; 3442 3443 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3444 sram_end = TI_END_SRAM_I; 3445 scratch_end = TI_END_SCRATCH_I; 3446 } else { 3447 sram_end = TI_END_SRAM_II; 3448 scratch_end = TI_END_SCRATCH_II; 3449 } 3450 3451 /* 3452 * For now, we'll only handle accessing regular SRAM, 3453 * nothing else. 3454 */ 3455 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3456 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3457 /* 3458 * In this instance, we always copy to/from user 3459 * space, so the user space argument is set to 1. 3460 */ 3461 error = ti_copy_mem(sc, mem_param->tgAddr, 3462 mem_param->len, 3463 mem_param->userAddr, 1, 3464 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3465 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3466 && (mem_param->tgAddr <= scratch_end)) { 3467 error = ti_copy_scratch(sc, mem_param->tgAddr, 3468 mem_param->len, 3469 mem_param->userAddr, 1, 3470 (cmd == ALT_READ_TG_MEM) ? 3471 1 : 0, TI_PROCESSOR_A); 3472 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3473 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3474 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3475 printf("ti%d: invalid memory range for " 3476 "Tigon I\n", sc->ti_unit); 3477 error = EINVAL; 3478 break; 3479 } 3480 error = ti_copy_scratch(sc, mem_param->tgAddr - 3481 TI_SCRATCH_DEBUG_OFF, 3482 mem_param->len, 3483 mem_param->userAddr, 1, 3484 (cmd == ALT_READ_TG_MEM) ? 3485 1 : 0, TI_PROCESSOR_B); 3486 } else { 3487 printf("ti%d: memory address %#x len %d is out of " 3488 "supported range\n", sc->ti_unit, 3489 mem_param->tgAddr, mem_param->len); 3490 error = EINVAL; 3491 } 3492 3493 break; 3494 } 3495 case ALT_READ_TG_REG: 3496 case ALT_WRITE_TG_REG: 3497 { 3498 struct tg_reg *regs; 3499 u_int32_t tmpval; 3500 3501 regs = (struct tg_reg *)addr; 3502 3503 /* 3504 * Make sure the address in question isn't out of range. 3505 */ 3506 if (regs->addr > TI_REG_MAX) { 3507 error = EINVAL; 3508 break; 3509 } 3510 if (cmd == ALT_READ_TG_REG) { 3511 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3512 regs->addr, &tmpval, 1); 3513 regs->data = ntohl(tmpval); 3514#if 0 3515 if ((regs->addr == TI_CPU_STATE) 3516 || (regs->addr == TI_CPU_CTL_B)) { 3517 printf("ti%d: register %#x = %#x\n", 3518 sc->ti_unit, regs->addr, tmpval); 3519 } 3520#endif 3521 } else { 3522 tmpval = htonl(regs->data); 3523 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3524 regs->addr, &tmpval, 1); 3525 } 3526 3527 break; 3528 } 3529 default: 3530 error = ENOTTY; 3531 break; 3532 } 3533 return(error); 3534} 3535 3536static void ti_watchdog(ifp) 3537 struct ifnet *ifp; 3538{ 3539 struct ti_softc *sc; 3540 3541 sc = ifp->if_softc; 3542 TI_LOCK(sc); 3543 3544 /* 3545 * When we're debugging, the chip is often stopped for long periods 3546 * of time, and that would normally cause the watchdog timer to fire. 3547 * Since that impedes debugging, we don't want to do that. 3548 */ 3549 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3550 TI_UNLOCK(sc); 3551 return; 3552 } 3553 3554 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3555 ti_stop(sc); 3556 ti_init(sc); 3557 3558 ifp->if_oerrors++; 3559 TI_UNLOCK(sc); 3560 3561 return; 3562} 3563 3564/* 3565 * Stop the adapter and free any mbufs allocated to the 3566 * RX and TX lists. 3567 */ 3568static void ti_stop(sc) 3569 struct ti_softc *sc; 3570{ 3571 struct ifnet *ifp; 3572 struct ti_cmd_desc cmd; 3573 3574 TI_LOCK(sc); 3575 3576 ifp = &sc->arpcom.ac_if; 3577 3578 /* Disable host interrupts. */ 3579 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3580 /* 3581 * Tell firmware we're shutting down. 3582 */ 3583 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3584 3585 /* Halt and reinitialize. */ 3586 ti_chipinit(sc); 3587 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3588 ti_chipinit(sc); 3589 3590 /* Free the RX lists. */ 3591 ti_free_rx_ring_std(sc); 3592 3593 /* Free jumbo RX list. */ 3594 ti_free_rx_ring_jumbo(sc); 3595 3596 /* Free mini RX list. */ 3597 ti_free_rx_ring_mini(sc); 3598 3599 /* Free TX buffers. */ 3600 ti_free_tx_ring(sc); 3601 3602 sc->ti_ev_prodidx.ti_idx = 0; 3603 sc->ti_return_prodidx.ti_idx = 0; 3604 sc->ti_tx_considx.ti_idx = 0; 3605 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3606 3607 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3608 TI_UNLOCK(sc); 3609 3610 return; 3611} 3612 3613/* 3614 * Stop all chip I/O so that the kernel's probe routines don't 3615 * get confused by errant DMAs when rebooting. 3616 */ 3617static void ti_shutdown(dev) 3618 device_t dev; 3619{ 3620 struct ti_softc *sc; 3621 3622 sc = device_get_softc(dev); 3623 TI_LOCK(sc); 3624 ti_chipinit(sc); 3625 TI_UNLOCK(sc); 3626 3627 return; 3628} 3629