if_ti.c revision 92739
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 92739 2002-03-20 02:08:01Z alfred $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include <sys/param.h> 8245386Swpaul#include <sys/systm.h> 8345386Swpaul#include <sys/sockio.h> 8445386Swpaul#include <sys/mbuf.h> 8545386Swpaul#include <sys/malloc.h> 8645386Swpaul#include <sys/kernel.h> 8745386Swpaul#include <sys/socket.h> 8845386Swpaul#include <sys/queue.h> 8945386Swpaul 9045386Swpaul#include <net/if.h> 9145386Swpaul#include <net/if_arp.h> 9245386Swpaul#include <net/ethernet.h> 9345386Swpaul#include <net/if_dl.h> 9445386Swpaul#include <net/if_media.h> 9583115Sbrooks#include <net/if_types.h> 9683115Sbrooks#include <net/if_vlan_var.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#include <netinet/in_systm.h> 10145386Swpaul#include <netinet/in.h> 10245386Swpaul#include <netinet/ip.h> 10345386Swpaul 10445386Swpaul#include <vm/vm.h> /* for vtophys */ 10545386Swpaul#include <vm/pmap.h> /* for vtophys */ 10645386Swpaul#include <machine/bus_memio.h> 10745386Swpaul#include <machine/bus.h> 10849011Swpaul#include <machine/resource.h> 10949011Swpaul#include <sys/bus.h> 11049011Swpaul#include <sys/rman.h> 11145386Swpaul 11245386Swpaul#include <pci/pcireg.h> 11345386Swpaul#include <pci/pcivar.h> 11445386Swpaul 11545386Swpaul#include <pci/if_tireg.h> 11645386Swpaul#include <pci/ti_fw.h> 11745386Swpaul#include <pci/ti_fw2.h> 11845386Swpaul 11958698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12045386Swpaul 12145386Swpaul#if !defined(lint) 12245386Swpaulstatic const char rcsid[] = 12350477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 92739 2002-03-20 02:08:01Z alfred $"; 12445386Swpaul#endif 12545386Swpaul 12645386Swpaul/* 12745386Swpaul * Various supported device vendors/types and their names. 12845386Swpaul */ 12945386Swpaul 13045386Swpaulstatic struct ti_type ti_devs[] = { 13145386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13263702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 13363699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 13463702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 13545386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 13645386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 13745386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 13864139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 13964139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 14064139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 14145386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14245386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14356206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 14456206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 14545386Swpaul { 0, 0, NULL } 14645386Swpaul}; 14745386Swpaul 14892739Salfredstatic int ti_probe (device_t); 14992739Salfredstatic int ti_attach (device_t); 15092739Salfredstatic int ti_detach (device_t); 15192739Salfredstatic void ti_txeof (struct ti_softc *); 15292739Salfredstatic void ti_rxeof (struct ti_softc *); 15345386Swpaul 15492739Salfredstatic void ti_stats_update (struct ti_softc *); 15592739Salfredstatic int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 15645386Swpaul 15792739Salfredstatic void ti_intr (void *); 15892739Salfredstatic void ti_start (struct ifnet *); 15992739Salfredstatic int ti_ioctl (struct ifnet *, u_long, caddr_t); 16092739Salfredstatic void ti_init (void *); 16192739Salfredstatic void ti_init2 (struct ti_softc *); 16292739Salfredstatic void ti_stop (struct ti_softc *); 16392739Salfredstatic void ti_watchdog (struct ifnet *); 16492739Salfredstatic void ti_shutdown (device_t); 16592739Salfredstatic int ti_ifmedia_upd (struct ifnet *); 16692739Salfredstatic void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16745386Swpaul 16892739Salfredstatic u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 16992739Salfredstatic u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 17092739Salfredstatic int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 17145386Swpaul 17292739Salfredstatic void ti_add_mcast (struct ti_softc *, struct ether_addr *); 17392739Salfredstatic void ti_del_mcast (struct ti_softc *, struct ether_addr *); 17492739Salfredstatic void ti_setmulti (struct ti_softc *); 17545386Swpaul 17692739Salfredstatic void ti_mem (struct ti_softc *, u_int32_t, 17792739Salfred u_int32_t, caddr_t); 17892739Salfredstatic void ti_loadfw (struct ti_softc *); 17992739Salfredstatic void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 18092739Salfredstatic void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 18192739Salfred caddr_t, int); 18292739Salfredstatic void ti_handle_events (struct ti_softc *); 18392739Salfredstatic int ti_alloc_jumbo_mem (struct ti_softc *); 18492739Salfredstatic void *ti_jalloc (struct ti_softc *); 18592739Salfredstatic void ti_jfree (caddr_t, void *); 18692739Salfredstatic int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 18792739Salfredstatic int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 18892739Salfredstatic int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 18992739Salfredstatic int ti_init_rx_ring_std (struct ti_softc *); 19092739Salfredstatic void ti_free_rx_ring_std (struct ti_softc *); 19192739Salfredstatic int ti_init_rx_ring_jumbo (struct ti_softc *); 19292739Salfredstatic void ti_free_rx_ring_jumbo (struct ti_softc *); 19392739Salfredstatic int ti_init_rx_ring_mini (struct ti_softc *); 19492739Salfredstatic void ti_free_rx_ring_mini (struct ti_softc *); 19592739Salfredstatic void ti_free_tx_ring (struct ti_softc *); 19692739Salfredstatic int ti_init_tx_ring (struct ti_softc *); 19745386Swpaul 19892739Salfredstatic int ti_64bitslot_war (struct ti_softc *); 19992739Salfredstatic int ti_chipinit (struct ti_softc *); 20092739Salfredstatic int ti_gibinit (struct ti_softc *); 20145386Swpaul 20249011Swpaulstatic device_method_t ti_methods[] = { 20349011Swpaul /* Device interface */ 20449011Swpaul DEVMETHOD(device_probe, ti_probe), 20549011Swpaul DEVMETHOD(device_attach, ti_attach), 20649011Swpaul DEVMETHOD(device_detach, ti_detach), 20749011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 20849011Swpaul { 0, 0 } 20949011Swpaul}; 21049011Swpaul 21149011Swpaulstatic driver_t ti_driver = { 21251455Swpaul "ti", 21349011Swpaul ti_methods, 21449011Swpaul sizeof(struct ti_softc) 21549011Swpaul}; 21649011Swpaul 21749011Swpaulstatic devclass_t ti_devclass; 21849011Swpaul 21951533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22049011Swpaul 22145386Swpaul/* 22245386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 22345386Swpaul */ 22445386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 22545386Swpaul struct ti_softc *sc; 22645386Swpaul int byte; 22745386Swpaul{ 22845386Swpaul register int i, ack = 0; 22945386Swpaul 23045386Swpaul /* 23145386Swpaul * Make sure we're in TX mode. 23245386Swpaul */ 23345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 23445386Swpaul 23545386Swpaul /* 23645386Swpaul * Feed in each bit and stobe the clock. 23745386Swpaul */ 23845386Swpaul for (i = 0x80; i; i >>= 1) { 23945386Swpaul if (byte & i) { 24045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24145386Swpaul } else { 24245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24345386Swpaul } 24445386Swpaul DELAY(1); 24545386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24645386Swpaul DELAY(1); 24745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24845386Swpaul } 24945386Swpaul 25045386Swpaul /* 25145386Swpaul * Turn off TX mode. 25245386Swpaul */ 25345386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 25445386Swpaul 25545386Swpaul /* 25645386Swpaul * Check for ack. 25745386Swpaul */ 25845386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25945386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26045386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26145386Swpaul 26245386Swpaul return(ack); 26345386Swpaul} 26445386Swpaul 26545386Swpaul/* 26645386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 26745386Swpaul * We have to send two address bytes since the EEPROM can hold 26845386Swpaul * more than 256 bytes of data. 26945386Swpaul */ 27045386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 27145386Swpaul struct ti_softc *sc; 27245386Swpaul int addr; 27345386Swpaul u_int8_t *dest; 27445386Swpaul{ 27545386Swpaul register int i; 27645386Swpaul u_int8_t byte = 0; 27745386Swpaul 27845386Swpaul EEPROM_START; 27945386Swpaul 28045386Swpaul /* 28145386Swpaul * Send write control code to EEPROM. 28245386Swpaul */ 28345386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 28445386Swpaul printf("ti%d: failed to send write command, status: %x\n", 28545386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 28645386Swpaul return(1); 28745386Swpaul } 28845386Swpaul 28945386Swpaul /* 29045386Swpaul * Send first byte of address of byte we want to read. 29145386Swpaul */ 29245386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 29345386Swpaul printf("ti%d: failed to send address, status: %x\n", 29445386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29545386Swpaul return(1); 29645386Swpaul } 29745386Swpaul /* 29845386Swpaul * Send second byte address of byte we want to read. 29945386Swpaul */ 30045386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 30145386Swpaul printf("ti%d: failed to send address, status: %x\n", 30245386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30345386Swpaul return(1); 30445386Swpaul } 30545386Swpaul 30645386Swpaul EEPROM_STOP; 30745386Swpaul EEPROM_START; 30845386Swpaul /* 30945386Swpaul * Send read control code to EEPROM. 31045386Swpaul */ 31145386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 31245386Swpaul printf("ti%d: failed to send read command, status: %x\n", 31345386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31445386Swpaul return(1); 31545386Swpaul } 31645386Swpaul 31745386Swpaul /* 31845386Swpaul * Start reading bits from EEPROM. 31945386Swpaul */ 32045386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 32145386Swpaul for (i = 0x80; i; i >>= 1) { 32245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 32345386Swpaul DELAY(1); 32445386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 32545386Swpaul byte |= i; 32645386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 32745386Swpaul DELAY(1); 32845386Swpaul } 32945386Swpaul 33045386Swpaul EEPROM_STOP; 33145386Swpaul 33245386Swpaul /* 33345386Swpaul * No ACK generated for read, so just return byte. 33445386Swpaul */ 33545386Swpaul 33645386Swpaul *dest = byte; 33745386Swpaul 33845386Swpaul return(0); 33945386Swpaul} 34045386Swpaul 34145386Swpaul/* 34245386Swpaul * Read a sequence of bytes from the EEPROM. 34345386Swpaul */ 34445386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 34545386Swpaul struct ti_softc *sc; 34645386Swpaul caddr_t dest; 34745386Swpaul int off; 34845386Swpaul int cnt; 34945386Swpaul{ 35045386Swpaul int err = 0, i; 35145386Swpaul u_int8_t byte = 0; 35245386Swpaul 35345386Swpaul for (i = 0; i < cnt; i++) { 35445386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 35545386Swpaul if (err) 35645386Swpaul break; 35745386Swpaul *(dest + i) = byte; 35845386Swpaul } 35945386Swpaul 36045386Swpaul return(err ? 1 : 0); 36145386Swpaul} 36245386Swpaul 36345386Swpaul/* 36445386Swpaul * NIC memory access function. Can be used to either clear a section 36545386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 36645386Swpaul */ 36745386Swpaulstatic void ti_mem(sc, addr, len, buf) 36845386Swpaul struct ti_softc *sc; 36945386Swpaul u_int32_t addr, len; 37045386Swpaul caddr_t buf; 37145386Swpaul{ 37245386Swpaul int segptr, segsize, cnt; 37345386Swpaul caddr_t ti_winbase, ptr; 37445386Swpaul 37545386Swpaul segptr = addr; 37645386Swpaul cnt = len; 37749133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 37845386Swpaul ptr = buf; 37945386Swpaul 38045386Swpaul while(cnt) { 38145386Swpaul if (cnt < TI_WINLEN) 38245386Swpaul segsize = cnt; 38345386Swpaul else 38445386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 38545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 38645386Swpaul if (buf == NULL) 38745386Swpaul bzero((char *)ti_winbase + (segptr & 38845386Swpaul (TI_WINLEN - 1)), segsize); 38945386Swpaul else { 39045386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 39145386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 39245386Swpaul ptr += segsize; 39345386Swpaul } 39445386Swpaul segptr += segsize; 39545386Swpaul cnt -= segsize; 39645386Swpaul } 39745386Swpaul 39845386Swpaul return; 39945386Swpaul} 40045386Swpaul 40145386Swpaul/* 40245386Swpaul * Load firmware image into the NIC. Check that the firmware revision 40345386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 40445386Swpaul * Tigon 2. 40545386Swpaul */ 40645386Swpaulstatic void ti_loadfw(sc) 40745386Swpaul struct ti_softc *sc; 40845386Swpaul{ 40945386Swpaul switch(sc->ti_hwrev) { 41045386Swpaul case TI_HWREV_TIGON: 41145386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 41245386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 41345386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 41445386Swpaul printf("ti%d: firmware revision mismatch; want " 41545386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 41645386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 41745386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 41845386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 41945386Swpaul return; 42045386Swpaul } 42145386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 42245386Swpaul (caddr_t)tigonFwText); 42345386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 42445386Swpaul (caddr_t)tigonFwData); 42545386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 42645386Swpaul (caddr_t)tigonFwRodata); 42745386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 42845386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 42945386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43045386Swpaul break; 43145386Swpaul case TI_HWREV_TIGON_II: 43245386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 43345386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 43445386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 43545386Swpaul printf("ti%d: firmware revision mismatch; want " 43645386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 43745386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 43845386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 43945386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44045386Swpaul return; 44145386Swpaul } 44245386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 44345386Swpaul (caddr_t)tigon2FwText); 44445386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 44545386Swpaul (caddr_t)tigon2FwData); 44645386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 44745386Swpaul (caddr_t)tigon2FwRodata); 44845386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 44945386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45045386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 45145386Swpaul break; 45245386Swpaul default: 45345386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 45445386Swpaul sc->ti_unit); 45545386Swpaul break; 45645386Swpaul } 45745386Swpaul 45845386Swpaul return; 45945386Swpaul} 46045386Swpaul 46145386Swpaul/* 46245386Swpaul * Send the NIC a command via the command ring. 46345386Swpaul */ 46445386Swpaulstatic void ti_cmd(sc, cmd) 46545386Swpaul struct ti_softc *sc; 46645386Swpaul struct ti_cmd_desc *cmd; 46745386Swpaul{ 46845386Swpaul u_int32_t index; 46945386Swpaul 47045386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 47145386Swpaul return; 47245386Swpaul 47345386Swpaul index = sc->ti_cmd_saved_prodidx; 47445386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 47545386Swpaul TI_INC(index, TI_CMD_RING_CNT); 47645386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 47745386Swpaul sc->ti_cmd_saved_prodidx = index; 47845386Swpaul 47945386Swpaul return; 48045386Swpaul} 48145386Swpaul 48245386Swpaul/* 48345386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 48445386Swpaul * number of command slots to include after the initial command. 48545386Swpaul */ 48645386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 48745386Swpaul struct ti_softc *sc; 48845386Swpaul struct ti_cmd_desc *cmd; 48945386Swpaul caddr_t arg; 49045386Swpaul int len; 49145386Swpaul{ 49245386Swpaul u_int32_t index; 49345386Swpaul register int i; 49445386Swpaul 49545386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 49645386Swpaul return; 49745386Swpaul 49845386Swpaul index = sc->ti_cmd_saved_prodidx; 49945386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50045386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50145386Swpaul for (i = 0; i < len; i++) { 50245386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 50345386Swpaul *(u_int32_t *)(&arg[i * 4])); 50445386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50545386Swpaul } 50645386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 50745386Swpaul sc->ti_cmd_saved_prodidx = index; 50845386Swpaul 50945386Swpaul return; 51045386Swpaul} 51145386Swpaul 51245386Swpaul/* 51345386Swpaul * Handle events that have triggered interrupts. 51445386Swpaul */ 51545386Swpaulstatic void ti_handle_events(sc) 51645386Swpaul struct ti_softc *sc; 51745386Swpaul{ 51845386Swpaul struct ti_event_desc *e; 51945386Swpaul 52045386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 52145386Swpaul return; 52245386Swpaul 52345386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 52445386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 52545386Swpaul switch(e->ti_event) { 52645386Swpaul case TI_EV_LINKSTAT_CHANGED: 52745386Swpaul sc->ti_linkstat = e->ti_code; 52845386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 52945386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53045386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 53145386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 53245386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 53345386Swpaul printf("ti%d: link down\n", sc->ti_unit); 53445386Swpaul break; 53545386Swpaul case TI_EV_ERROR: 53645386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 53745386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 53845386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 53945386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54045386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 54145386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 54245386Swpaul break; 54345386Swpaul case TI_EV_FIRMWARE_UP: 54445386Swpaul ti_init2(sc); 54545386Swpaul break; 54645386Swpaul case TI_EV_STATS_UPDATED: 54745386Swpaul ti_stats_update(sc); 54845386Swpaul break; 54945386Swpaul case TI_EV_RESET_JUMBO_RING: 55045386Swpaul case TI_EV_MCAST_UPDATED: 55145386Swpaul /* Who cares. */ 55245386Swpaul break; 55345386Swpaul default: 55445386Swpaul printf("ti%d: unknown event: %d\n", 55545386Swpaul sc->ti_unit, e->ti_event); 55645386Swpaul break; 55745386Swpaul } 55845386Swpaul /* Advance the consumer index. */ 55945386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56045386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 56145386Swpaul } 56245386Swpaul 56345386Swpaul return; 56445386Swpaul} 56545386Swpaul 56645386Swpaul/* 56745386Swpaul * Memory management for the jumbo receive ring is a pain in the 56845386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 56945386Swpaul * _and_ it has to be contiguous (unless you use the extended 57045386Swpaul * jumbo descriptor format). Using malloc() all the time won't 57145386Swpaul * work: malloc() allocates memory in powers of two, which means we 57245386Swpaul * would end up wasting a considerable amount of space by allocating 57345386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 57445386Swpaul * to do our own memory management. 57545386Swpaul * 57645386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 57745386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 57845386Swpaul * as external mbuf storage. 57945386Swpaul * 58045386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 58145386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 58245386Swpaul * RAM. This is a bit much, especially considering we also need 58345386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 58445386Swpaul * save space, we only actually allocate enough memory for 64 slots 58545386Swpaul * by default, which works out to between 500 and 600K. This can 58645386Swpaul * be tuned by changing a #define in if_tireg.h. 58745386Swpaul */ 58845386Swpaul 58945386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59045386Swpaul struct ti_softc *sc; 59145386Swpaul{ 59245386Swpaul caddr_t ptr; 59345386Swpaul register int i; 59445386Swpaul struct ti_jpool_entry *entry; 59545386Swpaul 59645386Swpaul /* Grab a big chunk o' storage. */ 59745386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 59850548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 59945386Swpaul 60045386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 60145386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 60245386Swpaul return(ENOBUFS); 60345386Swpaul } 60445386Swpaul 60545386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 60645386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 60745386Swpaul 60845386Swpaul /* 60945386Swpaul * Now divide it up into 9K pieces and save the addresses 61067405Sbmilekic * in an array. 61145386Swpaul */ 61245386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 61345386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 61467405Sbmilekic sc->ti_cdata.ti_jslots[i] = ptr; 61567405Sbmilekic ptr += TI_JLEN; 61645386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 61745386Swpaul M_DEVBUF, M_NOWAIT); 61845386Swpaul if (entry == NULL) { 61962793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 62062793Sgallatin M_DEVBUF); 62145386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 62245386Swpaul printf("ti%d: no memory for jumbo " 62345386Swpaul "buffer queue!\n", sc->ti_unit); 62445386Swpaul return(ENOBUFS); 62545386Swpaul } 62645386Swpaul entry->slot = i; 62745386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 62845386Swpaul } 62945386Swpaul 63045386Swpaul return(0); 63145386Swpaul} 63245386Swpaul 63345386Swpaul/* 63445386Swpaul * Allocate a jumbo buffer. 63545386Swpaul */ 63645386Swpaulstatic void *ti_jalloc(sc) 63745386Swpaul struct ti_softc *sc; 63845386Swpaul{ 63945386Swpaul struct ti_jpool_entry *entry; 64045386Swpaul 64145386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 64245386Swpaul 64345386Swpaul if (entry == NULL) { 64445386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 64545386Swpaul return(NULL); 64645386Swpaul } 64745386Swpaul 64845386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 64945386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 65067405Sbmilekic return(sc->ti_cdata.ti_jslots[entry->slot]); 65145386Swpaul} 65245386Swpaul 65345386Swpaul/* 65445386Swpaul * Release a jumbo buffer. 65545386Swpaul */ 65664837Sdwmalonestatic void ti_jfree(buf, args) 65745386Swpaul caddr_t buf; 65864837Sdwmalone void *args; 65945386Swpaul{ 66045386Swpaul struct ti_softc *sc; 66145386Swpaul int i; 66245386Swpaul struct ti_jpool_entry *entry; 66345386Swpaul 66445386Swpaul /* Extract the softc struct pointer. */ 66567405Sbmilekic sc = (struct ti_softc *)args; 66645386Swpaul 66745386Swpaul if (sc == NULL) 66867405Sbmilekic panic("ti_jfree: didn't get softc pointer!"); 66945386Swpaul 67045386Swpaul /* calculate the slot this buffer belongs to */ 67167405Sbmilekic i = ((vm_offset_t)buf 67245386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 67345386Swpaul 67445386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 67545386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 67645386Swpaul 67764837Sdwmalone entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 67864837Sdwmalone if (entry == NULL) 67964837Sdwmalone panic("ti_jfree: buffer not in use!"); 68064837Sdwmalone entry->slot = i; 68164837Sdwmalone SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 68264837Sdwmalone SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 68364837Sdwmalone 68445386Swpaul return; 68545386Swpaul} 68645386Swpaul 68745386Swpaul 68845386Swpaul/* 68945386Swpaul * Intialize a standard receive ring descriptor. 69045386Swpaul */ 69145386Swpaulstatic int ti_newbuf_std(sc, i, m) 69245386Swpaul struct ti_softc *sc; 69345386Swpaul int i; 69445386Swpaul struct mbuf *m; 69545386Swpaul{ 69645386Swpaul struct mbuf *m_new = NULL; 69745386Swpaul struct ti_rx_desc *r; 69845386Swpaul 69949036Swpaul if (m == NULL) { 70045386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 70187846Sluigi if (m_new == NULL) 70245386Swpaul return(ENOBUFS); 70345386Swpaul 70445386Swpaul MCLGET(m_new, M_DONTWAIT); 70545386Swpaul if (!(m_new->m_flags & M_EXT)) { 70645386Swpaul m_freem(m_new); 70745386Swpaul return(ENOBUFS); 70845386Swpaul } 70949036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 71049036Swpaul } else { 71149036Swpaul m_new = m; 71249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 71349036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 71445386Swpaul } 71545386Swpaul 71648597Swpaul m_adj(m_new, ETHER_ALIGN); 71745386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 71845386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 71945386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 72045386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 72145386Swpaul r->ti_flags = 0; 72258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 72358698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 72449036Swpaul r->ti_len = m_new->m_len; 72545386Swpaul r->ti_idx = i; 72645386Swpaul 72745386Swpaul return(0); 72845386Swpaul} 72945386Swpaul 73045386Swpaul/* 73145386Swpaul * Intialize a mini receive ring descriptor. This only applies to 73245386Swpaul * the Tigon 2. 73345386Swpaul */ 73445386Swpaulstatic int ti_newbuf_mini(sc, i, m) 73545386Swpaul struct ti_softc *sc; 73645386Swpaul int i; 73745386Swpaul struct mbuf *m; 73845386Swpaul{ 73945386Swpaul struct mbuf *m_new = NULL; 74045386Swpaul struct ti_rx_desc *r; 74145386Swpaul 74249036Swpaul if (m == NULL) { 74345386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 74445386Swpaul if (m_new == NULL) { 74545386Swpaul return(ENOBUFS); 74645386Swpaul } 74749036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 74849036Swpaul } else { 74949036Swpaul m_new = m; 75049036Swpaul m_new->m_data = m_new->m_pktdat; 75149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 75245386Swpaul } 75349036Swpaul 75448597Swpaul m_adj(m_new, ETHER_ALIGN); 75545386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 75645386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 75745386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 75845386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 75945386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 76058698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 76158698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 76249036Swpaul r->ti_len = m_new->m_len; 76345386Swpaul r->ti_idx = i; 76445386Swpaul 76545386Swpaul return(0); 76645386Swpaul} 76745386Swpaul 76845386Swpaul/* 76945386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 77045386Swpaul * a jumbo buffer from the pool managed internally by the driver. 77145386Swpaul */ 77245386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 77345386Swpaul struct ti_softc *sc; 77445386Swpaul int i; 77545386Swpaul struct mbuf *m; 77645386Swpaul{ 77745386Swpaul struct mbuf *m_new = NULL; 77845386Swpaul struct ti_rx_desc *r; 77945386Swpaul 78049036Swpaul if (m == NULL) { 78145386Swpaul caddr_t *buf = NULL; 78245386Swpaul 78345386Swpaul /* Allocate the mbuf. */ 78445386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 78545386Swpaul if (m_new == NULL) { 78645386Swpaul return(ENOBUFS); 78745386Swpaul } 78845386Swpaul 78945386Swpaul /* Allocate the jumbo buffer */ 79045386Swpaul buf = ti_jalloc(sc); 79145386Swpaul if (buf == NULL) { 79245386Swpaul m_freem(m_new); 79345386Swpaul printf("ti%d: jumbo allocation failed " 79445386Swpaul "-- packet dropped!\n", sc->ti_unit); 79545386Swpaul return(ENOBUFS); 79645386Swpaul } 79745386Swpaul 79845386Swpaul /* Attach the buffer to the mbuf. */ 79964837Sdwmalone m_new->m_data = (void *) buf; 80064837Sdwmalone m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 80167405Sbmilekic MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 80268621Sbmilekic (struct ti_softc *)sc, 0, EXT_NET_DRV); 80349036Swpaul } else { 80449036Swpaul m_new = m; 80549036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 80649036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 80745386Swpaul } 80845386Swpaul 80949780Swpaul m_adj(m_new, ETHER_ALIGN); 81045386Swpaul /* Set up the descriptor. */ 81145386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 81245386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 81345386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 81445386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 81545386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 81658698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 81758698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 81849036Swpaul r->ti_len = m_new->m_len; 81945386Swpaul r->ti_idx = i; 82045386Swpaul 82145386Swpaul return(0); 82245386Swpaul} 82345386Swpaul 82445386Swpaul/* 82545386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 82645386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 82745386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 82845386Swpaul * the NIC. 82945386Swpaul */ 83045386Swpaulstatic int ti_init_rx_ring_std(sc) 83145386Swpaul struct ti_softc *sc; 83245386Swpaul{ 83345386Swpaul register int i; 83445386Swpaul struct ti_cmd_desc cmd; 83545386Swpaul 83645386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 83745386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 83845386Swpaul return(ENOBUFS); 83945386Swpaul }; 84045386Swpaul 84145386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 84248597Swpaul sc->ti_std = i - 1; 84345386Swpaul 84445386Swpaul return(0); 84545386Swpaul} 84645386Swpaul 84745386Swpaulstatic void ti_free_rx_ring_std(sc) 84845386Swpaul struct ti_softc *sc; 84945386Swpaul{ 85045386Swpaul register int i; 85145386Swpaul 85245386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 85345386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 85445386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 85545386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 85645386Swpaul } 85745386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 85845386Swpaul sizeof(struct ti_rx_desc)); 85945386Swpaul } 86045386Swpaul 86145386Swpaul return; 86245386Swpaul} 86345386Swpaul 86445386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 86545386Swpaul struct ti_softc *sc; 86645386Swpaul{ 86745386Swpaul register int i; 86845386Swpaul struct ti_cmd_desc cmd; 86945386Swpaul 87063699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 87145386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 87245386Swpaul return(ENOBUFS); 87345386Swpaul }; 87445386Swpaul 87545386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 87648597Swpaul sc->ti_jumbo = i - 1; 87745386Swpaul 87845386Swpaul return(0); 87945386Swpaul} 88045386Swpaul 88145386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 88245386Swpaul struct ti_softc *sc; 88345386Swpaul{ 88445386Swpaul register int i; 88545386Swpaul 88645386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 88745386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 88845386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 88945386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 89045386Swpaul } 89145386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 89245386Swpaul sizeof(struct ti_rx_desc)); 89345386Swpaul } 89445386Swpaul 89545386Swpaul return; 89645386Swpaul} 89745386Swpaul 89845386Swpaulstatic int ti_init_rx_ring_mini(sc) 89945386Swpaul struct ti_softc *sc; 90045386Swpaul{ 90145386Swpaul register int i; 90245386Swpaul 90345386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 90445386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 90545386Swpaul return(ENOBUFS); 90645386Swpaul }; 90745386Swpaul 90845386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 90948597Swpaul sc->ti_mini = i - 1; 91045386Swpaul 91145386Swpaul return(0); 91245386Swpaul} 91345386Swpaul 91445386Swpaulstatic void ti_free_rx_ring_mini(sc) 91545386Swpaul struct ti_softc *sc; 91645386Swpaul{ 91745386Swpaul register int i; 91845386Swpaul 91945386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 92045386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 92145386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 92245386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 92345386Swpaul } 92445386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 92545386Swpaul sizeof(struct ti_rx_desc)); 92645386Swpaul } 92745386Swpaul 92845386Swpaul return; 92945386Swpaul} 93045386Swpaul 93145386Swpaulstatic void ti_free_tx_ring(sc) 93245386Swpaul struct ti_softc *sc; 93345386Swpaul{ 93445386Swpaul register int i; 93545386Swpaul 93645386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 93745386Swpaul return; 93845386Swpaul 93945386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 94045386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 94145386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 94245386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 94345386Swpaul } 94445386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 94545386Swpaul sizeof(struct ti_tx_desc)); 94645386Swpaul } 94745386Swpaul 94845386Swpaul return; 94945386Swpaul} 95045386Swpaul 95145386Swpaulstatic int ti_init_tx_ring(sc) 95245386Swpaul struct ti_softc *sc; 95345386Swpaul{ 95448011Swpaul sc->ti_txcnt = 0; 95545386Swpaul sc->ti_tx_saved_considx = 0; 95645386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 95745386Swpaul return(0); 95845386Swpaul} 95945386Swpaul 96045386Swpaul/* 96145386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 96245386Swpaul * but we have to support the old way too so that Tigon 1 cards will 96345386Swpaul * work. 96445386Swpaul */ 96545386Swpaulvoid ti_add_mcast(sc, addr) 96645386Swpaul struct ti_softc *sc; 96745386Swpaul struct ether_addr *addr; 96845386Swpaul{ 96945386Swpaul struct ti_cmd_desc cmd; 97045386Swpaul u_int16_t *m; 97145386Swpaul u_int32_t ext[2] = {0, 0}; 97245386Swpaul 97345386Swpaul m = (u_int16_t *)&addr->octet[0]; 97445386Swpaul 97545386Swpaul switch(sc->ti_hwrev) { 97645386Swpaul case TI_HWREV_TIGON: 97745386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 97845386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 97945386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 98045386Swpaul break; 98145386Swpaul case TI_HWREV_TIGON_II: 98245386Swpaul ext[0] = htons(m[0]); 98345386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 98445386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 98545386Swpaul break; 98645386Swpaul default: 98745386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 98845386Swpaul break; 98945386Swpaul } 99045386Swpaul 99145386Swpaul return; 99245386Swpaul} 99345386Swpaul 99445386Swpaulvoid ti_del_mcast(sc, addr) 99545386Swpaul struct ti_softc *sc; 99645386Swpaul struct ether_addr *addr; 99745386Swpaul{ 99845386Swpaul struct ti_cmd_desc cmd; 99945386Swpaul u_int16_t *m; 100045386Swpaul u_int32_t ext[2] = {0, 0}; 100145386Swpaul 100245386Swpaul m = (u_int16_t *)&addr->octet[0]; 100345386Swpaul 100445386Swpaul switch(sc->ti_hwrev) { 100545386Swpaul case TI_HWREV_TIGON: 100645386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 100745386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 100845386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 100945386Swpaul break; 101045386Swpaul case TI_HWREV_TIGON_II: 101145386Swpaul ext[0] = htons(m[0]); 101245386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 101345386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 101445386Swpaul break; 101545386Swpaul default: 101645386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 101745386Swpaul break; 101845386Swpaul } 101945386Swpaul 102045386Swpaul return; 102145386Swpaul} 102245386Swpaul 102345386Swpaul/* 102445386Swpaul * Configure the Tigon's multicast address filter. 102545386Swpaul * 102645386Swpaul * The actual multicast table management is a bit of a pain, thanks to 102745386Swpaul * slight brain damage on the part of both Alteon and us. With our 102845386Swpaul * multicast code, we are only alerted when the multicast address table 102945386Swpaul * changes and at that point we only have the current list of addresses: 103045386Swpaul * we only know the current state, not the previous state, so we don't 103145386Swpaul * actually know what addresses were removed or added. The firmware has 103245386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 103345386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 103445386Swpaul * state so we know what addresses have been programmed into the NIC at 103545386Swpaul * any given time. 103645386Swpaul */ 103745386Swpaulstatic void ti_setmulti(sc) 103845386Swpaul struct ti_softc *sc; 103945386Swpaul{ 104045386Swpaul struct ifnet *ifp; 104145386Swpaul struct ifmultiaddr *ifma; 104245386Swpaul struct ti_cmd_desc cmd; 104345386Swpaul struct ti_mc_entry *mc; 104445386Swpaul u_int32_t intrs; 104545386Swpaul 104645386Swpaul ifp = &sc->arpcom.ac_if; 104745386Swpaul 104845386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 104945386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 105045386Swpaul return; 105145386Swpaul } else { 105245386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 105345386Swpaul } 105445386Swpaul 105545386Swpaul /* Disable interrupts. */ 105645386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 105745386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 105845386Swpaul 105945386Swpaul /* First, zot all the existing filters. */ 106071999Sphk while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 106171999Sphk mc = SLIST_FIRST(&sc->ti_mc_listhead); 106245386Swpaul ti_del_mcast(sc, &mc->mc_addr); 106345386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 106445386Swpaul free(mc, M_DEVBUF); 106545386Swpaul } 106645386Swpaul 106745386Swpaul /* Now program new ones. */ 106872084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 106945386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 107045386Swpaul continue; 107145386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 107245386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 107345386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 107445386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 107545386Swpaul ti_add_mcast(sc, &mc->mc_addr); 107645386Swpaul } 107745386Swpaul 107845386Swpaul /* Re-enable interrupts. */ 107945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 108045386Swpaul 108145386Swpaul return; 108245386Swpaul} 108345386Swpaul 108445386Swpaul/* 108545386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 108645386Swpaul * we aren't actually in one. If we detect this condition, we can work 108745386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 108845386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 108945386Swpaul */ 109045386Swpaulstatic int ti_64bitslot_war(sc) 109145386Swpaul struct ti_softc *sc; 109245386Swpaul{ 109345386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 109445386Swpaul CSR_WRITE_4(sc, 0x600, 0); 109545386Swpaul CSR_WRITE_4(sc, 0x604, 0); 109645386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 109745386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 109845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 109945386Swpaul return(EINVAL); 110045386Swpaul else { 110145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 110245386Swpaul TI_PCISTATE_32BIT_BUS); 110345386Swpaul return(0); 110445386Swpaul } 110545386Swpaul } 110645386Swpaul } 110745386Swpaul 110845386Swpaul return(0); 110945386Swpaul} 111045386Swpaul 111145386Swpaul/* 111245386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 111345386Swpaul * self-test results. 111445386Swpaul */ 111545386Swpaulstatic int ti_chipinit(sc) 111645386Swpaul struct ti_softc *sc; 111745386Swpaul{ 111845386Swpaul u_int32_t cacheline; 111945386Swpaul u_int32_t pci_writemax = 0; 112045386Swpaul 112145386Swpaul /* Initialize link to down state. */ 112245386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 112345386Swpaul 112483630Sjlemon if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 112583630Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 112683630Sjlemon else 112783630Sjlemon sc->arpcom.ac_if.if_hwassist = 0; 112858698Sjlemon 112945386Swpaul /* Set endianness before we access any non-PCI registers. */ 113045386Swpaul#if BYTE_ORDER == BIG_ENDIAN 113145386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 113245386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 113345386Swpaul#else 113445386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 113545386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 113645386Swpaul#endif 113745386Swpaul 113845386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 113945386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 114045386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 114145386Swpaul return(ENODEV); 114245386Swpaul } 114345386Swpaul 114445386Swpaul /* Halt the CPU. */ 114545386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 114645386Swpaul 114745386Swpaul /* Figure out the hardware revision. */ 114845386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 114945386Swpaul case TI_REV_TIGON_I: 115045386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 115145386Swpaul break; 115245386Swpaul case TI_REV_TIGON_II: 115345386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 115445386Swpaul break; 115545386Swpaul default: 115645386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 115745386Swpaul return(ENODEV); 115845386Swpaul } 115945386Swpaul 116045386Swpaul /* Do special setup for Tigon 2. */ 116145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 116245386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 116376033Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 116445386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 116545386Swpaul } 116645386Swpaul 116745386Swpaul /* Set up the PCI state register. */ 116845386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 116945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 117045386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 117145386Swpaul } 117245386Swpaul 117345386Swpaul /* Clear the read/write max DMA parameters. */ 117445386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 117545386Swpaul TI_PCISTATE_READ_MAXDMA)); 117645386Swpaul 117745386Swpaul /* Get cache line size. */ 117845386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 117945386Swpaul 118045386Swpaul /* 118145386Swpaul * If the system has set enabled the PCI memory write 118245386Swpaul * and invalidate command in the command register, set 118345386Swpaul * the write max parameter accordingly. This is necessary 118445386Swpaul * to use MWI with the Tigon 2. 118545386Swpaul */ 118645386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 118745386Swpaul switch(cacheline) { 118845386Swpaul case 1: 118945386Swpaul case 4: 119045386Swpaul case 8: 119145386Swpaul case 16: 119245386Swpaul case 32: 119345386Swpaul case 64: 119445386Swpaul break; 119545386Swpaul default: 119645386Swpaul /* Disable PCI memory write and invalidate. */ 119745386Swpaul if (bootverbose) 119845386Swpaul printf("ti%d: cache line size %d not " 119945386Swpaul "supported; disabling PCI MWI\n", 120045386Swpaul sc->ti_unit, cacheline); 120145386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 120245386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 120345386Swpaul break; 120445386Swpaul } 120545386Swpaul } 120645386Swpaul 120745386Swpaul#ifdef __brokenalpha__ 120845386Swpaul /* 120945386Swpaul * From the Alteon sample driver: 121045386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 121145386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 121245386Swpaul * restriction on some ALPHA platforms with early revision 121345386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 121445386Swpaul */ 121545386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 121645386Swpaul#else 121745386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 121845386Swpaul#endif 121945386Swpaul 122045386Swpaul /* This sets the min dma param all the way up (0xff). */ 122145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 122245386Swpaul 122345386Swpaul /* Configure DMA variables. */ 122445386Swpaul#if BYTE_ORDER == BIG_ENDIAN 122545386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 122645386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 122745386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 122845386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 122945386Swpaul#else 123045386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 123145386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 123245386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 123345386Swpaul#endif 123445386Swpaul 123545386Swpaul /* 123645386Swpaul * Only allow 1 DMA channel to be active at a time. 123745386Swpaul * I don't think this is a good idea, but without it 123845386Swpaul * the firmware racks up lots of nicDmaReadRingFull 123958698Sjlemon * errors. This is not compatible with hardware checksums. 124045386Swpaul */ 124158698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 124258698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 124345386Swpaul 124445386Swpaul /* Recommended settings from Tigon manual. */ 124545386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 124645386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 124745386Swpaul 124845386Swpaul if (ti_64bitslot_war(sc)) { 124945386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 125045386Swpaul "but we aren't", sc->ti_unit); 125145386Swpaul return(EINVAL); 125245386Swpaul } 125345386Swpaul 125445386Swpaul return(0); 125545386Swpaul} 125645386Swpaul 125745386Swpaul/* 125845386Swpaul * Initialize the general information block and firmware, and 125945386Swpaul * start the CPU(s) running. 126045386Swpaul */ 126145386Swpaulstatic int ti_gibinit(sc) 126245386Swpaul struct ti_softc *sc; 126345386Swpaul{ 126445386Swpaul struct ti_rcb *rcb; 126545386Swpaul int i; 126645386Swpaul struct ifnet *ifp; 126745386Swpaul 126845386Swpaul ifp = &sc->arpcom.ac_if; 126945386Swpaul 127045386Swpaul /* Disable interrupts for now. */ 127145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 127245386Swpaul 127345386Swpaul /* Tell the chip where to find the general information block. */ 127445386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 127545386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 127645386Swpaul 127745386Swpaul /* Load the firmware into SRAM. */ 127845386Swpaul ti_loadfw(sc); 127945386Swpaul 128045386Swpaul /* Set up the contents of the general info and ring control blocks. */ 128145386Swpaul 128245386Swpaul /* Set up the event ring and producer pointer. */ 128345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 128445386Swpaul 128545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 128645386Swpaul rcb->ti_flags = 0; 128745386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 128845386Swpaul vtophys(&sc->ti_ev_prodidx); 128945386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 129045386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 129145386Swpaul sc->ti_ev_saved_considx = 0; 129245386Swpaul 129345386Swpaul /* Set up the command ring and producer mailbox. */ 129445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 129545386Swpaul 129645386Swpaul sc->ti_rdata->ti_cmd_ring = 129749133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 129845386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 129945386Swpaul rcb->ti_flags = 0; 130045386Swpaul rcb->ti_max_len = 0; 130145386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 130245386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 130345386Swpaul } 130445386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 130545386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 130645386Swpaul sc->ti_cmd_saved_prodidx = 0; 130745386Swpaul 130845386Swpaul /* 130945386Swpaul * Assign the address of the stats refresh buffer. 131045386Swpaul * We re-use the current stats buffer for this to 131145386Swpaul * conserve memory. 131245386Swpaul */ 131345386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 131445386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 131545386Swpaul 131645386Swpaul /* Set up the standard receive ring. */ 131745386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 131845386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 131945386Swpaul rcb->ti_max_len = TI_FRAMELEN; 132045386Swpaul rcb->ti_flags = 0; 132158698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 132258698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 132358698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 132445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 132545386Swpaul 132645386Swpaul /* Set up the jumbo receive ring. */ 132745386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 132845386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 132945386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 133049036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 133145386Swpaul rcb->ti_flags = 0; 133258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 133358698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 133458698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 133545386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 133645386Swpaul 133745386Swpaul /* 133845386Swpaul * Set up the mini ring. Only activated on the 133945386Swpaul * Tigon 2 but the slot in the config block is 134045386Swpaul * still there on the Tigon 1. 134145386Swpaul */ 134245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 134345386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 134445386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 134551352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 134645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 134745386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 134845386Swpaul else 134945386Swpaul rcb->ti_flags = 0; 135058698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 135158698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 135258698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 135345386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 135445386Swpaul 135545386Swpaul /* 135645386Swpaul * Set up the receive return ring. 135745386Swpaul */ 135845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 135945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 136045386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 136145386Swpaul rcb->ti_flags = 0; 136245386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 136345386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 136445386Swpaul vtophys(&sc->ti_return_prodidx); 136545386Swpaul 136645386Swpaul /* 136745386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 136845386Swpaul * of putting the transmit ring in the host's address space and 136945386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 137045386Swpaul * memory and accessing it through the shared memory region. We 137145386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 137245386Swpaul * so we have to revert to the shared memory scheme if we detect 137345386Swpaul * a Tigon 1 chip. 137445386Swpaul */ 137545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 137645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 137745386Swpaul sc->ti_rdata->ti_tx_ring_nic = 137849133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 137945386Swpaul } 138045386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 138145386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 138245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 138345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 138445386Swpaul rcb->ti_flags = 0; 138545386Swpaul else 138645386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 138745386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 138858698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 138958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 139058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 139145386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 139245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 139345386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 139445386Swpaul else 139545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 139645386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 139745386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 139845386Swpaul vtophys(&sc->ti_tx_considx); 139945386Swpaul 140045386Swpaul /* Set up tuneables */ 140145386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 140245386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 140345386Swpaul (sc->ti_rx_coal_ticks / 10)); 140445386Swpaul else 140545386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 140645386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 140745386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 140845386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 140945386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 141045386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 141145386Swpaul 141245386Swpaul /* Turn interrupts on. */ 141345386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 141445386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 141545386Swpaul 141645386Swpaul /* Start CPU. */ 141745386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 141845386Swpaul 141945386Swpaul return(0); 142045386Swpaul} 142145386Swpaul 142245386Swpaul/* 142345386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 142445386Swpaul * against our list and return its name if we find a match. 142545386Swpaul */ 142649011Swpaulstatic int ti_probe(dev) 142749011Swpaul device_t dev; 142845386Swpaul{ 142945386Swpaul struct ti_type *t; 143045386Swpaul 143145386Swpaul t = ti_devs; 143245386Swpaul 143345386Swpaul while(t->ti_name != NULL) { 143449011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 143549011Swpaul (pci_get_device(dev) == t->ti_did)) { 143649011Swpaul device_set_desc(dev, t->ti_name); 143749011Swpaul return(0); 143849011Swpaul } 143945386Swpaul t++; 144045386Swpaul } 144145386Swpaul 144249011Swpaul return(ENXIO); 144345386Swpaul} 144445386Swpaul 144549011Swpaulstatic int ti_attach(dev) 144649011Swpaul device_t dev; 144745386Swpaul{ 144845386Swpaul u_int32_t command; 144945386Swpaul struct ifnet *ifp; 145045386Swpaul struct ti_softc *sc; 145149011Swpaul int unit, error = 0, rid; 145245386Swpaul 145349011Swpaul sc = device_get_softc(dev); 145449011Swpaul unit = device_get_unit(dev); 145545386Swpaul bzero(sc, sizeof(struct ti_softc)); 145645386Swpaul 145771228Sbmilekic mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 145869583Swpaul TI_LOCK(sc); 145983630Sjlemon sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 146083630Sjlemon sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 146169583Swpaul 146245386Swpaul /* 146345386Swpaul * Map control/status registers. 146445386Swpaul */ 146572813Swpaul pci_enable_busmaster(dev); 146679472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 146761041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 146845386Swpaul 146945386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 147045386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 147149011Swpaul error = ENXIO; 147245386Swpaul goto fail; 147345386Swpaul } 147445386Swpaul 147549011Swpaul rid = TI_PCI_LOMEM; 147649011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 147765176Sdfr 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 147849011Swpaul 147949011Swpaul if (sc->ti_res == NULL) { 148045386Swpaul printf ("ti%d: couldn't map memory\n", unit); 148149011Swpaul error = ENXIO; 148245386Swpaul goto fail; 148345386Swpaul } 148445386Swpaul 148549035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 148649035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 148749133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 148849035Swpaul 148949011Swpaul /* Allocate interrupt */ 149049011Swpaul rid = 0; 149149133Swpaul 149249011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 149349011Swpaul RF_SHAREABLE | RF_ACTIVE); 149445386Swpaul 149549011Swpaul if (sc->ti_irq == NULL) { 149649011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 149749011Swpaul error = ENXIO; 149845386Swpaul goto fail; 149945386Swpaul } 150045386Swpaul 150149011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 150249011Swpaul ti_intr, sc, &sc->ti_intrhand); 150349011Swpaul 150449011Swpaul if (error) { 150549011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 150649011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 150749011Swpaul TI_PCI_LOMEM, sc->ti_res); 150849011Swpaul printf("ti%d: couldn't set up irq\n", unit); 150945386Swpaul goto fail; 151045386Swpaul } 151145386Swpaul 151245386Swpaul sc->ti_unit = unit; 151345386Swpaul 151445386Swpaul if (ti_chipinit(sc)) { 151545386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 151649011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 151749011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 151849011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 151949011Swpaul TI_PCI_LOMEM, sc->ti_res); 152049011Swpaul error = ENXIO; 152145386Swpaul goto fail; 152245386Swpaul } 152345386Swpaul 152445386Swpaul /* Zero out the NIC's on-board SRAM. */ 152545386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 152645386Swpaul 152745386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 152845386Swpaul if (ti_chipinit(sc)) { 152945386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 153049011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 153149011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 153249011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 153349011Swpaul TI_PCI_LOMEM, sc->ti_res); 153449011Swpaul error = ENXIO; 153545386Swpaul goto fail; 153645386Swpaul } 153745386Swpaul 153845386Swpaul /* 153945386Swpaul * Get station address from the EEPROM. Note: the manual states 154045386Swpaul * that the MAC address is at offset 0x8c, however the data is 154145386Swpaul * stored as two longwords (since that's how it's loaded into 154272645Sasmodai * the NIC). This means the MAC address is actually preceded 154345386Swpaul * by two zero bytes. We need to skip over those. 154445386Swpaul */ 154545386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 154645386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 154745386Swpaul printf("ti%d: failed to read station address\n", unit); 154849011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 154949011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 155049011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 155149011Swpaul TI_PCI_LOMEM, sc->ti_res); 155249011Swpaul error = ENXIO; 155345386Swpaul goto fail; 155445386Swpaul } 155545386Swpaul 155645386Swpaul /* 155745386Swpaul * A Tigon chip was detected. Inform the world. 155845386Swpaul */ 155945386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 156045386Swpaul sc->arpcom.ac_enaddr, ":"); 156145386Swpaul 156245386Swpaul /* Allocate the general information block and ring buffers. */ 156349011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 156450548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 156545386Swpaul 156649011Swpaul if (sc->ti_rdata == NULL) { 156749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 156849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 156949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 157049011Swpaul TI_PCI_LOMEM, sc->ti_res); 157149011Swpaul error = ENXIO; 157245386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 157345386Swpaul goto fail; 157445386Swpaul } 157545386Swpaul 157645386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 157745386Swpaul 157845386Swpaul /* Try to allocate memory for jumbo buffers. */ 157945386Swpaul if (ti_alloc_jumbo_mem(sc)) { 158045386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 158149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 158249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 158349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 158449011Swpaul TI_PCI_LOMEM, sc->ti_res); 158562793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 158662793Sgallatin M_DEVBUF); 158749011Swpaul error = ENXIO; 158845386Swpaul goto fail; 158945386Swpaul } 159045386Swpaul 159163699Swpaul /* 159263699Swpaul * We really need a better way to tell a 1000baseTX card 159363699Swpaul * from a 1000baseSX one, since in theory there could be 159463699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 159563699Swpaul * clever enough to change the PCI ID. For the moment 159663699Swpaul * though, the AceNIC is the only copper card available. 159763699Swpaul */ 159863699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 159963699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 160063699Swpaul sc->ti_copper = 1; 160164139Swpaul /* Ok, it's not the only copper card available. */ 160264139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 160364139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 160464139Swpaul sc->ti_copper = 1; 160563699Swpaul 160645386Swpaul /* Set default tuneable values. */ 160745386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 160845386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 160945386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 161045386Swpaul sc->ti_rx_max_coal_bds = 64; 161145386Swpaul sc->ti_tx_max_coal_bds = 128; 161245386Swpaul sc->ti_tx_buf_ratio = 21; 161345386Swpaul 161445386Swpaul /* Set up ifnet structure */ 161545386Swpaul ifp = &sc->arpcom.ac_if; 161645386Swpaul ifp->if_softc = sc; 161745386Swpaul ifp->if_unit = sc->ti_unit; 161845386Swpaul ifp->if_name = "ti"; 161945386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 162045386Swpaul ifp->if_ioctl = ti_ioctl; 162145386Swpaul ifp->if_output = ether_output; 162245386Swpaul ifp->if_start = ti_start; 162345386Swpaul ifp->if_watchdog = ti_watchdog; 162445386Swpaul ifp->if_init = ti_init; 162545386Swpaul ifp->if_mtu = ETHERMTU; 162645386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 162745386Swpaul 162845386Swpaul /* Set up ifmedia support. */ 162945386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 163063699Swpaul if (sc->ti_copper) { 163163699Swpaul /* 163263699Swpaul * Copper cards allow manual 10/100 mode selection, 163363699Swpaul * but not manual 1000baseTX mode selection. Why? 163463699Swpaul * Becuase currently there's no way to specify the 163563699Swpaul * master/slave setting through the firmware interface, 163663699Swpaul * so Alteon decided to just bag it and handle it 163763699Swpaul * via autonegotiation. 163863699Swpaul */ 163963699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 164063699Swpaul ifmedia_add(&sc->ifmedia, 164163699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 164263699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 164363699Swpaul ifmedia_add(&sc->ifmedia, 164463699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 164563699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 164663699Swpaul ifmedia_add(&sc->ifmedia, 164763699Swpaul IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 164863699Swpaul } else { 164963699Swpaul /* Fiber cards don't support 10/100 modes. */ 165063699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 165163699Swpaul ifmedia_add(&sc->ifmedia, 165263699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 165363699Swpaul } 165445386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 165545386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 165645386Swpaul 165745386Swpaul /* 165863090Sarchie * Call MI attach routine. 165945386Swpaul */ 166063090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 166167087Swpaul TI_UNLOCK(sc); 166267087Swpaul return(0); 166345386Swpaul 166445386Swpaulfail: 166567087Swpaul TI_UNLOCK(sc); 166667087Swpaul mtx_destroy(&sc->ti_mtx); 166749011Swpaul return(error); 166845386Swpaul} 166945386Swpaul 167049011Swpaulstatic int ti_detach(dev) 167149011Swpaul device_t dev; 167249011Swpaul{ 167349011Swpaul struct ti_softc *sc; 167449011Swpaul struct ifnet *ifp; 167549011Swpaul 167649011Swpaul 167749011Swpaul sc = device_get_softc(dev); 167867087Swpaul TI_LOCK(sc); 167949011Swpaul ifp = &sc->arpcom.ac_if; 168049011Swpaul 168163090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 168249011Swpaul ti_stop(sc); 168349011Swpaul 168449011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 168549011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 168649011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 168749011Swpaul 168862793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 168962793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 169049011Swpaul ifmedia_removeall(&sc->ifmedia); 169149011Swpaul 169267087Swpaul TI_UNLOCK(sc); 169367087Swpaul mtx_destroy(&sc->ti_mtx); 169449011Swpaul 169549011Swpaul return(0); 169649011Swpaul} 169749011Swpaul 169845386Swpaul/* 169945386Swpaul * Frame reception handling. This is called if there's a frame 170045386Swpaul * on the receive return list. 170145386Swpaul * 170245386Swpaul * Note: we have to be able to handle three possibilities here: 170345386Swpaul * 1) the frame is from the mini receive ring (can only happen) 170445386Swpaul * on Tigon 2 boards) 170545386Swpaul * 2) the frame is from the jumbo recieve ring 170645386Swpaul * 3) the frame is from the standard receive ring 170745386Swpaul */ 170845386Swpaul 170945386Swpaulstatic void ti_rxeof(sc) 171045386Swpaul struct ti_softc *sc; 171145386Swpaul{ 171245386Swpaul struct ifnet *ifp; 171348597Swpaul struct ti_cmd_desc cmd; 171445386Swpaul 171545386Swpaul ifp = &sc->arpcom.ac_if; 171645386Swpaul 171745386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 171845386Swpaul struct ti_rx_desc *cur_rx; 171945386Swpaul u_int32_t rxidx; 172045386Swpaul struct ether_header *eh; 172145386Swpaul struct mbuf *m = NULL; 172245386Swpaul u_int16_t vlan_tag = 0; 172345386Swpaul int have_tag = 0; 172445386Swpaul 172545386Swpaul cur_rx = 172645386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 172745386Swpaul rxidx = cur_rx->ti_idx; 172845386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 172945386Swpaul 173045386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 173145386Swpaul have_tag = 1; 173277058Sphk vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 173345386Swpaul } 173445386Swpaul 173545386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 173645386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 173745386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 173845386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 173945386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 174045386Swpaul ifp->if_ierrors++; 174145386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 174245386Swpaul continue; 174345386Swpaul } 174448597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 174548597Swpaul ifp->if_ierrors++; 174648597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 174748597Swpaul continue; 174848597Swpaul } 174945386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 175045386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 175145386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 175245386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 175345386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 175445386Swpaul ifp->if_ierrors++; 175545386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 175645386Swpaul continue; 175745386Swpaul } 175848597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 175948597Swpaul ifp->if_ierrors++; 176048597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 176148597Swpaul continue; 176248597Swpaul } 176345386Swpaul } else { 176445386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 176545386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 176645386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 176745386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 176845386Swpaul ifp->if_ierrors++; 176945386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 177045386Swpaul continue; 177145386Swpaul } 177248597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 177348597Swpaul ifp->if_ierrors++; 177448597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 177548597Swpaul continue; 177648597Swpaul } 177745386Swpaul } 177845386Swpaul 177945386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 178045386Swpaul ifp->if_ipackets++; 178145386Swpaul eh = mtod(m, struct ether_header *); 178245386Swpaul m->m_pkthdr.rcvif = ifp; 178345386Swpaul 178445386Swpaul /* Remove header from mbuf and pass it on. */ 178545386Swpaul m_adj(m, sizeof(struct ether_header)); 178645386Swpaul 178758698Sjlemon if (ifp->if_hwassist) { 178858698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 178958698Sjlemon CSUM_DATA_VALID; 179058698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 179158698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 179258698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 179358698Sjlemon } 179445386Swpaul 179545386Swpaul /* 179645386Swpaul * If we received a packet with a vlan tag, pass it 179745386Swpaul * to vlan_input() instead of ether_input(). 179845386Swpaul */ 179945386Swpaul if (have_tag) { 180087276Sbrooks VLAN_INPUT_TAG(eh, m, vlan_tag); 180145386Swpaul have_tag = vlan_tag = 0; 180245386Swpaul continue; 180345386Swpaul } 180445386Swpaul ether_input(ifp, eh, m); 180545386Swpaul } 180645386Swpaul 180745386Swpaul /* Only necessary on the Tigon 1. */ 180845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 180945386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 181045386Swpaul sc->ti_rx_saved_considx); 181145386Swpaul 181248597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 181348597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 181448597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 181545386Swpaul 181645386Swpaul return; 181745386Swpaul} 181845386Swpaul 181945386Swpaulstatic void ti_txeof(sc) 182045386Swpaul struct ti_softc *sc; 182145386Swpaul{ 182245386Swpaul struct ti_tx_desc *cur_tx = NULL; 182345386Swpaul struct ifnet *ifp; 182445386Swpaul 182545386Swpaul ifp = &sc->arpcom.ac_if; 182645386Swpaul 182745386Swpaul /* 182845386Swpaul * Go through our tx ring and free mbufs for those 182945386Swpaul * frames that have been sent. 183045386Swpaul */ 183145386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 183245386Swpaul u_int32_t idx = 0; 183345386Swpaul 183445386Swpaul idx = sc->ti_tx_saved_considx; 183545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 183645386Swpaul if (idx > 383) 183745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 183845386Swpaul TI_TX_RING_BASE + 6144); 183945386Swpaul else if (idx > 255) 184045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 184145386Swpaul TI_TX_RING_BASE + 4096); 184245386Swpaul else if (idx > 127) 184345386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 184445386Swpaul TI_TX_RING_BASE + 2048); 184545386Swpaul else 184645386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 184745386Swpaul TI_TX_RING_BASE); 184845386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 184945386Swpaul } else 185045386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 185145386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 185245386Swpaul ifp->if_opackets++; 185345386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 185445386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 185545386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 185645386Swpaul } 185748011Swpaul sc->ti_txcnt--; 185845386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 185945386Swpaul ifp->if_timer = 0; 186045386Swpaul } 186145386Swpaul 186245386Swpaul if (cur_tx != NULL) 186345386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 186445386Swpaul 186545386Swpaul return; 186645386Swpaul} 186745386Swpaul 186845386Swpaulstatic void ti_intr(xsc) 186945386Swpaul void *xsc; 187045386Swpaul{ 187145386Swpaul struct ti_softc *sc; 187245386Swpaul struct ifnet *ifp; 187345386Swpaul 187445386Swpaul sc = xsc; 187567087Swpaul TI_LOCK(sc); 187645386Swpaul ifp = &sc->arpcom.ac_if; 187745386Swpaul 187845386Swpaul#ifdef notdef 187945386Swpaul /* Avoid this for now -- checking this register is expensive. */ 188045386Swpaul /* Make sure this is really our interrupt. */ 188167087Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 188267087Swpaul TI_UNLOCK(sc); 188345386Swpaul return; 188467087Swpaul } 188545386Swpaul#endif 188645386Swpaul 188745386Swpaul /* Ack interrupt and stop others from occuring. */ 188845386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 188945386Swpaul 189045386Swpaul if (ifp->if_flags & IFF_RUNNING) { 189145386Swpaul /* Check RX return ring producer/consumer */ 189245386Swpaul ti_rxeof(sc); 189345386Swpaul 189445386Swpaul /* Check TX ring producer/consumer */ 189545386Swpaul ti_txeof(sc); 189645386Swpaul } 189745386Swpaul 189845386Swpaul ti_handle_events(sc); 189945386Swpaul 190045386Swpaul /* Re-enable interrupts. */ 190145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 190245386Swpaul 190345386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 190445386Swpaul ti_start(ifp); 190545386Swpaul 190667087Swpaul TI_UNLOCK(sc); 190767087Swpaul 190845386Swpaul return; 190945386Swpaul} 191045386Swpaul 191145386Swpaulstatic void ti_stats_update(sc) 191245386Swpaul struct ti_softc *sc; 191345386Swpaul{ 191445386Swpaul struct ifnet *ifp; 191545386Swpaul 191645386Swpaul ifp = &sc->arpcom.ac_if; 191745386Swpaul 191845386Swpaul ifp->if_collisions += 191945386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 192045386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 192145386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 192245386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 192345386Swpaul ifp->if_collisions; 192445386Swpaul 192545386Swpaul return; 192645386Swpaul} 192745386Swpaul 192845386Swpaul/* 192945386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 193045386Swpaul * pointers to descriptors. 193145386Swpaul */ 193245386Swpaulstatic int ti_encap(sc, m_head, txidx) 193345386Swpaul struct ti_softc *sc; 193445386Swpaul struct mbuf *m_head; 193545386Swpaul u_int32_t *txidx; 193645386Swpaul{ 193745386Swpaul struct ti_tx_desc *f = NULL; 193845386Swpaul struct mbuf *m; 193948011Swpaul u_int32_t frag, cur, cnt = 0; 194058698Sjlemon u_int16_t csum_flags = 0; 194145386Swpaul struct ifvlan *ifv = NULL; 194245386Swpaul 194345386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 194445386Swpaul m_head->m_pkthdr.rcvif != NULL && 194580307Sbrooks m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 194645386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 194745386Swpaul 194845386Swpaul m = m_head; 194945386Swpaul cur = frag = *txidx; 195045386Swpaul 195158698Sjlemon if (m_head->m_pkthdr.csum_flags) { 195258698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 195358698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 195458698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 195558698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 195658698Sjlemon if (m_head->m_flags & M_LASTFRAG) 195758698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 195858698Sjlemon else if (m_head->m_flags & M_FRAG) 195958698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 196058698Sjlemon } 196145386Swpaul /* 196245386Swpaul * Start packing the mbufs in this chain into 196345386Swpaul * the fragment pointers. Stop when we run out 196445386Swpaul * of fragments or hit the end of the mbuf chain. 196545386Swpaul */ 196645386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 196745386Swpaul if (m->m_len != 0) { 196845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 196945386Swpaul if (frag > 383) 197045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 197145386Swpaul TI_TX_RING_BASE + 6144); 197245386Swpaul else if (frag > 255) 197345386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 197445386Swpaul TI_TX_RING_BASE + 4096); 197545386Swpaul else if (frag > 127) 197645386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 197745386Swpaul TI_TX_RING_BASE + 2048); 197845386Swpaul else 197945386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 198045386Swpaul TI_TX_RING_BASE); 198145386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 198245386Swpaul } else 198345386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 198445386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 198545386Swpaul break; 198645386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 198745386Swpaul f->ti_len = m->m_len; 198858698Sjlemon f->ti_flags = csum_flags; 198983115Sbrooks 199045386Swpaul if (ifv != NULL) { 199145386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 199277058Sphk f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 199345386Swpaul } else { 199445386Swpaul f->ti_vlan_tag = 0; 199545386Swpaul } 199683115Sbrooks 199748011Swpaul /* 199848011Swpaul * Sanity check: avoid coming within 16 descriptors 199948011Swpaul * of the end of the ring. 200048011Swpaul */ 200148011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 200248011Swpaul return(ENOBUFS); 200345386Swpaul cur = frag; 200445386Swpaul TI_INC(frag, TI_TX_RING_CNT); 200548011Swpaul cnt++; 200645386Swpaul } 200745386Swpaul } 200845386Swpaul 200945386Swpaul if (m != NULL) 201045386Swpaul return(ENOBUFS); 201145386Swpaul 201246177Swpaul if (frag == sc->ti_tx_saved_considx) 201346177Swpaul return(ENOBUFS); 201446177Swpaul 201545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 201645386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 201745386Swpaul TI_BDFLAG_END; 201845386Swpaul else 201945386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 202047458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 202148011Swpaul sc->ti_txcnt += cnt; 202245386Swpaul 202345386Swpaul *txidx = frag; 202445386Swpaul 202545386Swpaul return(0); 202645386Swpaul} 202745386Swpaul 202845386Swpaul/* 202945386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 203045386Swpaul * to the mbuf data regions directly in the transmit descriptors. 203145386Swpaul */ 203245386Swpaulstatic void ti_start(ifp) 203345386Swpaul struct ifnet *ifp; 203445386Swpaul{ 203545386Swpaul struct ti_softc *sc; 203645386Swpaul struct mbuf *m_head = NULL; 203745386Swpaul u_int32_t prodidx = 0; 203845386Swpaul 203945386Swpaul sc = ifp->if_softc; 204067087Swpaul TI_LOCK(sc); 204145386Swpaul 204245386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 204345386Swpaul 204445386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 204545386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 204645386Swpaul if (m_head == NULL) 204745386Swpaul break; 204845386Swpaul 204945386Swpaul /* 205058698Sjlemon * XXX 205158698Sjlemon * safety overkill. If this is a fragmented packet chain 205258698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 205358698Sjlemon * it if we have enough descriptors to handle the entire 205458698Sjlemon * chain at once. 205558698Sjlemon * (paranoia -- may not actually be needed) 205658698Sjlemon */ 205758698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 205858698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 205958698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 206058698Sjlemon m_head->m_pkthdr.csum_data + 16) { 206158698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 206258698Sjlemon ifp->if_flags |= IFF_OACTIVE; 206358698Sjlemon break; 206458698Sjlemon } 206558698Sjlemon } 206658698Sjlemon 206758698Sjlemon /* 206845386Swpaul * Pack the data into the transmit ring. If we 206945386Swpaul * don't have room, set the OACTIVE flag and wait 207045386Swpaul * for the NIC to drain the ring. 207145386Swpaul */ 207245386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 207345386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 207445386Swpaul ifp->if_flags |= IFF_OACTIVE; 207545386Swpaul break; 207645386Swpaul } 207745386Swpaul 207845386Swpaul /* 207945386Swpaul * If there's a BPF listener, bounce a copy of this frame 208045386Swpaul * to him. 208145386Swpaul */ 208245386Swpaul if (ifp->if_bpf) 208345386Swpaul bpf_mtap(ifp, m_head); 208445386Swpaul } 208545386Swpaul 208645386Swpaul /* Transmit */ 208745386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 208845386Swpaul 208945386Swpaul /* 209045386Swpaul * Set a timeout in case the chip goes out to lunch. 209145386Swpaul */ 209245386Swpaul ifp->if_timer = 5; 209367087Swpaul TI_UNLOCK(sc); 209445386Swpaul 209545386Swpaul return; 209645386Swpaul} 209745386Swpaul 209845386Swpaulstatic void ti_init(xsc) 209945386Swpaul void *xsc; 210045386Swpaul{ 210145386Swpaul struct ti_softc *sc = xsc; 210245386Swpaul 210345386Swpaul /* Cancel pending I/O and flush buffers. */ 210445386Swpaul ti_stop(sc); 210545386Swpaul 210667087Swpaul TI_LOCK(sc); 210745386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 210845386Swpaul if (ti_gibinit(sc)) { 210945386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 211067087Swpaul TI_UNLOCK(sc); 211145386Swpaul return; 211245386Swpaul } 211345386Swpaul 211467087Swpaul TI_UNLOCK(sc); 211545386Swpaul 211645386Swpaul return; 211745386Swpaul} 211845386Swpaul 211945386Swpaulstatic void ti_init2(sc) 212045386Swpaul struct ti_softc *sc; 212145386Swpaul{ 212245386Swpaul struct ti_cmd_desc cmd; 212345386Swpaul struct ifnet *ifp; 212445386Swpaul u_int16_t *m; 212545386Swpaul struct ifmedia *ifm; 212645386Swpaul int tmp; 212745386Swpaul 212845386Swpaul ifp = &sc->arpcom.ac_if; 212945386Swpaul 213045386Swpaul /* Specify MTU and interface index. */ 213145386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 213245386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 213345386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 213445386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 213545386Swpaul 213645386Swpaul /* Load our MAC address. */ 213745386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 213845386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 213945386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 214045386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 214145386Swpaul 214245386Swpaul /* Enable or disable promiscuous mode as needed. */ 214345386Swpaul if (ifp->if_flags & IFF_PROMISC) { 214445386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 214545386Swpaul } else { 214645386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 214745386Swpaul } 214845386Swpaul 214945386Swpaul /* Program multicast filter. */ 215045386Swpaul ti_setmulti(sc); 215145386Swpaul 215245386Swpaul /* 215345386Swpaul * If this is a Tigon 1, we should tell the 215445386Swpaul * firmware to use software packet filtering. 215545386Swpaul */ 215645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 215745386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 215845386Swpaul } 215945386Swpaul 216045386Swpaul /* Init RX ring. */ 216145386Swpaul ti_init_rx_ring_std(sc); 216245386Swpaul 216345386Swpaul /* Init jumbo RX ring. */ 216445386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 216545386Swpaul ti_init_rx_ring_jumbo(sc); 216645386Swpaul 216745386Swpaul /* 216845386Swpaul * If this is a Tigon 2, we can also configure the 216945386Swpaul * mini ring. 217045386Swpaul */ 217145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 217245386Swpaul ti_init_rx_ring_mini(sc); 217345386Swpaul 217445386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 217545386Swpaul sc->ti_rx_saved_considx = 0; 217645386Swpaul 217745386Swpaul /* Init TX ring. */ 217845386Swpaul ti_init_tx_ring(sc); 217945386Swpaul 218045386Swpaul /* Tell firmware we're alive. */ 218145386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 218245386Swpaul 218345386Swpaul /* Enable host interrupts. */ 218445386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 218545386Swpaul 218645386Swpaul ifp->if_flags |= IFF_RUNNING; 218745386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 218845386Swpaul 218945386Swpaul /* 219045386Swpaul * Make sure to set media properly. We have to do this 219145386Swpaul * here since we have to issue commands in order to set 219245386Swpaul * the link negotiation and we can't issue commands until 219345386Swpaul * the firmware is running. 219445386Swpaul */ 219545386Swpaul ifm = &sc->ifmedia; 219645386Swpaul tmp = ifm->ifm_media; 219745386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 219845386Swpaul ti_ifmedia_upd(ifp); 219945386Swpaul ifm->ifm_media = tmp; 220045386Swpaul 220145386Swpaul return; 220245386Swpaul} 220345386Swpaul 220445386Swpaul/* 220545386Swpaul * Set media options. 220645386Swpaul */ 220745386Swpaulstatic int ti_ifmedia_upd(ifp) 220845386Swpaul struct ifnet *ifp; 220945386Swpaul{ 221045386Swpaul struct ti_softc *sc; 221145386Swpaul struct ifmedia *ifm; 221245386Swpaul struct ti_cmd_desc cmd; 221345386Swpaul 221445386Swpaul sc = ifp->if_softc; 221545386Swpaul ifm = &sc->ifmedia; 221645386Swpaul 221745386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 221845386Swpaul return(EINVAL); 221945386Swpaul 222045386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 222145386Swpaul case IFM_AUTO: 222245386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 222345386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 222445386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 222545386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 222645386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 222745386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 222845386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 222945386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 223045386Swpaul break; 223145386Swpaul case IFM_1000_SX: 223263699Swpaul case IFM_1000_TX: 223345386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 223463699Swpaul TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 223545386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 223663699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 223763699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 223863699Swpaul } 223945386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 224045386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 224145386Swpaul break; 224245386Swpaul case IFM_100_FX: 224345386Swpaul case IFM_10_FL: 224463699Swpaul case IFM_100_TX: 224563699Swpaul case IFM_10_T: 224645386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 224745386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 224863699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 224963699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 225045386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 225145386Swpaul } else { 225245386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 225345386Swpaul } 225445386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 225545386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 225645386Swpaul } else { 225745386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 225845386Swpaul } 225945386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 226045386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 226145386Swpaul break; 226245386Swpaul } 226345386Swpaul 226445386Swpaul return(0); 226545386Swpaul} 226645386Swpaul 226745386Swpaul/* 226845386Swpaul * Report current media status. 226945386Swpaul */ 227045386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 227145386Swpaul struct ifnet *ifp; 227245386Swpaul struct ifmediareq *ifmr; 227345386Swpaul{ 227445386Swpaul struct ti_softc *sc; 227563699Swpaul u_int32_t media = 0; 227645386Swpaul 227745386Swpaul sc = ifp->if_softc; 227845386Swpaul 227945386Swpaul ifmr->ifm_status = IFM_AVALID; 228045386Swpaul ifmr->ifm_active = IFM_ETHER; 228145386Swpaul 228245386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 228345386Swpaul return; 228445386Swpaul 228545386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 228645386Swpaul 228763699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 228863699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 228963699Swpaul if (sc->ti_copper) 229063699Swpaul ifmr->ifm_active |= IFM_1000_TX; 229163699Swpaul else 229263699Swpaul ifmr->ifm_active |= IFM_1000_SX; 229363699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 229463699Swpaul ifmr->ifm_active |= IFM_FDX; 229563699Swpaul else 229663699Swpaul ifmr->ifm_active |= IFM_HDX; 229763699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 229845386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 229963699Swpaul if (sc->ti_copper) { 230063699Swpaul if (media & TI_LNK_100MB) 230163699Swpaul ifmr->ifm_active |= IFM_100_TX; 230263699Swpaul if (media & TI_LNK_10MB) 230363699Swpaul ifmr->ifm_active |= IFM_10_T; 230463699Swpaul } else { 230563699Swpaul if (media & TI_LNK_100MB) 230663699Swpaul ifmr->ifm_active |= IFM_100_FX; 230763699Swpaul if (media & TI_LNK_10MB) 230863699Swpaul ifmr->ifm_active |= IFM_10_FL; 230963699Swpaul } 231045386Swpaul if (media & TI_LNK_FULL_DUPLEX) 231145386Swpaul ifmr->ifm_active |= IFM_FDX; 231245386Swpaul if (media & TI_LNK_HALF_DUPLEX) 231345386Swpaul ifmr->ifm_active |= IFM_HDX; 231445386Swpaul } 231545386Swpaul 231645386Swpaul return; 231745386Swpaul} 231845386Swpaul 231945386Swpaulstatic int ti_ioctl(ifp, command, data) 232045386Swpaul struct ifnet *ifp; 232145386Swpaul u_long command; 232245386Swpaul caddr_t data; 232345386Swpaul{ 232445386Swpaul struct ti_softc *sc = ifp->if_softc; 232545386Swpaul struct ifreq *ifr = (struct ifreq *) data; 232683630Sjlemon int mask, error = 0; 232745386Swpaul struct ti_cmd_desc cmd; 232845386Swpaul 232967087Swpaul TI_LOCK(sc); 233045386Swpaul 233145386Swpaul switch(command) { 233245386Swpaul case SIOCSIFADDR: 233345386Swpaul case SIOCGIFADDR: 233445386Swpaul error = ether_ioctl(ifp, command, data); 233545386Swpaul break; 233645386Swpaul case SIOCSIFMTU: 233745386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 233845386Swpaul error = EINVAL; 233945386Swpaul else { 234045386Swpaul ifp->if_mtu = ifr->ifr_mtu; 234145386Swpaul ti_init(sc); 234245386Swpaul } 234345386Swpaul break; 234445386Swpaul case SIOCSIFFLAGS: 234545386Swpaul if (ifp->if_flags & IFF_UP) { 234645386Swpaul /* 234745386Swpaul * If only the state of the PROMISC flag changed, 234845386Swpaul * then just use the 'set promisc mode' command 234945386Swpaul * instead of reinitializing the entire NIC. Doing 235045386Swpaul * a full re-init means reloading the firmware and 235145386Swpaul * waiting for it to start up, which may take a 235245386Swpaul * second or two. 235345386Swpaul */ 235445386Swpaul if (ifp->if_flags & IFF_RUNNING && 235545386Swpaul ifp->if_flags & IFF_PROMISC && 235645386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 235745386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 235845386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 235945386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 236045386Swpaul !(ifp->if_flags & IFF_PROMISC) && 236145386Swpaul sc->ti_if_flags & IFF_PROMISC) { 236245386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 236345386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 236445386Swpaul } else 236545386Swpaul ti_init(sc); 236645386Swpaul } else { 236745386Swpaul if (ifp->if_flags & IFF_RUNNING) { 236845386Swpaul ti_stop(sc); 236945386Swpaul } 237045386Swpaul } 237145386Swpaul sc->ti_if_flags = ifp->if_flags; 237245386Swpaul error = 0; 237345386Swpaul break; 237445386Swpaul case SIOCADDMULTI: 237545386Swpaul case SIOCDELMULTI: 237645386Swpaul if (ifp->if_flags & IFF_RUNNING) { 237745386Swpaul ti_setmulti(sc); 237845386Swpaul error = 0; 237945386Swpaul } 238045386Swpaul break; 238145386Swpaul case SIOCSIFMEDIA: 238245386Swpaul case SIOCGIFMEDIA: 238345386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 238445386Swpaul break; 238583630Sjlemon case SIOCSIFCAP: 238683630Sjlemon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 238783630Sjlemon if (mask & IFCAP_HWCSUM) { 238883630Sjlemon if (IFCAP_HWCSUM & ifp->if_capenable) 238983630Sjlemon ifp->if_capenable &= ~IFCAP_HWCSUM; 239083630Sjlemon else 239183630Sjlemon ifp->if_capenable |= IFCAP_HWCSUM; 239283630Sjlemon if (ifp->if_flags & IFF_RUNNING) 239383630Sjlemon ti_init(sc); 239483630Sjlemon } 239583630Sjlemon error = 0; 239683630Sjlemon break; 239745386Swpaul default: 239845386Swpaul error = EINVAL; 239945386Swpaul break; 240045386Swpaul } 240145386Swpaul 240267087Swpaul TI_UNLOCK(sc); 240345386Swpaul 240445386Swpaul return(error); 240545386Swpaul} 240645386Swpaul 240745386Swpaulstatic void ti_watchdog(ifp) 240845386Swpaul struct ifnet *ifp; 240945386Swpaul{ 241045386Swpaul struct ti_softc *sc; 241145386Swpaul 241245386Swpaul sc = ifp->if_softc; 241367087Swpaul TI_LOCK(sc); 241445386Swpaul 241545386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 241645386Swpaul ti_stop(sc); 241745386Swpaul ti_init(sc); 241845386Swpaul 241945386Swpaul ifp->if_oerrors++; 242067087Swpaul TI_UNLOCK(sc); 242145386Swpaul 242245386Swpaul return; 242345386Swpaul} 242445386Swpaul 242545386Swpaul/* 242645386Swpaul * Stop the adapter and free any mbufs allocated to the 242745386Swpaul * RX and TX lists. 242845386Swpaul */ 242945386Swpaulstatic void ti_stop(sc) 243045386Swpaul struct ti_softc *sc; 243145386Swpaul{ 243245386Swpaul struct ifnet *ifp; 243345386Swpaul struct ti_cmd_desc cmd; 243445386Swpaul 243567087Swpaul TI_LOCK(sc); 243667087Swpaul 243745386Swpaul ifp = &sc->arpcom.ac_if; 243845386Swpaul 243945386Swpaul /* Disable host interrupts. */ 244045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 244145386Swpaul /* 244245386Swpaul * Tell firmware we're shutting down. 244345386Swpaul */ 244445386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 244545386Swpaul 244645386Swpaul /* Halt and reinitialize. */ 244745386Swpaul ti_chipinit(sc); 244845386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 244945386Swpaul ti_chipinit(sc); 245045386Swpaul 245145386Swpaul /* Free the RX lists. */ 245245386Swpaul ti_free_rx_ring_std(sc); 245345386Swpaul 245445386Swpaul /* Free jumbo RX list. */ 245545386Swpaul ti_free_rx_ring_jumbo(sc); 245645386Swpaul 245745386Swpaul /* Free mini RX list. */ 245845386Swpaul ti_free_rx_ring_mini(sc); 245945386Swpaul 246045386Swpaul /* Free TX buffers. */ 246145386Swpaul ti_free_tx_ring(sc); 246245386Swpaul 246345386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 246445386Swpaul sc->ti_return_prodidx.ti_idx = 0; 246545386Swpaul sc->ti_tx_considx.ti_idx = 0; 246645386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 246745386Swpaul 246845386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 246967087Swpaul TI_UNLOCK(sc); 247045386Swpaul 247145386Swpaul return; 247245386Swpaul} 247345386Swpaul 247445386Swpaul/* 247545386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 247645386Swpaul * get confused by errant DMAs when rebooting. 247745386Swpaul */ 247849011Swpaulstatic void ti_shutdown(dev) 247949011Swpaul device_t dev; 248045386Swpaul{ 248145386Swpaul struct ti_softc *sc; 248245386Swpaul 248349011Swpaul sc = device_get_softc(dev); 248467087Swpaul TI_LOCK(sc); 248545386Swpaul ti_chipinit(sc); 248667087Swpaul TI_UNLOCK(sc); 248745386Swpaul 248845386Swpaul return; 248945386Swpaul} 2490