if_ti.c revision 87276
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 87276 2001-12-03 17:28:27Z brooks $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include <sys/param.h> 8245386Swpaul#include <sys/systm.h> 8345386Swpaul#include <sys/sockio.h> 8445386Swpaul#include <sys/mbuf.h> 8545386Swpaul#include <sys/malloc.h> 8645386Swpaul#include <sys/kernel.h> 8745386Swpaul#include <sys/socket.h> 8845386Swpaul#include <sys/queue.h> 8945386Swpaul 9045386Swpaul#include <net/if.h> 9145386Swpaul#include <net/if_arp.h> 9245386Swpaul#include <net/ethernet.h> 9345386Swpaul#include <net/if_dl.h> 9445386Swpaul#include <net/if_media.h> 9583115Sbrooks#include <net/if_types.h> 9683115Sbrooks#include <net/if_vlan_var.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#include <netinet/in_systm.h> 10145386Swpaul#include <netinet/in.h> 10245386Swpaul#include <netinet/ip.h> 10345386Swpaul 10445386Swpaul#include <vm/vm.h> /* for vtophys */ 10545386Swpaul#include <vm/pmap.h> /* for vtophys */ 10645386Swpaul#include <machine/bus_memio.h> 10745386Swpaul#include <machine/bus.h> 10849011Swpaul#include <machine/resource.h> 10949011Swpaul#include <sys/bus.h> 11049011Swpaul#include <sys/rman.h> 11145386Swpaul 11245386Swpaul#include <pci/pcireg.h> 11345386Swpaul#include <pci/pcivar.h> 11445386Swpaul 11545386Swpaul#include <pci/if_tireg.h> 11645386Swpaul#include <pci/ti_fw.h> 11745386Swpaul#include <pci/ti_fw2.h> 11845386Swpaul 11958698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12045386Swpaul 12145386Swpaul#if !defined(lint) 12245386Swpaulstatic const char rcsid[] = 12350477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 87276 2001-12-03 17:28:27Z brooks $"; 12445386Swpaul#endif 12545386Swpaul 12645386Swpaul/* 12745386Swpaul * Various supported device vendors/types and their names. 12845386Swpaul */ 12945386Swpaul 13045386Swpaulstatic struct ti_type ti_devs[] = { 13145386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13263702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 13363699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 13463702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 13545386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 13645386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 13745386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 13864139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 13964139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 14064139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 14145386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14245386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14356206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 14456206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 14545386Swpaul { 0, 0, NULL } 14645386Swpaul}; 14745386Swpaul 14849011Swpaulstatic int ti_probe __P((device_t)); 14949011Swpaulstatic int ti_attach __P((device_t)); 15049011Swpaulstatic int ti_detach __P((device_t)); 15145386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15245386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15345386Swpaul 15445386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 15545386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 15645386Swpaul u_int32_t *)); 15745386Swpaul 15845386Swpaulstatic void ti_intr __P((void *)); 15945386Swpaulstatic void ti_start __P((struct ifnet *)); 16045386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16145386Swpaulstatic void ti_init __P((void *)); 16245386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16345386Swpaulstatic void ti_stop __P((struct ti_softc *)); 16445386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 16549011Swpaulstatic void ti_shutdown __P((device_t)); 16645386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 16745386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 16845386Swpaul 16945386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17045386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17145386Swpaul int, u_int8_t *)); 17245386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17345386Swpaul 17445386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 17545386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 17645386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 17745386Swpaul 17845386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 17945386Swpaul u_int32_t, caddr_t)); 18045386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18145386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18245386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18345386Swpaul caddr_t, int)); 18445386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 18545386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 18645386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 18764837Sdwmalonestatic void ti_jfree __P((caddr_t, void *)); 18845386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 18945386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19045386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19145386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19245386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19345386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 19445386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 19545386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 19645386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 19745386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 19845386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 19945386Swpaul 20045386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20145386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20245386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 20345386Swpaul 20449011Swpaulstatic device_method_t ti_methods[] = { 20549011Swpaul /* Device interface */ 20649011Swpaul DEVMETHOD(device_probe, ti_probe), 20749011Swpaul DEVMETHOD(device_attach, ti_attach), 20849011Swpaul DEVMETHOD(device_detach, ti_detach), 20949011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 21049011Swpaul { 0, 0 } 21149011Swpaul}; 21249011Swpaul 21349011Swpaulstatic driver_t ti_driver = { 21451455Swpaul "ti", 21549011Swpaul ti_methods, 21649011Swpaul sizeof(struct ti_softc) 21749011Swpaul}; 21849011Swpaul 21949011Swpaulstatic devclass_t ti_devclass; 22049011Swpaul 22151533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22249011Swpaul 22345386Swpaul/* 22445386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 22545386Swpaul */ 22645386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 22745386Swpaul struct ti_softc *sc; 22845386Swpaul int byte; 22945386Swpaul{ 23045386Swpaul register int i, ack = 0; 23145386Swpaul 23245386Swpaul /* 23345386Swpaul * Make sure we're in TX mode. 23445386Swpaul */ 23545386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 23645386Swpaul 23745386Swpaul /* 23845386Swpaul * Feed in each bit and stobe the clock. 23945386Swpaul */ 24045386Swpaul for (i = 0x80; i; i >>= 1) { 24145386Swpaul if (byte & i) { 24245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24345386Swpaul } else { 24445386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24545386Swpaul } 24645386Swpaul DELAY(1); 24745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24845386Swpaul DELAY(1); 24945386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25045386Swpaul } 25145386Swpaul 25245386Swpaul /* 25345386Swpaul * Turn off TX mode. 25445386Swpaul */ 25545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 25645386Swpaul 25745386Swpaul /* 25845386Swpaul * Check for ack. 25945386Swpaul */ 26045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26145386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26345386Swpaul 26445386Swpaul return(ack); 26545386Swpaul} 26645386Swpaul 26745386Swpaul/* 26845386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 26945386Swpaul * We have to send two address bytes since the EEPROM can hold 27045386Swpaul * more than 256 bytes of data. 27145386Swpaul */ 27245386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 27345386Swpaul struct ti_softc *sc; 27445386Swpaul int addr; 27545386Swpaul u_int8_t *dest; 27645386Swpaul{ 27745386Swpaul register int i; 27845386Swpaul u_int8_t byte = 0; 27945386Swpaul 28045386Swpaul EEPROM_START; 28145386Swpaul 28245386Swpaul /* 28345386Swpaul * Send write control code to EEPROM. 28445386Swpaul */ 28545386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 28645386Swpaul printf("ti%d: failed to send write command, status: %x\n", 28745386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 28845386Swpaul return(1); 28945386Swpaul } 29045386Swpaul 29145386Swpaul /* 29245386Swpaul * Send first byte of address of byte we want to read. 29345386Swpaul */ 29445386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 29545386Swpaul printf("ti%d: failed to send address, status: %x\n", 29645386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29745386Swpaul return(1); 29845386Swpaul } 29945386Swpaul /* 30045386Swpaul * Send second byte address of byte we want to read. 30145386Swpaul */ 30245386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 30345386Swpaul printf("ti%d: failed to send address, status: %x\n", 30445386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30545386Swpaul return(1); 30645386Swpaul } 30745386Swpaul 30845386Swpaul EEPROM_STOP; 30945386Swpaul EEPROM_START; 31045386Swpaul /* 31145386Swpaul * Send read control code to EEPROM. 31245386Swpaul */ 31345386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 31445386Swpaul printf("ti%d: failed to send read command, status: %x\n", 31545386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31645386Swpaul return(1); 31745386Swpaul } 31845386Swpaul 31945386Swpaul /* 32045386Swpaul * Start reading bits from EEPROM. 32145386Swpaul */ 32245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 32345386Swpaul for (i = 0x80; i; i >>= 1) { 32445386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 32545386Swpaul DELAY(1); 32645386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 32745386Swpaul byte |= i; 32845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 32945386Swpaul DELAY(1); 33045386Swpaul } 33145386Swpaul 33245386Swpaul EEPROM_STOP; 33345386Swpaul 33445386Swpaul /* 33545386Swpaul * No ACK generated for read, so just return byte. 33645386Swpaul */ 33745386Swpaul 33845386Swpaul *dest = byte; 33945386Swpaul 34045386Swpaul return(0); 34145386Swpaul} 34245386Swpaul 34345386Swpaul/* 34445386Swpaul * Read a sequence of bytes from the EEPROM. 34545386Swpaul */ 34645386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 34745386Swpaul struct ti_softc *sc; 34845386Swpaul caddr_t dest; 34945386Swpaul int off; 35045386Swpaul int cnt; 35145386Swpaul{ 35245386Swpaul int err = 0, i; 35345386Swpaul u_int8_t byte = 0; 35445386Swpaul 35545386Swpaul for (i = 0; i < cnt; i++) { 35645386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 35745386Swpaul if (err) 35845386Swpaul break; 35945386Swpaul *(dest + i) = byte; 36045386Swpaul } 36145386Swpaul 36245386Swpaul return(err ? 1 : 0); 36345386Swpaul} 36445386Swpaul 36545386Swpaul/* 36645386Swpaul * NIC memory access function. Can be used to either clear a section 36745386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 36845386Swpaul */ 36945386Swpaulstatic void ti_mem(sc, addr, len, buf) 37045386Swpaul struct ti_softc *sc; 37145386Swpaul u_int32_t addr, len; 37245386Swpaul caddr_t buf; 37345386Swpaul{ 37445386Swpaul int segptr, segsize, cnt; 37545386Swpaul caddr_t ti_winbase, ptr; 37645386Swpaul 37745386Swpaul segptr = addr; 37845386Swpaul cnt = len; 37949133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 38045386Swpaul ptr = buf; 38145386Swpaul 38245386Swpaul while(cnt) { 38345386Swpaul if (cnt < TI_WINLEN) 38445386Swpaul segsize = cnt; 38545386Swpaul else 38645386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 38745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 38845386Swpaul if (buf == NULL) 38945386Swpaul bzero((char *)ti_winbase + (segptr & 39045386Swpaul (TI_WINLEN - 1)), segsize); 39145386Swpaul else { 39245386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 39345386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 39445386Swpaul ptr += segsize; 39545386Swpaul } 39645386Swpaul segptr += segsize; 39745386Swpaul cnt -= segsize; 39845386Swpaul } 39945386Swpaul 40045386Swpaul return; 40145386Swpaul} 40245386Swpaul 40345386Swpaul/* 40445386Swpaul * Load firmware image into the NIC. Check that the firmware revision 40545386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 40645386Swpaul * Tigon 2. 40745386Swpaul */ 40845386Swpaulstatic void ti_loadfw(sc) 40945386Swpaul struct ti_softc *sc; 41045386Swpaul{ 41145386Swpaul switch(sc->ti_hwrev) { 41245386Swpaul case TI_HWREV_TIGON: 41345386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 41445386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 41545386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 41645386Swpaul printf("ti%d: firmware revision mismatch; want " 41745386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 41845386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 41945386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 42045386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 42145386Swpaul return; 42245386Swpaul } 42345386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 42445386Swpaul (caddr_t)tigonFwText); 42545386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 42645386Swpaul (caddr_t)tigonFwData); 42745386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 42845386Swpaul (caddr_t)tigonFwRodata); 42945386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 43045386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 43145386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43245386Swpaul break; 43345386Swpaul case TI_HWREV_TIGON_II: 43445386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 43545386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 43645386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 43745386Swpaul printf("ti%d: firmware revision mismatch; want " 43845386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 43945386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 44045386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 44145386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44245386Swpaul return; 44345386Swpaul } 44445386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 44545386Swpaul (caddr_t)tigon2FwText); 44645386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 44745386Swpaul (caddr_t)tigon2FwData); 44845386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 44945386Swpaul (caddr_t)tigon2FwRodata); 45045386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 45145386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45245386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 45345386Swpaul break; 45445386Swpaul default: 45545386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 45645386Swpaul sc->ti_unit); 45745386Swpaul break; 45845386Swpaul } 45945386Swpaul 46045386Swpaul return; 46145386Swpaul} 46245386Swpaul 46345386Swpaul/* 46445386Swpaul * Send the NIC a command via the command ring. 46545386Swpaul */ 46645386Swpaulstatic void ti_cmd(sc, cmd) 46745386Swpaul struct ti_softc *sc; 46845386Swpaul struct ti_cmd_desc *cmd; 46945386Swpaul{ 47045386Swpaul u_int32_t index; 47145386Swpaul 47245386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 47345386Swpaul return; 47445386Swpaul 47545386Swpaul index = sc->ti_cmd_saved_prodidx; 47645386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 47745386Swpaul TI_INC(index, TI_CMD_RING_CNT); 47845386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 47945386Swpaul sc->ti_cmd_saved_prodidx = index; 48045386Swpaul 48145386Swpaul return; 48245386Swpaul} 48345386Swpaul 48445386Swpaul/* 48545386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 48645386Swpaul * number of command slots to include after the initial command. 48745386Swpaul */ 48845386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 48945386Swpaul struct ti_softc *sc; 49045386Swpaul struct ti_cmd_desc *cmd; 49145386Swpaul caddr_t arg; 49245386Swpaul int len; 49345386Swpaul{ 49445386Swpaul u_int32_t index; 49545386Swpaul register int i; 49645386Swpaul 49745386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 49845386Swpaul return; 49945386Swpaul 50045386Swpaul index = sc->ti_cmd_saved_prodidx; 50145386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50245386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50345386Swpaul for (i = 0; i < len; i++) { 50445386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 50545386Swpaul *(u_int32_t *)(&arg[i * 4])); 50645386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50745386Swpaul } 50845386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 50945386Swpaul sc->ti_cmd_saved_prodidx = index; 51045386Swpaul 51145386Swpaul return; 51245386Swpaul} 51345386Swpaul 51445386Swpaul/* 51545386Swpaul * Handle events that have triggered interrupts. 51645386Swpaul */ 51745386Swpaulstatic void ti_handle_events(sc) 51845386Swpaul struct ti_softc *sc; 51945386Swpaul{ 52045386Swpaul struct ti_event_desc *e; 52145386Swpaul 52245386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 52345386Swpaul return; 52445386Swpaul 52545386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 52645386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 52745386Swpaul switch(e->ti_event) { 52845386Swpaul case TI_EV_LINKSTAT_CHANGED: 52945386Swpaul sc->ti_linkstat = e->ti_code; 53045386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 53145386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53245386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 53345386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 53445386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 53545386Swpaul printf("ti%d: link down\n", sc->ti_unit); 53645386Swpaul break; 53745386Swpaul case TI_EV_ERROR: 53845386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 53945386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 54045386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 54145386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54245386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 54345386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 54445386Swpaul break; 54545386Swpaul case TI_EV_FIRMWARE_UP: 54645386Swpaul ti_init2(sc); 54745386Swpaul break; 54845386Swpaul case TI_EV_STATS_UPDATED: 54945386Swpaul ti_stats_update(sc); 55045386Swpaul break; 55145386Swpaul case TI_EV_RESET_JUMBO_RING: 55245386Swpaul case TI_EV_MCAST_UPDATED: 55345386Swpaul /* Who cares. */ 55445386Swpaul break; 55545386Swpaul default: 55645386Swpaul printf("ti%d: unknown event: %d\n", 55745386Swpaul sc->ti_unit, e->ti_event); 55845386Swpaul break; 55945386Swpaul } 56045386Swpaul /* Advance the consumer index. */ 56145386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56245386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 56345386Swpaul } 56445386Swpaul 56545386Swpaul return; 56645386Swpaul} 56745386Swpaul 56845386Swpaul/* 56945386Swpaul * Memory management for the jumbo receive ring is a pain in the 57045386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 57145386Swpaul * _and_ it has to be contiguous (unless you use the extended 57245386Swpaul * jumbo descriptor format). Using malloc() all the time won't 57345386Swpaul * work: malloc() allocates memory in powers of two, which means we 57445386Swpaul * would end up wasting a considerable amount of space by allocating 57545386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 57645386Swpaul * to do our own memory management. 57745386Swpaul * 57845386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 57945386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 58045386Swpaul * as external mbuf storage. 58145386Swpaul * 58245386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 58345386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 58445386Swpaul * RAM. This is a bit much, especially considering we also need 58545386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 58645386Swpaul * save space, we only actually allocate enough memory for 64 slots 58745386Swpaul * by default, which works out to between 500 and 600K. This can 58845386Swpaul * be tuned by changing a #define in if_tireg.h. 58945386Swpaul */ 59045386Swpaul 59145386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59245386Swpaul struct ti_softc *sc; 59345386Swpaul{ 59445386Swpaul caddr_t ptr; 59545386Swpaul register int i; 59645386Swpaul struct ti_jpool_entry *entry; 59745386Swpaul 59845386Swpaul /* Grab a big chunk o' storage. */ 59945386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 60050548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 60145386Swpaul 60245386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 60345386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 60445386Swpaul return(ENOBUFS); 60545386Swpaul } 60645386Swpaul 60745386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 60845386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 60945386Swpaul 61045386Swpaul /* 61145386Swpaul * Now divide it up into 9K pieces and save the addresses 61267405Sbmilekic * in an array. 61345386Swpaul */ 61445386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 61545386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 61667405Sbmilekic sc->ti_cdata.ti_jslots[i] = ptr; 61767405Sbmilekic ptr += TI_JLEN; 61845386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 61945386Swpaul M_DEVBUF, M_NOWAIT); 62045386Swpaul if (entry == NULL) { 62162793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 62262793Sgallatin M_DEVBUF); 62345386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 62445386Swpaul printf("ti%d: no memory for jumbo " 62545386Swpaul "buffer queue!\n", sc->ti_unit); 62645386Swpaul return(ENOBUFS); 62745386Swpaul } 62845386Swpaul entry->slot = i; 62945386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 63045386Swpaul } 63145386Swpaul 63245386Swpaul return(0); 63345386Swpaul} 63445386Swpaul 63545386Swpaul/* 63645386Swpaul * Allocate a jumbo buffer. 63745386Swpaul */ 63845386Swpaulstatic void *ti_jalloc(sc) 63945386Swpaul struct ti_softc *sc; 64045386Swpaul{ 64145386Swpaul struct ti_jpool_entry *entry; 64245386Swpaul 64345386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 64445386Swpaul 64545386Swpaul if (entry == NULL) { 64645386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 64745386Swpaul return(NULL); 64845386Swpaul } 64945386Swpaul 65045386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 65145386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 65267405Sbmilekic return(sc->ti_cdata.ti_jslots[entry->slot]); 65345386Swpaul} 65445386Swpaul 65545386Swpaul/* 65645386Swpaul * Release a jumbo buffer. 65745386Swpaul */ 65864837Sdwmalonestatic void ti_jfree(buf, args) 65945386Swpaul caddr_t buf; 66064837Sdwmalone void *args; 66145386Swpaul{ 66245386Swpaul struct ti_softc *sc; 66345386Swpaul int i; 66445386Swpaul struct ti_jpool_entry *entry; 66545386Swpaul 66645386Swpaul /* Extract the softc struct pointer. */ 66767405Sbmilekic sc = (struct ti_softc *)args; 66845386Swpaul 66945386Swpaul if (sc == NULL) 67067405Sbmilekic panic("ti_jfree: didn't get softc pointer!"); 67145386Swpaul 67245386Swpaul /* calculate the slot this buffer belongs to */ 67367405Sbmilekic i = ((vm_offset_t)buf 67445386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 67545386Swpaul 67645386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 67745386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 67845386Swpaul 67964837Sdwmalone entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 68064837Sdwmalone if (entry == NULL) 68164837Sdwmalone panic("ti_jfree: buffer not in use!"); 68264837Sdwmalone entry->slot = i; 68364837Sdwmalone SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 68464837Sdwmalone SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 68564837Sdwmalone 68645386Swpaul return; 68745386Swpaul} 68845386Swpaul 68945386Swpaul 69045386Swpaul/* 69145386Swpaul * Intialize a standard receive ring descriptor. 69245386Swpaul */ 69345386Swpaulstatic int ti_newbuf_std(sc, i, m) 69445386Swpaul struct ti_softc *sc; 69545386Swpaul int i; 69645386Swpaul struct mbuf *m; 69745386Swpaul{ 69845386Swpaul struct mbuf *m_new = NULL; 69945386Swpaul struct ti_rx_desc *r; 70045386Swpaul 70149036Swpaul if (m == NULL) { 70245386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 70345386Swpaul if (m_new == NULL) { 70445386Swpaul printf("ti%d: mbuf allocation failed " 70545386Swpaul "-- packet dropped!\n", sc->ti_unit); 70645386Swpaul return(ENOBUFS); 70745386Swpaul } 70845386Swpaul 70945386Swpaul MCLGET(m_new, M_DONTWAIT); 71045386Swpaul if (!(m_new->m_flags & M_EXT)) { 71145386Swpaul printf("ti%d: cluster allocation failed " 71245386Swpaul "-- packet dropped!\n", sc->ti_unit); 71345386Swpaul m_freem(m_new); 71445386Swpaul return(ENOBUFS); 71545386Swpaul } 71649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 71749036Swpaul } else { 71849036Swpaul m_new = m; 71949036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 72049036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 72145386Swpaul } 72245386Swpaul 72348597Swpaul m_adj(m_new, ETHER_ALIGN); 72445386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 72545386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 72645386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 72745386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 72845386Swpaul r->ti_flags = 0; 72958698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 73058698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 73149036Swpaul r->ti_len = m_new->m_len; 73245386Swpaul r->ti_idx = i; 73345386Swpaul 73445386Swpaul return(0); 73545386Swpaul} 73645386Swpaul 73745386Swpaul/* 73845386Swpaul * Intialize a mini receive ring descriptor. This only applies to 73945386Swpaul * the Tigon 2. 74045386Swpaul */ 74145386Swpaulstatic int ti_newbuf_mini(sc, i, m) 74245386Swpaul struct ti_softc *sc; 74345386Swpaul int i; 74445386Swpaul struct mbuf *m; 74545386Swpaul{ 74645386Swpaul struct mbuf *m_new = NULL; 74745386Swpaul struct ti_rx_desc *r; 74845386Swpaul 74949036Swpaul if (m == NULL) { 75045386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 75145386Swpaul if (m_new == NULL) { 75245386Swpaul printf("ti%d: mbuf allocation failed " 75345386Swpaul "-- packet dropped!\n", sc->ti_unit); 75445386Swpaul return(ENOBUFS); 75545386Swpaul } 75649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 75749036Swpaul } else { 75849036Swpaul m_new = m; 75949036Swpaul m_new->m_data = m_new->m_pktdat; 76049036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 76145386Swpaul } 76249036Swpaul 76348597Swpaul m_adj(m_new, ETHER_ALIGN); 76445386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 76545386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 76645386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 76745386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 76845386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 76958698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 77058698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 77149036Swpaul r->ti_len = m_new->m_len; 77245386Swpaul r->ti_idx = i; 77345386Swpaul 77445386Swpaul return(0); 77545386Swpaul} 77645386Swpaul 77745386Swpaul/* 77845386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 77945386Swpaul * a jumbo buffer from the pool managed internally by the driver. 78045386Swpaul */ 78145386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 78245386Swpaul struct ti_softc *sc; 78345386Swpaul int i; 78445386Swpaul struct mbuf *m; 78545386Swpaul{ 78645386Swpaul struct mbuf *m_new = NULL; 78745386Swpaul struct ti_rx_desc *r; 78845386Swpaul 78949036Swpaul if (m == NULL) { 79045386Swpaul caddr_t *buf = NULL; 79145386Swpaul 79245386Swpaul /* Allocate the mbuf. */ 79345386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 79445386Swpaul if (m_new == NULL) { 79545386Swpaul printf("ti%d: mbuf allocation failed " 79645386Swpaul "-- packet dropped!\n", sc->ti_unit); 79745386Swpaul return(ENOBUFS); 79845386Swpaul } 79945386Swpaul 80045386Swpaul /* Allocate the jumbo buffer */ 80145386Swpaul buf = ti_jalloc(sc); 80245386Swpaul if (buf == NULL) { 80345386Swpaul m_freem(m_new); 80445386Swpaul printf("ti%d: jumbo allocation failed " 80545386Swpaul "-- packet dropped!\n", sc->ti_unit); 80645386Swpaul return(ENOBUFS); 80745386Swpaul } 80845386Swpaul 80945386Swpaul /* Attach the buffer to the mbuf. */ 81064837Sdwmalone m_new->m_data = (void *) buf; 81164837Sdwmalone m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 81267405Sbmilekic MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 81368621Sbmilekic (struct ti_softc *)sc, 0, EXT_NET_DRV); 81449036Swpaul } else { 81549036Swpaul m_new = m; 81649036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 81749036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 81845386Swpaul } 81945386Swpaul 82049780Swpaul m_adj(m_new, ETHER_ALIGN); 82145386Swpaul /* Set up the descriptor. */ 82245386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 82345386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 82445386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 82545386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 82645386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 82758698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 82858698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 82949036Swpaul r->ti_len = m_new->m_len; 83045386Swpaul r->ti_idx = i; 83145386Swpaul 83245386Swpaul return(0); 83345386Swpaul} 83445386Swpaul 83545386Swpaul/* 83645386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 83745386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 83845386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 83945386Swpaul * the NIC. 84045386Swpaul */ 84145386Swpaulstatic int ti_init_rx_ring_std(sc) 84245386Swpaul struct ti_softc *sc; 84345386Swpaul{ 84445386Swpaul register int i; 84545386Swpaul struct ti_cmd_desc cmd; 84645386Swpaul 84745386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 84845386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 84945386Swpaul return(ENOBUFS); 85045386Swpaul }; 85145386Swpaul 85245386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 85348597Swpaul sc->ti_std = i - 1; 85445386Swpaul 85545386Swpaul return(0); 85645386Swpaul} 85745386Swpaul 85845386Swpaulstatic void ti_free_rx_ring_std(sc) 85945386Swpaul struct ti_softc *sc; 86045386Swpaul{ 86145386Swpaul register int i; 86245386Swpaul 86345386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 86445386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 86545386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 86645386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 86745386Swpaul } 86845386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 86945386Swpaul sizeof(struct ti_rx_desc)); 87045386Swpaul } 87145386Swpaul 87245386Swpaul return; 87345386Swpaul} 87445386Swpaul 87545386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 87645386Swpaul struct ti_softc *sc; 87745386Swpaul{ 87845386Swpaul register int i; 87945386Swpaul struct ti_cmd_desc cmd; 88045386Swpaul 88163699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 88245386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 88345386Swpaul return(ENOBUFS); 88445386Swpaul }; 88545386Swpaul 88645386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 88748597Swpaul sc->ti_jumbo = i - 1; 88845386Swpaul 88945386Swpaul return(0); 89045386Swpaul} 89145386Swpaul 89245386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 89345386Swpaul struct ti_softc *sc; 89445386Swpaul{ 89545386Swpaul register int i; 89645386Swpaul 89745386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 89845386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 89945386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 90045386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 90145386Swpaul } 90245386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 90345386Swpaul sizeof(struct ti_rx_desc)); 90445386Swpaul } 90545386Swpaul 90645386Swpaul return; 90745386Swpaul} 90845386Swpaul 90945386Swpaulstatic int ti_init_rx_ring_mini(sc) 91045386Swpaul struct ti_softc *sc; 91145386Swpaul{ 91245386Swpaul register int i; 91345386Swpaul 91445386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 91545386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 91645386Swpaul return(ENOBUFS); 91745386Swpaul }; 91845386Swpaul 91945386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 92048597Swpaul sc->ti_mini = i - 1; 92145386Swpaul 92245386Swpaul return(0); 92345386Swpaul} 92445386Swpaul 92545386Swpaulstatic void ti_free_rx_ring_mini(sc) 92645386Swpaul struct ti_softc *sc; 92745386Swpaul{ 92845386Swpaul register int i; 92945386Swpaul 93045386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 93145386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 93245386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 93345386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 93445386Swpaul } 93545386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 93645386Swpaul sizeof(struct ti_rx_desc)); 93745386Swpaul } 93845386Swpaul 93945386Swpaul return; 94045386Swpaul} 94145386Swpaul 94245386Swpaulstatic void ti_free_tx_ring(sc) 94345386Swpaul struct ti_softc *sc; 94445386Swpaul{ 94545386Swpaul register int i; 94645386Swpaul 94745386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 94845386Swpaul return; 94945386Swpaul 95045386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 95145386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 95245386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 95345386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 95445386Swpaul } 95545386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 95645386Swpaul sizeof(struct ti_tx_desc)); 95745386Swpaul } 95845386Swpaul 95945386Swpaul return; 96045386Swpaul} 96145386Swpaul 96245386Swpaulstatic int ti_init_tx_ring(sc) 96345386Swpaul struct ti_softc *sc; 96445386Swpaul{ 96548011Swpaul sc->ti_txcnt = 0; 96645386Swpaul sc->ti_tx_saved_considx = 0; 96745386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 96845386Swpaul return(0); 96945386Swpaul} 97045386Swpaul 97145386Swpaul/* 97245386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 97345386Swpaul * but we have to support the old way too so that Tigon 1 cards will 97445386Swpaul * work. 97545386Swpaul */ 97645386Swpaulvoid ti_add_mcast(sc, addr) 97745386Swpaul struct ti_softc *sc; 97845386Swpaul struct ether_addr *addr; 97945386Swpaul{ 98045386Swpaul struct ti_cmd_desc cmd; 98145386Swpaul u_int16_t *m; 98245386Swpaul u_int32_t ext[2] = {0, 0}; 98345386Swpaul 98445386Swpaul m = (u_int16_t *)&addr->octet[0]; 98545386Swpaul 98645386Swpaul switch(sc->ti_hwrev) { 98745386Swpaul case TI_HWREV_TIGON: 98845386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 98945386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 99045386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 99145386Swpaul break; 99245386Swpaul case TI_HWREV_TIGON_II: 99345386Swpaul ext[0] = htons(m[0]); 99445386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 99545386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 99645386Swpaul break; 99745386Swpaul default: 99845386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 99945386Swpaul break; 100045386Swpaul } 100145386Swpaul 100245386Swpaul return; 100345386Swpaul} 100445386Swpaul 100545386Swpaulvoid ti_del_mcast(sc, addr) 100645386Swpaul struct ti_softc *sc; 100745386Swpaul struct ether_addr *addr; 100845386Swpaul{ 100945386Swpaul struct ti_cmd_desc cmd; 101045386Swpaul u_int16_t *m; 101145386Swpaul u_int32_t ext[2] = {0, 0}; 101245386Swpaul 101345386Swpaul m = (u_int16_t *)&addr->octet[0]; 101445386Swpaul 101545386Swpaul switch(sc->ti_hwrev) { 101645386Swpaul case TI_HWREV_TIGON: 101745386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 101845386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 101945386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 102045386Swpaul break; 102145386Swpaul case TI_HWREV_TIGON_II: 102245386Swpaul ext[0] = htons(m[0]); 102345386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 102445386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 102545386Swpaul break; 102645386Swpaul default: 102745386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 102845386Swpaul break; 102945386Swpaul } 103045386Swpaul 103145386Swpaul return; 103245386Swpaul} 103345386Swpaul 103445386Swpaul/* 103545386Swpaul * Configure the Tigon's multicast address filter. 103645386Swpaul * 103745386Swpaul * The actual multicast table management is a bit of a pain, thanks to 103845386Swpaul * slight brain damage on the part of both Alteon and us. With our 103945386Swpaul * multicast code, we are only alerted when the multicast address table 104045386Swpaul * changes and at that point we only have the current list of addresses: 104145386Swpaul * we only know the current state, not the previous state, so we don't 104245386Swpaul * actually know what addresses were removed or added. The firmware has 104345386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 104445386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 104545386Swpaul * state so we know what addresses have been programmed into the NIC at 104645386Swpaul * any given time. 104745386Swpaul */ 104845386Swpaulstatic void ti_setmulti(sc) 104945386Swpaul struct ti_softc *sc; 105045386Swpaul{ 105145386Swpaul struct ifnet *ifp; 105245386Swpaul struct ifmultiaddr *ifma; 105345386Swpaul struct ti_cmd_desc cmd; 105445386Swpaul struct ti_mc_entry *mc; 105545386Swpaul u_int32_t intrs; 105645386Swpaul 105745386Swpaul ifp = &sc->arpcom.ac_if; 105845386Swpaul 105945386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 106045386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 106145386Swpaul return; 106245386Swpaul } else { 106345386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 106445386Swpaul } 106545386Swpaul 106645386Swpaul /* Disable interrupts. */ 106745386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 106845386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 106945386Swpaul 107045386Swpaul /* First, zot all the existing filters. */ 107171999Sphk while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 107271999Sphk mc = SLIST_FIRST(&sc->ti_mc_listhead); 107345386Swpaul ti_del_mcast(sc, &mc->mc_addr); 107445386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 107545386Swpaul free(mc, M_DEVBUF); 107645386Swpaul } 107745386Swpaul 107845386Swpaul /* Now program new ones. */ 107972084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 108045386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 108145386Swpaul continue; 108245386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 108345386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 108445386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 108545386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 108645386Swpaul ti_add_mcast(sc, &mc->mc_addr); 108745386Swpaul } 108845386Swpaul 108945386Swpaul /* Re-enable interrupts. */ 109045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 109145386Swpaul 109245386Swpaul return; 109345386Swpaul} 109445386Swpaul 109545386Swpaul/* 109645386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 109745386Swpaul * we aren't actually in one. If we detect this condition, we can work 109845386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 109945386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 110045386Swpaul */ 110145386Swpaulstatic int ti_64bitslot_war(sc) 110245386Swpaul struct ti_softc *sc; 110345386Swpaul{ 110445386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 110545386Swpaul CSR_WRITE_4(sc, 0x600, 0); 110645386Swpaul CSR_WRITE_4(sc, 0x604, 0); 110745386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 110845386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 110945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 111045386Swpaul return(EINVAL); 111145386Swpaul else { 111245386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 111345386Swpaul TI_PCISTATE_32BIT_BUS); 111445386Swpaul return(0); 111545386Swpaul } 111645386Swpaul } 111745386Swpaul } 111845386Swpaul 111945386Swpaul return(0); 112045386Swpaul} 112145386Swpaul 112245386Swpaul/* 112345386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 112445386Swpaul * self-test results. 112545386Swpaul */ 112645386Swpaulstatic int ti_chipinit(sc) 112745386Swpaul struct ti_softc *sc; 112845386Swpaul{ 112945386Swpaul u_int32_t cacheline; 113045386Swpaul u_int32_t pci_writemax = 0; 113145386Swpaul 113245386Swpaul /* Initialize link to down state. */ 113345386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 113445386Swpaul 113583630Sjlemon if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 113683630Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 113783630Sjlemon else 113883630Sjlemon sc->arpcom.ac_if.if_hwassist = 0; 113958698Sjlemon 114045386Swpaul /* Set endianness before we access any non-PCI registers. */ 114145386Swpaul#if BYTE_ORDER == BIG_ENDIAN 114245386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 114345386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 114445386Swpaul#else 114545386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 114645386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 114745386Swpaul#endif 114845386Swpaul 114945386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 115045386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 115145386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 115245386Swpaul return(ENODEV); 115345386Swpaul } 115445386Swpaul 115545386Swpaul /* Halt the CPU. */ 115645386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 115745386Swpaul 115845386Swpaul /* Figure out the hardware revision. */ 115945386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 116045386Swpaul case TI_REV_TIGON_I: 116145386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 116245386Swpaul break; 116345386Swpaul case TI_REV_TIGON_II: 116445386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 116545386Swpaul break; 116645386Swpaul default: 116745386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 116845386Swpaul return(ENODEV); 116945386Swpaul } 117045386Swpaul 117145386Swpaul /* Do special setup for Tigon 2. */ 117245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 117345386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 117476033Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 117545386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 117645386Swpaul } 117745386Swpaul 117845386Swpaul /* Set up the PCI state register. */ 117945386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 118045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 118145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 118245386Swpaul } 118345386Swpaul 118445386Swpaul /* Clear the read/write max DMA parameters. */ 118545386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 118645386Swpaul TI_PCISTATE_READ_MAXDMA)); 118745386Swpaul 118845386Swpaul /* Get cache line size. */ 118945386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 119045386Swpaul 119145386Swpaul /* 119245386Swpaul * If the system has set enabled the PCI memory write 119345386Swpaul * and invalidate command in the command register, set 119445386Swpaul * the write max parameter accordingly. This is necessary 119545386Swpaul * to use MWI with the Tigon 2. 119645386Swpaul */ 119745386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 119845386Swpaul switch(cacheline) { 119945386Swpaul case 1: 120045386Swpaul case 4: 120145386Swpaul case 8: 120245386Swpaul case 16: 120345386Swpaul case 32: 120445386Swpaul case 64: 120545386Swpaul break; 120645386Swpaul default: 120745386Swpaul /* Disable PCI memory write and invalidate. */ 120845386Swpaul if (bootverbose) 120945386Swpaul printf("ti%d: cache line size %d not " 121045386Swpaul "supported; disabling PCI MWI\n", 121145386Swpaul sc->ti_unit, cacheline); 121245386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 121345386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 121445386Swpaul break; 121545386Swpaul } 121645386Swpaul } 121745386Swpaul 121845386Swpaul#ifdef __brokenalpha__ 121945386Swpaul /* 122045386Swpaul * From the Alteon sample driver: 122145386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 122245386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 122345386Swpaul * restriction on some ALPHA platforms with early revision 122445386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 122545386Swpaul */ 122645386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 122745386Swpaul#else 122845386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 122945386Swpaul#endif 123045386Swpaul 123145386Swpaul /* This sets the min dma param all the way up (0xff). */ 123245386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 123345386Swpaul 123445386Swpaul /* Configure DMA variables. */ 123545386Swpaul#if BYTE_ORDER == BIG_ENDIAN 123645386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 123745386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 123845386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 123945386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 124045386Swpaul#else 124145386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 124245386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 124345386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 124445386Swpaul#endif 124545386Swpaul 124645386Swpaul /* 124745386Swpaul * Only allow 1 DMA channel to be active at a time. 124845386Swpaul * I don't think this is a good idea, but without it 124945386Swpaul * the firmware racks up lots of nicDmaReadRingFull 125058698Sjlemon * errors. This is not compatible with hardware checksums. 125145386Swpaul */ 125258698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 125358698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 125445386Swpaul 125545386Swpaul /* Recommended settings from Tigon manual. */ 125645386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 125745386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 125845386Swpaul 125945386Swpaul if (ti_64bitslot_war(sc)) { 126045386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 126145386Swpaul "but we aren't", sc->ti_unit); 126245386Swpaul return(EINVAL); 126345386Swpaul } 126445386Swpaul 126545386Swpaul return(0); 126645386Swpaul} 126745386Swpaul 126845386Swpaul/* 126945386Swpaul * Initialize the general information block and firmware, and 127045386Swpaul * start the CPU(s) running. 127145386Swpaul */ 127245386Swpaulstatic int ti_gibinit(sc) 127345386Swpaul struct ti_softc *sc; 127445386Swpaul{ 127545386Swpaul struct ti_rcb *rcb; 127645386Swpaul int i; 127745386Swpaul struct ifnet *ifp; 127845386Swpaul 127945386Swpaul ifp = &sc->arpcom.ac_if; 128045386Swpaul 128145386Swpaul /* Disable interrupts for now. */ 128245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 128345386Swpaul 128445386Swpaul /* Tell the chip where to find the general information block. */ 128545386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 128645386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 128745386Swpaul 128845386Swpaul /* Load the firmware into SRAM. */ 128945386Swpaul ti_loadfw(sc); 129045386Swpaul 129145386Swpaul /* Set up the contents of the general info and ring control blocks. */ 129245386Swpaul 129345386Swpaul /* Set up the event ring and producer pointer. */ 129445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 129545386Swpaul 129645386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 129745386Swpaul rcb->ti_flags = 0; 129845386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 129945386Swpaul vtophys(&sc->ti_ev_prodidx); 130045386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 130145386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 130245386Swpaul sc->ti_ev_saved_considx = 0; 130345386Swpaul 130445386Swpaul /* Set up the command ring and producer mailbox. */ 130545386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 130645386Swpaul 130745386Swpaul sc->ti_rdata->ti_cmd_ring = 130849133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 130945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 131045386Swpaul rcb->ti_flags = 0; 131145386Swpaul rcb->ti_max_len = 0; 131245386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 131345386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 131445386Swpaul } 131545386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 131645386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 131745386Swpaul sc->ti_cmd_saved_prodidx = 0; 131845386Swpaul 131945386Swpaul /* 132045386Swpaul * Assign the address of the stats refresh buffer. 132145386Swpaul * We re-use the current stats buffer for this to 132245386Swpaul * conserve memory. 132345386Swpaul */ 132445386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 132545386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 132645386Swpaul 132745386Swpaul /* Set up the standard receive ring. */ 132845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 132945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 133045386Swpaul rcb->ti_max_len = TI_FRAMELEN; 133145386Swpaul rcb->ti_flags = 0; 133258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 133358698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 133458698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 133545386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 133645386Swpaul 133745386Swpaul /* Set up the jumbo receive ring. */ 133845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 133945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 134045386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 134149036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 134245386Swpaul rcb->ti_flags = 0; 134358698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 134458698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 134558698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 134645386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 134745386Swpaul 134845386Swpaul /* 134945386Swpaul * Set up the mini ring. Only activated on the 135045386Swpaul * Tigon 2 but the slot in the config block is 135145386Swpaul * still there on the Tigon 1. 135245386Swpaul */ 135345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 135445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 135545386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 135651352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 135745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 135845386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 135945386Swpaul else 136045386Swpaul rcb->ti_flags = 0; 136158698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 136258698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 136358698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 136445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 136545386Swpaul 136645386Swpaul /* 136745386Swpaul * Set up the receive return ring. 136845386Swpaul */ 136945386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 137045386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 137145386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 137245386Swpaul rcb->ti_flags = 0; 137345386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 137445386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 137545386Swpaul vtophys(&sc->ti_return_prodidx); 137645386Swpaul 137745386Swpaul /* 137845386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 137945386Swpaul * of putting the transmit ring in the host's address space and 138045386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 138145386Swpaul * memory and accessing it through the shared memory region. We 138245386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 138345386Swpaul * so we have to revert to the shared memory scheme if we detect 138445386Swpaul * a Tigon 1 chip. 138545386Swpaul */ 138645386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 138745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 138845386Swpaul sc->ti_rdata->ti_tx_ring_nic = 138949133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 139045386Swpaul } 139145386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 139245386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 139345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 139445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 139545386Swpaul rcb->ti_flags = 0; 139645386Swpaul else 139745386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 139845386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 139958698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 140058698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 140158698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 140245386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 140345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 140445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 140545386Swpaul else 140645386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 140745386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 140845386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 140945386Swpaul vtophys(&sc->ti_tx_considx); 141045386Swpaul 141145386Swpaul /* Set up tuneables */ 141245386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 141345386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 141445386Swpaul (sc->ti_rx_coal_ticks / 10)); 141545386Swpaul else 141645386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 141745386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 141845386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 141945386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 142045386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 142145386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 142245386Swpaul 142345386Swpaul /* Turn interrupts on. */ 142445386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 142545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 142645386Swpaul 142745386Swpaul /* Start CPU. */ 142845386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 142945386Swpaul 143045386Swpaul return(0); 143145386Swpaul} 143245386Swpaul 143345386Swpaul/* 143445386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 143545386Swpaul * against our list and return its name if we find a match. 143645386Swpaul */ 143749011Swpaulstatic int ti_probe(dev) 143849011Swpaul device_t dev; 143945386Swpaul{ 144045386Swpaul struct ti_type *t; 144145386Swpaul 144245386Swpaul t = ti_devs; 144345386Swpaul 144445386Swpaul while(t->ti_name != NULL) { 144549011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 144649011Swpaul (pci_get_device(dev) == t->ti_did)) { 144749011Swpaul device_set_desc(dev, t->ti_name); 144849011Swpaul return(0); 144949011Swpaul } 145045386Swpaul t++; 145145386Swpaul } 145245386Swpaul 145349011Swpaul return(ENXIO); 145445386Swpaul} 145545386Swpaul 145649011Swpaulstatic int ti_attach(dev) 145749011Swpaul device_t dev; 145845386Swpaul{ 145945386Swpaul u_int32_t command; 146045386Swpaul struct ifnet *ifp; 146145386Swpaul struct ti_softc *sc; 146249011Swpaul int unit, error = 0, rid; 146345386Swpaul 146449011Swpaul sc = device_get_softc(dev); 146549011Swpaul unit = device_get_unit(dev); 146645386Swpaul bzero(sc, sizeof(struct ti_softc)); 146745386Swpaul 146871228Sbmilekic mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 146969583Swpaul TI_LOCK(sc); 147083630Sjlemon sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 147183630Sjlemon sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 147269583Swpaul 147345386Swpaul /* 147445386Swpaul * Map control/status registers. 147545386Swpaul */ 147672813Swpaul pci_enable_busmaster(dev); 147779472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 147861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 147945386Swpaul 148045386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 148145386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 148249011Swpaul error = ENXIO; 148345386Swpaul goto fail; 148445386Swpaul } 148545386Swpaul 148649011Swpaul rid = TI_PCI_LOMEM; 148749011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 148865176Sdfr 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 148949011Swpaul 149049011Swpaul if (sc->ti_res == NULL) { 149145386Swpaul printf ("ti%d: couldn't map memory\n", unit); 149249011Swpaul error = ENXIO; 149345386Swpaul goto fail; 149445386Swpaul } 149545386Swpaul 149649035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 149749035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 149849133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 149949035Swpaul 150049011Swpaul /* Allocate interrupt */ 150149011Swpaul rid = 0; 150249133Swpaul 150349011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 150449011Swpaul RF_SHAREABLE | RF_ACTIVE); 150545386Swpaul 150649011Swpaul if (sc->ti_irq == NULL) { 150749011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 150849011Swpaul error = ENXIO; 150945386Swpaul goto fail; 151045386Swpaul } 151145386Swpaul 151249011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 151349011Swpaul ti_intr, sc, &sc->ti_intrhand); 151449011Swpaul 151549011Swpaul if (error) { 151649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 151749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 151849011Swpaul TI_PCI_LOMEM, sc->ti_res); 151949011Swpaul printf("ti%d: couldn't set up irq\n", unit); 152045386Swpaul goto fail; 152145386Swpaul } 152245386Swpaul 152345386Swpaul sc->ti_unit = unit; 152445386Swpaul 152545386Swpaul if (ti_chipinit(sc)) { 152645386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 152749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 152849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 152949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 153049011Swpaul TI_PCI_LOMEM, sc->ti_res); 153149011Swpaul error = ENXIO; 153245386Swpaul goto fail; 153345386Swpaul } 153445386Swpaul 153545386Swpaul /* Zero out the NIC's on-board SRAM. */ 153645386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 153745386Swpaul 153845386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 153945386Swpaul if (ti_chipinit(sc)) { 154045386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 154149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 154249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 154349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 154449011Swpaul TI_PCI_LOMEM, sc->ti_res); 154549011Swpaul error = ENXIO; 154645386Swpaul goto fail; 154745386Swpaul } 154845386Swpaul 154945386Swpaul /* 155045386Swpaul * Get station address from the EEPROM. Note: the manual states 155145386Swpaul * that the MAC address is at offset 0x8c, however the data is 155245386Swpaul * stored as two longwords (since that's how it's loaded into 155372645Sasmodai * the NIC). This means the MAC address is actually preceded 155445386Swpaul * by two zero bytes. We need to skip over those. 155545386Swpaul */ 155645386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 155745386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 155845386Swpaul printf("ti%d: failed to read station address\n", unit); 155949011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 156049011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 156149011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 156249011Swpaul TI_PCI_LOMEM, sc->ti_res); 156349011Swpaul error = ENXIO; 156445386Swpaul goto fail; 156545386Swpaul } 156645386Swpaul 156745386Swpaul /* 156845386Swpaul * A Tigon chip was detected. Inform the world. 156945386Swpaul */ 157045386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 157145386Swpaul sc->arpcom.ac_enaddr, ":"); 157245386Swpaul 157345386Swpaul /* Allocate the general information block and ring buffers. */ 157449011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 157550548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 157645386Swpaul 157749011Swpaul if (sc->ti_rdata == NULL) { 157849011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 157949011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 158049011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 158149011Swpaul TI_PCI_LOMEM, sc->ti_res); 158249011Swpaul error = ENXIO; 158345386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 158445386Swpaul goto fail; 158545386Swpaul } 158645386Swpaul 158745386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 158845386Swpaul 158945386Swpaul /* Try to allocate memory for jumbo buffers. */ 159045386Swpaul if (ti_alloc_jumbo_mem(sc)) { 159145386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 159249011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 159349011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 159449011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 159549011Swpaul TI_PCI_LOMEM, sc->ti_res); 159662793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 159762793Sgallatin M_DEVBUF); 159849011Swpaul error = ENXIO; 159945386Swpaul goto fail; 160045386Swpaul } 160145386Swpaul 160263699Swpaul /* 160363699Swpaul * We really need a better way to tell a 1000baseTX card 160463699Swpaul * from a 1000baseSX one, since in theory there could be 160563699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 160663699Swpaul * clever enough to change the PCI ID. For the moment 160763699Swpaul * though, the AceNIC is the only copper card available. 160863699Swpaul */ 160963699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 161063699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 161163699Swpaul sc->ti_copper = 1; 161264139Swpaul /* Ok, it's not the only copper card available. */ 161364139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 161464139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 161564139Swpaul sc->ti_copper = 1; 161663699Swpaul 161745386Swpaul /* Set default tuneable values. */ 161845386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 161945386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 162045386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 162145386Swpaul sc->ti_rx_max_coal_bds = 64; 162245386Swpaul sc->ti_tx_max_coal_bds = 128; 162345386Swpaul sc->ti_tx_buf_ratio = 21; 162445386Swpaul 162545386Swpaul /* Set up ifnet structure */ 162645386Swpaul ifp = &sc->arpcom.ac_if; 162745386Swpaul ifp->if_softc = sc; 162845386Swpaul ifp->if_unit = sc->ti_unit; 162945386Swpaul ifp->if_name = "ti"; 163045386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 163145386Swpaul ifp->if_ioctl = ti_ioctl; 163245386Swpaul ifp->if_output = ether_output; 163345386Swpaul ifp->if_start = ti_start; 163445386Swpaul ifp->if_watchdog = ti_watchdog; 163545386Swpaul ifp->if_init = ti_init; 163645386Swpaul ifp->if_mtu = ETHERMTU; 163745386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 163845386Swpaul 163945386Swpaul /* Set up ifmedia support. */ 164045386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 164163699Swpaul if (sc->ti_copper) { 164263699Swpaul /* 164363699Swpaul * Copper cards allow manual 10/100 mode selection, 164463699Swpaul * but not manual 1000baseTX mode selection. Why? 164563699Swpaul * Becuase currently there's no way to specify the 164663699Swpaul * master/slave setting through the firmware interface, 164763699Swpaul * so Alteon decided to just bag it and handle it 164863699Swpaul * via autonegotiation. 164963699Swpaul */ 165063699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 165163699Swpaul ifmedia_add(&sc->ifmedia, 165263699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 165363699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 165463699Swpaul ifmedia_add(&sc->ifmedia, 165563699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 165663699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 165763699Swpaul ifmedia_add(&sc->ifmedia, 165863699Swpaul IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 165963699Swpaul } else { 166063699Swpaul /* Fiber cards don't support 10/100 modes. */ 166163699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 166263699Swpaul ifmedia_add(&sc->ifmedia, 166363699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 166463699Swpaul } 166545386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 166645386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 166745386Swpaul 166845386Swpaul /* 166963090Sarchie * Call MI attach routine. 167045386Swpaul */ 167163090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 167267087Swpaul TI_UNLOCK(sc); 167367087Swpaul return(0); 167445386Swpaul 167545386Swpaulfail: 167667087Swpaul TI_UNLOCK(sc); 167767087Swpaul mtx_destroy(&sc->ti_mtx); 167849011Swpaul return(error); 167945386Swpaul} 168045386Swpaul 168149011Swpaulstatic int ti_detach(dev) 168249011Swpaul device_t dev; 168349011Swpaul{ 168449011Swpaul struct ti_softc *sc; 168549011Swpaul struct ifnet *ifp; 168649011Swpaul 168749011Swpaul 168849011Swpaul sc = device_get_softc(dev); 168967087Swpaul TI_LOCK(sc); 169049011Swpaul ifp = &sc->arpcom.ac_if; 169149011Swpaul 169263090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 169349011Swpaul ti_stop(sc); 169449011Swpaul 169549011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 169649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 169749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 169849011Swpaul 169962793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 170062793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 170149011Swpaul ifmedia_removeall(&sc->ifmedia); 170249011Swpaul 170367087Swpaul TI_UNLOCK(sc); 170467087Swpaul mtx_destroy(&sc->ti_mtx); 170549011Swpaul 170649011Swpaul return(0); 170749011Swpaul} 170849011Swpaul 170945386Swpaul/* 171045386Swpaul * Frame reception handling. This is called if there's a frame 171145386Swpaul * on the receive return list. 171245386Swpaul * 171345386Swpaul * Note: we have to be able to handle three possibilities here: 171445386Swpaul * 1) the frame is from the mini receive ring (can only happen) 171545386Swpaul * on Tigon 2 boards) 171645386Swpaul * 2) the frame is from the jumbo recieve ring 171745386Swpaul * 3) the frame is from the standard receive ring 171845386Swpaul */ 171945386Swpaul 172045386Swpaulstatic void ti_rxeof(sc) 172145386Swpaul struct ti_softc *sc; 172245386Swpaul{ 172345386Swpaul struct ifnet *ifp; 172448597Swpaul struct ti_cmd_desc cmd; 172545386Swpaul 172645386Swpaul ifp = &sc->arpcom.ac_if; 172745386Swpaul 172845386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 172945386Swpaul struct ti_rx_desc *cur_rx; 173045386Swpaul u_int32_t rxidx; 173145386Swpaul struct ether_header *eh; 173245386Swpaul struct mbuf *m = NULL; 173345386Swpaul u_int16_t vlan_tag = 0; 173445386Swpaul int have_tag = 0; 173545386Swpaul 173645386Swpaul cur_rx = 173745386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 173845386Swpaul rxidx = cur_rx->ti_idx; 173945386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 174045386Swpaul 174145386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 174245386Swpaul have_tag = 1; 174377058Sphk vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 174445386Swpaul } 174545386Swpaul 174645386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 174745386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 174845386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 174945386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 175045386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 175145386Swpaul ifp->if_ierrors++; 175245386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 175345386Swpaul continue; 175445386Swpaul } 175548597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 175648597Swpaul ifp->if_ierrors++; 175748597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 175848597Swpaul continue; 175948597Swpaul } 176045386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 176145386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 176245386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 176345386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 176445386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 176545386Swpaul ifp->if_ierrors++; 176645386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 176745386Swpaul continue; 176845386Swpaul } 176948597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 177048597Swpaul ifp->if_ierrors++; 177148597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 177248597Swpaul continue; 177348597Swpaul } 177445386Swpaul } else { 177545386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 177645386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 177745386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 177845386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 177945386Swpaul ifp->if_ierrors++; 178045386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 178145386Swpaul continue; 178245386Swpaul } 178348597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 178448597Swpaul ifp->if_ierrors++; 178548597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 178648597Swpaul continue; 178748597Swpaul } 178845386Swpaul } 178945386Swpaul 179045386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 179145386Swpaul ifp->if_ipackets++; 179245386Swpaul eh = mtod(m, struct ether_header *); 179345386Swpaul m->m_pkthdr.rcvif = ifp; 179445386Swpaul 179545386Swpaul /* Remove header from mbuf and pass it on. */ 179645386Swpaul m_adj(m, sizeof(struct ether_header)); 179745386Swpaul 179858698Sjlemon if (ifp->if_hwassist) { 179958698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 180058698Sjlemon CSUM_DATA_VALID; 180158698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 180258698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 180358698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 180458698Sjlemon } 180545386Swpaul 180645386Swpaul /* 180745386Swpaul * If we received a packet with a vlan tag, pass it 180845386Swpaul * to vlan_input() instead of ether_input(). 180945386Swpaul */ 181045386Swpaul if (have_tag) { 181187276Sbrooks VLAN_INPUT_TAG(eh, m, vlan_tag); 181245386Swpaul have_tag = vlan_tag = 0; 181345386Swpaul continue; 181445386Swpaul } 181545386Swpaul ether_input(ifp, eh, m); 181645386Swpaul } 181745386Swpaul 181845386Swpaul /* Only necessary on the Tigon 1. */ 181945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 182045386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 182145386Swpaul sc->ti_rx_saved_considx); 182245386Swpaul 182348597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 182448597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 182548597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 182645386Swpaul 182745386Swpaul return; 182845386Swpaul} 182945386Swpaul 183045386Swpaulstatic void ti_txeof(sc) 183145386Swpaul struct ti_softc *sc; 183245386Swpaul{ 183345386Swpaul struct ti_tx_desc *cur_tx = NULL; 183445386Swpaul struct ifnet *ifp; 183545386Swpaul 183645386Swpaul ifp = &sc->arpcom.ac_if; 183745386Swpaul 183845386Swpaul /* 183945386Swpaul * Go through our tx ring and free mbufs for those 184045386Swpaul * frames that have been sent. 184145386Swpaul */ 184245386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 184345386Swpaul u_int32_t idx = 0; 184445386Swpaul 184545386Swpaul idx = sc->ti_tx_saved_considx; 184645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 184745386Swpaul if (idx > 383) 184845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 184945386Swpaul TI_TX_RING_BASE + 6144); 185045386Swpaul else if (idx > 255) 185145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 185245386Swpaul TI_TX_RING_BASE + 4096); 185345386Swpaul else if (idx > 127) 185445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 185545386Swpaul TI_TX_RING_BASE + 2048); 185645386Swpaul else 185745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 185845386Swpaul TI_TX_RING_BASE); 185945386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 186045386Swpaul } else 186145386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 186245386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 186345386Swpaul ifp->if_opackets++; 186445386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 186545386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 186645386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 186745386Swpaul } 186848011Swpaul sc->ti_txcnt--; 186945386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 187045386Swpaul ifp->if_timer = 0; 187145386Swpaul } 187245386Swpaul 187345386Swpaul if (cur_tx != NULL) 187445386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 187545386Swpaul 187645386Swpaul return; 187745386Swpaul} 187845386Swpaul 187945386Swpaulstatic void ti_intr(xsc) 188045386Swpaul void *xsc; 188145386Swpaul{ 188245386Swpaul struct ti_softc *sc; 188345386Swpaul struct ifnet *ifp; 188445386Swpaul 188545386Swpaul sc = xsc; 188667087Swpaul TI_LOCK(sc); 188745386Swpaul ifp = &sc->arpcom.ac_if; 188845386Swpaul 188945386Swpaul#ifdef notdef 189045386Swpaul /* Avoid this for now -- checking this register is expensive. */ 189145386Swpaul /* Make sure this is really our interrupt. */ 189267087Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 189367087Swpaul TI_UNLOCK(sc); 189445386Swpaul return; 189567087Swpaul } 189645386Swpaul#endif 189745386Swpaul 189845386Swpaul /* Ack interrupt and stop others from occuring. */ 189945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 190045386Swpaul 190145386Swpaul if (ifp->if_flags & IFF_RUNNING) { 190245386Swpaul /* Check RX return ring producer/consumer */ 190345386Swpaul ti_rxeof(sc); 190445386Swpaul 190545386Swpaul /* Check TX ring producer/consumer */ 190645386Swpaul ti_txeof(sc); 190745386Swpaul } 190845386Swpaul 190945386Swpaul ti_handle_events(sc); 191045386Swpaul 191145386Swpaul /* Re-enable interrupts. */ 191245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 191345386Swpaul 191445386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 191545386Swpaul ti_start(ifp); 191645386Swpaul 191767087Swpaul TI_UNLOCK(sc); 191867087Swpaul 191945386Swpaul return; 192045386Swpaul} 192145386Swpaul 192245386Swpaulstatic void ti_stats_update(sc) 192345386Swpaul struct ti_softc *sc; 192445386Swpaul{ 192545386Swpaul struct ifnet *ifp; 192645386Swpaul 192745386Swpaul ifp = &sc->arpcom.ac_if; 192845386Swpaul 192945386Swpaul ifp->if_collisions += 193045386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 193145386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 193245386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 193345386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 193445386Swpaul ifp->if_collisions; 193545386Swpaul 193645386Swpaul return; 193745386Swpaul} 193845386Swpaul 193945386Swpaul/* 194045386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 194145386Swpaul * pointers to descriptors. 194245386Swpaul */ 194345386Swpaulstatic int ti_encap(sc, m_head, txidx) 194445386Swpaul struct ti_softc *sc; 194545386Swpaul struct mbuf *m_head; 194645386Swpaul u_int32_t *txidx; 194745386Swpaul{ 194845386Swpaul struct ti_tx_desc *f = NULL; 194945386Swpaul struct mbuf *m; 195048011Swpaul u_int32_t frag, cur, cnt = 0; 195158698Sjlemon u_int16_t csum_flags = 0; 195245386Swpaul struct ifvlan *ifv = NULL; 195345386Swpaul 195445386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 195545386Swpaul m_head->m_pkthdr.rcvif != NULL && 195680307Sbrooks m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 195745386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 195845386Swpaul 195945386Swpaul m = m_head; 196045386Swpaul cur = frag = *txidx; 196145386Swpaul 196258698Sjlemon if (m_head->m_pkthdr.csum_flags) { 196358698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 196458698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 196558698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 196658698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 196758698Sjlemon if (m_head->m_flags & M_LASTFRAG) 196858698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 196958698Sjlemon else if (m_head->m_flags & M_FRAG) 197058698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 197158698Sjlemon } 197245386Swpaul /* 197345386Swpaul * Start packing the mbufs in this chain into 197445386Swpaul * the fragment pointers. Stop when we run out 197545386Swpaul * of fragments or hit the end of the mbuf chain. 197645386Swpaul */ 197745386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 197845386Swpaul if (m->m_len != 0) { 197945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 198045386Swpaul if (frag > 383) 198145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 198245386Swpaul TI_TX_RING_BASE + 6144); 198345386Swpaul else if (frag > 255) 198445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 198545386Swpaul TI_TX_RING_BASE + 4096); 198645386Swpaul else if (frag > 127) 198745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 198845386Swpaul TI_TX_RING_BASE + 2048); 198945386Swpaul else 199045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 199145386Swpaul TI_TX_RING_BASE); 199245386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 199345386Swpaul } else 199445386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 199545386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 199645386Swpaul break; 199745386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 199845386Swpaul f->ti_len = m->m_len; 199958698Sjlemon f->ti_flags = csum_flags; 200083115Sbrooks 200145386Swpaul if (ifv != NULL) { 200245386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 200377058Sphk f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 200445386Swpaul } else { 200545386Swpaul f->ti_vlan_tag = 0; 200645386Swpaul } 200783115Sbrooks 200848011Swpaul /* 200948011Swpaul * Sanity check: avoid coming within 16 descriptors 201048011Swpaul * of the end of the ring. 201148011Swpaul */ 201248011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 201348011Swpaul return(ENOBUFS); 201445386Swpaul cur = frag; 201545386Swpaul TI_INC(frag, TI_TX_RING_CNT); 201648011Swpaul cnt++; 201745386Swpaul } 201845386Swpaul } 201945386Swpaul 202045386Swpaul if (m != NULL) 202145386Swpaul return(ENOBUFS); 202245386Swpaul 202346177Swpaul if (frag == sc->ti_tx_saved_considx) 202446177Swpaul return(ENOBUFS); 202546177Swpaul 202645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 202745386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 202845386Swpaul TI_BDFLAG_END; 202945386Swpaul else 203045386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 203147458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 203248011Swpaul sc->ti_txcnt += cnt; 203345386Swpaul 203445386Swpaul *txidx = frag; 203545386Swpaul 203645386Swpaul return(0); 203745386Swpaul} 203845386Swpaul 203945386Swpaul/* 204045386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 204145386Swpaul * to the mbuf data regions directly in the transmit descriptors. 204245386Swpaul */ 204345386Swpaulstatic void ti_start(ifp) 204445386Swpaul struct ifnet *ifp; 204545386Swpaul{ 204645386Swpaul struct ti_softc *sc; 204745386Swpaul struct mbuf *m_head = NULL; 204845386Swpaul u_int32_t prodidx = 0; 204945386Swpaul 205045386Swpaul sc = ifp->if_softc; 205167087Swpaul TI_LOCK(sc); 205245386Swpaul 205345386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 205445386Swpaul 205545386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 205645386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 205745386Swpaul if (m_head == NULL) 205845386Swpaul break; 205945386Swpaul 206045386Swpaul /* 206158698Sjlemon * XXX 206258698Sjlemon * safety overkill. If this is a fragmented packet chain 206358698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 206458698Sjlemon * it if we have enough descriptors to handle the entire 206558698Sjlemon * chain at once. 206658698Sjlemon * (paranoia -- may not actually be needed) 206758698Sjlemon */ 206858698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 206958698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 207058698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 207158698Sjlemon m_head->m_pkthdr.csum_data + 16) { 207258698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 207358698Sjlemon ifp->if_flags |= IFF_OACTIVE; 207458698Sjlemon break; 207558698Sjlemon } 207658698Sjlemon } 207758698Sjlemon 207858698Sjlemon /* 207945386Swpaul * Pack the data into the transmit ring. If we 208045386Swpaul * don't have room, set the OACTIVE flag and wait 208145386Swpaul * for the NIC to drain the ring. 208245386Swpaul */ 208345386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 208445386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 208545386Swpaul ifp->if_flags |= IFF_OACTIVE; 208645386Swpaul break; 208745386Swpaul } 208845386Swpaul 208945386Swpaul /* 209045386Swpaul * If there's a BPF listener, bounce a copy of this frame 209145386Swpaul * to him. 209245386Swpaul */ 209345386Swpaul if (ifp->if_bpf) 209445386Swpaul bpf_mtap(ifp, m_head); 209545386Swpaul } 209645386Swpaul 209745386Swpaul /* Transmit */ 209845386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 209945386Swpaul 210045386Swpaul /* 210145386Swpaul * Set a timeout in case the chip goes out to lunch. 210245386Swpaul */ 210345386Swpaul ifp->if_timer = 5; 210467087Swpaul TI_UNLOCK(sc); 210545386Swpaul 210645386Swpaul return; 210745386Swpaul} 210845386Swpaul 210945386Swpaulstatic void ti_init(xsc) 211045386Swpaul void *xsc; 211145386Swpaul{ 211245386Swpaul struct ti_softc *sc = xsc; 211345386Swpaul 211445386Swpaul /* Cancel pending I/O and flush buffers. */ 211545386Swpaul ti_stop(sc); 211645386Swpaul 211767087Swpaul TI_LOCK(sc); 211845386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 211945386Swpaul if (ti_gibinit(sc)) { 212045386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 212167087Swpaul TI_UNLOCK(sc); 212245386Swpaul return; 212345386Swpaul } 212445386Swpaul 212567087Swpaul TI_UNLOCK(sc); 212645386Swpaul 212745386Swpaul return; 212845386Swpaul} 212945386Swpaul 213045386Swpaulstatic void ti_init2(sc) 213145386Swpaul struct ti_softc *sc; 213245386Swpaul{ 213345386Swpaul struct ti_cmd_desc cmd; 213445386Swpaul struct ifnet *ifp; 213545386Swpaul u_int16_t *m; 213645386Swpaul struct ifmedia *ifm; 213745386Swpaul int tmp; 213845386Swpaul 213945386Swpaul ifp = &sc->arpcom.ac_if; 214045386Swpaul 214145386Swpaul /* Specify MTU and interface index. */ 214245386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 214345386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 214445386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 214545386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 214645386Swpaul 214745386Swpaul /* Load our MAC address. */ 214845386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 214945386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 215045386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 215145386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 215245386Swpaul 215345386Swpaul /* Enable or disable promiscuous mode as needed. */ 215445386Swpaul if (ifp->if_flags & IFF_PROMISC) { 215545386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 215645386Swpaul } else { 215745386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 215845386Swpaul } 215945386Swpaul 216045386Swpaul /* Program multicast filter. */ 216145386Swpaul ti_setmulti(sc); 216245386Swpaul 216345386Swpaul /* 216445386Swpaul * If this is a Tigon 1, we should tell the 216545386Swpaul * firmware to use software packet filtering. 216645386Swpaul */ 216745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 216845386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 216945386Swpaul } 217045386Swpaul 217145386Swpaul /* Init RX ring. */ 217245386Swpaul ti_init_rx_ring_std(sc); 217345386Swpaul 217445386Swpaul /* Init jumbo RX ring. */ 217545386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 217645386Swpaul ti_init_rx_ring_jumbo(sc); 217745386Swpaul 217845386Swpaul /* 217945386Swpaul * If this is a Tigon 2, we can also configure the 218045386Swpaul * mini ring. 218145386Swpaul */ 218245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 218345386Swpaul ti_init_rx_ring_mini(sc); 218445386Swpaul 218545386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 218645386Swpaul sc->ti_rx_saved_considx = 0; 218745386Swpaul 218845386Swpaul /* Init TX ring. */ 218945386Swpaul ti_init_tx_ring(sc); 219045386Swpaul 219145386Swpaul /* Tell firmware we're alive. */ 219245386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 219345386Swpaul 219445386Swpaul /* Enable host interrupts. */ 219545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 219645386Swpaul 219745386Swpaul ifp->if_flags |= IFF_RUNNING; 219845386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 219945386Swpaul 220045386Swpaul /* 220145386Swpaul * Make sure to set media properly. We have to do this 220245386Swpaul * here since we have to issue commands in order to set 220345386Swpaul * the link negotiation and we can't issue commands until 220445386Swpaul * the firmware is running. 220545386Swpaul */ 220645386Swpaul ifm = &sc->ifmedia; 220745386Swpaul tmp = ifm->ifm_media; 220845386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 220945386Swpaul ti_ifmedia_upd(ifp); 221045386Swpaul ifm->ifm_media = tmp; 221145386Swpaul 221245386Swpaul return; 221345386Swpaul} 221445386Swpaul 221545386Swpaul/* 221645386Swpaul * Set media options. 221745386Swpaul */ 221845386Swpaulstatic int ti_ifmedia_upd(ifp) 221945386Swpaul struct ifnet *ifp; 222045386Swpaul{ 222145386Swpaul struct ti_softc *sc; 222245386Swpaul struct ifmedia *ifm; 222345386Swpaul struct ti_cmd_desc cmd; 222445386Swpaul 222545386Swpaul sc = ifp->if_softc; 222645386Swpaul ifm = &sc->ifmedia; 222745386Swpaul 222845386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 222945386Swpaul return(EINVAL); 223045386Swpaul 223145386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 223245386Swpaul case IFM_AUTO: 223345386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 223445386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 223545386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 223645386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 223745386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 223845386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 223945386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 224045386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 224145386Swpaul break; 224245386Swpaul case IFM_1000_SX: 224363699Swpaul case IFM_1000_TX: 224445386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 224563699Swpaul TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 224645386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 224763699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 224863699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 224963699Swpaul } 225045386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 225145386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 225245386Swpaul break; 225345386Swpaul case IFM_100_FX: 225445386Swpaul case IFM_10_FL: 225563699Swpaul case IFM_100_TX: 225663699Swpaul case IFM_10_T: 225745386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 225845386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 225963699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 226063699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 226145386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 226245386Swpaul } else { 226345386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 226445386Swpaul } 226545386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 226645386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 226745386Swpaul } else { 226845386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 226945386Swpaul } 227045386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 227145386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 227245386Swpaul break; 227345386Swpaul } 227445386Swpaul 227545386Swpaul return(0); 227645386Swpaul} 227745386Swpaul 227845386Swpaul/* 227945386Swpaul * Report current media status. 228045386Swpaul */ 228145386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 228245386Swpaul struct ifnet *ifp; 228345386Swpaul struct ifmediareq *ifmr; 228445386Swpaul{ 228545386Swpaul struct ti_softc *sc; 228663699Swpaul u_int32_t media = 0; 228745386Swpaul 228845386Swpaul sc = ifp->if_softc; 228945386Swpaul 229045386Swpaul ifmr->ifm_status = IFM_AVALID; 229145386Swpaul ifmr->ifm_active = IFM_ETHER; 229245386Swpaul 229345386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 229445386Swpaul return; 229545386Swpaul 229645386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 229745386Swpaul 229863699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 229963699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 230063699Swpaul if (sc->ti_copper) 230163699Swpaul ifmr->ifm_active |= IFM_1000_TX; 230263699Swpaul else 230363699Swpaul ifmr->ifm_active |= IFM_1000_SX; 230463699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 230563699Swpaul ifmr->ifm_active |= IFM_FDX; 230663699Swpaul else 230763699Swpaul ifmr->ifm_active |= IFM_HDX; 230863699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 230945386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 231063699Swpaul if (sc->ti_copper) { 231163699Swpaul if (media & TI_LNK_100MB) 231263699Swpaul ifmr->ifm_active |= IFM_100_TX; 231363699Swpaul if (media & TI_LNK_10MB) 231463699Swpaul ifmr->ifm_active |= IFM_10_T; 231563699Swpaul } else { 231663699Swpaul if (media & TI_LNK_100MB) 231763699Swpaul ifmr->ifm_active |= IFM_100_FX; 231863699Swpaul if (media & TI_LNK_10MB) 231963699Swpaul ifmr->ifm_active |= IFM_10_FL; 232063699Swpaul } 232145386Swpaul if (media & TI_LNK_FULL_DUPLEX) 232245386Swpaul ifmr->ifm_active |= IFM_FDX; 232345386Swpaul if (media & TI_LNK_HALF_DUPLEX) 232445386Swpaul ifmr->ifm_active |= IFM_HDX; 232545386Swpaul } 232645386Swpaul 232745386Swpaul return; 232845386Swpaul} 232945386Swpaul 233045386Swpaulstatic int ti_ioctl(ifp, command, data) 233145386Swpaul struct ifnet *ifp; 233245386Swpaul u_long command; 233345386Swpaul caddr_t data; 233445386Swpaul{ 233545386Swpaul struct ti_softc *sc = ifp->if_softc; 233645386Swpaul struct ifreq *ifr = (struct ifreq *) data; 233783630Sjlemon int mask, error = 0; 233845386Swpaul struct ti_cmd_desc cmd; 233945386Swpaul 234067087Swpaul TI_LOCK(sc); 234145386Swpaul 234245386Swpaul switch(command) { 234345386Swpaul case SIOCSIFADDR: 234445386Swpaul case SIOCGIFADDR: 234545386Swpaul error = ether_ioctl(ifp, command, data); 234645386Swpaul break; 234745386Swpaul case SIOCSIFMTU: 234845386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 234945386Swpaul error = EINVAL; 235045386Swpaul else { 235145386Swpaul ifp->if_mtu = ifr->ifr_mtu; 235245386Swpaul ti_init(sc); 235345386Swpaul } 235445386Swpaul break; 235545386Swpaul case SIOCSIFFLAGS: 235645386Swpaul if (ifp->if_flags & IFF_UP) { 235745386Swpaul /* 235845386Swpaul * If only the state of the PROMISC flag changed, 235945386Swpaul * then just use the 'set promisc mode' command 236045386Swpaul * instead of reinitializing the entire NIC. Doing 236145386Swpaul * a full re-init means reloading the firmware and 236245386Swpaul * waiting for it to start up, which may take a 236345386Swpaul * second or two. 236445386Swpaul */ 236545386Swpaul if (ifp->if_flags & IFF_RUNNING && 236645386Swpaul ifp->if_flags & IFF_PROMISC && 236745386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 236845386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 236945386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 237045386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 237145386Swpaul !(ifp->if_flags & IFF_PROMISC) && 237245386Swpaul sc->ti_if_flags & IFF_PROMISC) { 237345386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 237445386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 237545386Swpaul } else 237645386Swpaul ti_init(sc); 237745386Swpaul } else { 237845386Swpaul if (ifp->if_flags & IFF_RUNNING) { 237945386Swpaul ti_stop(sc); 238045386Swpaul } 238145386Swpaul } 238245386Swpaul sc->ti_if_flags = ifp->if_flags; 238345386Swpaul error = 0; 238445386Swpaul break; 238545386Swpaul case SIOCADDMULTI: 238645386Swpaul case SIOCDELMULTI: 238745386Swpaul if (ifp->if_flags & IFF_RUNNING) { 238845386Swpaul ti_setmulti(sc); 238945386Swpaul error = 0; 239045386Swpaul } 239145386Swpaul break; 239245386Swpaul case SIOCSIFMEDIA: 239345386Swpaul case SIOCGIFMEDIA: 239445386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 239545386Swpaul break; 239683630Sjlemon case SIOCSIFCAP: 239783630Sjlemon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 239883630Sjlemon if (mask & IFCAP_HWCSUM) { 239983630Sjlemon if (IFCAP_HWCSUM & ifp->if_capenable) 240083630Sjlemon ifp->if_capenable &= ~IFCAP_HWCSUM; 240183630Sjlemon else 240283630Sjlemon ifp->if_capenable |= IFCAP_HWCSUM; 240383630Sjlemon if (ifp->if_flags & IFF_RUNNING) 240483630Sjlemon ti_init(sc); 240583630Sjlemon } 240683630Sjlemon error = 0; 240783630Sjlemon break; 240845386Swpaul default: 240945386Swpaul error = EINVAL; 241045386Swpaul break; 241145386Swpaul } 241245386Swpaul 241367087Swpaul TI_UNLOCK(sc); 241445386Swpaul 241545386Swpaul return(error); 241645386Swpaul} 241745386Swpaul 241845386Swpaulstatic void ti_watchdog(ifp) 241945386Swpaul struct ifnet *ifp; 242045386Swpaul{ 242145386Swpaul struct ti_softc *sc; 242245386Swpaul 242345386Swpaul sc = ifp->if_softc; 242467087Swpaul TI_LOCK(sc); 242545386Swpaul 242645386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 242745386Swpaul ti_stop(sc); 242845386Swpaul ti_init(sc); 242945386Swpaul 243045386Swpaul ifp->if_oerrors++; 243167087Swpaul TI_UNLOCK(sc); 243245386Swpaul 243345386Swpaul return; 243445386Swpaul} 243545386Swpaul 243645386Swpaul/* 243745386Swpaul * Stop the adapter and free any mbufs allocated to the 243845386Swpaul * RX and TX lists. 243945386Swpaul */ 244045386Swpaulstatic void ti_stop(sc) 244145386Swpaul struct ti_softc *sc; 244245386Swpaul{ 244345386Swpaul struct ifnet *ifp; 244445386Swpaul struct ti_cmd_desc cmd; 244545386Swpaul 244667087Swpaul TI_LOCK(sc); 244767087Swpaul 244845386Swpaul ifp = &sc->arpcom.ac_if; 244945386Swpaul 245045386Swpaul /* Disable host interrupts. */ 245145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 245245386Swpaul /* 245345386Swpaul * Tell firmware we're shutting down. 245445386Swpaul */ 245545386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 245645386Swpaul 245745386Swpaul /* Halt and reinitialize. */ 245845386Swpaul ti_chipinit(sc); 245945386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 246045386Swpaul ti_chipinit(sc); 246145386Swpaul 246245386Swpaul /* Free the RX lists. */ 246345386Swpaul ti_free_rx_ring_std(sc); 246445386Swpaul 246545386Swpaul /* Free jumbo RX list. */ 246645386Swpaul ti_free_rx_ring_jumbo(sc); 246745386Swpaul 246845386Swpaul /* Free mini RX list. */ 246945386Swpaul ti_free_rx_ring_mini(sc); 247045386Swpaul 247145386Swpaul /* Free TX buffers. */ 247245386Swpaul ti_free_tx_ring(sc); 247345386Swpaul 247445386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 247545386Swpaul sc->ti_return_prodidx.ti_idx = 0; 247645386Swpaul sc->ti_tx_considx.ti_idx = 0; 247745386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 247845386Swpaul 247945386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 248067087Swpaul TI_UNLOCK(sc); 248145386Swpaul 248245386Swpaul return; 248345386Swpaul} 248445386Swpaul 248545386Swpaul/* 248645386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 248745386Swpaul * get confused by errant DMAs when rebooting. 248845386Swpaul */ 248949011Swpaulstatic void ti_shutdown(dev) 249049011Swpaul device_t dev; 249145386Swpaul{ 249245386Swpaul struct ti_softc *sc; 249345386Swpaul 249449011Swpaul sc = device_get_softc(dev); 249567087Swpaul TI_LOCK(sc); 249645386Swpaul ti_chipinit(sc); 249767087Swpaul TI_UNLOCK(sc); 249845386Swpaul 249945386Swpaul return; 250045386Swpaul} 2501