if_ti.c revision 71228
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 71228 2001-01-19 01:59:14Z bmilekic $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include "vlan.h" 8245386Swpaul 8345386Swpaul#include <sys/param.h> 8445386Swpaul#include <sys/systm.h> 8545386Swpaul#include <sys/sockio.h> 8645386Swpaul#include <sys/mbuf.h> 8745386Swpaul#include <sys/malloc.h> 8845386Swpaul#include <sys/kernel.h> 8945386Swpaul#include <sys/socket.h> 9045386Swpaul#include <sys/queue.h> 9145386Swpaul 9245386Swpaul#include <net/if.h> 9345386Swpaul#include <net/if_arp.h> 9445386Swpaul#include <net/ethernet.h> 9545386Swpaul#include <net/if_dl.h> 9645386Swpaul#include <net/if_media.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#if NVLAN > 0 10145386Swpaul#include <net/if_types.h> 10245386Swpaul#include <net/if_vlan_var.h> 10345386Swpaul#endif 10445386Swpaul 10545386Swpaul#include <netinet/in_systm.h> 10645386Swpaul#include <netinet/in.h> 10745386Swpaul#include <netinet/ip.h> 10845386Swpaul 10945386Swpaul#include <vm/vm.h> /* for vtophys */ 11045386Swpaul#include <vm/pmap.h> /* for vtophys */ 11145386Swpaul#include <machine/bus_memio.h> 11245386Swpaul#include <machine/bus.h> 11349011Swpaul#include <machine/resource.h> 11449011Swpaul#include <sys/bus.h> 11549011Swpaul#include <sys/rman.h> 11645386Swpaul 11745386Swpaul#include <pci/pcireg.h> 11845386Swpaul#include <pci/pcivar.h> 11945386Swpaul 12045386Swpaul#include <pci/if_tireg.h> 12145386Swpaul#include <pci/ti_fw.h> 12245386Swpaul#include <pci/ti_fw2.h> 12345386Swpaul 12458698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12545386Swpaul 12645386Swpaul#if !defined(lint) 12745386Swpaulstatic const char rcsid[] = 12850477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 71228 2001-01-19 01:59:14Z bmilekic $"; 12945386Swpaul#endif 13045386Swpaul 13145386Swpaul/* 13245386Swpaul * Various supported device vendors/types and their names. 13345386Swpaul */ 13445386Swpaul 13545386Swpaulstatic struct ti_type ti_devs[] = { 13645386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13763702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 13863699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 13963702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 14045386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 14145386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 14245386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 14364139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 14464139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 14564139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 14645386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14745386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14856206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 14956206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 15045386Swpaul { 0, 0, NULL } 15145386Swpaul}; 15245386Swpaul 15349011Swpaulstatic int ti_probe __P((device_t)); 15449011Swpaulstatic int ti_attach __P((device_t)); 15549011Swpaulstatic int ti_detach __P((device_t)); 15645386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15745386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15845386Swpaul 15945386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 16045386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 16145386Swpaul u_int32_t *)); 16245386Swpaul 16345386Swpaulstatic void ti_intr __P((void *)); 16445386Swpaulstatic void ti_start __P((struct ifnet *)); 16545386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16645386Swpaulstatic void ti_init __P((void *)); 16745386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16845386Swpaulstatic void ti_stop __P((struct ti_softc *)); 16945386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 17049011Swpaulstatic void ti_shutdown __P((device_t)); 17145386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 17245386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17345386Swpaul 17445386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17545386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17645386Swpaul int, u_int8_t *)); 17745386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17845386Swpaul 17945386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 18045386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 18145386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 18245386Swpaul 18345386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18445386Swpaul u_int32_t, caddr_t)); 18545386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18645386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18745386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18845386Swpaul caddr_t, int)); 18945386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 19045386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 19145386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 19264837Sdwmalonestatic void ti_jfree __P((caddr_t, void *)); 19345386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19445386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19545386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19645386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19745386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19845386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 19945386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 20045386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 20145386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20245386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 20345386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 20445386Swpaul 20545386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20645386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20745386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 20845386Swpaul 20949011Swpaulstatic device_method_t ti_methods[] = { 21049011Swpaul /* Device interface */ 21149011Swpaul DEVMETHOD(device_probe, ti_probe), 21249011Swpaul DEVMETHOD(device_attach, ti_attach), 21349011Swpaul DEVMETHOD(device_detach, ti_detach), 21449011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 21549011Swpaul { 0, 0 } 21649011Swpaul}; 21749011Swpaul 21849011Swpaulstatic driver_t ti_driver = { 21951455Swpaul "ti", 22049011Swpaul ti_methods, 22149011Swpaul sizeof(struct ti_softc) 22249011Swpaul}; 22349011Swpaul 22449011Swpaulstatic devclass_t ti_devclass; 22549011Swpaul 22651533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22749011Swpaul 22845386Swpaul/* 22945386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 23045386Swpaul */ 23145386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 23245386Swpaul struct ti_softc *sc; 23345386Swpaul int byte; 23445386Swpaul{ 23545386Swpaul register int i, ack = 0; 23645386Swpaul 23745386Swpaul /* 23845386Swpaul * Make sure we're in TX mode. 23945386Swpaul */ 24045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 24145386Swpaul 24245386Swpaul /* 24345386Swpaul * Feed in each bit and stobe the clock. 24445386Swpaul */ 24545386Swpaul for (i = 0x80; i; i >>= 1) { 24645386Swpaul if (byte & i) { 24745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24845386Swpaul } else { 24945386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 25045386Swpaul } 25145386Swpaul DELAY(1); 25245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25345386Swpaul DELAY(1); 25445386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25545386Swpaul } 25645386Swpaul 25745386Swpaul /* 25845386Swpaul * Turn off TX mode. 25945386Swpaul */ 26045386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 26145386Swpaul 26245386Swpaul /* 26345386Swpaul * Check for ack. 26445386Swpaul */ 26545386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26645386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26845386Swpaul 26945386Swpaul return(ack); 27045386Swpaul} 27145386Swpaul 27245386Swpaul/* 27345386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 27445386Swpaul * We have to send two address bytes since the EEPROM can hold 27545386Swpaul * more than 256 bytes of data. 27645386Swpaul */ 27745386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 27845386Swpaul struct ti_softc *sc; 27945386Swpaul int addr; 28045386Swpaul u_int8_t *dest; 28145386Swpaul{ 28245386Swpaul register int i; 28345386Swpaul u_int8_t byte = 0; 28445386Swpaul 28545386Swpaul EEPROM_START; 28645386Swpaul 28745386Swpaul /* 28845386Swpaul * Send write control code to EEPROM. 28945386Swpaul */ 29045386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 29145386Swpaul printf("ti%d: failed to send write command, status: %x\n", 29245386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29345386Swpaul return(1); 29445386Swpaul } 29545386Swpaul 29645386Swpaul /* 29745386Swpaul * Send first byte of address of byte we want to read. 29845386Swpaul */ 29945386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 30045386Swpaul printf("ti%d: failed to send address, status: %x\n", 30145386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30245386Swpaul return(1); 30345386Swpaul } 30445386Swpaul /* 30545386Swpaul * Send second byte address of byte we want to read. 30645386Swpaul */ 30745386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 30845386Swpaul printf("ti%d: failed to send address, status: %x\n", 30945386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31045386Swpaul return(1); 31145386Swpaul } 31245386Swpaul 31345386Swpaul EEPROM_STOP; 31445386Swpaul EEPROM_START; 31545386Swpaul /* 31645386Swpaul * Send read control code to EEPROM. 31745386Swpaul */ 31845386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 31945386Swpaul printf("ti%d: failed to send read command, status: %x\n", 32045386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 32145386Swpaul return(1); 32245386Swpaul } 32345386Swpaul 32445386Swpaul /* 32545386Swpaul * Start reading bits from EEPROM. 32645386Swpaul */ 32745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 32845386Swpaul for (i = 0x80; i; i >>= 1) { 32945386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33045386Swpaul DELAY(1); 33145386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 33245386Swpaul byte |= i; 33345386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33445386Swpaul DELAY(1); 33545386Swpaul } 33645386Swpaul 33745386Swpaul EEPROM_STOP; 33845386Swpaul 33945386Swpaul /* 34045386Swpaul * No ACK generated for read, so just return byte. 34145386Swpaul */ 34245386Swpaul 34345386Swpaul *dest = byte; 34445386Swpaul 34545386Swpaul return(0); 34645386Swpaul} 34745386Swpaul 34845386Swpaul/* 34945386Swpaul * Read a sequence of bytes from the EEPROM. 35045386Swpaul */ 35145386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 35245386Swpaul struct ti_softc *sc; 35345386Swpaul caddr_t dest; 35445386Swpaul int off; 35545386Swpaul int cnt; 35645386Swpaul{ 35745386Swpaul int err = 0, i; 35845386Swpaul u_int8_t byte = 0; 35945386Swpaul 36045386Swpaul for (i = 0; i < cnt; i++) { 36145386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 36245386Swpaul if (err) 36345386Swpaul break; 36445386Swpaul *(dest + i) = byte; 36545386Swpaul } 36645386Swpaul 36745386Swpaul return(err ? 1 : 0); 36845386Swpaul} 36945386Swpaul 37045386Swpaul/* 37145386Swpaul * NIC memory access function. Can be used to either clear a section 37245386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 37345386Swpaul */ 37445386Swpaulstatic void ti_mem(sc, addr, len, buf) 37545386Swpaul struct ti_softc *sc; 37645386Swpaul u_int32_t addr, len; 37745386Swpaul caddr_t buf; 37845386Swpaul{ 37945386Swpaul int segptr, segsize, cnt; 38045386Swpaul caddr_t ti_winbase, ptr; 38145386Swpaul 38245386Swpaul segptr = addr; 38345386Swpaul cnt = len; 38449133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 38545386Swpaul ptr = buf; 38645386Swpaul 38745386Swpaul while(cnt) { 38845386Swpaul if (cnt < TI_WINLEN) 38945386Swpaul segsize = cnt; 39045386Swpaul else 39145386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 39245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 39345386Swpaul if (buf == NULL) 39445386Swpaul bzero((char *)ti_winbase + (segptr & 39545386Swpaul (TI_WINLEN - 1)), segsize); 39645386Swpaul else { 39745386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 39845386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 39945386Swpaul ptr += segsize; 40045386Swpaul } 40145386Swpaul segptr += segsize; 40245386Swpaul cnt -= segsize; 40345386Swpaul } 40445386Swpaul 40545386Swpaul return; 40645386Swpaul} 40745386Swpaul 40845386Swpaul/* 40945386Swpaul * Load firmware image into the NIC. Check that the firmware revision 41045386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 41145386Swpaul * Tigon 2. 41245386Swpaul */ 41345386Swpaulstatic void ti_loadfw(sc) 41445386Swpaul struct ti_softc *sc; 41545386Swpaul{ 41645386Swpaul switch(sc->ti_hwrev) { 41745386Swpaul case TI_HWREV_TIGON: 41845386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 41945386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 42045386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 42145386Swpaul printf("ti%d: firmware revision mismatch; want " 42245386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 42345386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 42445386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 42545386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 42645386Swpaul return; 42745386Swpaul } 42845386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 42945386Swpaul (caddr_t)tigonFwText); 43045386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 43145386Swpaul (caddr_t)tigonFwData); 43245386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 43345386Swpaul (caddr_t)tigonFwRodata); 43445386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 43545386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 43645386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43745386Swpaul break; 43845386Swpaul case TI_HWREV_TIGON_II: 43945386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 44045386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 44145386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 44245386Swpaul printf("ti%d: firmware revision mismatch; want " 44345386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 44445386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 44545386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 44645386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44745386Swpaul return; 44845386Swpaul } 44945386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 45045386Swpaul (caddr_t)tigon2FwText); 45145386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 45245386Swpaul (caddr_t)tigon2FwData); 45345386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 45445386Swpaul (caddr_t)tigon2FwRodata); 45545386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 45645386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45745386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 45845386Swpaul break; 45945386Swpaul default: 46045386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 46145386Swpaul sc->ti_unit); 46245386Swpaul break; 46345386Swpaul } 46445386Swpaul 46545386Swpaul return; 46645386Swpaul} 46745386Swpaul 46845386Swpaul/* 46945386Swpaul * Send the NIC a command via the command ring. 47045386Swpaul */ 47145386Swpaulstatic void ti_cmd(sc, cmd) 47245386Swpaul struct ti_softc *sc; 47345386Swpaul struct ti_cmd_desc *cmd; 47445386Swpaul{ 47545386Swpaul u_int32_t index; 47645386Swpaul 47745386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 47845386Swpaul return; 47945386Swpaul 48045386Swpaul index = sc->ti_cmd_saved_prodidx; 48145386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 48245386Swpaul TI_INC(index, TI_CMD_RING_CNT); 48345386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 48445386Swpaul sc->ti_cmd_saved_prodidx = index; 48545386Swpaul 48645386Swpaul return; 48745386Swpaul} 48845386Swpaul 48945386Swpaul/* 49045386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 49145386Swpaul * number of command slots to include after the initial command. 49245386Swpaul */ 49345386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 49445386Swpaul struct ti_softc *sc; 49545386Swpaul struct ti_cmd_desc *cmd; 49645386Swpaul caddr_t arg; 49745386Swpaul int len; 49845386Swpaul{ 49945386Swpaul u_int32_t index; 50045386Swpaul register int i; 50145386Swpaul 50245386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 50345386Swpaul return; 50445386Swpaul 50545386Swpaul index = sc->ti_cmd_saved_prodidx; 50645386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50745386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50845386Swpaul for (i = 0; i < len; i++) { 50945386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 51045386Swpaul *(u_int32_t *)(&arg[i * 4])); 51145386Swpaul TI_INC(index, TI_CMD_RING_CNT); 51245386Swpaul } 51345386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 51445386Swpaul sc->ti_cmd_saved_prodidx = index; 51545386Swpaul 51645386Swpaul return; 51745386Swpaul} 51845386Swpaul 51945386Swpaul/* 52045386Swpaul * Handle events that have triggered interrupts. 52145386Swpaul */ 52245386Swpaulstatic void ti_handle_events(sc) 52345386Swpaul struct ti_softc *sc; 52445386Swpaul{ 52545386Swpaul struct ti_event_desc *e; 52645386Swpaul 52745386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 52845386Swpaul return; 52945386Swpaul 53045386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 53145386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 53245386Swpaul switch(e->ti_event) { 53345386Swpaul case TI_EV_LINKSTAT_CHANGED: 53445386Swpaul sc->ti_linkstat = e->ti_code; 53545386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 53645386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53745386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 53845386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 53945386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 54045386Swpaul printf("ti%d: link down\n", sc->ti_unit); 54145386Swpaul break; 54245386Swpaul case TI_EV_ERROR: 54345386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 54445386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 54545386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 54645386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54745386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 54845386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 54945386Swpaul break; 55045386Swpaul case TI_EV_FIRMWARE_UP: 55145386Swpaul ti_init2(sc); 55245386Swpaul break; 55345386Swpaul case TI_EV_STATS_UPDATED: 55445386Swpaul ti_stats_update(sc); 55545386Swpaul break; 55645386Swpaul case TI_EV_RESET_JUMBO_RING: 55745386Swpaul case TI_EV_MCAST_UPDATED: 55845386Swpaul /* Who cares. */ 55945386Swpaul break; 56045386Swpaul default: 56145386Swpaul printf("ti%d: unknown event: %d\n", 56245386Swpaul sc->ti_unit, e->ti_event); 56345386Swpaul break; 56445386Swpaul } 56545386Swpaul /* Advance the consumer index. */ 56645386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56745386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 56845386Swpaul } 56945386Swpaul 57045386Swpaul return; 57145386Swpaul} 57245386Swpaul 57345386Swpaul/* 57445386Swpaul * Memory management for the jumbo receive ring is a pain in the 57545386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 57645386Swpaul * _and_ it has to be contiguous (unless you use the extended 57745386Swpaul * jumbo descriptor format). Using malloc() all the time won't 57845386Swpaul * work: malloc() allocates memory in powers of two, which means we 57945386Swpaul * would end up wasting a considerable amount of space by allocating 58045386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 58145386Swpaul * to do our own memory management. 58245386Swpaul * 58345386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 58445386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 58545386Swpaul * as external mbuf storage. 58645386Swpaul * 58745386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 58845386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 58945386Swpaul * RAM. This is a bit much, especially considering we also need 59045386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 59145386Swpaul * save space, we only actually allocate enough memory for 64 slots 59245386Swpaul * by default, which works out to between 500 and 600K. This can 59345386Swpaul * be tuned by changing a #define in if_tireg.h. 59445386Swpaul */ 59545386Swpaul 59645386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59745386Swpaul struct ti_softc *sc; 59845386Swpaul{ 59945386Swpaul caddr_t ptr; 60045386Swpaul register int i; 60145386Swpaul struct ti_jpool_entry *entry; 60245386Swpaul 60345386Swpaul /* Grab a big chunk o' storage. */ 60445386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 60550548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 60645386Swpaul 60745386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 60845386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 60945386Swpaul return(ENOBUFS); 61045386Swpaul } 61145386Swpaul 61245386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 61345386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 61445386Swpaul 61545386Swpaul /* 61645386Swpaul * Now divide it up into 9K pieces and save the addresses 61767405Sbmilekic * in an array. 61845386Swpaul */ 61945386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 62045386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 62167405Sbmilekic sc->ti_cdata.ti_jslots[i] = ptr; 62267405Sbmilekic ptr += TI_JLEN; 62345386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 62445386Swpaul M_DEVBUF, M_NOWAIT); 62545386Swpaul if (entry == NULL) { 62662793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 62762793Sgallatin M_DEVBUF); 62845386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 62945386Swpaul printf("ti%d: no memory for jumbo " 63045386Swpaul "buffer queue!\n", sc->ti_unit); 63145386Swpaul return(ENOBUFS); 63245386Swpaul } 63345386Swpaul entry->slot = i; 63445386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 63545386Swpaul } 63645386Swpaul 63745386Swpaul return(0); 63845386Swpaul} 63945386Swpaul 64045386Swpaul/* 64145386Swpaul * Allocate a jumbo buffer. 64245386Swpaul */ 64345386Swpaulstatic void *ti_jalloc(sc) 64445386Swpaul struct ti_softc *sc; 64545386Swpaul{ 64645386Swpaul struct ti_jpool_entry *entry; 64745386Swpaul 64845386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 64945386Swpaul 65045386Swpaul if (entry == NULL) { 65145386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 65245386Swpaul return(NULL); 65345386Swpaul } 65445386Swpaul 65545386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 65645386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 65767405Sbmilekic return(sc->ti_cdata.ti_jslots[entry->slot]); 65845386Swpaul} 65945386Swpaul 66045386Swpaul/* 66145386Swpaul * Release a jumbo buffer. 66245386Swpaul */ 66364837Sdwmalonestatic void ti_jfree(buf, args) 66445386Swpaul caddr_t buf; 66564837Sdwmalone void *args; 66645386Swpaul{ 66745386Swpaul struct ti_softc *sc; 66845386Swpaul int i; 66945386Swpaul struct ti_jpool_entry *entry; 67045386Swpaul 67145386Swpaul /* Extract the softc struct pointer. */ 67267405Sbmilekic sc = (struct ti_softc *)args; 67345386Swpaul 67445386Swpaul if (sc == NULL) 67567405Sbmilekic panic("ti_jfree: didn't get softc pointer!"); 67645386Swpaul 67745386Swpaul /* calculate the slot this buffer belongs to */ 67867405Sbmilekic i = ((vm_offset_t)buf 67945386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 68045386Swpaul 68145386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 68245386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 68345386Swpaul 68464837Sdwmalone entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 68564837Sdwmalone if (entry == NULL) 68664837Sdwmalone panic("ti_jfree: buffer not in use!"); 68764837Sdwmalone entry->slot = i; 68864837Sdwmalone SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 68964837Sdwmalone SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 69064837Sdwmalone 69145386Swpaul return; 69245386Swpaul} 69345386Swpaul 69445386Swpaul 69545386Swpaul/* 69645386Swpaul * Intialize a standard receive ring descriptor. 69745386Swpaul */ 69845386Swpaulstatic int ti_newbuf_std(sc, i, m) 69945386Swpaul struct ti_softc *sc; 70045386Swpaul int i; 70145386Swpaul struct mbuf *m; 70245386Swpaul{ 70345386Swpaul struct mbuf *m_new = NULL; 70445386Swpaul struct ti_rx_desc *r; 70545386Swpaul 70649036Swpaul if (m == NULL) { 70745386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 70845386Swpaul if (m_new == NULL) { 70945386Swpaul printf("ti%d: mbuf allocation failed " 71045386Swpaul "-- packet dropped!\n", sc->ti_unit); 71145386Swpaul return(ENOBUFS); 71245386Swpaul } 71345386Swpaul 71445386Swpaul MCLGET(m_new, M_DONTWAIT); 71545386Swpaul if (!(m_new->m_flags & M_EXT)) { 71645386Swpaul printf("ti%d: cluster allocation failed " 71745386Swpaul "-- packet dropped!\n", sc->ti_unit); 71845386Swpaul m_freem(m_new); 71945386Swpaul return(ENOBUFS); 72045386Swpaul } 72149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 72249036Swpaul } else { 72349036Swpaul m_new = m; 72449036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 72549036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 72645386Swpaul } 72745386Swpaul 72848597Swpaul m_adj(m_new, ETHER_ALIGN); 72945386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 73045386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 73145386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 73245386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 73345386Swpaul r->ti_flags = 0; 73458698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 73558698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 73649036Swpaul r->ti_len = m_new->m_len; 73745386Swpaul r->ti_idx = i; 73845386Swpaul 73945386Swpaul return(0); 74045386Swpaul} 74145386Swpaul 74245386Swpaul/* 74345386Swpaul * Intialize a mini receive ring descriptor. This only applies to 74445386Swpaul * the Tigon 2. 74545386Swpaul */ 74645386Swpaulstatic int ti_newbuf_mini(sc, i, m) 74745386Swpaul struct ti_softc *sc; 74845386Swpaul int i; 74945386Swpaul struct mbuf *m; 75045386Swpaul{ 75145386Swpaul struct mbuf *m_new = NULL; 75245386Swpaul struct ti_rx_desc *r; 75345386Swpaul 75449036Swpaul if (m == NULL) { 75545386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 75645386Swpaul if (m_new == NULL) { 75745386Swpaul printf("ti%d: mbuf allocation failed " 75845386Swpaul "-- packet dropped!\n", sc->ti_unit); 75945386Swpaul return(ENOBUFS); 76045386Swpaul } 76149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 76249036Swpaul } else { 76349036Swpaul m_new = m; 76449036Swpaul m_new->m_data = m_new->m_pktdat; 76549036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 76645386Swpaul } 76749036Swpaul 76848597Swpaul m_adj(m_new, ETHER_ALIGN); 76945386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 77045386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 77145386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 77245386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 77345386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 77458698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 77558698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 77649036Swpaul r->ti_len = m_new->m_len; 77745386Swpaul r->ti_idx = i; 77845386Swpaul 77945386Swpaul return(0); 78045386Swpaul} 78145386Swpaul 78245386Swpaul/* 78345386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 78445386Swpaul * a jumbo buffer from the pool managed internally by the driver. 78545386Swpaul */ 78645386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 78745386Swpaul struct ti_softc *sc; 78845386Swpaul int i; 78945386Swpaul struct mbuf *m; 79045386Swpaul{ 79145386Swpaul struct mbuf *m_new = NULL; 79245386Swpaul struct ti_rx_desc *r; 79345386Swpaul 79449036Swpaul if (m == NULL) { 79545386Swpaul caddr_t *buf = NULL; 79645386Swpaul 79745386Swpaul /* Allocate the mbuf. */ 79845386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 79945386Swpaul if (m_new == NULL) { 80045386Swpaul printf("ti%d: mbuf allocation failed " 80145386Swpaul "-- packet dropped!\n", sc->ti_unit); 80245386Swpaul return(ENOBUFS); 80345386Swpaul } 80445386Swpaul 80545386Swpaul /* Allocate the jumbo buffer */ 80645386Swpaul buf = ti_jalloc(sc); 80745386Swpaul if (buf == NULL) { 80845386Swpaul m_freem(m_new); 80945386Swpaul printf("ti%d: jumbo allocation failed " 81045386Swpaul "-- packet dropped!\n", sc->ti_unit); 81145386Swpaul return(ENOBUFS); 81245386Swpaul } 81345386Swpaul 81445386Swpaul /* Attach the buffer to the mbuf. */ 81564837Sdwmalone m_new->m_data = (void *) buf; 81664837Sdwmalone m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 81767405Sbmilekic MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 81868621Sbmilekic (struct ti_softc *)sc, 0, EXT_NET_DRV); 81949036Swpaul } else { 82049036Swpaul m_new = m; 82149036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 82249036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 82345386Swpaul } 82445386Swpaul 82549780Swpaul m_adj(m_new, ETHER_ALIGN); 82645386Swpaul /* Set up the descriptor. */ 82745386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 82845386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 82945386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 83045386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 83145386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 83258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 83358698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 83449036Swpaul r->ti_len = m_new->m_len; 83545386Swpaul r->ti_idx = i; 83645386Swpaul 83745386Swpaul return(0); 83845386Swpaul} 83945386Swpaul 84045386Swpaul/* 84145386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 84245386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 84345386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 84445386Swpaul * the NIC. 84545386Swpaul */ 84645386Swpaulstatic int ti_init_rx_ring_std(sc) 84745386Swpaul struct ti_softc *sc; 84845386Swpaul{ 84945386Swpaul register int i; 85045386Swpaul struct ti_cmd_desc cmd; 85145386Swpaul 85245386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 85345386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 85445386Swpaul return(ENOBUFS); 85545386Swpaul }; 85645386Swpaul 85745386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 85848597Swpaul sc->ti_std = i - 1; 85945386Swpaul 86045386Swpaul return(0); 86145386Swpaul} 86245386Swpaul 86345386Swpaulstatic void ti_free_rx_ring_std(sc) 86445386Swpaul struct ti_softc *sc; 86545386Swpaul{ 86645386Swpaul register int i; 86745386Swpaul 86845386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 86945386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 87045386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 87145386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 87245386Swpaul } 87345386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 87445386Swpaul sizeof(struct ti_rx_desc)); 87545386Swpaul } 87645386Swpaul 87745386Swpaul return; 87845386Swpaul} 87945386Swpaul 88045386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 88145386Swpaul struct ti_softc *sc; 88245386Swpaul{ 88345386Swpaul register int i; 88445386Swpaul struct ti_cmd_desc cmd; 88545386Swpaul 88663699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 88745386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 88845386Swpaul return(ENOBUFS); 88945386Swpaul }; 89045386Swpaul 89145386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 89248597Swpaul sc->ti_jumbo = i - 1; 89345386Swpaul 89445386Swpaul return(0); 89545386Swpaul} 89645386Swpaul 89745386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 89845386Swpaul struct ti_softc *sc; 89945386Swpaul{ 90045386Swpaul register int i; 90145386Swpaul 90245386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 90345386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 90445386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 90545386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 90645386Swpaul } 90745386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 90845386Swpaul sizeof(struct ti_rx_desc)); 90945386Swpaul } 91045386Swpaul 91145386Swpaul return; 91245386Swpaul} 91345386Swpaul 91445386Swpaulstatic int ti_init_rx_ring_mini(sc) 91545386Swpaul struct ti_softc *sc; 91645386Swpaul{ 91745386Swpaul register int i; 91845386Swpaul 91945386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 92045386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 92145386Swpaul return(ENOBUFS); 92245386Swpaul }; 92345386Swpaul 92445386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 92548597Swpaul sc->ti_mini = i - 1; 92645386Swpaul 92745386Swpaul return(0); 92845386Swpaul} 92945386Swpaul 93045386Swpaulstatic void ti_free_rx_ring_mini(sc) 93145386Swpaul struct ti_softc *sc; 93245386Swpaul{ 93345386Swpaul register int i; 93445386Swpaul 93545386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 93645386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 93745386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 93845386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 93945386Swpaul } 94045386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 94145386Swpaul sizeof(struct ti_rx_desc)); 94245386Swpaul } 94345386Swpaul 94445386Swpaul return; 94545386Swpaul} 94645386Swpaul 94745386Swpaulstatic void ti_free_tx_ring(sc) 94845386Swpaul struct ti_softc *sc; 94945386Swpaul{ 95045386Swpaul register int i; 95145386Swpaul 95245386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 95345386Swpaul return; 95445386Swpaul 95545386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 95645386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 95745386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 95845386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 95945386Swpaul } 96045386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 96145386Swpaul sizeof(struct ti_tx_desc)); 96245386Swpaul } 96345386Swpaul 96445386Swpaul return; 96545386Swpaul} 96645386Swpaul 96745386Swpaulstatic int ti_init_tx_ring(sc) 96845386Swpaul struct ti_softc *sc; 96945386Swpaul{ 97048011Swpaul sc->ti_txcnt = 0; 97145386Swpaul sc->ti_tx_saved_considx = 0; 97245386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 97345386Swpaul return(0); 97445386Swpaul} 97545386Swpaul 97645386Swpaul/* 97745386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 97845386Swpaul * but we have to support the old way too so that Tigon 1 cards will 97945386Swpaul * work. 98045386Swpaul */ 98145386Swpaulvoid ti_add_mcast(sc, addr) 98245386Swpaul struct ti_softc *sc; 98345386Swpaul struct ether_addr *addr; 98445386Swpaul{ 98545386Swpaul struct ti_cmd_desc cmd; 98645386Swpaul u_int16_t *m; 98745386Swpaul u_int32_t ext[2] = {0, 0}; 98845386Swpaul 98945386Swpaul m = (u_int16_t *)&addr->octet[0]; 99045386Swpaul 99145386Swpaul switch(sc->ti_hwrev) { 99245386Swpaul case TI_HWREV_TIGON: 99345386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 99445386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 99545386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 99645386Swpaul break; 99745386Swpaul case TI_HWREV_TIGON_II: 99845386Swpaul ext[0] = htons(m[0]); 99945386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 100045386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 100145386Swpaul break; 100245386Swpaul default: 100345386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 100445386Swpaul break; 100545386Swpaul } 100645386Swpaul 100745386Swpaul return; 100845386Swpaul} 100945386Swpaul 101045386Swpaulvoid ti_del_mcast(sc, addr) 101145386Swpaul struct ti_softc *sc; 101245386Swpaul struct ether_addr *addr; 101345386Swpaul{ 101445386Swpaul struct ti_cmd_desc cmd; 101545386Swpaul u_int16_t *m; 101645386Swpaul u_int32_t ext[2] = {0, 0}; 101745386Swpaul 101845386Swpaul m = (u_int16_t *)&addr->octet[0]; 101945386Swpaul 102045386Swpaul switch(sc->ti_hwrev) { 102145386Swpaul case TI_HWREV_TIGON: 102245386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 102345386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 102445386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 102545386Swpaul break; 102645386Swpaul case TI_HWREV_TIGON_II: 102745386Swpaul ext[0] = htons(m[0]); 102845386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 102945386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 103045386Swpaul break; 103145386Swpaul default: 103245386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 103345386Swpaul break; 103445386Swpaul } 103545386Swpaul 103645386Swpaul return; 103745386Swpaul} 103845386Swpaul 103945386Swpaul/* 104045386Swpaul * Configure the Tigon's multicast address filter. 104145386Swpaul * 104245386Swpaul * The actual multicast table management is a bit of a pain, thanks to 104345386Swpaul * slight brain damage on the part of both Alteon and us. With our 104445386Swpaul * multicast code, we are only alerted when the multicast address table 104545386Swpaul * changes and at that point we only have the current list of addresses: 104645386Swpaul * we only know the current state, not the previous state, so we don't 104745386Swpaul * actually know what addresses were removed or added. The firmware has 104845386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 104945386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 105045386Swpaul * state so we know what addresses have been programmed into the NIC at 105145386Swpaul * any given time. 105245386Swpaul */ 105345386Swpaulstatic void ti_setmulti(sc) 105445386Swpaul struct ti_softc *sc; 105545386Swpaul{ 105645386Swpaul struct ifnet *ifp; 105745386Swpaul struct ifmultiaddr *ifma; 105845386Swpaul struct ti_cmd_desc cmd; 105945386Swpaul struct ti_mc_entry *mc; 106045386Swpaul u_int32_t intrs; 106145386Swpaul 106245386Swpaul ifp = &sc->arpcom.ac_if; 106345386Swpaul 106445386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 106545386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 106645386Swpaul return; 106745386Swpaul } else { 106845386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 106945386Swpaul } 107045386Swpaul 107145386Swpaul /* Disable interrupts. */ 107245386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 107345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 107445386Swpaul 107545386Swpaul /* First, zot all the existing filters. */ 107645386Swpaul while (sc->ti_mc_listhead.slh_first != NULL) { 107745386Swpaul mc = sc->ti_mc_listhead.slh_first; 107845386Swpaul ti_del_mcast(sc, &mc->mc_addr); 107945386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 108045386Swpaul free(mc, M_DEVBUF); 108145386Swpaul } 108245386Swpaul 108345386Swpaul /* Now program new ones. */ 108445386Swpaul for (ifma = ifp->if_multiaddrs.lh_first; 108545386Swpaul ifma != NULL; ifma = ifma->ifma_link.le_next) { 108645386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 108745386Swpaul continue; 108845386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 108945386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 109045386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 109145386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 109245386Swpaul ti_add_mcast(sc, &mc->mc_addr); 109345386Swpaul } 109445386Swpaul 109545386Swpaul /* Re-enable interrupts. */ 109645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 109745386Swpaul 109845386Swpaul return; 109945386Swpaul} 110045386Swpaul 110145386Swpaul/* 110245386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 110345386Swpaul * we aren't actually in one. If we detect this condition, we can work 110445386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 110545386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 110645386Swpaul */ 110745386Swpaulstatic int ti_64bitslot_war(sc) 110845386Swpaul struct ti_softc *sc; 110945386Swpaul{ 111045386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 111145386Swpaul CSR_WRITE_4(sc, 0x600, 0); 111245386Swpaul CSR_WRITE_4(sc, 0x604, 0); 111345386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 111445386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 111545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 111645386Swpaul return(EINVAL); 111745386Swpaul else { 111845386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 111945386Swpaul TI_PCISTATE_32BIT_BUS); 112045386Swpaul return(0); 112145386Swpaul } 112245386Swpaul } 112345386Swpaul } 112445386Swpaul 112545386Swpaul return(0); 112645386Swpaul} 112745386Swpaul 112845386Swpaul/* 112945386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 113045386Swpaul * self-test results. 113145386Swpaul */ 113245386Swpaulstatic int ti_chipinit(sc) 113345386Swpaul struct ti_softc *sc; 113445386Swpaul{ 113545386Swpaul u_int32_t cacheline; 113645386Swpaul u_int32_t pci_writemax = 0; 113745386Swpaul 113845386Swpaul /* Initialize link to down state. */ 113945386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 114045386Swpaul 114158698Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 114258698Sjlemon 114345386Swpaul /* Set endianness before we access any non-PCI registers. */ 114445386Swpaul#if BYTE_ORDER == BIG_ENDIAN 114545386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 114645386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 114745386Swpaul#else 114845386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 114945386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 115045386Swpaul#endif 115145386Swpaul 115245386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 115345386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 115445386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 115545386Swpaul return(ENODEV); 115645386Swpaul } 115745386Swpaul 115845386Swpaul /* Halt the CPU. */ 115945386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 116045386Swpaul 116145386Swpaul /* Figure out the hardware revision. */ 116245386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 116345386Swpaul case TI_REV_TIGON_I: 116445386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 116545386Swpaul break; 116645386Swpaul case TI_REV_TIGON_II: 116745386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 116845386Swpaul break; 116945386Swpaul default: 117045386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 117145386Swpaul return(ENODEV); 117245386Swpaul } 117345386Swpaul 117445386Swpaul /* Do special setup for Tigon 2. */ 117545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 117645386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 117745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 117845386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 117945386Swpaul } 118045386Swpaul 118145386Swpaul /* Set up the PCI state register. */ 118245386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 118345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 118445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 118545386Swpaul } 118645386Swpaul 118745386Swpaul /* Clear the read/write max DMA parameters. */ 118845386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 118945386Swpaul TI_PCISTATE_READ_MAXDMA)); 119045386Swpaul 119145386Swpaul /* Get cache line size. */ 119245386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 119345386Swpaul 119445386Swpaul /* 119545386Swpaul * If the system has set enabled the PCI memory write 119645386Swpaul * and invalidate command in the command register, set 119745386Swpaul * the write max parameter accordingly. This is necessary 119845386Swpaul * to use MWI with the Tigon 2. 119945386Swpaul */ 120045386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 120145386Swpaul switch(cacheline) { 120245386Swpaul case 1: 120345386Swpaul case 4: 120445386Swpaul case 8: 120545386Swpaul case 16: 120645386Swpaul case 32: 120745386Swpaul case 64: 120845386Swpaul break; 120945386Swpaul default: 121045386Swpaul /* Disable PCI memory write and invalidate. */ 121145386Swpaul if (bootverbose) 121245386Swpaul printf("ti%d: cache line size %d not " 121345386Swpaul "supported; disabling PCI MWI\n", 121445386Swpaul sc->ti_unit, cacheline); 121545386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 121645386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 121745386Swpaul break; 121845386Swpaul } 121945386Swpaul } 122045386Swpaul 122145386Swpaul#ifdef __brokenalpha__ 122245386Swpaul /* 122345386Swpaul * From the Alteon sample driver: 122445386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 122545386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 122645386Swpaul * restriction on some ALPHA platforms with early revision 122745386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 122845386Swpaul */ 122945386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 123045386Swpaul#else 123145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 123245386Swpaul#endif 123345386Swpaul 123445386Swpaul /* This sets the min dma param all the way up (0xff). */ 123545386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 123645386Swpaul 123745386Swpaul /* Configure DMA variables. */ 123845386Swpaul#if BYTE_ORDER == BIG_ENDIAN 123945386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 124045386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 124145386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 124245386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 124345386Swpaul#else 124445386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 124545386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 124645386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 124745386Swpaul#endif 124845386Swpaul 124945386Swpaul /* 125045386Swpaul * Only allow 1 DMA channel to be active at a time. 125145386Swpaul * I don't think this is a good idea, but without it 125245386Swpaul * the firmware racks up lots of nicDmaReadRingFull 125358698Sjlemon * errors. This is not compatible with hardware checksums. 125445386Swpaul */ 125558698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 125658698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 125745386Swpaul 125845386Swpaul /* Recommended settings from Tigon manual. */ 125945386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 126045386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 126145386Swpaul 126245386Swpaul if (ti_64bitslot_war(sc)) { 126345386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 126445386Swpaul "but we aren't", sc->ti_unit); 126545386Swpaul return(EINVAL); 126645386Swpaul } 126745386Swpaul 126845386Swpaul return(0); 126945386Swpaul} 127045386Swpaul 127145386Swpaul/* 127245386Swpaul * Initialize the general information block and firmware, and 127345386Swpaul * start the CPU(s) running. 127445386Swpaul */ 127545386Swpaulstatic int ti_gibinit(sc) 127645386Swpaul struct ti_softc *sc; 127745386Swpaul{ 127845386Swpaul struct ti_rcb *rcb; 127945386Swpaul int i; 128045386Swpaul struct ifnet *ifp; 128145386Swpaul 128245386Swpaul ifp = &sc->arpcom.ac_if; 128345386Swpaul 128445386Swpaul /* Disable interrupts for now. */ 128545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 128645386Swpaul 128745386Swpaul /* Tell the chip where to find the general information block. */ 128845386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 128945386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 129045386Swpaul 129145386Swpaul /* Load the firmware into SRAM. */ 129245386Swpaul ti_loadfw(sc); 129345386Swpaul 129445386Swpaul /* Set up the contents of the general info and ring control blocks. */ 129545386Swpaul 129645386Swpaul /* Set up the event ring and producer pointer. */ 129745386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 129845386Swpaul 129945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 130045386Swpaul rcb->ti_flags = 0; 130145386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 130245386Swpaul vtophys(&sc->ti_ev_prodidx); 130345386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 130445386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 130545386Swpaul sc->ti_ev_saved_considx = 0; 130645386Swpaul 130745386Swpaul /* Set up the command ring and producer mailbox. */ 130845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 130945386Swpaul 131045386Swpaul sc->ti_rdata->ti_cmd_ring = 131149133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 131245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 131345386Swpaul rcb->ti_flags = 0; 131445386Swpaul rcb->ti_max_len = 0; 131545386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 131645386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 131745386Swpaul } 131845386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 131945386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 132045386Swpaul sc->ti_cmd_saved_prodidx = 0; 132145386Swpaul 132245386Swpaul /* 132345386Swpaul * Assign the address of the stats refresh buffer. 132445386Swpaul * We re-use the current stats buffer for this to 132545386Swpaul * conserve memory. 132645386Swpaul */ 132745386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 132845386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 132945386Swpaul 133045386Swpaul /* Set up the standard receive ring. */ 133145386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 133245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 133345386Swpaul rcb->ti_max_len = TI_FRAMELEN; 133445386Swpaul rcb->ti_flags = 0; 133558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 133658698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 133758698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 133845386Swpaul#if NVLAN > 0 133945386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 134045386Swpaul#endif 134145386Swpaul 134245386Swpaul /* Set up the jumbo receive ring. */ 134345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 134445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 134545386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 134649036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 134745386Swpaul rcb->ti_flags = 0; 134858698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 134958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 135058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 135145386Swpaul#if NVLAN > 0 135245386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 135345386Swpaul#endif 135445386Swpaul 135545386Swpaul /* 135645386Swpaul * Set up the mini ring. Only activated on the 135745386Swpaul * Tigon 2 but the slot in the config block is 135845386Swpaul * still there on the Tigon 1. 135945386Swpaul */ 136045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 136145386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 136245386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 136351352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 136445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 136545386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 136645386Swpaul else 136745386Swpaul rcb->ti_flags = 0; 136858698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 136958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 137058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 137145386Swpaul#if NVLAN > 0 137245386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 137345386Swpaul#endif 137445386Swpaul 137545386Swpaul /* 137645386Swpaul * Set up the receive return ring. 137745386Swpaul */ 137845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 137945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 138045386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 138145386Swpaul rcb->ti_flags = 0; 138245386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 138345386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 138445386Swpaul vtophys(&sc->ti_return_prodidx); 138545386Swpaul 138645386Swpaul /* 138745386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 138845386Swpaul * of putting the transmit ring in the host's address space and 138945386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 139045386Swpaul * memory and accessing it through the shared memory region. We 139145386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 139245386Swpaul * so we have to revert to the shared memory scheme if we detect 139345386Swpaul * a Tigon 1 chip. 139445386Swpaul */ 139545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 139645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 139745386Swpaul sc->ti_rdata->ti_tx_ring_nic = 139849133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 139945386Swpaul } 140045386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 140145386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 140245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 140345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 140445386Swpaul rcb->ti_flags = 0; 140545386Swpaul else 140645386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 140745386Swpaul#if NVLAN > 0 140845386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 140945386Swpaul#endif 141058698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 141158698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 141258698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 141345386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 141445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 141545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 141645386Swpaul else 141745386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 141845386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 141945386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 142045386Swpaul vtophys(&sc->ti_tx_considx); 142145386Swpaul 142245386Swpaul /* Set up tuneables */ 142345386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 142445386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 142545386Swpaul (sc->ti_rx_coal_ticks / 10)); 142645386Swpaul else 142745386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 142845386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 142945386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 143045386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 143145386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 143245386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 143345386Swpaul 143445386Swpaul /* Turn interrupts on. */ 143545386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 143645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 143745386Swpaul 143845386Swpaul /* Start CPU. */ 143945386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 144045386Swpaul 144145386Swpaul return(0); 144245386Swpaul} 144345386Swpaul 144445386Swpaul/* 144545386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 144645386Swpaul * against our list and return its name if we find a match. 144745386Swpaul */ 144849011Swpaulstatic int ti_probe(dev) 144949011Swpaul device_t dev; 145045386Swpaul{ 145145386Swpaul struct ti_type *t; 145245386Swpaul 145345386Swpaul t = ti_devs; 145445386Swpaul 145545386Swpaul while(t->ti_name != NULL) { 145649011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 145749011Swpaul (pci_get_device(dev) == t->ti_did)) { 145849011Swpaul device_set_desc(dev, t->ti_name); 145949011Swpaul return(0); 146049011Swpaul } 146145386Swpaul t++; 146245386Swpaul } 146345386Swpaul 146449011Swpaul return(ENXIO); 146545386Swpaul} 146645386Swpaul 146749011Swpaulstatic int ti_attach(dev) 146849011Swpaul device_t dev; 146945386Swpaul{ 147045386Swpaul u_int32_t command; 147145386Swpaul struct ifnet *ifp; 147245386Swpaul struct ti_softc *sc; 147349011Swpaul int unit, error = 0, rid; 147445386Swpaul 147549011Swpaul sc = device_get_softc(dev); 147649011Swpaul unit = device_get_unit(dev); 147745386Swpaul bzero(sc, sizeof(struct ti_softc)); 147845386Swpaul 147971228Sbmilekic mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 148069583Swpaul TI_LOCK(sc); 148169583Swpaul 148245386Swpaul /* 148345386Swpaul * Map control/status registers. 148445386Swpaul */ 148561041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 148645386Swpaul command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 148761041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 148861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 148945386Swpaul 149045386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 149145386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 149249011Swpaul error = ENXIO; 149345386Swpaul goto fail; 149445386Swpaul } 149545386Swpaul 149649011Swpaul rid = TI_PCI_LOMEM; 149749011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 149865176Sdfr 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 149949011Swpaul 150049011Swpaul if (sc->ti_res == NULL) { 150145386Swpaul printf ("ti%d: couldn't map memory\n", unit); 150249011Swpaul error = ENXIO; 150345386Swpaul goto fail; 150445386Swpaul } 150545386Swpaul 150649035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 150749035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 150849133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 150949035Swpaul 151049011Swpaul /* Allocate interrupt */ 151149011Swpaul rid = 0; 151249133Swpaul 151349011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 151449011Swpaul RF_SHAREABLE | RF_ACTIVE); 151545386Swpaul 151649011Swpaul if (sc->ti_irq == NULL) { 151749011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 151849011Swpaul error = ENXIO; 151945386Swpaul goto fail; 152045386Swpaul } 152145386Swpaul 152249011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 152349011Swpaul ti_intr, sc, &sc->ti_intrhand); 152449011Swpaul 152549011Swpaul if (error) { 152649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 152749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 152849011Swpaul TI_PCI_LOMEM, sc->ti_res); 152949011Swpaul printf("ti%d: couldn't set up irq\n", unit); 153045386Swpaul goto fail; 153145386Swpaul } 153245386Swpaul 153345386Swpaul sc->ti_unit = unit; 153445386Swpaul 153545386Swpaul if (ti_chipinit(sc)) { 153645386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 153749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 153849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 153949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 154049011Swpaul TI_PCI_LOMEM, sc->ti_res); 154149011Swpaul error = ENXIO; 154245386Swpaul goto fail; 154345386Swpaul } 154445386Swpaul 154545386Swpaul /* Zero out the NIC's on-board SRAM. */ 154645386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 154745386Swpaul 154845386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 154945386Swpaul if (ti_chipinit(sc)) { 155045386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 155149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 155249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 155349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 155449011Swpaul TI_PCI_LOMEM, sc->ti_res); 155549011Swpaul error = ENXIO; 155645386Swpaul goto fail; 155745386Swpaul } 155845386Swpaul 155945386Swpaul /* 156045386Swpaul * Get station address from the EEPROM. Note: the manual states 156145386Swpaul * that the MAC address is at offset 0x8c, however the data is 156245386Swpaul * stored as two longwords (since that's how it's loaded into 156345386Swpaul * the NIC). This means the MAC address is actually preceeded 156445386Swpaul * by two zero bytes. We need to skip over those. 156545386Swpaul */ 156645386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 156745386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 156845386Swpaul printf("ti%d: failed to read station address\n", unit); 156949011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 157049011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 157149011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 157249011Swpaul TI_PCI_LOMEM, sc->ti_res); 157349011Swpaul error = ENXIO; 157445386Swpaul goto fail; 157545386Swpaul } 157645386Swpaul 157745386Swpaul /* 157845386Swpaul * A Tigon chip was detected. Inform the world. 157945386Swpaul */ 158045386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 158145386Swpaul sc->arpcom.ac_enaddr, ":"); 158245386Swpaul 158345386Swpaul /* Allocate the general information block and ring buffers. */ 158449011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 158550548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 158645386Swpaul 158749011Swpaul if (sc->ti_rdata == NULL) { 158849011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 158949011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 159049011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 159149011Swpaul TI_PCI_LOMEM, sc->ti_res); 159249011Swpaul error = ENXIO; 159345386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 159445386Swpaul goto fail; 159545386Swpaul } 159645386Swpaul 159745386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 159845386Swpaul 159945386Swpaul /* Try to allocate memory for jumbo buffers. */ 160045386Swpaul if (ti_alloc_jumbo_mem(sc)) { 160145386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 160249011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 160349011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 160449011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 160549011Swpaul TI_PCI_LOMEM, sc->ti_res); 160662793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 160762793Sgallatin M_DEVBUF); 160849011Swpaul error = ENXIO; 160945386Swpaul goto fail; 161045386Swpaul } 161145386Swpaul 161263699Swpaul /* 161363699Swpaul * We really need a better way to tell a 1000baseTX card 161463699Swpaul * from a 1000baseSX one, since in theory there could be 161563699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 161663699Swpaul * clever enough to change the PCI ID. For the moment 161763699Swpaul * though, the AceNIC is the only copper card available. 161863699Swpaul */ 161963699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 162063699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 162163699Swpaul sc->ti_copper = 1; 162264139Swpaul /* Ok, it's not the only copper card available. */ 162364139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 162464139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 162564139Swpaul sc->ti_copper = 1; 162663699Swpaul 162745386Swpaul /* Set default tuneable values. */ 162845386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 162945386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 163045386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 163145386Swpaul sc->ti_rx_max_coal_bds = 64; 163245386Swpaul sc->ti_tx_max_coal_bds = 128; 163345386Swpaul sc->ti_tx_buf_ratio = 21; 163445386Swpaul 163545386Swpaul /* Set up ifnet structure */ 163645386Swpaul ifp = &sc->arpcom.ac_if; 163745386Swpaul ifp->if_softc = sc; 163845386Swpaul ifp->if_unit = sc->ti_unit; 163945386Swpaul ifp->if_name = "ti"; 164045386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 164145386Swpaul ifp->if_ioctl = ti_ioctl; 164245386Swpaul ifp->if_output = ether_output; 164345386Swpaul ifp->if_start = ti_start; 164445386Swpaul ifp->if_watchdog = ti_watchdog; 164545386Swpaul ifp->if_init = ti_init; 164645386Swpaul ifp->if_mtu = ETHERMTU; 164745386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 164845386Swpaul 164945386Swpaul /* Set up ifmedia support. */ 165045386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 165163699Swpaul if (sc->ti_copper) { 165263699Swpaul /* 165363699Swpaul * Copper cards allow manual 10/100 mode selection, 165463699Swpaul * but not manual 1000baseTX mode selection. Why? 165563699Swpaul * Becuase currently there's no way to specify the 165663699Swpaul * master/slave setting through the firmware interface, 165763699Swpaul * so Alteon decided to just bag it and handle it 165863699Swpaul * via autonegotiation. 165963699Swpaul */ 166063699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 166163699Swpaul ifmedia_add(&sc->ifmedia, 166263699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 166363699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 166463699Swpaul ifmedia_add(&sc->ifmedia, 166563699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 166663699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 166763699Swpaul ifmedia_add(&sc->ifmedia, 166863699Swpaul IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 166963699Swpaul } else { 167063699Swpaul /* Fiber cards don't support 10/100 modes. */ 167163699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 167263699Swpaul ifmedia_add(&sc->ifmedia, 167363699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 167463699Swpaul } 167545386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 167645386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 167745386Swpaul 167845386Swpaul /* 167963090Sarchie * Call MI attach routine. 168045386Swpaul */ 168163090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 168267087Swpaul TI_UNLOCK(sc); 168367087Swpaul return(0); 168445386Swpaul 168545386Swpaulfail: 168667087Swpaul TI_UNLOCK(sc); 168767087Swpaul mtx_destroy(&sc->ti_mtx); 168849011Swpaul return(error); 168945386Swpaul} 169045386Swpaul 169149011Swpaulstatic int ti_detach(dev) 169249011Swpaul device_t dev; 169349011Swpaul{ 169449011Swpaul struct ti_softc *sc; 169549011Swpaul struct ifnet *ifp; 169649011Swpaul 169749011Swpaul 169849011Swpaul sc = device_get_softc(dev); 169967087Swpaul TI_LOCK(sc); 170049011Swpaul ifp = &sc->arpcom.ac_if; 170149011Swpaul 170263090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 170349011Swpaul ti_stop(sc); 170449011Swpaul 170549011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 170649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 170749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 170849011Swpaul 170962793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 171062793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 171149011Swpaul ifmedia_removeall(&sc->ifmedia); 171249011Swpaul 171367087Swpaul TI_UNLOCK(sc); 171467087Swpaul mtx_destroy(&sc->ti_mtx); 171549011Swpaul 171649011Swpaul return(0); 171749011Swpaul} 171849011Swpaul 171945386Swpaul/* 172045386Swpaul * Frame reception handling. This is called if there's a frame 172145386Swpaul * on the receive return list. 172245386Swpaul * 172345386Swpaul * Note: we have to be able to handle three possibilities here: 172445386Swpaul * 1) the frame is from the mini receive ring (can only happen) 172545386Swpaul * on Tigon 2 boards) 172645386Swpaul * 2) the frame is from the jumbo recieve ring 172745386Swpaul * 3) the frame is from the standard receive ring 172845386Swpaul */ 172945386Swpaul 173045386Swpaulstatic void ti_rxeof(sc) 173145386Swpaul struct ti_softc *sc; 173245386Swpaul{ 173345386Swpaul struct ifnet *ifp; 173448597Swpaul struct ti_cmd_desc cmd; 173545386Swpaul 173645386Swpaul ifp = &sc->arpcom.ac_if; 173745386Swpaul 173845386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 173945386Swpaul struct ti_rx_desc *cur_rx; 174045386Swpaul u_int32_t rxidx; 174145386Swpaul struct ether_header *eh; 174245386Swpaul struct mbuf *m = NULL; 174345386Swpaul#if NVLAN > 0 174445386Swpaul u_int16_t vlan_tag = 0; 174545386Swpaul int have_tag = 0; 174645386Swpaul#endif 174745386Swpaul 174845386Swpaul cur_rx = 174945386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 175045386Swpaul rxidx = cur_rx->ti_idx; 175145386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 175245386Swpaul 175345386Swpaul#if NVLAN > 0 175445386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 175545386Swpaul have_tag = 1; 175645386Swpaul vlan_tag = cur_rx->ti_vlan_tag; 175745386Swpaul } 175845386Swpaul#endif 175945386Swpaul 176045386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 176145386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 176245386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 176345386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 176445386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 176545386Swpaul ifp->if_ierrors++; 176645386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 176745386Swpaul continue; 176845386Swpaul } 176948597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 177048597Swpaul ifp->if_ierrors++; 177148597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 177248597Swpaul continue; 177348597Swpaul } 177445386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 177545386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 177645386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 177745386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 177845386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 177945386Swpaul ifp->if_ierrors++; 178045386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 178145386Swpaul continue; 178245386Swpaul } 178348597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 178448597Swpaul ifp->if_ierrors++; 178548597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 178648597Swpaul continue; 178748597Swpaul } 178845386Swpaul } else { 178945386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 179045386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 179145386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 179245386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 179345386Swpaul ifp->if_ierrors++; 179445386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 179545386Swpaul continue; 179645386Swpaul } 179748597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 179848597Swpaul ifp->if_ierrors++; 179948597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 180048597Swpaul continue; 180148597Swpaul } 180245386Swpaul } 180345386Swpaul 180445386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 180545386Swpaul ifp->if_ipackets++; 180645386Swpaul eh = mtod(m, struct ether_header *); 180745386Swpaul m->m_pkthdr.rcvif = ifp; 180845386Swpaul 180945386Swpaul /* Remove header from mbuf and pass it on. */ 181045386Swpaul m_adj(m, sizeof(struct ether_header)); 181145386Swpaul 181258698Sjlemon if (ifp->if_hwassist) { 181358698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 181458698Sjlemon CSUM_DATA_VALID; 181558698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 181658698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 181758698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 181858698Sjlemon } 181945386Swpaul 182045386Swpaul#if NVLAN > 0 182145386Swpaul /* 182245386Swpaul * If we received a packet with a vlan tag, pass it 182345386Swpaul * to vlan_input() instead of ether_input(). 182445386Swpaul */ 182545386Swpaul if (have_tag) { 182645386Swpaul vlan_input_tag(eh, m, vlan_tag); 182745386Swpaul have_tag = vlan_tag = 0; 182845386Swpaul continue; 182945386Swpaul } 183045386Swpaul#endif 183145386Swpaul ether_input(ifp, eh, m); 183245386Swpaul } 183345386Swpaul 183445386Swpaul /* Only necessary on the Tigon 1. */ 183545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 183645386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 183745386Swpaul sc->ti_rx_saved_considx); 183845386Swpaul 183948597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 184048597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 184148597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 184245386Swpaul 184345386Swpaul return; 184445386Swpaul} 184545386Swpaul 184645386Swpaulstatic void ti_txeof(sc) 184745386Swpaul struct ti_softc *sc; 184845386Swpaul{ 184945386Swpaul struct ti_tx_desc *cur_tx = NULL; 185045386Swpaul struct ifnet *ifp; 185145386Swpaul 185245386Swpaul ifp = &sc->arpcom.ac_if; 185345386Swpaul 185445386Swpaul /* 185545386Swpaul * Go through our tx ring and free mbufs for those 185645386Swpaul * frames that have been sent. 185745386Swpaul */ 185845386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 185945386Swpaul u_int32_t idx = 0; 186045386Swpaul 186145386Swpaul idx = sc->ti_tx_saved_considx; 186245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 186345386Swpaul if (idx > 383) 186445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 186545386Swpaul TI_TX_RING_BASE + 6144); 186645386Swpaul else if (idx > 255) 186745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 186845386Swpaul TI_TX_RING_BASE + 4096); 186945386Swpaul else if (idx > 127) 187045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 187145386Swpaul TI_TX_RING_BASE + 2048); 187245386Swpaul else 187345386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 187445386Swpaul TI_TX_RING_BASE); 187545386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 187645386Swpaul } else 187745386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 187845386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 187945386Swpaul ifp->if_opackets++; 188045386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 188145386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 188245386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 188345386Swpaul } 188448011Swpaul sc->ti_txcnt--; 188545386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 188645386Swpaul ifp->if_timer = 0; 188745386Swpaul } 188845386Swpaul 188945386Swpaul if (cur_tx != NULL) 189045386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 189145386Swpaul 189245386Swpaul return; 189345386Swpaul} 189445386Swpaul 189545386Swpaulstatic void ti_intr(xsc) 189645386Swpaul void *xsc; 189745386Swpaul{ 189845386Swpaul struct ti_softc *sc; 189945386Swpaul struct ifnet *ifp; 190045386Swpaul 190145386Swpaul sc = xsc; 190267087Swpaul TI_LOCK(sc); 190345386Swpaul ifp = &sc->arpcom.ac_if; 190445386Swpaul 190545386Swpaul#ifdef notdef 190645386Swpaul /* Avoid this for now -- checking this register is expensive. */ 190745386Swpaul /* Make sure this is really our interrupt. */ 190867087Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 190967087Swpaul TI_UNLOCK(sc); 191045386Swpaul return; 191167087Swpaul } 191245386Swpaul#endif 191345386Swpaul 191445386Swpaul /* Ack interrupt and stop others from occuring. */ 191545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 191645386Swpaul 191745386Swpaul if (ifp->if_flags & IFF_RUNNING) { 191845386Swpaul /* Check RX return ring producer/consumer */ 191945386Swpaul ti_rxeof(sc); 192045386Swpaul 192145386Swpaul /* Check TX ring producer/consumer */ 192245386Swpaul ti_txeof(sc); 192345386Swpaul } 192445386Swpaul 192545386Swpaul ti_handle_events(sc); 192645386Swpaul 192745386Swpaul /* Re-enable interrupts. */ 192845386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 192945386Swpaul 193045386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 193145386Swpaul ti_start(ifp); 193245386Swpaul 193367087Swpaul TI_UNLOCK(sc); 193467087Swpaul 193545386Swpaul return; 193645386Swpaul} 193745386Swpaul 193845386Swpaulstatic void ti_stats_update(sc) 193945386Swpaul struct ti_softc *sc; 194045386Swpaul{ 194145386Swpaul struct ifnet *ifp; 194245386Swpaul 194345386Swpaul ifp = &sc->arpcom.ac_if; 194445386Swpaul 194545386Swpaul ifp->if_collisions += 194645386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 194745386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 194845386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 194945386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 195045386Swpaul ifp->if_collisions; 195145386Swpaul 195245386Swpaul return; 195345386Swpaul} 195445386Swpaul 195545386Swpaul/* 195645386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 195745386Swpaul * pointers to descriptors. 195845386Swpaul */ 195945386Swpaulstatic int ti_encap(sc, m_head, txidx) 196045386Swpaul struct ti_softc *sc; 196145386Swpaul struct mbuf *m_head; 196245386Swpaul u_int32_t *txidx; 196345386Swpaul{ 196445386Swpaul struct ti_tx_desc *f = NULL; 196545386Swpaul struct mbuf *m; 196648011Swpaul u_int32_t frag, cur, cnt = 0; 196758698Sjlemon u_int16_t csum_flags = 0; 196845386Swpaul#if NVLAN > 0 196945386Swpaul struct ifvlan *ifv = NULL; 197045386Swpaul 197145386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 197245386Swpaul m_head->m_pkthdr.rcvif != NULL && 197345386Swpaul m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 197445386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 197545386Swpaul#endif 197645386Swpaul 197745386Swpaul m = m_head; 197845386Swpaul cur = frag = *txidx; 197945386Swpaul 198058698Sjlemon if (m_head->m_pkthdr.csum_flags) { 198158698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 198258698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 198358698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 198458698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 198558698Sjlemon if (m_head->m_flags & M_LASTFRAG) 198658698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 198758698Sjlemon else if (m_head->m_flags & M_FRAG) 198858698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 198958698Sjlemon } 199045386Swpaul /* 199145386Swpaul * Start packing the mbufs in this chain into 199245386Swpaul * the fragment pointers. Stop when we run out 199345386Swpaul * of fragments or hit the end of the mbuf chain. 199445386Swpaul */ 199545386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 199645386Swpaul if (m->m_len != 0) { 199745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 199845386Swpaul if (frag > 383) 199945386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200045386Swpaul TI_TX_RING_BASE + 6144); 200145386Swpaul else if (frag > 255) 200245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200345386Swpaul TI_TX_RING_BASE + 4096); 200445386Swpaul else if (frag > 127) 200545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200645386Swpaul TI_TX_RING_BASE + 2048); 200745386Swpaul else 200845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200945386Swpaul TI_TX_RING_BASE); 201045386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 201145386Swpaul } else 201245386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 201345386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 201445386Swpaul break; 201545386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 201645386Swpaul f->ti_len = m->m_len; 201758698Sjlemon f->ti_flags = csum_flags; 201845386Swpaul#if NVLAN > 0 201945386Swpaul if (ifv != NULL) { 202045386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 202145386Swpaul f->ti_vlan_tag = ifv->ifv_tag; 202245386Swpaul } else { 202345386Swpaul f->ti_vlan_tag = 0; 202445386Swpaul } 202545386Swpaul#endif 202648011Swpaul /* 202748011Swpaul * Sanity check: avoid coming within 16 descriptors 202848011Swpaul * of the end of the ring. 202948011Swpaul */ 203048011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 203148011Swpaul return(ENOBUFS); 203245386Swpaul cur = frag; 203345386Swpaul TI_INC(frag, TI_TX_RING_CNT); 203448011Swpaul cnt++; 203545386Swpaul } 203645386Swpaul } 203745386Swpaul 203845386Swpaul if (m != NULL) 203945386Swpaul return(ENOBUFS); 204045386Swpaul 204146177Swpaul if (frag == sc->ti_tx_saved_considx) 204246177Swpaul return(ENOBUFS); 204346177Swpaul 204445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 204545386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 204645386Swpaul TI_BDFLAG_END; 204745386Swpaul else 204845386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 204947458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 205048011Swpaul sc->ti_txcnt += cnt; 205145386Swpaul 205245386Swpaul *txidx = frag; 205345386Swpaul 205445386Swpaul return(0); 205545386Swpaul} 205645386Swpaul 205745386Swpaul/* 205845386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 205945386Swpaul * to the mbuf data regions directly in the transmit descriptors. 206045386Swpaul */ 206145386Swpaulstatic void ti_start(ifp) 206245386Swpaul struct ifnet *ifp; 206345386Swpaul{ 206445386Swpaul struct ti_softc *sc; 206545386Swpaul struct mbuf *m_head = NULL; 206645386Swpaul u_int32_t prodidx = 0; 206745386Swpaul 206845386Swpaul sc = ifp->if_softc; 206967087Swpaul TI_LOCK(sc); 207045386Swpaul 207145386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 207245386Swpaul 207345386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 207445386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 207545386Swpaul if (m_head == NULL) 207645386Swpaul break; 207745386Swpaul 207845386Swpaul /* 207958698Sjlemon * XXX 208058698Sjlemon * safety overkill. If this is a fragmented packet chain 208158698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 208258698Sjlemon * it if we have enough descriptors to handle the entire 208358698Sjlemon * chain at once. 208458698Sjlemon * (paranoia -- may not actually be needed) 208558698Sjlemon */ 208658698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 208758698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 208858698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 208958698Sjlemon m_head->m_pkthdr.csum_data + 16) { 209058698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 209158698Sjlemon ifp->if_flags |= IFF_OACTIVE; 209258698Sjlemon break; 209358698Sjlemon } 209458698Sjlemon } 209558698Sjlemon 209658698Sjlemon /* 209745386Swpaul * Pack the data into the transmit ring. If we 209845386Swpaul * don't have room, set the OACTIVE flag and wait 209945386Swpaul * for the NIC to drain the ring. 210045386Swpaul */ 210145386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 210245386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 210345386Swpaul ifp->if_flags |= IFF_OACTIVE; 210445386Swpaul break; 210545386Swpaul } 210645386Swpaul 210745386Swpaul /* 210845386Swpaul * If there's a BPF listener, bounce a copy of this frame 210945386Swpaul * to him. 211045386Swpaul */ 211145386Swpaul if (ifp->if_bpf) 211245386Swpaul bpf_mtap(ifp, m_head); 211345386Swpaul } 211445386Swpaul 211545386Swpaul /* Transmit */ 211645386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 211745386Swpaul 211845386Swpaul /* 211945386Swpaul * Set a timeout in case the chip goes out to lunch. 212045386Swpaul */ 212145386Swpaul ifp->if_timer = 5; 212267087Swpaul TI_UNLOCK(sc); 212345386Swpaul 212445386Swpaul return; 212545386Swpaul} 212645386Swpaul 212745386Swpaulstatic void ti_init(xsc) 212845386Swpaul void *xsc; 212945386Swpaul{ 213045386Swpaul struct ti_softc *sc = xsc; 213145386Swpaul 213245386Swpaul /* Cancel pending I/O and flush buffers. */ 213345386Swpaul ti_stop(sc); 213445386Swpaul 213567087Swpaul TI_LOCK(sc); 213645386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 213745386Swpaul if (ti_gibinit(sc)) { 213845386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 213967087Swpaul TI_UNLOCK(sc); 214045386Swpaul return; 214145386Swpaul } 214245386Swpaul 214367087Swpaul TI_UNLOCK(sc); 214445386Swpaul 214545386Swpaul return; 214645386Swpaul} 214745386Swpaul 214845386Swpaulstatic void ti_init2(sc) 214945386Swpaul struct ti_softc *sc; 215045386Swpaul{ 215145386Swpaul struct ti_cmd_desc cmd; 215245386Swpaul struct ifnet *ifp; 215345386Swpaul u_int16_t *m; 215445386Swpaul struct ifmedia *ifm; 215545386Swpaul int tmp; 215645386Swpaul 215745386Swpaul ifp = &sc->arpcom.ac_if; 215845386Swpaul 215945386Swpaul /* Specify MTU and interface index. */ 216045386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 216145386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 216245386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 216345386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 216445386Swpaul 216545386Swpaul /* Load our MAC address. */ 216645386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 216745386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 216845386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 216945386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 217045386Swpaul 217145386Swpaul /* Enable or disable promiscuous mode as needed. */ 217245386Swpaul if (ifp->if_flags & IFF_PROMISC) { 217345386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 217445386Swpaul } else { 217545386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 217645386Swpaul } 217745386Swpaul 217845386Swpaul /* Program multicast filter. */ 217945386Swpaul ti_setmulti(sc); 218045386Swpaul 218145386Swpaul /* 218245386Swpaul * If this is a Tigon 1, we should tell the 218345386Swpaul * firmware to use software packet filtering. 218445386Swpaul */ 218545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 218645386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 218745386Swpaul } 218845386Swpaul 218945386Swpaul /* Init RX ring. */ 219045386Swpaul ti_init_rx_ring_std(sc); 219145386Swpaul 219245386Swpaul /* Init jumbo RX ring. */ 219345386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 219445386Swpaul ti_init_rx_ring_jumbo(sc); 219545386Swpaul 219645386Swpaul /* 219745386Swpaul * If this is a Tigon 2, we can also configure the 219845386Swpaul * mini ring. 219945386Swpaul */ 220045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 220145386Swpaul ti_init_rx_ring_mini(sc); 220245386Swpaul 220345386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 220445386Swpaul sc->ti_rx_saved_considx = 0; 220545386Swpaul 220645386Swpaul /* Init TX ring. */ 220745386Swpaul ti_init_tx_ring(sc); 220845386Swpaul 220945386Swpaul /* Tell firmware we're alive. */ 221045386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 221145386Swpaul 221245386Swpaul /* Enable host interrupts. */ 221345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 221445386Swpaul 221545386Swpaul ifp->if_flags |= IFF_RUNNING; 221645386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 221745386Swpaul 221845386Swpaul /* 221945386Swpaul * Make sure to set media properly. We have to do this 222045386Swpaul * here since we have to issue commands in order to set 222145386Swpaul * the link negotiation and we can't issue commands until 222245386Swpaul * the firmware is running. 222345386Swpaul */ 222445386Swpaul ifm = &sc->ifmedia; 222545386Swpaul tmp = ifm->ifm_media; 222645386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 222745386Swpaul ti_ifmedia_upd(ifp); 222845386Swpaul ifm->ifm_media = tmp; 222945386Swpaul 223045386Swpaul return; 223145386Swpaul} 223245386Swpaul 223345386Swpaul/* 223445386Swpaul * Set media options. 223545386Swpaul */ 223645386Swpaulstatic int ti_ifmedia_upd(ifp) 223745386Swpaul struct ifnet *ifp; 223845386Swpaul{ 223945386Swpaul struct ti_softc *sc; 224045386Swpaul struct ifmedia *ifm; 224145386Swpaul struct ti_cmd_desc cmd; 224245386Swpaul 224345386Swpaul sc = ifp->if_softc; 224445386Swpaul ifm = &sc->ifmedia; 224545386Swpaul 224645386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 224745386Swpaul return(EINVAL); 224845386Swpaul 224945386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 225045386Swpaul case IFM_AUTO: 225145386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 225245386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 225345386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 225445386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 225545386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 225645386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 225745386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 225845386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 225945386Swpaul break; 226045386Swpaul case IFM_1000_SX: 226163699Swpaul case IFM_1000_TX: 226245386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 226363699Swpaul TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 226445386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 226563699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 226663699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 226763699Swpaul } 226845386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 226945386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 227045386Swpaul break; 227145386Swpaul case IFM_100_FX: 227245386Swpaul case IFM_10_FL: 227363699Swpaul case IFM_100_TX: 227463699Swpaul case IFM_10_T: 227545386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 227645386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 227763699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 227863699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 227945386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 228045386Swpaul } else { 228145386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 228245386Swpaul } 228345386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 228445386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 228545386Swpaul } else { 228645386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 228745386Swpaul } 228845386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 228945386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 229045386Swpaul break; 229145386Swpaul } 229245386Swpaul 229345386Swpaul return(0); 229445386Swpaul} 229545386Swpaul 229645386Swpaul/* 229745386Swpaul * Report current media status. 229845386Swpaul */ 229945386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 230045386Swpaul struct ifnet *ifp; 230145386Swpaul struct ifmediareq *ifmr; 230245386Swpaul{ 230345386Swpaul struct ti_softc *sc; 230463699Swpaul u_int32_t media = 0; 230545386Swpaul 230645386Swpaul sc = ifp->if_softc; 230745386Swpaul 230845386Swpaul ifmr->ifm_status = IFM_AVALID; 230945386Swpaul ifmr->ifm_active = IFM_ETHER; 231045386Swpaul 231145386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 231245386Swpaul return; 231345386Swpaul 231445386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 231545386Swpaul 231663699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 231763699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 231863699Swpaul if (sc->ti_copper) 231963699Swpaul ifmr->ifm_active |= IFM_1000_TX; 232063699Swpaul else 232163699Swpaul ifmr->ifm_active |= IFM_1000_SX; 232263699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 232363699Swpaul ifmr->ifm_active |= IFM_FDX; 232463699Swpaul else 232563699Swpaul ifmr->ifm_active |= IFM_HDX; 232663699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 232745386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 232863699Swpaul if (sc->ti_copper) { 232963699Swpaul if (media & TI_LNK_100MB) 233063699Swpaul ifmr->ifm_active |= IFM_100_TX; 233163699Swpaul if (media & TI_LNK_10MB) 233263699Swpaul ifmr->ifm_active |= IFM_10_T; 233363699Swpaul } else { 233463699Swpaul if (media & TI_LNK_100MB) 233563699Swpaul ifmr->ifm_active |= IFM_100_FX; 233663699Swpaul if (media & TI_LNK_10MB) 233763699Swpaul ifmr->ifm_active |= IFM_10_FL; 233863699Swpaul } 233945386Swpaul if (media & TI_LNK_FULL_DUPLEX) 234045386Swpaul ifmr->ifm_active |= IFM_FDX; 234145386Swpaul if (media & TI_LNK_HALF_DUPLEX) 234245386Swpaul ifmr->ifm_active |= IFM_HDX; 234345386Swpaul } 234445386Swpaul 234545386Swpaul return; 234645386Swpaul} 234745386Swpaul 234845386Swpaulstatic int ti_ioctl(ifp, command, data) 234945386Swpaul struct ifnet *ifp; 235045386Swpaul u_long command; 235145386Swpaul caddr_t data; 235245386Swpaul{ 235345386Swpaul struct ti_softc *sc = ifp->if_softc; 235445386Swpaul struct ifreq *ifr = (struct ifreq *) data; 235567087Swpaul int error = 0; 235645386Swpaul struct ti_cmd_desc cmd; 235745386Swpaul 235867087Swpaul TI_LOCK(sc); 235945386Swpaul 236045386Swpaul switch(command) { 236145386Swpaul case SIOCSIFADDR: 236245386Swpaul case SIOCGIFADDR: 236345386Swpaul error = ether_ioctl(ifp, command, data); 236445386Swpaul break; 236545386Swpaul case SIOCSIFMTU: 236645386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 236745386Swpaul error = EINVAL; 236845386Swpaul else { 236945386Swpaul ifp->if_mtu = ifr->ifr_mtu; 237045386Swpaul ti_init(sc); 237145386Swpaul } 237245386Swpaul break; 237345386Swpaul case SIOCSIFFLAGS: 237445386Swpaul if (ifp->if_flags & IFF_UP) { 237545386Swpaul /* 237645386Swpaul * If only the state of the PROMISC flag changed, 237745386Swpaul * then just use the 'set promisc mode' command 237845386Swpaul * instead of reinitializing the entire NIC. Doing 237945386Swpaul * a full re-init means reloading the firmware and 238045386Swpaul * waiting for it to start up, which may take a 238145386Swpaul * second or two. 238245386Swpaul */ 238345386Swpaul if (ifp->if_flags & IFF_RUNNING && 238445386Swpaul ifp->if_flags & IFF_PROMISC && 238545386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 238645386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 238745386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 238845386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 238945386Swpaul !(ifp->if_flags & IFF_PROMISC) && 239045386Swpaul sc->ti_if_flags & IFF_PROMISC) { 239145386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 239245386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 239345386Swpaul } else 239445386Swpaul ti_init(sc); 239545386Swpaul } else { 239645386Swpaul if (ifp->if_flags & IFF_RUNNING) { 239745386Swpaul ti_stop(sc); 239845386Swpaul } 239945386Swpaul } 240045386Swpaul sc->ti_if_flags = ifp->if_flags; 240145386Swpaul error = 0; 240245386Swpaul break; 240345386Swpaul case SIOCADDMULTI: 240445386Swpaul case SIOCDELMULTI: 240545386Swpaul if (ifp->if_flags & IFF_RUNNING) { 240645386Swpaul ti_setmulti(sc); 240745386Swpaul error = 0; 240845386Swpaul } 240945386Swpaul break; 241045386Swpaul case SIOCSIFMEDIA: 241145386Swpaul case SIOCGIFMEDIA: 241245386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 241345386Swpaul break; 241445386Swpaul default: 241545386Swpaul error = EINVAL; 241645386Swpaul break; 241745386Swpaul } 241845386Swpaul 241967087Swpaul TI_UNLOCK(sc); 242045386Swpaul 242145386Swpaul return(error); 242245386Swpaul} 242345386Swpaul 242445386Swpaulstatic void ti_watchdog(ifp) 242545386Swpaul struct ifnet *ifp; 242645386Swpaul{ 242745386Swpaul struct ti_softc *sc; 242845386Swpaul 242945386Swpaul sc = ifp->if_softc; 243067087Swpaul TI_LOCK(sc); 243145386Swpaul 243245386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 243345386Swpaul ti_stop(sc); 243445386Swpaul ti_init(sc); 243545386Swpaul 243645386Swpaul ifp->if_oerrors++; 243767087Swpaul TI_UNLOCK(sc); 243845386Swpaul 243945386Swpaul return; 244045386Swpaul} 244145386Swpaul 244245386Swpaul/* 244345386Swpaul * Stop the adapter and free any mbufs allocated to the 244445386Swpaul * RX and TX lists. 244545386Swpaul */ 244645386Swpaulstatic void ti_stop(sc) 244745386Swpaul struct ti_softc *sc; 244845386Swpaul{ 244945386Swpaul struct ifnet *ifp; 245045386Swpaul struct ti_cmd_desc cmd; 245145386Swpaul 245267087Swpaul TI_LOCK(sc); 245367087Swpaul 245445386Swpaul ifp = &sc->arpcom.ac_if; 245545386Swpaul 245645386Swpaul /* Disable host interrupts. */ 245745386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 245845386Swpaul /* 245945386Swpaul * Tell firmware we're shutting down. 246045386Swpaul */ 246145386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 246245386Swpaul 246345386Swpaul /* Halt and reinitialize. */ 246445386Swpaul ti_chipinit(sc); 246545386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 246645386Swpaul ti_chipinit(sc); 246745386Swpaul 246845386Swpaul /* Free the RX lists. */ 246945386Swpaul ti_free_rx_ring_std(sc); 247045386Swpaul 247145386Swpaul /* Free jumbo RX list. */ 247245386Swpaul ti_free_rx_ring_jumbo(sc); 247345386Swpaul 247445386Swpaul /* Free mini RX list. */ 247545386Swpaul ti_free_rx_ring_mini(sc); 247645386Swpaul 247745386Swpaul /* Free TX buffers. */ 247845386Swpaul ti_free_tx_ring(sc); 247945386Swpaul 248045386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 248145386Swpaul sc->ti_return_prodidx.ti_idx = 0; 248245386Swpaul sc->ti_tx_considx.ti_idx = 0; 248345386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 248445386Swpaul 248545386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 248667087Swpaul TI_UNLOCK(sc); 248745386Swpaul 248845386Swpaul return; 248945386Swpaul} 249045386Swpaul 249145386Swpaul/* 249245386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 249345386Swpaul * get confused by errant DMAs when rebooting. 249445386Swpaul */ 249549011Swpaulstatic void ti_shutdown(dev) 249649011Swpaul device_t dev; 249745386Swpaul{ 249845386Swpaul struct ti_softc *sc; 249945386Swpaul 250049011Swpaul sc = device_get_softc(dev); 250167087Swpaul TI_LOCK(sc); 250245386Swpaul ti_chipinit(sc); 250367087Swpaul TI_UNLOCK(sc); 250445386Swpaul 250545386Swpaul return; 250645386Swpaul} 2507