if_ti.c revision 65176
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 65176 2000-08-28 21:48:13Z dfr $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include "vlan.h" 8245386Swpaul 8345386Swpaul#include <sys/param.h> 8445386Swpaul#include <sys/systm.h> 8545386Swpaul#include <sys/sockio.h> 8645386Swpaul#include <sys/mbuf.h> 8745386Swpaul#include <sys/malloc.h> 8845386Swpaul#include <sys/kernel.h> 8945386Swpaul#include <sys/socket.h> 9045386Swpaul#include <sys/queue.h> 9145386Swpaul 9245386Swpaul#include <net/if.h> 9345386Swpaul#include <net/if_arp.h> 9445386Swpaul#include <net/ethernet.h> 9545386Swpaul#include <net/if_dl.h> 9645386Swpaul#include <net/if_media.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#if NVLAN > 0 10145386Swpaul#include <net/if_types.h> 10245386Swpaul#include <net/if_vlan_var.h> 10345386Swpaul#endif 10445386Swpaul 10545386Swpaul#include <netinet/in_systm.h> 10645386Swpaul#include <netinet/in.h> 10745386Swpaul#include <netinet/ip.h> 10845386Swpaul 10945386Swpaul#include <vm/vm.h> /* for vtophys */ 11045386Swpaul#include <vm/pmap.h> /* for vtophys */ 11145386Swpaul#include <machine/clock.h> /* for DELAY */ 11245386Swpaul#include <machine/bus_memio.h> 11345386Swpaul#include <machine/bus.h> 11449011Swpaul#include <machine/resource.h> 11549011Swpaul#include <sys/bus.h> 11649011Swpaul#include <sys/rman.h> 11745386Swpaul 11845386Swpaul#include <pci/pcireg.h> 11945386Swpaul#include <pci/pcivar.h> 12045386Swpaul 12145386Swpaul#include <pci/if_tireg.h> 12245386Swpaul#include <pci/ti_fw.h> 12345386Swpaul#include <pci/ti_fw2.h> 12445386Swpaul 12558698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12645386Swpaul 12745386Swpaul#if !defined(lint) 12845386Swpaulstatic const char rcsid[] = 12950477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 65176 2000-08-28 21:48:13Z dfr $"; 13045386Swpaul#endif 13145386Swpaul 13245386Swpaul/* 13345386Swpaul * Various supported device vendors/types and their names. 13445386Swpaul */ 13545386Swpaul 13645386Swpaulstatic struct ti_type ti_devs[] = { 13745386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13863702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 13963699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 14063702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 14145386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 14245386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 14345386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 14464139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 14564139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 14664139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 14745386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14845386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14956206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 15056206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 15145386Swpaul { 0, 0, NULL } 15245386Swpaul}; 15345386Swpaul 15449011Swpaulstatic int ti_probe __P((device_t)); 15549011Swpaulstatic int ti_attach __P((device_t)); 15649011Swpaulstatic int ti_detach __P((device_t)); 15745386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15845386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15945386Swpaul 16045386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 16145386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 16245386Swpaul u_int32_t *)); 16345386Swpaul 16445386Swpaulstatic void ti_intr __P((void *)); 16545386Swpaulstatic void ti_start __P((struct ifnet *)); 16645386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16745386Swpaulstatic void ti_init __P((void *)); 16845386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16945386Swpaulstatic void ti_stop __P((struct ti_softc *)); 17045386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 17149011Swpaulstatic void ti_shutdown __P((device_t)); 17245386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 17345386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17445386Swpaul 17545386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17645386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17745386Swpaul int, u_int8_t *)); 17845386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17945386Swpaul 18045386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 18145386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 18245386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 18345386Swpaul 18445386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18545386Swpaul u_int32_t, caddr_t)); 18645386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18745386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18845386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18945386Swpaul caddr_t, int)); 19045386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 19145386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 19245386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 19364837Sdwmalonestatic void ti_jfree __P((caddr_t, void *)); 19445386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19545386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19645386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19745386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19845386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19945386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 20045386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 20145386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 20245386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20345386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 20445386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 20545386Swpaul 20645386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20745386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20845386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 20945386Swpaul 21049011Swpaulstatic device_method_t ti_methods[] = { 21149011Swpaul /* Device interface */ 21249011Swpaul DEVMETHOD(device_probe, ti_probe), 21349011Swpaul DEVMETHOD(device_attach, ti_attach), 21449011Swpaul DEVMETHOD(device_detach, ti_detach), 21549011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 21649011Swpaul { 0, 0 } 21749011Swpaul}; 21849011Swpaul 21949011Swpaulstatic driver_t ti_driver = { 22051455Swpaul "ti", 22149011Swpaul ti_methods, 22249011Swpaul sizeof(struct ti_softc) 22349011Swpaul}; 22449011Swpaul 22549011Swpaulstatic devclass_t ti_devclass; 22649011Swpaul 22751533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22849011Swpaul 22945386Swpaul/* 23045386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 23145386Swpaul */ 23245386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 23345386Swpaul struct ti_softc *sc; 23445386Swpaul int byte; 23545386Swpaul{ 23645386Swpaul register int i, ack = 0; 23745386Swpaul 23845386Swpaul /* 23945386Swpaul * Make sure we're in TX mode. 24045386Swpaul */ 24145386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 24245386Swpaul 24345386Swpaul /* 24445386Swpaul * Feed in each bit and stobe the clock. 24545386Swpaul */ 24645386Swpaul for (i = 0x80; i; i >>= 1) { 24745386Swpaul if (byte & i) { 24845386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24945386Swpaul } else { 25045386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 25145386Swpaul } 25245386Swpaul DELAY(1); 25345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25445386Swpaul DELAY(1); 25545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25645386Swpaul } 25745386Swpaul 25845386Swpaul /* 25945386Swpaul * Turn off TX mode. 26045386Swpaul */ 26145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 26245386Swpaul 26345386Swpaul /* 26445386Swpaul * Check for ack. 26545386Swpaul */ 26645386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26745386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26945386Swpaul 27045386Swpaul return(ack); 27145386Swpaul} 27245386Swpaul 27345386Swpaul/* 27445386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 27545386Swpaul * We have to send two address bytes since the EEPROM can hold 27645386Swpaul * more than 256 bytes of data. 27745386Swpaul */ 27845386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 27945386Swpaul struct ti_softc *sc; 28045386Swpaul int addr; 28145386Swpaul u_int8_t *dest; 28245386Swpaul{ 28345386Swpaul register int i; 28445386Swpaul u_int8_t byte = 0; 28545386Swpaul 28645386Swpaul EEPROM_START; 28745386Swpaul 28845386Swpaul /* 28945386Swpaul * Send write control code to EEPROM. 29045386Swpaul */ 29145386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 29245386Swpaul printf("ti%d: failed to send write command, status: %x\n", 29345386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29445386Swpaul return(1); 29545386Swpaul } 29645386Swpaul 29745386Swpaul /* 29845386Swpaul * Send first byte of address of byte we want to read. 29945386Swpaul */ 30045386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 30145386Swpaul printf("ti%d: failed to send address, status: %x\n", 30245386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30345386Swpaul return(1); 30445386Swpaul } 30545386Swpaul /* 30645386Swpaul * Send second byte address of byte we want to read. 30745386Swpaul */ 30845386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 30945386Swpaul printf("ti%d: failed to send address, status: %x\n", 31045386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31145386Swpaul return(1); 31245386Swpaul } 31345386Swpaul 31445386Swpaul EEPROM_STOP; 31545386Swpaul EEPROM_START; 31645386Swpaul /* 31745386Swpaul * Send read control code to EEPROM. 31845386Swpaul */ 31945386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 32045386Swpaul printf("ti%d: failed to send read command, status: %x\n", 32145386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 32245386Swpaul return(1); 32345386Swpaul } 32445386Swpaul 32545386Swpaul /* 32645386Swpaul * Start reading bits from EEPROM. 32745386Swpaul */ 32845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 32945386Swpaul for (i = 0x80; i; i >>= 1) { 33045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33145386Swpaul DELAY(1); 33245386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 33345386Swpaul byte |= i; 33445386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33545386Swpaul DELAY(1); 33645386Swpaul } 33745386Swpaul 33845386Swpaul EEPROM_STOP; 33945386Swpaul 34045386Swpaul /* 34145386Swpaul * No ACK generated for read, so just return byte. 34245386Swpaul */ 34345386Swpaul 34445386Swpaul *dest = byte; 34545386Swpaul 34645386Swpaul return(0); 34745386Swpaul} 34845386Swpaul 34945386Swpaul/* 35045386Swpaul * Read a sequence of bytes from the EEPROM. 35145386Swpaul */ 35245386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 35345386Swpaul struct ti_softc *sc; 35445386Swpaul caddr_t dest; 35545386Swpaul int off; 35645386Swpaul int cnt; 35745386Swpaul{ 35845386Swpaul int err = 0, i; 35945386Swpaul u_int8_t byte = 0; 36045386Swpaul 36145386Swpaul for (i = 0; i < cnt; i++) { 36245386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 36345386Swpaul if (err) 36445386Swpaul break; 36545386Swpaul *(dest + i) = byte; 36645386Swpaul } 36745386Swpaul 36845386Swpaul return(err ? 1 : 0); 36945386Swpaul} 37045386Swpaul 37145386Swpaul/* 37245386Swpaul * NIC memory access function. Can be used to either clear a section 37345386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 37445386Swpaul */ 37545386Swpaulstatic void ti_mem(sc, addr, len, buf) 37645386Swpaul struct ti_softc *sc; 37745386Swpaul u_int32_t addr, len; 37845386Swpaul caddr_t buf; 37945386Swpaul{ 38045386Swpaul int segptr, segsize, cnt; 38145386Swpaul caddr_t ti_winbase, ptr; 38245386Swpaul 38345386Swpaul segptr = addr; 38445386Swpaul cnt = len; 38549133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 38645386Swpaul ptr = buf; 38745386Swpaul 38845386Swpaul while(cnt) { 38945386Swpaul if (cnt < TI_WINLEN) 39045386Swpaul segsize = cnt; 39145386Swpaul else 39245386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 39345386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 39445386Swpaul if (buf == NULL) 39545386Swpaul bzero((char *)ti_winbase + (segptr & 39645386Swpaul (TI_WINLEN - 1)), segsize); 39745386Swpaul else { 39845386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 39945386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 40045386Swpaul ptr += segsize; 40145386Swpaul } 40245386Swpaul segptr += segsize; 40345386Swpaul cnt -= segsize; 40445386Swpaul } 40545386Swpaul 40645386Swpaul return; 40745386Swpaul} 40845386Swpaul 40945386Swpaul/* 41045386Swpaul * Load firmware image into the NIC. Check that the firmware revision 41145386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 41245386Swpaul * Tigon 2. 41345386Swpaul */ 41445386Swpaulstatic void ti_loadfw(sc) 41545386Swpaul struct ti_softc *sc; 41645386Swpaul{ 41745386Swpaul switch(sc->ti_hwrev) { 41845386Swpaul case TI_HWREV_TIGON: 41945386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 42045386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 42145386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 42245386Swpaul printf("ti%d: firmware revision mismatch; want " 42345386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 42445386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 42545386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 42645386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 42745386Swpaul return; 42845386Swpaul } 42945386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 43045386Swpaul (caddr_t)tigonFwText); 43145386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 43245386Swpaul (caddr_t)tigonFwData); 43345386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 43445386Swpaul (caddr_t)tigonFwRodata); 43545386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 43645386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 43745386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43845386Swpaul break; 43945386Swpaul case TI_HWREV_TIGON_II: 44045386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 44145386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 44245386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 44345386Swpaul printf("ti%d: firmware revision mismatch; want " 44445386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 44545386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 44645386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 44745386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44845386Swpaul return; 44945386Swpaul } 45045386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 45145386Swpaul (caddr_t)tigon2FwText); 45245386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 45345386Swpaul (caddr_t)tigon2FwData); 45445386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 45545386Swpaul (caddr_t)tigon2FwRodata); 45645386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 45745386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45845386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 45945386Swpaul break; 46045386Swpaul default: 46145386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 46245386Swpaul sc->ti_unit); 46345386Swpaul break; 46445386Swpaul } 46545386Swpaul 46645386Swpaul return; 46745386Swpaul} 46845386Swpaul 46945386Swpaul/* 47045386Swpaul * Send the NIC a command via the command ring. 47145386Swpaul */ 47245386Swpaulstatic void ti_cmd(sc, cmd) 47345386Swpaul struct ti_softc *sc; 47445386Swpaul struct ti_cmd_desc *cmd; 47545386Swpaul{ 47645386Swpaul u_int32_t index; 47745386Swpaul 47845386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 47945386Swpaul return; 48045386Swpaul 48145386Swpaul index = sc->ti_cmd_saved_prodidx; 48245386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 48345386Swpaul TI_INC(index, TI_CMD_RING_CNT); 48445386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 48545386Swpaul sc->ti_cmd_saved_prodidx = index; 48645386Swpaul 48745386Swpaul return; 48845386Swpaul} 48945386Swpaul 49045386Swpaul/* 49145386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 49245386Swpaul * number of command slots to include after the initial command. 49345386Swpaul */ 49445386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 49545386Swpaul struct ti_softc *sc; 49645386Swpaul struct ti_cmd_desc *cmd; 49745386Swpaul caddr_t arg; 49845386Swpaul int len; 49945386Swpaul{ 50045386Swpaul u_int32_t index; 50145386Swpaul register int i; 50245386Swpaul 50345386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 50445386Swpaul return; 50545386Swpaul 50645386Swpaul index = sc->ti_cmd_saved_prodidx; 50745386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50845386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50945386Swpaul for (i = 0; i < len; i++) { 51045386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 51145386Swpaul *(u_int32_t *)(&arg[i * 4])); 51245386Swpaul TI_INC(index, TI_CMD_RING_CNT); 51345386Swpaul } 51445386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 51545386Swpaul sc->ti_cmd_saved_prodidx = index; 51645386Swpaul 51745386Swpaul return; 51845386Swpaul} 51945386Swpaul 52045386Swpaul/* 52145386Swpaul * Handle events that have triggered interrupts. 52245386Swpaul */ 52345386Swpaulstatic void ti_handle_events(sc) 52445386Swpaul struct ti_softc *sc; 52545386Swpaul{ 52645386Swpaul struct ti_event_desc *e; 52745386Swpaul 52845386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 52945386Swpaul return; 53045386Swpaul 53145386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 53245386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 53345386Swpaul switch(e->ti_event) { 53445386Swpaul case TI_EV_LINKSTAT_CHANGED: 53545386Swpaul sc->ti_linkstat = e->ti_code; 53645386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 53745386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53845386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 53945386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 54045386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 54145386Swpaul printf("ti%d: link down\n", sc->ti_unit); 54245386Swpaul break; 54345386Swpaul case TI_EV_ERROR: 54445386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 54545386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 54645386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 54745386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54845386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 54945386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 55045386Swpaul break; 55145386Swpaul case TI_EV_FIRMWARE_UP: 55245386Swpaul ti_init2(sc); 55345386Swpaul break; 55445386Swpaul case TI_EV_STATS_UPDATED: 55545386Swpaul ti_stats_update(sc); 55645386Swpaul break; 55745386Swpaul case TI_EV_RESET_JUMBO_RING: 55845386Swpaul case TI_EV_MCAST_UPDATED: 55945386Swpaul /* Who cares. */ 56045386Swpaul break; 56145386Swpaul default: 56245386Swpaul printf("ti%d: unknown event: %d\n", 56345386Swpaul sc->ti_unit, e->ti_event); 56445386Swpaul break; 56545386Swpaul } 56645386Swpaul /* Advance the consumer index. */ 56745386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56845386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 56945386Swpaul } 57045386Swpaul 57145386Swpaul return; 57245386Swpaul} 57345386Swpaul 57445386Swpaul/* 57545386Swpaul * Memory management for the jumbo receive ring is a pain in the 57645386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 57745386Swpaul * _and_ it has to be contiguous (unless you use the extended 57845386Swpaul * jumbo descriptor format). Using malloc() all the time won't 57945386Swpaul * work: malloc() allocates memory in powers of two, which means we 58045386Swpaul * would end up wasting a considerable amount of space by allocating 58145386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 58245386Swpaul * to do our own memory management. 58345386Swpaul * 58445386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 58545386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 58645386Swpaul * as external mbuf storage. 58745386Swpaul * 58845386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 58945386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 59045386Swpaul * RAM. This is a bit much, especially considering we also need 59145386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 59245386Swpaul * save space, we only actually allocate enough memory for 64 slots 59345386Swpaul * by default, which works out to between 500 and 600K. This can 59445386Swpaul * be tuned by changing a #define in if_tireg.h. 59545386Swpaul */ 59645386Swpaul 59745386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59845386Swpaul struct ti_softc *sc; 59945386Swpaul{ 60045386Swpaul caddr_t ptr; 60145386Swpaul register int i; 60245386Swpaul struct ti_jpool_entry *entry; 60345386Swpaul 60445386Swpaul /* Grab a big chunk o' storage. */ 60545386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 60650548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 60745386Swpaul 60845386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 60945386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 61045386Swpaul return(ENOBUFS); 61145386Swpaul } 61245386Swpaul 61345386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 61445386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 61545386Swpaul 61645386Swpaul /* 61745386Swpaul * Now divide it up into 9K pieces and save the addresses 61845386Swpaul * in an array. Note that we play an evil trick here by using 61945386Swpaul * the first few bytes in the buffer to hold the the address 62045386Swpaul * of the softc structure for this interface. This is because 62145386Swpaul * ti_jfree() needs it, but it is called by the mbuf management 62245386Swpaul * code which will not pass it to us explicitly. 62345386Swpaul */ 62445386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 62545386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 62645386Swpaul u_int64_t **aptr; 62745386Swpaul aptr = (u_int64_t **)ptr; 62845386Swpaul aptr[0] = (u_int64_t *)sc; 62945386Swpaul ptr += sizeof(u_int64_t); 63045386Swpaul sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 63145386Swpaul ptr += (TI_JLEN - sizeof(u_int64_t)); 63245386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 63345386Swpaul M_DEVBUF, M_NOWAIT); 63445386Swpaul if (entry == NULL) { 63562793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 63662793Sgallatin M_DEVBUF); 63745386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 63845386Swpaul printf("ti%d: no memory for jumbo " 63945386Swpaul "buffer queue!\n", sc->ti_unit); 64045386Swpaul return(ENOBUFS); 64145386Swpaul } 64245386Swpaul entry->slot = i; 64345386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 64445386Swpaul } 64545386Swpaul 64645386Swpaul return(0); 64745386Swpaul} 64845386Swpaul 64945386Swpaul/* 65045386Swpaul * Allocate a jumbo buffer. 65145386Swpaul */ 65245386Swpaulstatic void *ti_jalloc(sc) 65345386Swpaul struct ti_softc *sc; 65445386Swpaul{ 65545386Swpaul struct ti_jpool_entry *entry; 65645386Swpaul 65745386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 65845386Swpaul 65945386Swpaul if (entry == NULL) { 66045386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 66145386Swpaul return(NULL); 66245386Swpaul } 66345386Swpaul 66445386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 66545386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 66645386Swpaul return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 66745386Swpaul} 66845386Swpaul 66945386Swpaul/* 67045386Swpaul * Release a jumbo buffer. 67145386Swpaul */ 67264837Sdwmalonestatic void ti_jfree(buf, args) 67345386Swpaul caddr_t buf; 67464837Sdwmalone void *args; 67545386Swpaul{ 67645386Swpaul struct ti_softc *sc; 67745386Swpaul u_int64_t **aptr; 67845386Swpaul int i; 67945386Swpaul struct ti_jpool_entry *entry; 68045386Swpaul 68145386Swpaul /* Extract the softc struct pointer. */ 68245386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 68345386Swpaul sc = (struct ti_softc *)(aptr[0]); 68445386Swpaul 68545386Swpaul if (sc == NULL) 68645386Swpaul panic("ti_jfree: can't find softc pointer!"); 68745386Swpaul 68845386Swpaul /* calculate the slot this buffer belongs to */ 68945386Swpaul i = ((vm_offset_t)aptr 69045386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 69145386Swpaul 69245386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 69345386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 69445386Swpaul 69564837Sdwmalone entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 69664837Sdwmalone if (entry == NULL) 69764837Sdwmalone panic("ti_jfree: buffer not in use!"); 69864837Sdwmalone entry->slot = i; 69964837Sdwmalone SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 70064837Sdwmalone SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 70164837Sdwmalone 70245386Swpaul return; 70345386Swpaul} 70445386Swpaul 70545386Swpaul 70645386Swpaul/* 70745386Swpaul * Intialize a standard receive ring descriptor. 70845386Swpaul */ 70945386Swpaulstatic int ti_newbuf_std(sc, i, m) 71045386Swpaul struct ti_softc *sc; 71145386Swpaul int i; 71245386Swpaul struct mbuf *m; 71345386Swpaul{ 71445386Swpaul struct mbuf *m_new = NULL; 71545386Swpaul struct ti_rx_desc *r; 71645386Swpaul 71749036Swpaul if (m == NULL) { 71845386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 71945386Swpaul if (m_new == NULL) { 72045386Swpaul printf("ti%d: mbuf allocation failed " 72145386Swpaul "-- packet dropped!\n", sc->ti_unit); 72245386Swpaul return(ENOBUFS); 72345386Swpaul } 72445386Swpaul 72545386Swpaul MCLGET(m_new, M_DONTWAIT); 72645386Swpaul if (!(m_new->m_flags & M_EXT)) { 72745386Swpaul printf("ti%d: cluster allocation failed " 72845386Swpaul "-- packet dropped!\n", sc->ti_unit); 72945386Swpaul m_freem(m_new); 73045386Swpaul return(ENOBUFS); 73145386Swpaul } 73249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 73349036Swpaul } else { 73449036Swpaul m_new = m; 73549036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 73649036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 73745386Swpaul } 73845386Swpaul 73948597Swpaul m_adj(m_new, ETHER_ALIGN); 74045386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 74145386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 74245386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 74345386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 74445386Swpaul r->ti_flags = 0; 74558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 74658698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 74749036Swpaul r->ti_len = m_new->m_len; 74845386Swpaul r->ti_idx = i; 74945386Swpaul 75045386Swpaul return(0); 75145386Swpaul} 75245386Swpaul 75345386Swpaul/* 75445386Swpaul * Intialize a mini receive ring descriptor. This only applies to 75545386Swpaul * the Tigon 2. 75645386Swpaul */ 75745386Swpaulstatic int ti_newbuf_mini(sc, i, m) 75845386Swpaul struct ti_softc *sc; 75945386Swpaul int i; 76045386Swpaul struct mbuf *m; 76145386Swpaul{ 76245386Swpaul struct mbuf *m_new = NULL; 76345386Swpaul struct ti_rx_desc *r; 76445386Swpaul 76549036Swpaul if (m == NULL) { 76645386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 76745386Swpaul if (m_new == NULL) { 76845386Swpaul printf("ti%d: mbuf allocation failed " 76945386Swpaul "-- packet dropped!\n", sc->ti_unit); 77045386Swpaul return(ENOBUFS); 77145386Swpaul } 77249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 77349036Swpaul } else { 77449036Swpaul m_new = m; 77549036Swpaul m_new->m_data = m_new->m_pktdat; 77649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 77745386Swpaul } 77849036Swpaul 77948597Swpaul m_adj(m_new, ETHER_ALIGN); 78045386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 78145386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 78245386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 78345386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 78445386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 78558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 78658698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 78749036Swpaul r->ti_len = m_new->m_len; 78845386Swpaul r->ti_idx = i; 78945386Swpaul 79045386Swpaul return(0); 79145386Swpaul} 79245386Swpaul 79345386Swpaul/* 79445386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 79545386Swpaul * a jumbo buffer from the pool managed internally by the driver. 79645386Swpaul */ 79745386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 79845386Swpaul struct ti_softc *sc; 79945386Swpaul int i; 80045386Swpaul struct mbuf *m; 80145386Swpaul{ 80245386Swpaul struct mbuf *m_new = NULL; 80345386Swpaul struct ti_rx_desc *r; 80445386Swpaul 80549036Swpaul if (m == NULL) { 80645386Swpaul caddr_t *buf = NULL; 80745386Swpaul 80845386Swpaul /* Allocate the mbuf. */ 80945386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 81045386Swpaul if (m_new == NULL) { 81145386Swpaul printf("ti%d: mbuf allocation failed " 81245386Swpaul "-- packet dropped!\n", sc->ti_unit); 81345386Swpaul return(ENOBUFS); 81445386Swpaul } 81545386Swpaul 81645386Swpaul /* Allocate the jumbo buffer */ 81745386Swpaul buf = ti_jalloc(sc); 81845386Swpaul if (buf == NULL) { 81945386Swpaul m_freem(m_new); 82045386Swpaul printf("ti%d: jumbo allocation failed " 82145386Swpaul "-- packet dropped!\n", sc->ti_unit); 82245386Swpaul return(ENOBUFS); 82345386Swpaul } 82445386Swpaul 82545386Swpaul /* Attach the buffer to the mbuf. */ 82664837Sdwmalone m_new->m_data = (void *) buf; 82764837Sdwmalone m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 82864837Sdwmalone MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, NULL); 82949036Swpaul } else { 83049036Swpaul m_new = m; 83149036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 83249036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 83345386Swpaul } 83445386Swpaul 83549780Swpaul m_adj(m_new, ETHER_ALIGN); 83645386Swpaul /* Set up the descriptor. */ 83745386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 83845386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 83945386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 84045386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 84145386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 84258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 84358698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 84449036Swpaul r->ti_len = m_new->m_len; 84545386Swpaul r->ti_idx = i; 84645386Swpaul 84745386Swpaul return(0); 84845386Swpaul} 84945386Swpaul 85045386Swpaul/* 85145386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 85245386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 85345386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 85445386Swpaul * the NIC. 85545386Swpaul */ 85645386Swpaulstatic int ti_init_rx_ring_std(sc) 85745386Swpaul struct ti_softc *sc; 85845386Swpaul{ 85945386Swpaul register int i; 86045386Swpaul struct ti_cmd_desc cmd; 86145386Swpaul 86245386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 86345386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 86445386Swpaul return(ENOBUFS); 86545386Swpaul }; 86645386Swpaul 86745386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 86848597Swpaul sc->ti_std = i - 1; 86945386Swpaul 87045386Swpaul return(0); 87145386Swpaul} 87245386Swpaul 87345386Swpaulstatic void ti_free_rx_ring_std(sc) 87445386Swpaul struct ti_softc *sc; 87545386Swpaul{ 87645386Swpaul register int i; 87745386Swpaul 87845386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 87945386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 88045386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 88145386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 88245386Swpaul } 88345386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 88445386Swpaul sizeof(struct ti_rx_desc)); 88545386Swpaul } 88645386Swpaul 88745386Swpaul return; 88845386Swpaul} 88945386Swpaul 89045386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 89145386Swpaul struct ti_softc *sc; 89245386Swpaul{ 89345386Swpaul register int i; 89445386Swpaul struct ti_cmd_desc cmd; 89545386Swpaul 89663699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 89745386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 89845386Swpaul return(ENOBUFS); 89945386Swpaul }; 90045386Swpaul 90145386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 90248597Swpaul sc->ti_jumbo = i - 1; 90345386Swpaul 90445386Swpaul return(0); 90545386Swpaul} 90645386Swpaul 90745386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 90845386Swpaul struct ti_softc *sc; 90945386Swpaul{ 91045386Swpaul register int i; 91145386Swpaul 91245386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 91345386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 91445386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 91545386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 91645386Swpaul } 91745386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 91845386Swpaul sizeof(struct ti_rx_desc)); 91945386Swpaul } 92045386Swpaul 92145386Swpaul return; 92245386Swpaul} 92345386Swpaul 92445386Swpaulstatic int ti_init_rx_ring_mini(sc) 92545386Swpaul struct ti_softc *sc; 92645386Swpaul{ 92745386Swpaul register int i; 92845386Swpaul 92945386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 93045386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 93145386Swpaul return(ENOBUFS); 93245386Swpaul }; 93345386Swpaul 93445386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 93548597Swpaul sc->ti_mini = i - 1; 93645386Swpaul 93745386Swpaul return(0); 93845386Swpaul} 93945386Swpaul 94045386Swpaulstatic void ti_free_rx_ring_mini(sc) 94145386Swpaul struct ti_softc *sc; 94245386Swpaul{ 94345386Swpaul register int i; 94445386Swpaul 94545386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 94645386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 94745386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 94845386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 94945386Swpaul } 95045386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 95145386Swpaul sizeof(struct ti_rx_desc)); 95245386Swpaul } 95345386Swpaul 95445386Swpaul return; 95545386Swpaul} 95645386Swpaul 95745386Swpaulstatic void ti_free_tx_ring(sc) 95845386Swpaul struct ti_softc *sc; 95945386Swpaul{ 96045386Swpaul register int i; 96145386Swpaul 96245386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 96345386Swpaul return; 96445386Swpaul 96545386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 96645386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 96745386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 96845386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 96945386Swpaul } 97045386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 97145386Swpaul sizeof(struct ti_tx_desc)); 97245386Swpaul } 97345386Swpaul 97445386Swpaul return; 97545386Swpaul} 97645386Swpaul 97745386Swpaulstatic int ti_init_tx_ring(sc) 97845386Swpaul struct ti_softc *sc; 97945386Swpaul{ 98048011Swpaul sc->ti_txcnt = 0; 98145386Swpaul sc->ti_tx_saved_considx = 0; 98245386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 98345386Swpaul return(0); 98445386Swpaul} 98545386Swpaul 98645386Swpaul/* 98745386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 98845386Swpaul * but we have to support the old way too so that Tigon 1 cards will 98945386Swpaul * work. 99045386Swpaul */ 99145386Swpaulvoid ti_add_mcast(sc, addr) 99245386Swpaul struct ti_softc *sc; 99345386Swpaul struct ether_addr *addr; 99445386Swpaul{ 99545386Swpaul struct ti_cmd_desc cmd; 99645386Swpaul u_int16_t *m; 99745386Swpaul u_int32_t ext[2] = {0, 0}; 99845386Swpaul 99945386Swpaul m = (u_int16_t *)&addr->octet[0]; 100045386Swpaul 100145386Swpaul switch(sc->ti_hwrev) { 100245386Swpaul case TI_HWREV_TIGON: 100345386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 100445386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 100545386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 100645386Swpaul break; 100745386Swpaul case TI_HWREV_TIGON_II: 100845386Swpaul ext[0] = htons(m[0]); 100945386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 101045386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 101145386Swpaul break; 101245386Swpaul default: 101345386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 101445386Swpaul break; 101545386Swpaul } 101645386Swpaul 101745386Swpaul return; 101845386Swpaul} 101945386Swpaul 102045386Swpaulvoid ti_del_mcast(sc, addr) 102145386Swpaul struct ti_softc *sc; 102245386Swpaul struct ether_addr *addr; 102345386Swpaul{ 102445386Swpaul struct ti_cmd_desc cmd; 102545386Swpaul u_int16_t *m; 102645386Swpaul u_int32_t ext[2] = {0, 0}; 102745386Swpaul 102845386Swpaul m = (u_int16_t *)&addr->octet[0]; 102945386Swpaul 103045386Swpaul switch(sc->ti_hwrev) { 103145386Swpaul case TI_HWREV_TIGON: 103245386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 103345386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 103445386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 103545386Swpaul break; 103645386Swpaul case TI_HWREV_TIGON_II: 103745386Swpaul ext[0] = htons(m[0]); 103845386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 103945386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 104045386Swpaul break; 104145386Swpaul default: 104245386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 104345386Swpaul break; 104445386Swpaul } 104545386Swpaul 104645386Swpaul return; 104745386Swpaul} 104845386Swpaul 104945386Swpaul/* 105045386Swpaul * Configure the Tigon's multicast address filter. 105145386Swpaul * 105245386Swpaul * The actual multicast table management is a bit of a pain, thanks to 105345386Swpaul * slight brain damage on the part of both Alteon and us. With our 105445386Swpaul * multicast code, we are only alerted when the multicast address table 105545386Swpaul * changes and at that point we only have the current list of addresses: 105645386Swpaul * we only know the current state, not the previous state, so we don't 105745386Swpaul * actually know what addresses were removed or added. The firmware has 105845386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 105945386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 106045386Swpaul * state so we know what addresses have been programmed into the NIC at 106145386Swpaul * any given time. 106245386Swpaul */ 106345386Swpaulstatic void ti_setmulti(sc) 106445386Swpaul struct ti_softc *sc; 106545386Swpaul{ 106645386Swpaul struct ifnet *ifp; 106745386Swpaul struct ifmultiaddr *ifma; 106845386Swpaul struct ti_cmd_desc cmd; 106945386Swpaul struct ti_mc_entry *mc; 107045386Swpaul u_int32_t intrs; 107145386Swpaul 107245386Swpaul ifp = &sc->arpcom.ac_if; 107345386Swpaul 107445386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 107545386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 107645386Swpaul return; 107745386Swpaul } else { 107845386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 107945386Swpaul } 108045386Swpaul 108145386Swpaul /* Disable interrupts. */ 108245386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 108345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 108445386Swpaul 108545386Swpaul /* First, zot all the existing filters. */ 108645386Swpaul while (sc->ti_mc_listhead.slh_first != NULL) { 108745386Swpaul mc = sc->ti_mc_listhead.slh_first; 108845386Swpaul ti_del_mcast(sc, &mc->mc_addr); 108945386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 109045386Swpaul free(mc, M_DEVBUF); 109145386Swpaul } 109245386Swpaul 109345386Swpaul /* Now program new ones. */ 109445386Swpaul for (ifma = ifp->if_multiaddrs.lh_first; 109545386Swpaul ifma != NULL; ifma = ifma->ifma_link.le_next) { 109645386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 109745386Swpaul continue; 109845386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 109945386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 110045386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 110145386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 110245386Swpaul ti_add_mcast(sc, &mc->mc_addr); 110345386Swpaul } 110445386Swpaul 110545386Swpaul /* Re-enable interrupts. */ 110645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 110745386Swpaul 110845386Swpaul return; 110945386Swpaul} 111045386Swpaul 111145386Swpaul/* 111245386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 111345386Swpaul * we aren't actually in one. If we detect this condition, we can work 111445386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 111545386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 111645386Swpaul */ 111745386Swpaulstatic int ti_64bitslot_war(sc) 111845386Swpaul struct ti_softc *sc; 111945386Swpaul{ 112045386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 112145386Swpaul CSR_WRITE_4(sc, 0x600, 0); 112245386Swpaul CSR_WRITE_4(sc, 0x604, 0); 112345386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 112445386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 112545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 112645386Swpaul return(EINVAL); 112745386Swpaul else { 112845386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 112945386Swpaul TI_PCISTATE_32BIT_BUS); 113045386Swpaul return(0); 113145386Swpaul } 113245386Swpaul } 113345386Swpaul } 113445386Swpaul 113545386Swpaul return(0); 113645386Swpaul} 113745386Swpaul 113845386Swpaul/* 113945386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 114045386Swpaul * self-test results. 114145386Swpaul */ 114245386Swpaulstatic int ti_chipinit(sc) 114345386Swpaul struct ti_softc *sc; 114445386Swpaul{ 114545386Swpaul u_int32_t cacheline; 114645386Swpaul u_int32_t pci_writemax = 0; 114745386Swpaul 114845386Swpaul /* Initialize link to down state. */ 114945386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 115045386Swpaul 115158698Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 115258698Sjlemon 115345386Swpaul /* Set endianness before we access any non-PCI registers. */ 115445386Swpaul#if BYTE_ORDER == BIG_ENDIAN 115545386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 115645386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 115745386Swpaul#else 115845386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 115945386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 116045386Swpaul#endif 116145386Swpaul 116245386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 116345386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 116445386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 116545386Swpaul return(ENODEV); 116645386Swpaul } 116745386Swpaul 116845386Swpaul /* Halt the CPU. */ 116945386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 117045386Swpaul 117145386Swpaul /* Figure out the hardware revision. */ 117245386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 117345386Swpaul case TI_REV_TIGON_I: 117445386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 117545386Swpaul break; 117645386Swpaul case TI_REV_TIGON_II: 117745386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 117845386Swpaul break; 117945386Swpaul default: 118045386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 118145386Swpaul return(ENODEV); 118245386Swpaul } 118345386Swpaul 118445386Swpaul /* Do special setup for Tigon 2. */ 118545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 118645386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 118745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 118845386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 118945386Swpaul } 119045386Swpaul 119145386Swpaul /* Set up the PCI state register. */ 119245386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 119345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 119445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 119545386Swpaul } 119645386Swpaul 119745386Swpaul /* Clear the read/write max DMA parameters. */ 119845386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 119945386Swpaul TI_PCISTATE_READ_MAXDMA)); 120045386Swpaul 120145386Swpaul /* Get cache line size. */ 120245386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 120345386Swpaul 120445386Swpaul /* 120545386Swpaul * If the system has set enabled the PCI memory write 120645386Swpaul * and invalidate command in the command register, set 120745386Swpaul * the write max parameter accordingly. This is necessary 120845386Swpaul * to use MWI with the Tigon 2. 120945386Swpaul */ 121045386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 121145386Swpaul switch(cacheline) { 121245386Swpaul case 1: 121345386Swpaul case 4: 121445386Swpaul case 8: 121545386Swpaul case 16: 121645386Swpaul case 32: 121745386Swpaul case 64: 121845386Swpaul break; 121945386Swpaul default: 122045386Swpaul /* Disable PCI memory write and invalidate. */ 122145386Swpaul if (bootverbose) 122245386Swpaul printf("ti%d: cache line size %d not " 122345386Swpaul "supported; disabling PCI MWI\n", 122445386Swpaul sc->ti_unit, cacheline); 122545386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 122645386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 122745386Swpaul break; 122845386Swpaul } 122945386Swpaul } 123045386Swpaul 123145386Swpaul#ifdef __brokenalpha__ 123245386Swpaul /* 123345386Swpaul * From the Alteon sample driver: 123445386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 123545386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 123645386Swpaul * restriction on some ALPHA platforms with early revision 123745386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 123845386Swpaul */ 123945386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 124045386Swpaul#else 124145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 124245386Swpaul#endif 124345386Swpaul 124445386Swpaul /* This sets the min dma param all the way up (0xff). */ 124545386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 124645386Swpaul 124745386Swpaul /* Configure DMA variables. */ 124845386Swpaul#if BYTE_ORDER == BIG_ENDIAN 124945386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 125045386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 125145386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 125245386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 125345386Swpaul#else 125445386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 125545386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 125645386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 125745386Swpaul#endif 125845386Swpaul 125945386Swpaul /* 126045386Swpaul * Only allow 1 DMA channel to be active at a time. 126145386Swpaul * I don't think this is a good idea, but without it 126245386Swpaul * the firmware racks up lots of nicDmaReadRingFull 126358698Sjlemon * errors. This is not compatible with hardware checksums. 126445386Swpaul */ 126558698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 126658698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 126745386Swpaul 126845386Swpaul /* Recommended settings from Tigon manual. */ 126945386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 127045386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 127145386Swpaul 127245386Swpaul if (ti_64bitslot_war(sc)) { 127345386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 127445386Swpaul "but we aren't", sc->ti_unit); 127545386Swpaul return(EINVAL); 127645386Swpaul } 127745386Swpaul 127845386Swpaul return(0); 127945386Swpaul} 128045386Swpaul 128145386Swpaul/* 128245386Swpaul * Initialize the general information block and firmware, and 128345386Swpaul * start the CPU(s) running. 128445386Swpaul */ 128545386Swpaulstatic int ti_gibinit(sc) 128645386Swpaul struct ti_softc *sc; 128745386Swpaul{ 128845386Swpaul struct ti_rcb *rcb; 128945386Swpaul int i; 129045386Swpaul struct ifnet *ifp; 129145386Swpaul 129245386Swpaul ifp = &sc->arpcom.ac_if; 129345386Swpaul 129445386Swpaul /* Disable interrupts for now. */ 129545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 129645386Swpaul 129745386Swpaul /* Tell the chip where to find the general information block. */ 129845386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 129945386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 130045386Swpaul 130145386Swpaul /* Load the firmware into SRAM. */ 130245386Swpaul ti_loadfw(sc); 130345386Swpaul 130445386Swpaul /* Set up the contents of the general info and ring control blocks. */ 130545386Swpaul 130645386Swpaul /* Set up the event ring and producer pointer. */ 130745386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 130845386Swpaul 130945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 131045386Swpaul rcb->ti_flags = 0; 131145386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 131245386Swpaul vtophys(&sc->ti_ev_prodidx); 131345386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 131445386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 131545386Swpaul sc->ti_ev_saved_considx = 0; 131645386Swpaul 131745386Swpaul /* Set up the command ring and producer mailbox. */ 131845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 131945386Swpaul 132045386Swpaul sc->ti_rdata->ti_cmd_ring = 132149133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 132245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 132345386Swpaul rcb->ti_flags = 0; 132445386Swpaul rcb->ti_max_len = 0; 132545386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 132645386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 132745386Swpaul } 132845386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 132945386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 133045386Swpaul sc->ti_cmd_saved_prodidx = 0; 133145386Swpaul 133245386Swpaul /* 133345386Swpaul * Assign the address of the stats refresh buffer. 133445386Swpaul * We re-use the current stats buffer for this to 133545386Swpaul * conserve memory. 133645386Swpaul */ 133745386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 133845386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 133945386Swpaul 134045386Swpaul /* Set up the standard receive ring. */ 134145386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 134245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 134345386Swpaul rcb->ti_max_len = TI_FRAMELEN; 134445386Swpaul rcb->ti_flags = 0; 134558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 134658698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 134758698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 134845386Swpaul#if NVLAN > 0 134945386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 135045386Swpaul#endif 135145386Swpaul 135245386Swpaul /* Set up the jumbo receive ring. */ 135345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 135445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 135545386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 135649036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 135745386Swpaul rcb->ti_flags = 0; 135858698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 135958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 136058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 136145386Swpaul#if NVLAN > 0 136245386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 136345386Swpaul#endif 136445386Swpaul 136545386Swpaul /* 136645386Swpaul * Set up the mini ring. Only activated on the 136745386Swpaul * Tigon 2 but the slot in the config block is 136845386Swpaul * still there on the Tigon 1. 136945386Swpaul */ 137045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 137145386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 137245386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 137351352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 137445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 137545386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 137645386Swpaul else 137745386Swpaul rcb->ti_flags = 0; 137858698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 137958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 138058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 138145386Swpaul#if NVLAN > 0 138245386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 138345386Swpaul#endif 138445386Swpaul 138545386Swpaul /* 138645386Swpaul * Set up the receive return ring. 138745386Swpaul */ 138845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 138945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 139045386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 139145386Swpaul rcb->ti_flags = 0; 139245386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 139345386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 139445386Swpaul vtophys(&sc->ti_return_prodidx); 139545386Swpaul 139645386Swpaul /* 139745386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 139845386Swpaul * of putting the transmit ring in the host's address space and 139945386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 140045386Swpaul * memory and accessing it through the shared memory region. We 140145386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 140245386Swpaul * so we have to revert to the shared memory scheme if we detect 140345386Swpaul * a Tigon 1 chip. 140445386Swpaul */ 140545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 140645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 140745386Swpaul sc->ti_rdata->ti_tx_ring_nic = 140849133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 140945386Swpaul } 141045386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 141145386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 141245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 141345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 141445386Swpaul rcb->ti_flags = 0; 141545386Swpaul else 141645386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 141745386Swpaul#if NVLAN > 0 141845386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 141945386Swpaul#endif 142058698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 142158698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 142258698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 142345386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 142445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 142545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 142645386Swpaul else 142745386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 142845386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 142945386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 143045386Swpaul vtophys(&sc->ti_tx_considx); 143145386Swpaul 143245386Swpaul /* Set up tuneables */ 143345386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 143445386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 143545386Swpaul (sc->ti_rx_coal_ticks / 10)); 143645386Swpaul else 143745386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 143845386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 143945386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 144045386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 144145386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 144245386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 144345386Swpaul 144445386Swpaul /* Turn interrupts on. */ 144545386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 144645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 144745386Swpaul 144845386Swpaul /* Start CPU. */ 144945386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 145045386Swpaul 145145386Swpaul return(0); 145245386Swpaul} 145345386Swpaul 145445386Swpaul/* 145545386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 145645386Swpaul * against our list and return its name if we find a match. 145745386Swpaul */ 145849011Swpaulstatic int ti_probe(dev) 145949011Swpaul device_t dev; 146045386Swpaul{ 146145386Swpaul struct ti_type *t; 146245386Swpaul 146345386Swpaul t = ti_devs; 146445386Swpaul 146545386Swpaul while(t->ti_name != NULL) { 146649011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 146749011Swpaul (pci_get_device(dev) == t->ti_did)) { 146849011Swpaul device_set_desc(dev, t->ti_name); 146949011Swpaul return(0); 147049011Swpaul } 147145386Swpaul t++; 147245386Swpaul } 147345386Swpaul 147449011Swpaul return(ENXIO); 147545386Swpaul} 147645386Swpaul 147749011Swpaulstatic int ti_attach(dev) 147849011Swpaul device_t dev; 147945386Swpaul{ 148045386Swpaul int s; 148145386Swpaul u_int32_t command; 148245386Swpaul struct ifnet *ifp; 148345386Swpaul struct ti_softc *sc; 148449011Swpaul int unit, error = 0, rid; 148545386Swpaul 148645386Swpaul s = splimp(); 148745386Swpaul 148849011Swpaul sc = device_get_softc(dev); 148949011Swpaul unit = device_get_unit(dev); 149045386Swpaul bzero(sc, sizeof(struct ti_softc)); 149145386Swpaul 149245386Swpaul /* 149345386Swpaul * Map control/status registers. 149445386Swpaul */ 149561041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 149645386Swpaul command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 149761041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 149861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 149945386Swpaul 150045386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 150145386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 150249011Swpaul error = ENXIO; 150345386Swpaul goto fail; 150445386Swpaul } 150545386Swpaul 150649011Swpaul rid = TI_PCI_LOMEM; 150749011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 150865176Sdfr 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 150949011Swpaul 151049011Swpaul if (sc->ti_res == NULL) { 151145386Swpaul printf ("ti%d: couldn't map memory\n", unit); 151249011Swpaul error = ENXIO; 151345386Swpaul goto fail; 151445386Swpaul } 151545386Swpaul 151649035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 151749035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 151849133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 151949035Swpaul 152049011Swpaul /* Allocate interrupt */ 152149011Swpaul rid = 0; 152249133Swpaul 152349011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 152449011Swpaul RF_SHAREABLE | RF_ACTIVE); 152545386Swpaul 152649011Swpaul if (sc->ti_irq == NULL) { 152749011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 152849011Swpaul error = ENXIO; 152945386Swpaul goto fail; 153045386Swpaul } 153145386Swpaul 153249011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 153349011Swpaul ti_intr, sc, &sc->ti_intrhand); 153449011Swpaul 153549011Swpaul if (error) { 153649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 153749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 153849011Swpaul TI_PCI_LOMEM, sc->ti_res); 153949011Swpaul printf("ti%d: couldn't set up irq\n", unit); 154045386Swpaul goto fail; 154145386Swpaul } 154245386Swpaul 154345386Swpaul sc->ti_unit = unit; 154445386Swpaul 154545386Swpaul if (ti_chipinit(sc)) { 154645386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 154749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 154849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 154949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 155049011Swpaul TI_PCI_LOMEM, sc->ti_res); 155149011Swpaul error = ENXIO; 155245386Swpaul goto fail; 155345386Swpaul } 155445386Swpaul 155545386Swpaul /* Zero out the NIC's on-board SRAM. */ 155645386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 155745386Swpaul 155845386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 155945386Swpaul if (ti_chipinit(sc)) { 156045386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 156149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 156249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 156349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 156449011Swpaul TI_PCI_LOMEM, sc->ti_res); 156549011Swpaul error = ENXIO; 156645386Swpaul goto fail; 156745386Swpaul } 156845386Swpaul 156945386Swpaul /* 157045386Swpaul * Get station address from the EEPROM. Note: the manual states 157145386Swpaul * that the MAC address is at offset 0x8c, however the data is 157245386Swpaul * stored as two longwords (since that's how it's loaded into 157345386Swpaul * the NIC). This means the MAC address is actually preceeded 157445386Swpaul * by two zero bytes. We need to skip over those. 157545386Swpaul */ 157645386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 157745386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 157845386Swpaul printf("ti%d: failed to read station address\n", unit); 157949011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 158049011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 158149011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 158249011Swpaul TI_PCI_LOMEM, sc->ti_res); 158349011Swpaul error = ENXIO; 158445386Swpaul goto fail; 158545386Swpaul } 158645386Swpaul 158745386Swpaul /* 158845386Swpaul * A Tigon chip was detected. Inform the world. 158945386Swpaul */ 159045386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 159145386Swpaul sc->arpcom.ac_enaddr, ":"); 159245386Swpaul 159345386Swpaul /* Allocate the general information block and ring buffers. */ 159449011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 159550548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 159645386Swpaul 159749011Swpaul if (sc->ti_rdata == NULL) { 159849011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 159949011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 160049011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 160149011Swpaul TI_PCI_LOMEM, sc->ti_res); 160249011Swpaul error = ENXIO; 160345386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 160445386Swpaul goto fail; 160545386Swpaul } 160645386Swpaul 160745386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 160845386Swpaul 160945386Swpaul /* Try to allocate memory for jumbo buffers. */ 161045386Swpaul if (ti_alloc_jumbo_mem(sc)) { 161145386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 161249011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 161349011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 161449011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 161549011Swpaul TI_PCI_LOMEM, sc->ti_res); 161662793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 161762793Sgallatin M_DEVBUF); 161849011Swpaul error = ENXIO; 161945386Swpaul goto fail; 162045386Swpaul } 162145386Swpaul 162263699Swpaul /* 162363699Swpaul * We really need a better way to tell a 1000baseTX card 162463699Swpaul * from a 1000baseSX one, since in theory there could be 162563699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 162663699Swpaul * clever enough to change the PCI ID. For the moment 162763699Swpaul * though, the AceNIC is the only copper card available. 162863699Swpaul */ 162963699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 163063699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 163163699Swpaul sc->ti_copper = 1; 163264139Swpaul /* Ok, it's not the only copper card available. */ 163364139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 163464139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 163564139Swpaul sc->ti_copper = 1; 163663699Swpaul 163745386Swpaul /* Set default tuneable values. */ 163845386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 163945386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 164045386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 164145386Swpaul sc->ti_rx_max_coal_bds = 64; 164245386Swpaul sc->ti_tx_max_coal_bds = 128; 164345386Swpaul sc->ti_tx_buf_ratio = 21; 164445386Swpaul 164545386Swpaul /* Set up ifnet structure */ 164645386Swpaul ifp = &sc->arpcom.ac_if; 164745386Swpaul ifp->if_softc = sc; 164845386Swpaul ifp->if_unit = sc->ti_unit; 164945386Swpaul ifp->if_name = "ti"; 165045386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 165145386Swpaul ifp->if_ioctl = ti_ioctl; 165245386Swpaul ifp->if_output = ether_output; 165345386Swpaul ifp->if_start = ti_start; 165445386Swpaul ifp->if_watchdog = ti_watchdog; 165545386Swpaul ifp->if_init = ti_init; 165645386Swpaul ifp->if_mtu = ETHERMTU; 165745386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 165845386Swpaul 165945386Swpaul /* Set up ifmedia support. */ 166045386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 166163699Swpaul if (sc->ti_copper) { 166263699Swpaul /* 166363699Swpaul * Copper cards allow manual 10/100 mode selection, 166463699Swpaul * but not manual 1000baseTX mode selection. Why? 166563699Swpaul * Becuase currently there's no way to specify the 166663699Swpaul * master/slave setting through the firmware interface, 166763699Swpaul * so Alteon decided to just bag it and handle it 166863699Swpaul * via autonegotiation. 166963699Swpaul */ 167063699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 167163699Swpaul ifmedia_add(&sc->ifmedia, 167263699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 167363699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 167463699Swpaul ifmedia_add(&sc->ifmedia, 167563699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 167663699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 167763699Swpaul ifmedia_add(&sc->ifmedia, 167863699Swpaul IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 167963699Swpaul } else { 168063699Swpaul /* Fiber cards don't support 10/100 modes. */ 168163699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 168263699Swpaul ifmedia_add(&sc->ifmedia, 168363699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 168463699Swpaul } 168545386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 168645386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 168745386Swpaul 168845386Swpaul /* 168963090Sarchie * Call MI attach routine. 169045386Swpaul */ 169163090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 169245386Swpaul 169345386Swpaulfail: 169445386Swpaul splx(s); 169545386Swpaul 169649011Swpaul return(error); 169745386Swpaul} 169845386Swpaul 169949011Swpaulstatic int ti_detach(dev) 170049011Swpaul device_t dev; 170149011Swpaul{ 170249011Swpaul struct ti_softc *sc; 170349011Swpaul struct ifnet *ifp; 170449011Swpaul int s; 170549011Swpaul 170649011Swpaul s = splimp(); 170749011Swpaul 170849011Swpaul sc = device_get_softc(dev); 170949011Swpaul ifp = &sc->arpcom.ac_if; 171049011Swpaul 171163090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 171249011Swpaul ti_stop(sc); 171349011Swpaul 171449011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 171549011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 171649011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 171749011Swpaul 171862793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 171962793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 172049011Swpaul ifmedia_removeall(&sc->ifmedia); 172149011Swpaul 172249011Swpaul splx(s); 172349011Swpaul 172449011Swpaul return(0); 172549011Swpaul} 172649011Swpaul 172745386Swpaul/* 172845386Swpaul * Frame reception handling. This is called if there's a frame 172945386Swpaul * on the receive return list. 173045386Swpaul * 173145386Swpaul * Note: we have to be able to handle three possibilities here: 173245386Swpaul * 1) the frame is from the mini receive ring (can only happen) 173345386Swpaul * on Tigon 2 boards) 173445386Swpaul * 2) the frame is from the jumbo recieve ring 173545386Swpaul * 3) the frame is from the standard receive ring 173645386Swpaul */ 173745386Swpaul 173845386Swpaulstatic void ti_rxeof(sc) 173945386Swpaul struct ti_softc *sc; 174045386Swpaul{ 174145386Swpaul struct ifnet *ifp; 174248597Swpaul struct ti_cmd_desc cmd; 174345386Swpaul 174445386Swpaul ifp = &sc->arpcom.ac_if; 174545386Swpaul 174645386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 174745386Swpaul struct ti_rx_desc *cur_rx; 174845386Swpaul u_int32_t rxidx; 174945386Swpaul struct ether_header *eh; 175045386Swpaul struct mbuf *m = NULL; 175145386Swpaul#if NVLAN > 0 175245386Swpaul u_int16_t vlan_tag = 0; 175345386Swpaul int have_tag = 0; 175445386Swpaul#endif 175545386Swpaul 175645386Swpaul cur_rx = 175745386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 175845386Swpaul rxidx = cur_rx->ti_idx; 175945386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 176045386Swpaul 176145386Swpaul#if NVLAN > 0 176245386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 176345386Swpaul have_tag = 1; 176445386Swpaul vlan_tag = cur_rx->ti_vlan_tag; 176545386Swpaul } 176645386Swpaul#endif 176745386Swpaul 176845386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 176945386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 177045386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 177145386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 177245386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 177345386Swpaul ifp->if_ierrors++; 177445386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 177545386Swpaul continue; 177645386Swpaul } 177748597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 177848597Swpaul ifp->if_ierrors++; 177948597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 178048597Swpaul continue; 178148597Swpaul } 178245386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 178345386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 178445386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 178545386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 178645386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 178745386Swpaul ifp->if_ierrors++; 178845386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 178945386Swpaul continue; 179045386Swpaul } 179148597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 179248597Swpaul ifp->if_ierrors++; 179348597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 179448597Swpaul continue; 179548597Swpaul } 179645386Swpaul } else { 179745386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 179845386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 179945386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 180045386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 180145386Swpaul ifp->if_ierrors++; 180245386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 180345386Swpaul continue; 180445386Swpaul } 180548597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 180648597Swpaul ifp->if_ierrors++; 180748597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 180848597Swpaul continue; 180948597Swpaul } 181045386Swpaul } 181145386Swpaul 181245386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 181345386Swpaul ifp->if_ipackets++; 181445386Swpaul eh = mtod(m, struct ether_header *); 181545386Swpaul m->m_pkthdr.rcvif = ifp; 181645386Swpaul 181745386Swpaul /* Remove header from mbuf and pass it on. */ 181845386Swpaul m_adj(m, sizeof(struct ether_header)); 181945386Swpaul 182058698Sjlemon if (ifp->if_hwassist) { 182158698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 182258698Sjlemon CSUM_DATA_VALID; 182358698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 182458698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 182558698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 182658698Sjlemon } 182745386Swpaul 182845386Swpaul#if NVLAN > 0 182945386Swpaul /* 183045386Swpaul * If we received a packet with a vlan tag, pass it 183145386Swpaul * to vlan_input() instead of ether_input(). 183245386Swpaul */ 183345386Swpaul if (have_tag) { 183445386Swpaul vlan_input_tag(eh, m, vlan_tag); 183545386Swpaul have_tag = vlan_tag = 0; 183645386Swpaul continue; 183745386Swpaul } 183845386Swpaul#endif 183945386Swpaul ether_input(ifp, eh, m); 184045386Swpaul } 184145386Swpaul 184245386Swpaul /* Only necessary on the Tigon 1. */ 184345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 184445386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 184545386Swpaul sc->ti_rx_saved_considx); 184645386Swpaul 184748597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 184848597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 184948597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 185045386Swpaul 185145386Swpaul return; 185245386Swpaul} 185345386Swpaul 185445386Swpaulstatic void ti_txeof(sc) 185545386Swpaul struct ti_softc *sc; 185645386Swpaul{ 185745386Swpaul struct ti_tx_desc *cur_tx = NULL; 185845386Swpaul struct ifnet *ifp; 185945386Swpaul 186045386Swpaul ifp = &sc->arpcom.ac_if; 186145386Swpaul 186245386Swpaul /* 186345386Swpaul * Go through our tx ring and free mbufs for those 186445386Swpaul * frames that have been sent. 186545386Swpaul */ 186645386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 186745386Swpaul u_int32_t idx = 0; 186845386Swpaul 186945386Swpaul idx = sc->ti_tx_saved_considx; 187045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 187145386Swpaul if (idx > 383) 187245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 187345386Swpaul TI_TX_RING_BASE + 6144); 187445386Swpaul else if (idx > 255) 187545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 187645386Swpaul TI_TX_RING_BASE + 4096); 187745386Swpaul else if (idx > 127) 187845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 187945386Swpaul TI_TX_RING_BASE + 2048); 188045386Swpaul else 188145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 188245386Swpaul TI_TX_RING_BASE); 188345386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 188445386Swpaul } else 188545386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 188645386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 188745386Swpaul ifp->if_opackets++; 188845386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 188945386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 189045386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 189145386Swpaul } 189248011Swpaul sc->ti_txcnt--; 189345386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 189445386Swpaul ifp->if_timer = 0; 189545386Swpaul } 189645386Swpaul 189745386Swpaul if (cur_tx != NULL) 189845386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 189945386Swpaul 190045386Swpaul return; 190145386Swpaul} 190245386Swpaul 190345386Swpaulstatic void ti_intr(xsc) 190445386Swpaul void *xsc; 190545386Swpaul{ 190645386Swpaul struct ti_softc *sc; 190745386Swpaul struct ifnet *ifp; 190845386Swpaul 190945386Swpaul sc = xsc; 191045386Swpaul ifp = &sc->arpcom.ac_if; 191145386Swpaul 191245386Swpaul#ifdef notdef 191345386Swpaul /* Avoid this for now -- checking this register is expensive. */ 191445386Swpaul /* Make sure this is really our interrupt. */ 191545386Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 191645386Swpaul return; 191745386Swpaul#endif 191845386Swpaul 191945386Swpaul /* Ack interrupt and stop others from occuring. */ 192045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 192145386Swpaul 192245386Swpaul if (ifp->if_flags & IFF_RUNNING) { 192345386Swpaul /* Check RX return ring producer/consumer */ 192445386Swpaul ti_rxeof(sc); 192545386Swpaul 192645386Swpaul /* Check TX ring producer/consumer */ 192745386Swpaul ti_txeof(sc); 192845386Swpaul } 192945386Swpaul 193045386Swpaul ti_handle_events(sc); 193145386Swpaul 193245386Swpaul /* Re-enable interrupts. */ 193345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 193445386Swpaul 193545386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 193645386Swpaul ti_start(ifp); 193745386Swpaul 193845386Swpaul return; 193945386Swpaul} 194045386Swpaul 194145386Swpaulstatic void ti_stats_update(sc) 194245386Swpaul struct ti_softc *sc; 194345386Swpaul{ 194445386Swpaul struct ifnet *ifp; 194545386Swpaul 194645386Swpaul ifp = &sc->arpcom.ac_if; 194745386Swpaul 194845386Swpaul ifp->if_collisions += 194945386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 195045386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 195145386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 195245386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 195345386Swpaul ifp->if_collisions; 195445386Swpaul 195545386Swpaul return; 195645386Swpaul} 195745386Swpaul 195845386Swpaul/* 195945386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 196045386Swpaul * pointers to descriptors. 196145386Swpaul */ 196245386Swpaulstatic int ti_encap(sc, m_head, txidx) 196345386Swpaul struct ti_softc *sc; 196445386Swpaul struct mbuf *m_head; 196545386Swpaul u_int32_t *txidx; 196645386Swpaul{ 196745386Swpaul struct ti_tx_desc *f = NULL; 196845386Swpaul struct mbuf *m; 196948011Swpaul u_int32_t frag, cur, cnt = 0; 197058698Sjlemon u_int16_t csum_flags = 0; 197145386Swpaul#if NVLAN > 0 197245386Swpaul struct ifvlan *ifv = NULL; 197345386Swpaul 197445386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 197545386Swpaul m_head->m_pkthdr.rcvif != NULL && 197645386Swpaul m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 197745386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 197845386Swpaul#endif 197945386Swpaul 198045386Swpaul m = m_head; 198145386Swpaul cur = frag = *txidx; 198245386Swpaul 198358698Sjlemon if (m_head->m_pkthdr.csum_flags) { 198458698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 198558698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 198658698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 198758698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 198858698Sjlemon if (m_head->m_flags & M_LASTFRAG) 198958698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 199058698Sjlemon else if (m_head->m_flags & M_FRAG) 199158698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 199258698Sjlemon } 199345386Swpaul /* 199445386Swpaul * Start packing the mbufs in this chain into 199545386Swpaul * the fragment pointers. Stop when we run out 199645386Swpaul * of fragments or hit the end of the mbuf chain. 199745386Swpaul */ 199845386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 199945386Swpaul if (m->m_len != 0) { 200045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 200145386Swpaul if (frag > 383) 200245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200345386Swpaul TI_TX_RING_BASE + 6144); 200445386Swpaul else if (frag > 255) 200545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200645386Swpaul TI_TX_RING_BASE + 4096); 200745386Swpaul else if (frag > 127) 200845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 200945386Swpaul TI_TX_RING_BASE + 2048); 201045386Swpaul else 201145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 201245386Swpaul TI_TX_RING_BASE); 201345386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 201445386Swpaul } else 201545386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 201645386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 201745386Swpaul break; 201845386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 201945386Swpaul f->ti_len = m->m_len; 202058698Sjlemon f->ti_flags = csum_flags; 202145386Swpaul#if NVLAN > 0 202245386Swpaul if (ifv != NULL) { 202345386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 202445386Swpaul f->ti_vlan_tag = ifv->ifv_tag; 202545386Swpaul } else { 202645386Swpaul f->ti_vlan_tag = 0; 202745386Swpaul } 202845386Swpaul#endif 202948011Swpaul /* 203048011Swpaul * Sanity check: avoid coming within 16 descriptors 203148011Swpaul * of the end of the ring. 203248011Swpaul */ 203348011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 203448011Swpaul return(ENOBUFS); 203545386Swpaul cur = frag; 203645386Swpaul TI_INC(frag, TI_TX_RING_CNT); 203748011Swpaul cnt++; 203845386Swpaul } 203945386Swpaul } 204045386Swpaul 204145386Swpaul if (m != NULL) 204245386Swpaul return(ENOBUFS); 204345386Swpaul 204446177Swpaul if (frag == sc->ti_tx_saved_considx) 204546177Swpaul return(ENOBUFS); 204646177Swpaul 204745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 204845386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 204945386Swpaul TI_BDFLAG_END; 205045386Swpaul else 205145386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 205247458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 205348011Swpaul sc->ti_txcnt += cnt; 205445386Swpaul 205545386Swpaul *txidx = frag; 205645386Swpaul 205745386Swpaul return(0); 205845386Swpaul} 205945386Swpaul 206045386Swpaul/* 206145386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 206245386Swpaul * to the mbuf data regions directly in the transmit descriptors. 206345386Swpaul */ 206445386Swpaulstatic void ti_start(ifp) 206545386Swpaul struct ifnet *ifp; 206645386Swpaul{ 206745386Swpaul struct ti_softc *sc; 206845386Swpaul struct mbuf *m_head = NULL; 206945386Swpaul u_int32_t prodidx = 0; 207045386Swpaul 207145386Swpaul sc = ifp->if_softc; 207245386Swpaul 207345386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 207445386Swpaul 207545386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 207645386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 207745386Swpaul if (m_head == NULL) 207845386Swpaul break; 207945386Swpaul 208045386Swpaul /* 208158698Sjlemon * XXX 208258698Sjlemon * safety overkill. If this is a fragmented packet chain 208358698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 208458698Sjlemon * it if we have enough descriptors to handle the entire 208558698Sjlemon * chain at once. 208658698Sjlemon * (paranoia -- may not actually be needed) 208758698Sjlemon */ 208858698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 208958698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 209058698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 209158698Sjlemon m_head->m_pkthdr.csum_data + 16) { 209258698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 209358698Sjlemon ifp->if_flags |= IFF_OACTIVE; 209458698Sjlemon break; 209558698Sjlemon } 209658698Sjlemon } 209758698Sjlemon 209858698Sjlemon /* 209945386Swpaul * Pack the data into the transmit ring. If we 210045386Swpaul * don't have room, set the OACTIVE flag and wait 210145386Swpaul * for the NIC to drain the ring. 210245386Swpaul */ 210345386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 210445386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 210545386Swpaul ifp->if_flags |= IFF_OACTIVE; 210645386Swpaul break; 210745386Swpaul } 210845386Swpaul 210945386Swpaul /* 211045386Swpaul * If there's a BPF listener, bounce a copy of this frame 211145386Swpaul * to him. 211245386Swpaul */ 211345386Swpaul if (ifp->if_bpf) 211445386Swpaul bpf_mtap(ifp, m_head); 211545386Swpaul } 211645386Swpaul 211745386Swpaul /* Transmit */ 211845386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 211945386Swpaul 212045386Swpaul /* 212145386Swpaul * Set a timeout in case the chip goes out to lunch. 212245386Swpaul */ 212345386Swpaul ifp->if_timer = 5; 212445386Swpaul 212545386Swpaul return; 212645386Swpaul} 212745386Swpaul 212845386Swpaulstatic void ti_init(xsc) 212945386Swpaul void *xsc; 213045386Swpaul{ 213145386Swpaul struct ti_softc *sc = xsc; 213245386Swpaul int s; 213345386Swpaul 213445386Swpaul s = splimp(); 213545386Swpaul 213645386Swpaul /* Cancel pending I/O and flush buffers. */ 213745386Swpaul ti_stop(sc); 213845386Swpaul 213945386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 214045386Swpaul if (ti_gibinit(sc)) { 214145386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 214245386Swpaul splx(s); 214345386Swpaul return; 214445386Swpaul } 214545386Swpaul 214645386Swpaul splx(s); 214745386Swpaul 214845386Swpaul return; 214945386Swpaul} 215045386Swpaul 215145386Swpaulstatic void ti_init2(sc) 215245386Swpaul struct ti_softc *sc; 215345386Swpaul{ 215445386Swpaul struct ti_cmd_desc cmd; 215545386Swpaul struct ifnet *ifp; 215645386Swpaul u_int16_t *m; 215745386Swpaul struct ifmedia *ifm; 215845386Swpaul int tmp; 215945386Swpaul 216045386Swpaul ifp = &sc->arpcom.ac_if; 216145386Swpaul 216245386Swpaul /* Specify MTU and interface index. */ 216345386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 216445386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 216545386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 216645386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 216745386Swpaul 216845386Swpaul /* Load our MAC address. */ 216945386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 217045386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 217145386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 217245386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 217345386Swpaul 217445386Swpaul /* Enable or disable promiscuous mode as needed. */ 217545386Swpaul if (ifp->if_flags & IFF_PROMISC) { 217645386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 217745386Swpaul } else { 217845386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 217945386Swpaul } 218045386Swpaul 218145386Swpaul /* Program multicast filter. */ 218245386Swpaul ti_setmulti(sc); 218345386Swpaul 218445386Swpaul /* 218545386Swpaul * If this is a Tigon 1, we should tell the 218645386Swpaul * firmware to use software packet filtering. 218745386Swpaul */ 218845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 218945386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 219045386Swpaul } 219145386Swpaul 219245386Swpaul /* Init RX ring. */ 219345386Swpaul ti_init_rx_ring_std(sc); 219445386Swpaul 219545386Swpaul /* Init jumbo RX ring. */ 219645386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 219745386Swpaul ti_init_rx_ring_jumbo(sc); 219845386Swpaul 219945386Swpaul /* 220045386Swpaul * If this is a Tigon 2, we can also configure the 220145386Swpaul * mini ring. 220245386Swpaul */ 220345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 220445386Swpaul ti_init_rx_ring_mini(sc); 220545386Swpaul 220645386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 220745386Swpaul sc->ti_rx_saved_considx = 0; 220845386Swpaul 220945386Swpaul /* Init TX ring. */ 221045386Swpaul ti_init_tx_ring(sc); 221145386Swpaul 221245386Swpaul /* Tell firmware we're alive. */ 221345386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 221445386Swpaul 221545386Swpaul /* Enable host interrupts. */ 221645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 221745386Swpaul 221845386Swpaul ifp->if_flags |= IFF_RUNNING; 221945386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 222045386Swpaul 222145386Swpaul /* 222245386Swpaul * Make sure to set media properly. We have to do this 222345386Swpaul * here since we have to issue commands in order to set 222445386Swpaul * the link negotiation and we can't issue commands until 222545386Swpaul * the firmware is running. 222645386Swpaul */ 222745386Swpaul ifm = &sc->ifmedia; 222845386Swpaul tmp = ifm->ifm_media; 222945386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 223045386Swpaul ti_ifmedia_upd(ifp); 223145386Swpaul ifm->ifm_media = tmp; 223245386Swpaul 223345386Swpaul return; 223445386Swpaul} 223545386Swpaul 223645386Swpaul/* 223745386Swpaul * Set media options. 223845386Swpaul */ 223945386Swpaulstatic int ti_ifmedia_upd(ifp) 224045386Swpaul struct ifnet *ifp; 224145386Swpaul{ 224245386Swpaul struct ti_softc *sc; 224345386Swpaul struct ifmedia *ifm; 224445386Swpaul struct ti_cmd_desc cmd; 224545386Swpaul 224645386Swpaul sc = ifp->if_softc; 224745386Swpaul ifm = &sc->ifmedia; 224845386Swpaul 224945386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 225045386Swpaul return(EINVAL); 225145386Swpaul 225245386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 225345386Swpaul case IFM_AUTO: 225445386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 225545386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 225645386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 225745386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 225845386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 225945386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 226045386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 226145386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 226245386Swpaul break; 226345386Swpaul case IFM_1000_SX: 226463699Swpaul case IFM_1000_TX: 226545386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 226663699Swpaul TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 226745386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 226863699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 226963699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 227063699Swpaul } 227145386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 227245386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 227345386Swpaul break; 227445386Swpaul case IFM_100_FX: 227545386Swpaul case IFM_10_FL: 227663699Swpaul case IFM_100_TX: 227763699Swpaul case IFM_10_T: 227845386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 227945386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 228063699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 228163699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 228245386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 228345386Swpaul } else { 228445386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 228545386Swpaul } 228645386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 228745386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 228845386Swpaul } else { 228945386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 229045386Swpaul } 229145386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 229245386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 229345386Swpaul break; 229445386Swpaul } 229545386Swpaul 229645386Swpaul return(0); 229745386Swpaul} 229845386Swpaul 229945386Swpaul/* 230045386Swpaul * Report current media status. 230145386Swpaul */ 230245386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 230345386Swpaul struct ifnet *ifp; 230445386Swpaul struct ifmediareq *ifmr; 230545386Swpaul{ 230645386Swpaul struct ti_softc *sc; 230763699Swpaul u_int32_t media = 0; 230845386Swpaul 230945386Swpaul sc = ifp->if_softc; 231045386Swpaul 231145386Swpaul ifmr->ifm_status = IFM_AVALID; 231245386Swpaul ifmr->ifm_active = IFM_ETHER; 231345386Swpaul 231445386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 231545386Swpaul return; 231645386Swpaul 231745386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 231845386Swpaul 231963699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 232063699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 232163699Swpaul if (sc->ti_copper) 232263699Swpaul ifmr->ifm_active |= IFM_1000_TX; 232363699Swpaul else 232463699Swpaul ifmr->ifm_active |= IFM_1000_SX; 232563699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 232663699Swpaul ifmr->ifm_active |= IFM_FDX; 232763699Swpaul else 232863699Swpaul ifmr->ifm_active |= IFM_HDX; 232963699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 233045386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 233163699Swpaul if (sc->ti_copper) { 233263699Swpaul if (media & TI_LNK_100MB) 233363699Swpaul ifmr->ifm_active |= IFM_100_TX; 233463699Swpaul if (media & TI_LNK_10MB) 233563699Swpaul ifmr->ifm_active |= IFM_10_T; 233663699Swpaul } else { 233763699Swpaul if (media & TI_LNK_100MB) 233863699Swpaul ifmr->ifm_active |= IFM_100_FX; 233963699Swpaul if (media & TI_LNK_10MB) 234063699Swpaul ifmr->ifm_active |= IFM_10_FL; 234163699Swpaul } 234245386Swpaul if (media & TI_LNK_FULL_DUPLEX) 234345386Swpaul ifmr->ifm_active |= IFM_FDX; 234445386Swpaul if (media & TI_LNK_HALF_DUPLEX) 234545386Swpaul ifmr->ifm_active |= IFM_HDX; 234645386Swpaul } 234745386Swpaul 234845386Swpaul return; 234945386Swpaul} 235045386Swpaul 235145386Swpaulstatic int ti_ioctl(ifp, command, data) 235245386Swpaul struct ifnet *ifp; 235345386Swpaul u_long command; 235445386Swpaul caddr_t data; 235545386Swpaul{ 235645386Swpaul struct ti_softc *sc = ifp->if_softc; 235745386Swpaul struct ifreq *ifr = (struct ifreq *) data; 235845386Swpaul int s, error = 0; 235945386Swpaul struct ti_cmd_desc cmd; 236045386Swpaul 236145386Swpaul s = splimp(); 236245386Swpaul 236345386Swpaul switch(command) { 236445386Swpaul case SIOCSIFADDR: 236545386Swpaul case SIOCGIFADDR: 236645386Swpaul error = ether_ioctl(ifp, command, data); 236745386Swpaul break; 236845386Swpaul case SIOCSIFMTU: 236945386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 237045386Swpaul error = EINVAL; 237145386Swpaul else { 237245386Swpaul ifp->if_mtu = ifr->ifr_mtu; 237345386Swpaul ti_init(sc); 237445386Swpaul } 237545386Swpaul break; 237645386Swpaul case SIOCSIFFLAGS: 237745386Swpaul if (ifp->if_flags & IFF_UP) { 237845386Swpaul /* 237945386Swpaul * If only the state of the PROMISC flag changed, 238045386Swpaul * then just use the 'set promisc mode' command 238145386Swpaul * instead of reinitializing the entire NIC. Doing 238245386Swpaul * a full re-init means reloading the firmware and 238345386Swpaul * waiting for it to start up, which may take a 238445386Swpaul * second or two. 238545386Swpaul */ 238645386Swpaul if (ifp->if_flags & IFF_RUNNING && 238745386Swpaul ifp->if_flags & IFF_PROMISC && 238845386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 238945386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 239045386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 239145386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 239245386Swpaul !(ifp->if_flags & IFF_PROMISC) && 239345386Swpaul sc->ti_if_flags & IFF_PROMISC) { 239445386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 239545386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 239645386Swpaul } else 239745386Swpaul ti_init(sc); 239845386Swpaul } else { 239945386Swpaul if (ifp->if_flags & IFF_RUNNING) { 240045386Swpaul ti_stop(sc); 240145386Swpaul } 240245386Swpaul } 240345386Swpaul sc->ti_if_flags = ifp->if_flags; 240445386Swpaul error = 0; 240545386Swpaul break; 240645386Swpaul case SIOCADDMULTI: 240745386Swpaul case SIOCDELMULTI: 240845386Swpaul if (ifp->if_flags & IFF_RUNNING) { 240945386Swpaul ti_setmulti(sc); 241045386Swpaul error = 0; 241145386Swpaul } 241245386Swpaul break; 241345386Swpaul case SIOCSIFMEDIA: 241445386Swpaul case SIOCGIFMEDIA: 241545386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 241645386Swpaul break; 241745386Swpaul default: 241845386Swpaul error = EINVAL; 241945386Swpaul break; 242045386Swpaul } 242145386Swpaul 242245386Swpaul (void)splx(s); 242345386Swpaul 242445386Swpaul return(error); 242545386Swpaul} 242645386Swpaul 242745386Swpaulstatic void ti_watchdog(ifp) 242845386Swpaul struct ifnet *ifp; 242945386Swpaul{ 243045386Swpaul struct ti_softc *sc; 243145386Swpaul 243245386Swpaul sc = ifp->if_softc; 243345386Swpaul 243445386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 243545386Swpaul ti_stop(sc); 243645386Swpaul ti_init(sc); 243745386Swpaul 243845386Swpaul ifp->if_oerrors++; 243945386Swpaul 244045386Swpaul return; 244145386Swpaul} 244245386Swpaul 244345386Swpaul/* 244445386Swpaul * Stop the adapter and free any mbufs allocated to the 244545386Swpaul * RX and TX lists. 244645386Swpaul */ 244745386Swpaulstatic void ti_stop(sc) 244845386Swpaul struct ti_softc *sc; 244945386Swpaul{ 245045386Swpaul struct ifnet *ifp; 245145386Swpaul struct ti_cmd_desc cmd; 245245386Swpaul 245345386Swpaul ifp = &sc->arpcom.ac_if; 245445386Swpaul 245545386Swpaul /* Disable host interrupts. */ 245645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 245745386Swpaul /* 245845386Swpaul * Tell firmware we're shutting down. 245945386Swpaul */ 246045386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 246145386Swpaul 246245386Swpaul /* Halt and reinitialize. */ 246345386Swpaul ti_chipinit(sc); 246445386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 246545386Swpaul ti_chipinit(sc); 246645386Swpaul 246745386Swpaul /* Free the RX lists. */ 246845386Swpaul ti_free_rx_ring_std(sc); 246945386Swpaul 247045386Swpaul /* Free jumbo RX list. */ 247145386Swpaul ti_free_rx_ring_jumbo(sc); 247245386Swpaul 247345386Swpaul /* Free mini RX list. */ 247445386Swpaul ti_free_rx_ring_mini(sc); 247545386Swpaul 247645386Swpaul /* Free TX buffers. */ 247745386Swpaul ti_free_tx_ring(sc); 247845386Swpaul 247945386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 248045386Swpaul sc->ti_return_prodidx.ti_idx = 0; 248145386Swpaul sc->ti_tx_considx.ti_idx = 0; 248245386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 248345386Swpaul 248445386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 248545386Swpaul 248645386Swpaul return; 248745386Swpaul} 248845386Swpaul 248945386Swpaul/* 249045386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 249145386Swpaul * get confused by errant DMAs when rebooting. 249245386Swpaul */ 249349011Swpaulstatic void ti_shutdown(dev) 249449011Swpaul device_t dev; 249545386Swpaul{ 249645386Swpaul struct ti_softc *sc; 249745386Swpaul 249849011Swpaul sc = device_get_softc(dev); 249945386Swpaul 250045386Swpaul ti_chipinit(sc); 250145386Swpaul 250245386Swpaul return; 250345386Swpaul} 2504