if_ti.c revision 64139
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 64139 2000-08-02 18:49:17Z wpaul $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include "vlan.h" 8245386Swpaul 8345386Swpaul#include <sys/param.h> 8445386Swpaul#include <sys/systm.h> 8545386Swpaul#include <sys/sockio.h> 8645386Swpaul#include <sys/mbuf.h> 8745386Swpaul#include <sys/malloc.h> 8845386Swpaul#include <sys/kernel.h> 8945386Swpaul#include <sys/socket.h> 9045386Swpaul#include <sys/queue.h> 9145386Swpaul 9245386Swpaul#include <net/if.h> 9345386Swpaul#include <net/if_arp.h> 9445386Swpaul#include <net/ethernet.h> 9545386Swpaul#include <net/if_dl.h> 9645386Swpaul#include <net/if_media.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#if NVLAN > 0 10145386Swpaul#include <net/if_types.h> 10245386Swpaul#include <net/if_vlan_var.h> 10345386Swpaul#endif 10445386Swpaul 10545386Swpaul#include <netinet/in_systm.h> 10645386Swpaul#include <netinet/in.h> 10745386Swpaul#include <netinet/ip.h> 10845386Swpaul 10945386Swpaul#include <vm/vm.h> /* for vtophys */ 11045386Swpaul#include <vm/pmap.h> /* for vtophys */ 11145386Swpaul#include <machine/clock.h> /* for DELAY */ 11245386Swpaul#include <machine/bus_memio.h> 11345386Swpaul#include <machine/bus.h> 11449011Swpaul#include <machine/resource.h> 11549011Swpaul#include <sys/bus.h> 11649011Swpaul#include <sys/rman.h> 11745386Swpaul 11845386Swpaul#include <pci/pcireg.h> 11945386Swpaul#include <pci/pcivar.h> 12045386Swpaul 12145386Swpaul#include <pci/if_tireg.h> 12245386Swpaul#include <pci/ti_fw.h> 12345386Swpaul#include <pci/ti_fw2.h> 12445386Swpaul 12558698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12645386Swpaul 12745386Swpaul#if !defined(lint) 12845386Swpaulstatic const char rcsid[] = 12950477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 64139 2000-08-02 18:49:17Z wpaul $"; 13045386Swpaul#endif 13145386Swpaul 13245386Swpaul/* 13345386Swpaul * Various supported device vendors/types and their names. 13445386Swpaul */ 13545386Swpaul 13645386Swpaulstatic struct ti_type ti_devs[] = { 13745386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13863702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 13963699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 14063702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 14145386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 14245386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 14345386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 14464139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 14564139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 14664139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 14745386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14845386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14956206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 15056206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 15145386Swpaul { 0, 0, NULL } 15245386Swpaul}; 15345386Swpaul 15449011Swpaulstatic int ti_probe __P((device_t)); 15549011Swpaulstatic int ti_attach __P((device_t)); 15649011Swpaulstatic int ti_detach __P((device_t)); 15745386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15845386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15945386Swpaul 16045386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 16145386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 16245386Swpaul u_int32_t *)); 16345386Swpaul 16445386Swpaulstatic void ti_intr __P((void *)); 16545386Swpaulstatic void ti_start __P((struct ifnet *)); 16645386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16745386Swpaulstatic void ti_init __P((void *)); 16845386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16945386Swpaulstatic void ti_stop __P((struct ti_softc *)); 17045386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 17149011Swpaulstatic void ti_shutdown __P((device_t)); 17245386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 17345386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17445386Swpaul 17545386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17645386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17745386Swpaul int, u_int8_t *)); 17845386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17945386Swpaul 18045386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 18145386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 18245386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 18345386Swpaul 18445386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18545386Swpaul u_int32_t, caddr_t)); 18645386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18745386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18845386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18945386Swpaul caddr_t, int)); 19045386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 19145386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 19245386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 19345386Swpaulstatic void ti_jfree __P((caddr_t, u_int)); 19445386Swpaulstatic void ti_jref __P((caddr_t, u_int)); 19545386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19645386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19745386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19845386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19945386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 20045386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 20145386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 20245386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 20345386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20445386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 20545386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 20645386Swpaul 20745386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20845386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20945386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 21045386Swpaul 21149011Swpaulstatic device_method_t ti_methods[] = { 21249011Swpaul /* Device interface */ 21349011Swpaul DEVMETHOD(device_probe, ti_probe), 21449011Swpaul DEVMETHOD(device_attach, ti_attach), 21549011Swpaul DEVMETHOD(device_detach, ti_detach), 21649011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 21749011Swpaul { 0, 0 } 21849011Swpaul}; 21949011Swpaul 22049011Swpaulstatic driver_t ti_driver = { 22151455Swpaul "ti", 22249011Swpaul ti_methods, 22349011Swpaul sizeof(struct ti_softc) 22449011Swpaul}; 22549011Swpaul 22649011Swpaulstatic devclass_t ti_devclass; 22749011Swpaul 22851533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22949011Swpaul 23045386Swpaul/* 23145386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 23245386Swpaul */ 23345386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 23445386Swpaul struct ti_softc *sc; 23545386Swpaul int byte; 23645386Swpaul{ 23745386Swpaul register int i, ack = 0; 23845386Swpaul 23945386Swpaul /* 24045386Swpaul * Make sure we're in TX mode. 24145386Swpaul */ 24245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 24345386Swpaul 24445386Swpaul /* 24545386Swpaul * Feed in each bit and stobe the clock. 24645386Swpaul */ 24745386Swpaul for (i = 0x80; i; i >>= 1) { 24845386Swpaul if (byte & i) { 24945386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 25045386Swpaul } else { 25145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 25245386Swpaul } 25345386Swpaul DELAY(1); 25445386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25545386Swpaul DELAY(1); 25645386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25745386Swpaul } 25845386Swpaul 25945386Swpaul /* 26045386Swpaul * Turn off TX mode. 26145386Swpaul */ 26245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 26345386Swpaul 26445386Swpaul /* 26545386Swpaul * Check for ack. 26645386Swpaul */ 26745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26845386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26945386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 27045386Swpaul 27145386Swpaul return(ack); 27245386Swpaul} 27345386Swpaul 27445386Swpaul/* 27545386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 27645386Swpaul * We have to send two address bytes since the EEPROM can hold 27745386Swpaul * more than 256 bytes of data. 27845386Swpaul */ 27945386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 28045386Swpaul struct ti_softc *sc; 28145386Swpaul int addr; 28245386Swpaul u_int8_t *dest; 28345386Swpaul{ 28445386Swpaul register int i; 28545386Swpaul u_int8_t byte = 0; 28645386Swpaul 28745386Swpaul EEPROM_START; 28845386Swpaul 28945386Swpaul /* 29045386Swpaul * Send write control code to EEPROM. 29145386Swpaul */ 29245386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 29345386Swpaul printf("ti%d: failed to send write command, status: %x\n", 29445386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29545386Swpaul return(1); 29645386Swpaul } 29745386Swpaul 29845386Swpaul /* 29945386Swpaul * Send first byte of address of byte we want to read. 30045386Swpaul */ 30145386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 30245386Swpaul printf("ti%d: failed to send address, status: %x\n", 30345386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30445386Swpaul return(1); 30545386Swpaul } 30645386Swpaul /* 30745386Swpaul * Send second byte address of byte we want to read. 30845386Swpaul */ 30945386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 31045386Swpaul printf("ti%d: failed to send address, status: %x\n", 31145386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31245386Swpaul return(1); 31345386Swpaul } 31445386Swpaul 31545386Swpaul EEPROM_STOP; 31645386Swpaul EEPROM_START; 31745386Swpaul /* 31845386Swpaul * Send read control code to EEPROM. 31945386Swpaul */ 32045386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 32145386Swpaul printf("ti%d: failed to send read command, status: %x\n", 32245386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 32345386Swpaul return(1); 32445386Swpaul } 32545386Swpaul 32645386Swpaul /* 32745386Swpaul * Start reading bits from EEPROM. 32845386Swpaul */ 32945386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 33045386Swpaul for (i = 0x80; i; i >>= 1) { 33145386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33245386Swpaul DELAY(1); 33345386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 33445386Swpaul byte |= i; 33545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33645386Swpaul DELAY(1); 33745386Swpaul } 33845386Swpaul 33945386Swpaul EEPROM_STOP; 34045386Swpaul 34145386Swpaul /* 34245386Swpaul * No ACK generated for read, so just return byte. 34345386Swpaul */ 34445386Swpaul 34545386Swpaul *dest = byte; 34645386Swpaul 34745386Swpaul return(0); 34845386Swpaul} 34945386Swpaul 35045386Swpaul/* 35145386Swpaul * Read a sequence of bytes from the EEPROM. 35245386Swpaul */ 35345386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 35445386Swpaul struct ti_softc *sc; 35545386Swpaul caddr_t dest; 35645386Swpaul int off; 35745386Swpaul int cnt; 35845386Swpaul{ 35945386Swpaul int err = 0, i; 36045386Swpaul u_int8_t byte = 0; 36145386Swpaul 36245386Swpaul for (i = 0; i < cnt; i++) { 36345386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 36445386Swpaul if (err) 36545386Swpaul break; 36645386Swpaul *(dest + i) = byte; 36745386Swpaul } 36845386Swpaul 36945386Swpaul return(err ? 1 : 0); 37045386Swpaul} 37145386Swpaul 37245386Swpaul/* 37345386Swpaul * NIC memory access function. Can be used to either clear a section 37445386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 37545386Swpaul */ 37645386Swpaulstatic void ti_mem(sc, addr, len, buf) 37745386Swpaul struct ti_softc *sc; 37845386Swpaul u_int32_t addr, len; 37945386Swpaul caddr_t buf; 38045386Swpaul{ 38145386Swpaul int segptr, segsize, cnt; 38245386Swpaul caddr_t ti_winbase, ptr; 38345386Swpaul 38445386Swpaul segptr = addr; 38545386Swpaul cnt = len; 38649133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 38745386Swpaul ptr = buf; 38845386Swpaul 38945386Swpaul while(cnt) { 39045386Swpaul if (cnt < TI_WINLEN) 39145386Swpaul segsize = cnt; 39245386Swpaul else 39345386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 39445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 39545386Swpaul if (buf == NULL) 39645386Swpaul bzero((char *)ti_winbase + (segptr & 39745386Swpaul (TI_WINLEN - 1)), segsize); 39845386Swpaul else { 39945386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 40045386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 40145386Swpaul ptr += segsize; 40245386Swpaul } 40345386Swpaul segptr += segsize; 40445386Swpaul cnt -= segsize; 40545386Swpaul } 40645386Swpaul 40745386Swpaul return; 40845386Swpaul} 40945386Swpaul 41045386Swpaul/* 41145386Swpaul * Load firmware image into the NIC. Check that the firmware revision 41245386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 41345386Swpaul * Tigon 2. 41445386Swpaul */ 41545386Swpaulstatic void ti_loadfw(sc) 41645386Swpaul struct ti_softc *sc; 41745386Swpaul{ 41845386Swpaul switch(sc->ti_hwrev) { 41945386Swpaul case TI_HWREV_TIGON: 42045386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 42145386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 42245386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 42345386Swpaul printf("ti%d: firmware revision mismatch; want " 42445386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 42545386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 42645386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 42745386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 42845386Swpaul return; 42945386Swpaul } 43045386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 43145386Swpaul (caddr_t)tigonFwText); 43245386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 43345386Swpaul (caddr_t)tigonFwData); 43445386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 43545386Swpaul (caddr_t)tigonFwRodata); 43645386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 43745386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 43845386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43945386Swpaul break; 44045386Swpaul case TI_HWREV_TIGON_II: 44145386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 44245386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 44345386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 44445386Swpaul printf("ti%d: firmware revision mismatch; want " 44545386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 44645386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 44745386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 44845386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44945386Swpaul return; 45045386Swpaul } 45145386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 45245386Swpaul (caddr_t)tigon2FwText); 45345386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 45445386Swpaul (caddr_t)tigon2FwData); 45545386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 45645386Swpaul (caddr_t)tigon2FwRodata); 45745386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 45845386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45945386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 46045386Swpaul break; 46145386Swpaul default: 46245386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 46345386Swpaul sc->ti_unit); 46445386Swpaul break; 46545386Swpaul } 46645386Swpaul 46745386Swpaul return; 46845386Swpaul} 46945386Swpaul 47045386Swpaul/* 47145386Swpaul * Send the NIC a command via the command ring. 47245386Swpaul */ 47345386Swpaulstatic void ti_cmd(sc, cmd) 47445386Swpaul struct ti_softc *sc; 47545386Swpaul struct ti_cmd_desc *cmd; 47645386Swpaul{ 47745386Swpaul u_int32_t index; 47845386Swpaul 47945386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 48045386Swpaul return; 48145386Swpaul 48245386Swpaul index = sc->ti_cmd_saved_prodidx; 48345386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 48445386Swpaul TI_INC(index, TI_CMD_RING_CNT); 48545386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 48645386Swpaul sc->ti_cmd_saved_prodidx = index; 48745386Swpaul 48845386Swpaul return; 48945386Swpaul} 49045386Swpaul 49145386Swpaul/* 49245386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 49345386Swpaul * number of command slots to include after the initial command. 49445386Swpaul */ 49545386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 49645386Swpaul struct ti_softc *sc; 49745386Swpaul struct ti_cmd_desc *cmd; 49845386Swpaul caddr_t arg; 49945386Swpaul int len; 50045386Swpaul{ 50145386Swpaul u_int32_t index; 50245386Swpaul register int i; 50345386Swpaul 50445386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 50545386Swpaul return; 50645386Swpaul 50745386Swpaul index = sc->ti_cmd_saved_prodidx; 50845386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50945386Swpaul TI_INC(index, TI_CMD_RING_CNT); 51045386Swpaul for (i = 0; i < len; i++) { 51145386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 51245386Swpaul *(u_int32_t *)(&arg[i * 4])); 51345386Swpaul TI_INC(index, TI_CMD_RING_CNT); 51445386Swpaul } 51545386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 51645386Swpaul sc->ti_cmd_saved_prodidx = index; 51745386Swpaul 51845386Swpaul return; 51945386Swpaul} 52045386Swpaul 52145386Swpaul/* 52245386Swpaul * Handle events that have triggered interrupts. 52345386Swpaul */ 52445386Swpaulstatic void ti_handle_events(sc) 52545386Swpaul struct ti_softc *sc; 52645386Swpaul{ 52745386Swpaul struct ti_event_desc *e; 52845386Swpaul 52945386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 53045386Swpaul return; 53145386Swpaul 53245386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 53345386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 53445386Swpaul switch(e->ti_event) { 53545386Swpaul case TI_EV_LINKSTAT_CHANGED: 53645386Swpaul sc->ti_linkstat = e->ti_code; 53745386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 53845386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53945386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 54045386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 54145386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 54245386Swpaul printf("ti%d: link down\n", sc->ti_unit); 54345386Swpaul break; 54445386Swpaul case TI_EV_ERROR: 54545386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 54645386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 54745386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 54845386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54945386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 55045386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 55145386Swpaul break; 55245386Swpaul case TI_EV_FIRMWARE_UP: 55345386Swpaul ti_init2(sc); 55445386Swpaul break; 55545386Swpaul case TI_EV_STATS_UPDATED: 55645386Swpaul ti_stats_update(sc); 55745386Swpaul break; 55845386Swpaul case TI_EV_RESET_JUMBO_RING: 55945386Swpaul case TI_EV_MCAST_UPDATED: 56045386Swpaul /* Who cares. */ 56145386Swpaul break; 56245386Swpaul default: 56345386Swpaul printf("ti%d: unknown event: %d\n", 56445386Swpaul sc->ti_unit, e->ti_event); 56545386Swpaul break; 56645386Swpaul } 56745386Swpaul /* Advance the consumer index. */ 56845386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56945386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 57045386Swpaul } 57145386Swpaul 57245386Swpaul return; 57345386Swpaul} 57445386Swpaul 57545386Swpaul/* 57645386Swpaul * Memory management for the jumbo receive ring is a pain in the 57745386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 57845386Swpaul * _and_ it has to be contiguous (unless you use the extended 57945386Swpaul * jumbo descriptor format). Using malloc() all the time won't 58045386Swpaul * work: malloc() allocates memory in powers of two, which means we 58145386Swpaul * would end up wasting a considerable amount of space by allocating 58245386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 58345386Swpaul * to do our own memory management. 58445386Swpaul * 58545386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 58645386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 58745386Swpaul * as external mbuf storage. 58845386Swpaul * 58945386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 59045386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 59145386Swpaul * RAM. This is a bit much, especially considering we also need 59245386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 59345386Swpaul * save space, we only actually allocate enough memory for 64 slots 59445386Swpaul * by default, which works out to between 500 and 600K. This can 59545386Swpaul * be tuned by changing a #define in if_tireg.h. 59645386Swpaul */ 59745386Swpaul 59845386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59945386Swpaul struct ti_softc *sc; 60045386Swpaul{ 60145386Swpaul caddr_t ptr; 60245386Swpaul register int i; 60345386Swpaul struct ti_jpool_entry *entry; 60445386Swpaul 60545386Swpaul /* Grab a big chunk o' storage. */ 60645386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 60750548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 60845386Swpaul 60945386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 61045386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 61145386Swpaul return(ENOBUFS); 61245386Swpaul } 61345386Swpaul 61445386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 61545386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 61645386Swpaul 61745386Swpaul /* 61845386Swpaul * Now divide it up into 9K pieces and save the addresses 61945386Swpaul * in an array. Note that we play an evil trick here by using 62045386Swpaul * the first few bytes in the buffer to hold the the address 62145386Swpaul * of the softc structure for this interface. This is because 62245386Swpaul * ti_jfree() needs it, but it is called by the mbuf management 62345386Swpaul * code which will not pass it to us explicitly. 62445386Swpaul */ 62545386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 62645386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 62745386Swpaul u_int64_t **aptr; 62845386Swpaul aptr = (u_int64_t **)ptr; 62945386Swpaul aptr[0] = (u_int64_t *)sc; 63045386Swpaul ptr += sizeof(u_int64_t); 63145386Swpaul sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 63245386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 63345386Swpaul ptr += (TI_JLEN - sizeof(u_int64_t)); 63445386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 63545386Swpaul M_DEVBUF, M_NOWAIT); 63645386Swpaul if (entry == NULL) { 63762793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 63862793Sgallatin M_DEVBUF); 63945386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 64045386Swpaul printf("ti%d: no memory for jumbo " 64145386Swpaul "buffer queue!\n", sc->ti_unit); 64245386Swpaul return(ENOBUFS); 64345386Swpaul } 64445386Swpaul entry->slot = i; 64545386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 64645386Swpaul } 64745386Swpaul 64845386Swpaul return(0); 64945386Swpaul} 65045386Swpaul 65145386Swpaul/* 65245386Swpaul * Allocate a jumbo buffer. 65345386Swpaul */ 65445386Swpaulstatic void *ti_jalloc(sc) 65545386Swpaul struct ti_softc *sc; 65645386Swpaul{ 65745386Swpaul struct ti_jpool_entry *entry; 65845386Swpaul 65945386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 66045386Swpaul 66145386Swpaul if (entry == NULL) { 66245386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 66345386Swpaul return(NULL); 66445386Swpaul } 66545386Swpaul 66645386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 66745386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 66845386Swpaul sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 66945386Swpaul return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 67045386Swpaul} 67145386Swpaul 67245386Swpaul/* 67345386Swpaul * Adjust usage count on a jumbo buffer. In general this doesn't 67445386Swpaul * get used much because our jumbo buffers don't get passed around 67545386Swpaul * too much, but it's implemented for correctness. 67645386Swpaul */ 67745386Swpaulstatic void ti_jref(buf, size) 67845386Swpaul caddr_t buf; 67945386Swpaul u_int size; 68045386Swpaul{ 68145386Swpaul struct ti_softc *sc; 68245386Swpaul u_int64_t **aptr; 68345386Swpaul register int i; 68445386Swpaul 68545386Swpaul /* Extract the softc struct pointer. */ 68645386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 68745386Swpaul sc = (struct ti_softc *)(aptr[0]); 68845386Swpaul 68945386Swpaul if (sc == NULL) 69045386Swpaul panic("ti_jref: can't find softc pointer!"); 69145386Swpaul 69249036Swpaul if (size != TI_JUMBO_FRAMELEN) 69345386Swpaul panic("ti_jref: adjusting refcount of buf of wrong size!"); 69445386Swpaul 69545386Swpaul /* calculate the slot this buffer belongs to */ 69645386Swpaul 69745386Swpaul i = ((vm_offset_t)aptr 69845386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 69945386Swpaul 70045386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 70145386Swpaul panic("ti_jref: asked to reference buffer " 70245386Swpaul "that we don't manage!"); 70345386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 70445386Swpaul panic("ti_jref: buffer already free!"); 70545386Swpaul else 70645386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse++; 70745386Swpaul 70845386Swpaul return; 70945386Swpaul} 71045386Swpaul 71145386Swpaul/* 71245386Swpaul * Release a jumbo buffer. 71345386Swpaul */ 71445386Swpaulstatic void ti_jfree(buf, size) 71545386Swpaul caddr_t buf; 71645386Swpaul u_int size; 71745386Swpaul{ 71845386Swpaul struct ti_softc *sc; 71945386Swpaul u_int64_t **aptr; 72045386Swpaul int i; 72145386Swpaul struct ti_jpool_entry *entry; 72245386Swpaul 72345386Swpaul /* Extract the softc struct pointer. */ 72445386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 72545386Swpaul sc = (struct ti_softc *)(aptr[0]); 72645386Swpaul 72745386Swpaul if (sc == NULL) 72845386Swpaul panic("ti_jfree: can't find softc pointer!"); 72945386Swpaul 73049036Swpaul if (size != TI_JUMBO_FRAMELEN) 73145386Swpaul panic("ti_jfree: freeing buffer of wrong size!"); 73245386Swpaul 73345386Swpaul /* calculate the slot this buffer belongs to */ 73445386Swpaul 73545386Swpaul i = ((vm_offset_t)aptr 73645386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 73745386Swpaul 73845386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 73945386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 74045386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 74145386Swpaul panic("ti_jfree: buffer already free!"); 74245386Swpaul else { 74345386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse--; 74445386Swpaul if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 74545386Swpaul entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 74645386Swpaul if (entry == NULL) 74745386Swpaul panic("ti_jfree: buffer not in use!"); 74845386Swpaul entry->slot = i; 74945386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 75045386Swpaul jpool_entries); 75145386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 75245386Swpaul entry, jpool_entries); 75345386Swpaul } 75445386Swpaul } 75545386Swpaul 75645386Swpaul return; 75745386Swpaul} 75845386Swpaul 75945386Swpaul 76045386Swpaul/* 76145386Swpaul * Intialize a standard receive ring descriptor. 76245386Swpaul */ 76345386Swpaulstatic int ti_newbuf_std(sc, i, m) 76445386Swpaul struct ti_softc *sc; 76545386Swpaul int i; 76645386Swpaul struct mbuf *m; 76745386Swpaul{ 76845386Swpaul struct mbuf *m_new = NULL; 76945386Swpaul struct ti_rx_desc *r; 77045386Swpaul 77149036Swpaul if (m == NULL) { 77245386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 77345386Swpaul if (m_new == NULL) { 77445386Swpaul printf("ti%d: mbuf allocation failed " 77545386Swpaul "-- packet dropped!\n", sc->ti_unit); 77645386Swpaul return(ENOBUFS); 77745386Swpaul } 77845386Swpaul 77945386Swpaul MCLGET(m_new, M_DONTWAIT); 78045386Swpaul if (!(m_new->m_flags & M_EXT)) { 78145386Swpaul printf("ti%d: cluster allocation failed " 78245386Swpaul "-- packet dropped!\n", sc->ti_unit); 78345386Swpaul m_freem(m_new); 78445386Swpaul return(ENOBUFS); 78545386Swpaul } 78649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 78749036Swpaul } else { 78849036Swpaul m_new = m; 78949036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 79049036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 79145386Swpaul } 79245386Swpaul 79348597Swpaul m_adj(m_new, ETHER_ALIGN); 79445386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 79545386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 79645386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 79745386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 79845386Swpaul r->ti_flags = 0; 79958698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 80058698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 80149036Swpaul r->ti_len = m_new->m_len; 80245386Swpaul r->ti_idx = i; 80345386Swpaul 80445386Swpaul return(0); 80545386Swpaul} 80645386Swpaul 80745386Swpaul/* 80845386Swpaul * Intialize a mini receive ring descriptor. This only applies to 80945386Swpaul * the Tigon 2. 81045386Swpaul */ 81145386Swpaulstatic int ti_newbuf_mini(sc, i, m) 81245386Swpaul struct ti_softc *sc; 81345386Swpaul int i; 81445386Swpaul struct mbuf *m; 81545386Swpaul{ 81645386Swpaul struct mbuf *m_new = NULL; 81745386Swpaul struct ti_rx_desc *r; 81845386Swpaul 81949036Swpaul if (m == NULL) { 82045386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 82145386Swpaul if (m_new == NULL) { 82245386Swpaul printf("ti%d: mbuf allocation failed " 82345386Swpaul "-- packet dropped!\n", sc->ti_unit); 82445386Swpaul return(ENOBUFS); 82545386Swpaul } 82649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 82749036Swpaul } else { 82849036Swpaul m_new = m; 82949036Swpaul m_new->m_data = m_new->m_pktdat; 83049036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 83145386Swpaul } 83249036Swpaul 83348597Swpaul m_adj(m_new, ETHER_ALIGN); 83445386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 83545386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 83645386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 83745386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 83845386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 83958698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 84058698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 84149036Swpaul r->ti_len = m_new->m_len; 84245386Swpaul r->ti_idx = i; 84345386Swpaul 84445386Swpaul return(0); 84545386Swpaul} 84645386Swpaul 84745386Swpaul/* 84845386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 84945386Swpaul * a jumbo buffer from the pool managed internally by the driver. 85045386Swpaul */ 85145386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 85245386Swpaul struct ti_softc *sc; 85345386Swpaul int i; 85445386Swpaul struct mbuf *m; 85545386Swpaul{ 85645386Swpaul struct mbuf *m_new = NULL; 85745386Swpaul struct ti_rx_desc *r; 85845386Swpaul 85949036Swpaul if (m == NULL) { 86045386Swpaul caddr_t *buf = NULL; 86145386Swpaul 86245386Swpaul /* Allocate the mbuf. */ 86345386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 86445386Swpaul if (m_new == NULL) { 86545386Swpaul printf("ti%d: mbuf allocation failed " 86645386Swpaul "-- packet dropped!\n", sc->ti_unit); 86745386Swpaul return(ENOBUFS); 86845386Swpaul } 86945386Swpaul 87045386Swpaul /* Allocate the jumbo buffer */ 87145386Swpaul buf = ti_jalloc(sc); 87245386Swpaul if (buf == NULL) { 87345386Swpaul m_freem(m_new); 87445386Swpaul printf("ti%d: jumbo allocation failed " 87545386Swpaul "-- packet dropped!\n", sc->ti_unit); 87645386Swpaul return(ENOBUFS); 87745386Swpaul } 87845386Swpaul 87945386Swpaul /* Attach the buffer to the mbuf. */ 88045386Swpaul m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 88145386Swpaul m_new->m_flags |= M_EXT; 88249036Swpaul m_new->m_len = m_new->m_pkthdr.len = 88349036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 88445386Swpaul m_new->m_ext.ext_free = ti_jfree; 88545386Swpaul m_new->m_ext.ext_ref = ti_jref; 88649036Swpaul } else { 88749036Swpaul m_new = m; 88849036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 88949036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 89045386Swpaul } 89145386Swpaul 89249780Swpaul m_adj(m_new, ETHER_ALIGN); 89345386Swpaul /* Set up the descriptor. */ 89445386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 89545386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 89645386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 89745386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 89845386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 89958698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 90058698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 90149036Swpaul r->ti_len = m_new->m_len; 90245386Swpaul r->ti_idx = i; 90345386Swpaul 90445386Swpaul return(0); 90545386Swpaul} 90645386Swpaul 90745386Swpaul/* 90845386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 90945386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 91045386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 91145386Swpaul * the NIC. 91245386Swpaul */ 91345386Swpaulstatic int ti_init_rx_ring_std(sc) 91445386Swpaul struct ti_softc *sc; 91545386Swpaul{ 91645386Swpaul register int i; 91745386Swpaul struct ti_cmd_desc cmd; 91845386Swpaul 91945386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 92045386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 92145386Swpaul return(ENOBUFS); 92245386Swpaul }; 92345386Swpaul 92445386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 92548597Swpaul sc->ti_std = i - 1; 92645386Swpaul 92745386Swpaul return(0); 92845386Swpaul} 92945386Swpaul 93045386Swpaulstatic void ti_free_rx_ring_std(sc) 93145386Swpaul struct ti_softc *sc; 93245386Swpaul{ 93345386Swpaul register int i; 93445386Swpaul 93545386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 93645386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 93745386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 93845386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 93945386Swpaul } 94045386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 94145386Swpaul sizeof(struct ti_rx_desc)); 94245386Swpaul } 94345386Swpaul 94445386Swpaul return; 94545386Swpaul} 94645386Swpaul 94745386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 94845386Swpaul struct ti_softc *sc; 94945386Swpaul{ 95045386Swpaul register int i; 95145386Swpaul struct ti_cmd_desc cmd; 95245386Swpaul 95363699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 95445386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 95545386Swpaul return(ENOBUFS); 95645386Swpaul }; 95745386Swpaul 95845386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 95948597Swpaul sc->ti_jumbo = i - 1; 96045386Swpaul 96145386Swpaul return(0); 96245386Swpaul} 96345386Swpaul 96445386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 96545386Swpaul struct ti_softc *sc; 96645386Swpaul{ 96745386Swpaul register int i; 96845386Swpaul 96945386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 97045386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 97145386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 97245386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 97345386Swpaul } 97445386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 97545386Swpaul sizeof(struct ti_rx_desc)); 97645386Swpaul } 97745386Swpaul 97845386Swpaul return; 97945386Swpaul} 98045386Swpaul 98145386Swpaulstatic int ti_init_rx_ring_mini(sc) 98245386Swpaul struct ti_softc *sc; 98345386Swpaul{ 98445386Swpaul register int i; 98545386Swpaul 98645386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 98745386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 98845386Swpaul return(ENOBUFS); 98945386Swpaul }; 99045386Swpaul 99145386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 99248597Swpaul sc->ti_mini = i - 1; 99345386Swpaul 99445386Swpaul return(0); 99545386Swpaul} 99645386Swpaul 99745386Swpaulstatic void ti_free_rx_ring_mini(sc) 99845386Swpaul struct ti_softc *sc; 99945386Swpaul{ 100045386Swpaul register int i; 100145386Swpaul 100245386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 100345386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 100445386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 100545386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 100645386Swpaul } 100745386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 100845386Swpaul sizeof(struct ti_rx_desc)); 100945386Swpaul } 101045386Swpaul 101145386Swpaul return; 101245386Swpaul} 101345386Swpaul 101445386Swpaulstatic void ti_free_tx_ring(sc) 101545386Swpaul struct ti_softc *sc; 101645386Swpaul{ 101745386Swpaul register int i; 101845386Swpaul 101945386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 102045386Swpaul return; 102145386Swpaul 102245386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 102345386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 102445386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 102545386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 102645386Swpaul } 102745386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 102845386Swpaul sizeof(struct ti_tx_desc)); 102945386Swpaul } 103045386Swpaul 103145386Swpaul return; 103245386Swpaul} 103345386Swpaul 103445386Swpaulstatic int ti_init_tx_ring(sc) 103545386Swpaul struct ti_softc *sc; 103645386Swpaul{ 103748011Swpaul sc->ti_txcnt = 0; 103845386Swpaul sc->ti_tx_saved_considx = 0; 103945386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 104045386Swpaul return(0); 104145386Swpaul} 104245386Swpaul 104345386Swpaul/* 104445386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 104545386Swpaul * but we have to support the old way too so that Tigon 1 cards will 104645386Swpaul * work. 104745386Swpaul */ 104845386Swpaulvoid ti_add_mcast(sc, addr) 104945386Swpaul struct ti_softc *sc; 105045386Swpaul struct ether_addr *addr; 105145386Swpaul{ 105245386Swpaul struct ti_cmd_desc cmd; 105345386Swpaul u_int16_t *m; 105445386Swpaul u_int32_t ext[2] = {0, 0}; 105545386Swpaul 105645386Swpaul m = (u_int16_t *)&addr->octet[0]; 105745386Swpaul 105845386Swpaul switch(sc->ti_hwrev) { 105945386Swpaul case TI_HWREV_TIGON: 106045386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 106145386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 106245386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 106345386Swpaul break; 106445386Swpaul case TI_HWREV_TIGON_II: 106545386Swpaul ext[0] = htons(m[0]); 106645386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 106745386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 106845386Swpaul break; 106945386Swpaul default: 107045386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 107145386Swpaul break; 107245386Swpaul } 107345386Swpaul 107445386Swpaul return; 107545386Swpaul} 107645386Swpaul 107745386Swpaulvoid ti_del_mcast(sc, addr) 107845386Swpaul struct ti_softc *sc; 107945386Swpaul struct ether_addr *addr; 108045386Swpaul{ 108145386Swpaul struct ti_cmd_desc cmd; 108245386Swpaul u_int16_t *m; 108345386Swpaul u_int32_t ext[2] = {0, 0}; 108445386Swpaul 108545386Swpaul m = (u_int16_t *)&addr->octet[0]; 108645386Swpaul 108745386Swpaul switch(sc->ti_hwrev) { 108845386Swpaul case TI_HWREV_TIGON: 108945386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 109045386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 109145386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 109245386Swpaul break; 109345386Swpaul case TI_HWREV_TIGON_II: 109445386Swpaul ext[0] = htons(m[0]); 109545386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 109645386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 109745386Swpaul break; 109845386Swpaul default: 109945386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 110045386Swpaul break; 110145386Swpaul } 110245386Swpaul 110345386Swpaul return; 110445386Swpaul} 110545386Swpaul 110645386Swpaul/* 110745386Swpaul * Configure the Tigon's multicast address filter. 110845386Swpaul * 110945386Swpaul * The actual multicast table management is a bit of a pain, thanks to 111045386Swpaul * slight brain damage on the part of both Alteon and us. With our 111145386Swpaul * multicast code, we are only alerted when the multicast address table 111245386Swpaul * changes and at that point we only have the current list of addresses: 111345386Swpaul * we only know the current state, not the previous state, so we don't 111445386Swpaul * actually know what addresses were removed or added. The firmware has 111545386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 111645386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 111745386Swpaul * state so we know what addresses have been programmed into the NIC at 111845386Swpaul * any given time. 111945386Swpaul */ 112045386Swpaulstatic void ti_setmulti(sc) 112145386Swpaul struct ti_softc *sc; 112245386Swpaul{ 112345386Swpaul struct ifnet *ifp; 112445386Swpaul struct ifmultiaddr *ifma; 112545386Swpaul struct ti_cmd_desc cmd; 112645386Swpaul struct ti_mc_entry *mc; 112745386Swpaul u_int32_t intrs; 112845386Swpaul 112945386Swpaul ifp = &sc->arpcom.ac_if; 113045386Swpaul 113145386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 113245386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 113345386Swpaul return; 113445386Swpaul } else { 113545386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 113645386Swpaul } 113745386Swpaul 113845386Swpaul /* Disable interrupts. */ 113945386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 114045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 114145386Swpaul 114245386Swpaul /* First, zot all the existing filters. */ 114345386Swpaul while (sc->ti_mc_listhead.slh_first != NULL) { 114445386Swpaul mc = sc->ti_mc_listhead.slh_first; 114545386Swpaul ti_del_mcast(sc, &mc->mc_addr); 114645386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 114745386Swpaul free(mc, M_DEVBUF); 114845386Swpaul } 114945386Swpaul 115045386Swpaul /* Now program new ones. */ 115145386Swpaul for (ifma = ifp->if_multiaddrs.lh_first; 115245386Swpaul ifma != NULL; ifma = ifma->ifma_link.le_next) { 115345386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 115445386Swpaul continue; 115545386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 115645386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 115745386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 115845386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 115945386Swpaul ti_add_mcast(sc, &mc->mc_addr); 116045386Swpaul } 116145386Swpaul 116245386Swpaul /* Re-enable interrupts. */ 116345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 116445386Swpaul 116545386Swpaul return; 116645386Swpaul} 116745386Swpaul 116845386Swpaul/* 116945386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 117045386Swpaul * we aren't actually in one. If we detect this condition, we can work 117145386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 117245386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 117345386Swpaul */ 117445386Swpaulstatic int ti_64bitslot_war(sc) 117545386Swpaul struct ti_softc *sc; 117645386Swpaul{ 117745386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 117845386Swpaul CSR_WRITE_4(sc, 0x600, 0); 117945386Swpaul CSR_WRITE_4(sc, 0x604, 0); 118045386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 118145386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 118245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 118345386Swpaul return(EINVAL); 118445386Swpaul else { 118545386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 118645386Swpaul TI_PCISTATE_32BIT_BUS); 118745386Swpaul return(0); 118845386Swpaul } 118945386Swpaul } 119045386Swpaul } 119145386Swpaul 119245386Swpaul return(0); 119345386Swpaul} 119445386Swpaul 119545386Swpaul/* 119645386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 119745386Swpaul * self-test results. 119845386Swpaul */ 119945386Swpaulstatic int ti_chipinit(sc) 120045386Swpaul struct ti_softc *sc; 120145386Swpaul{ 120245386Swpaul u_int32_t cacheline; 120345386Swpaul u_int32_t pci_writemax = 0; 120445386Swpaul 120545386Swpaul /* Initialize link to down state. */ 120645386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 120745386Swpaul 120858698Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 120958698Sjlemon 121045386Swpaul /* Set endianness before we access any non-PCI registers. */ 121145386Swpaul#if BYTE_ORDER == BIG_ENDIAN 121245386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 121345386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 121445386Swpaul#else 121545386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 121645386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 121745386Swpaul#endif 121845386Swpaul 121945386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 122045386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 122145386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 122245386Swpaul return(ENODEV); 122345386Swpaul } 122445386Swpaul 122545386Swpaul /* Halt the CPU. */ 122645386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 122745386Swpaul 122845386Swpaul /* Figure out the hardware revision. */ 122945386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 123045386Swpaul case TI_REV_TIGON_I: 123145386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 123245386Swpaul break; 123345386Swpaul case TI_REV_TIGON_II: 123445386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 123545386Swpaul break; 123645386Swpaul default: 123745386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 123845386Swpaul return(ENODEV); 123945386Swpaul } 124045386Swpaul 124145386Swpaul /* Do special setup for Tigon 2. */ 124245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 124345386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 124445386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 124545386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 124645386Swpaul } 124745386Swpaul 124845386Swpaul /* Set up the PCI state register. */ 124945386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 125045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 125145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 125245386Swpaul } 125345386Swpaul 125445386Swpaul /* Clear the read/write max DMA parameters. */ 125545386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 125645386Swpaul TI_PCISTATE_READ_MAXDMA)); 125745386Swpaul 125845386Swpaul /* Get cache line size. */ 125945386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 126045386Swpaul 126145386Swpaul /* 126245386Swpaul * If the system has set enabled the PCI memory write 126345386Swpaul * and invalidate command in the command register, set 126445386Swpaul * the write max parameter accordingly. This is necessary 126545386Swpaul * to use MWI with the Tigon 2. 126645386Swpaul */ 126745386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 126845386Swpaul switch(cacheline) { 126945386Swpaul case 1: 127045386Swpaul case 4: 127145386Swpaul case 8: 127245386Swpaul case 16: 127345386Swpaul case 32: 127445386Swpaul case 64: 127545386Swpaul break; 127645386Swpaul default: 127745386Swpaul /* Disable PCI memory write and invalidate. */ 127845386Swpaul if (bootverbose) 127945386Swpaul printf("ti%d: cache line size %d not " 128045386Swpaul "supported; disabling PCI MWI\n", 128145386Swpaul sc->ti_unit, cacheline); 128245386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 128345386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 128445386Swpaul break; 128545386Swpaul } 128645386Swpaul } 128745386Swpaul 128845386Swpaul#ifdef __brokenalpha__ 128945386Swpaul /* 129045386Swpaul * From the Alteon sample driver: 129145386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 129245386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 129345386Swpaul * restriction on some ALPHA platforms with early revision 129445386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 129545386Swpaul */ 129645386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 129745386Swpaul#else 129845386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 129945386Swpaul#endif 130045386Swpaul 130145386Swpaul /* This sets the min dma param all the way up (0xff). */ 130245386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 130345386Swpaul 130445386Swpaul /* Configure DMA variables. */ 130545386Swpaul#if BYTE_ORDER == BIG_ENDIAN 130645386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 130745386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 130845386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 130945386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 131045386Swpaul#else 131145386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 131245386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 131345386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 131445386Swpaul#endif 131545386Swpaul 131645386Swpaul /* 131745386Swpaul * Only allow 1 DMA channel to be active at a time. 131845386Swpaul * I don't think this is a good idea, but without it 131945386Swpaul * the firmware racks up lots of nicDmaReadRingFull 132058698Sjlemon * errors. This is not compatible with hardware checksums. 132145386Swpaul */ 132258698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 132358698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 132445386Swpaul 132545386Swpaul /* Recommended settings from Tigon manual. */ 132645386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 132745386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 132845386Swpaul 132945386Swpaul if (ti_64bitslot_war(sc)) { 133045386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 133145386Swpaul "but we aren't", sc->ti_unit); 133245386Swpaul return(EINVAL); 133345386Swpaul } 133445386Swpaul 133545386Swpaul return(0); 133645386Swpaul} 133745386Swpaul 133845386Swpaul/* 133945386Swpaul * Initialize the general information block and firmware, and 134045386Swpaul * start the CPU(s) running. 134145386Swpaul */ 134245386Swpaulstatic int ti_gibinit(sc) 134345386Swpaul struct ti_softc *sc; 134445386Swpaul{ 134545386Swpaul struct ti_rcb *rcb; 134645386Swpaul int i; 134745386Swpaul struct ifnet *ifp; 134845386Swpaul 134945386Swpaul ifp = &sc->arpcom.ac_if; 135045386Swpaul 135145386Swpaul /* Disable interrupts for now. */ 135245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 135345386Swpaul 135445386Swpaul /* Tell the chip where to find the general information block. */ 135545386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 135645386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 135745386Swpaul 135845386Swpaul /* Load the firmware into SRAM. */ 135945386Swpaul ti_loadfw(sc); 136045386Swpaul 136145386Swpaul /* Set up the contents of the general info and ring control blocks. */ 136245386Swpaul 136345386Swpaul /* Set up the event ring and producer pointer. */ 136445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 136545386Swpaul 136645386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 136745386Swpaul rcb->ti_flags = 0; 136845386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 136945386Swpaul vtophys(&sc->ti_ev_prodidx); 137045386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 137145386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 137245386Swpaul sc->ti_ev_saved_considx = 0; 137345386Swpaul 137445386Swpaul /* Set up the command ring and producer mailbox. */ 137545386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 137645386Swpaul 137745386Swpaul sc->ti_rdata->ti_cmd_ring = 137849133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 137945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 138045386Swpaul rcb->ti_flags = 0; 138145386Swpaul rcb->ti_max_len = 0; 138245386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 138345386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 138445386Swpaul } 138545386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 138645386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 138745386Swpaul sc->ti_cmd_saved_prodidx = 0; 138845386Swpaul 138945386Swpaul /* 139045386Swpaul * Assign the address of the stats refresh buffer. 139145386Swpaul * We re-use the current stats buffer for this to 139245386Swpaul * conserve memory. 139345386Swpaul */ 139445386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 139545386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 139645386Swpaul 139745386Swpaul /* Set up the standard receive ring. */ 139845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 139945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 140045386Swpaul rcb->ti_max_len = TI_FRAMELEN; 140145386Swpaul rcb->ti_flags = 0; 140258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 140358698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 140458698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 140545386Swpaul#if NVLAN > 0 140645386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 140745386Swpaul#endif 140845386Swpaul 140945386Swpaul /* Set up the jumbo receive ring. */ 141045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 141145386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 141245386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 141349036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 141445386Swpaul rcb->ti_flags = 0; 141558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 141658698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 141758698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 141845386Swpaul#if NVLAN > 0 141945386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 142045386Swpaul#endif 142145386Swpaul 142245386Swpaul /* 142345386Swpaul * Set up the mini ring. Only activated on the 142445386Swpaul * Tigon 2 but the slot in the config block is 142545386Swpaul * still there on the Tigon 1. 142645386Swpaul */ 142745386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 142845386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 142945386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 143051352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 143145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 143245386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 143345386Swpaul else 143445386Swpaul rcb->ti_flags = 0; 143558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 143658698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 143758698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 143845386Swpaul#if NVLAN > 0 143945386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 144045386Swpaul#endif 144145386Swpaul 144245386Swpaul /* 144345386Swpaul * Set up the receive return ring. 144445386Swpaul */ 144545386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 144645386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 144745386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 144845386Swpaul rcb->ti_flags = 0; 144945386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 145045386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 145145386Swpaul vtophys(&sc->ti_return_prodidx); 145245386Swpaul 145345386Swpaul /* 145445386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 145545386Swpaul * of putting the transmit ring in the host's address space and 145645386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 145745386Swpaul * memory and accessing it through the shared memory region. We 145845386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 145945386Swpaul * so we have to revert to the shared memory scheme if we detect 146045386Swpaul * a Tigon 1 chip. 146145386Swpaul */ 146245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 146345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 146445386Swpaul sc->ti_rdata->ti_tx_ring_nic = 146549133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 146645386Swpaul } 146745386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 146845386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 146945386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 147045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 147145386Swpaul rcb->ti_flags = 0; 147245386Swpaul else 147345386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 147445386Swpaul#if NVLAN > 0 147545386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 147645386Swpaul#endif 147758698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 147858698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 147958698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 148045386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 148145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 148245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 148345386Swpaul else 148445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 148545386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 148645386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 148745386Swpaul vtophys(&sc->ti_tx_considx); 148845386Swpaul 148945386Swpaul /* Set up tuneables */ 149045386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 149145386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 149245386Swpaul (sc->ti_rx_coal_ticks / 10)); 149345386Swpaul else 149445386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 149545386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 149645386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 149745386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 149845386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 149945386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 150045386Swpaul 150145386Swpaul /* Turn interrupts on. */ 150245386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 150345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 150445386Swpaul 150545386Swpaul /* Start CPU. */ 150645386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 150745386Swpaul 150845386Swpaul return(0); 150945386Swpaul} 151045386Swpaul 151145386Swpaul/* 151245386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 151345386Swpaul * against our list and return its name if we find a match. 151445386Swpaul */ 151549011Swpaulstatic int ti_probe(dev) 151649011Swpaul device_t dev; 151745386Swpaul{ 151845386Swpaul struct ti_type *t; 151945386Swpaul 152045386Swpaul t = ti_devs; 152145386Swpaul 152245386Swpaul while(t->ti_name != NULL) { 152349011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 152449011Swpaul (pci_get_device(dev) == t->ti_did)) { 152549011Swpaul device_set_desc(dev, t->ti_name); 152649011Swpaul return(0); 152749011Swpaul } 152845386Swpaul t++; 152945386Swpaul } 153045386Swpaul 153149011Swpaul return(ENXIO); 153245386Swpaul} 153345386Swpaul 153449011Swpaulstatic int ti_attach(dev) 153549011Swpaul device_t dev; 153645386Swpaul{ 153745386Swpaul int s; 153845386Swpaul u_int32_t command; 153945386Swpaul struct ifnet *ifp; 154045386Swpaul struct ti_softc *sc; 154149011Swpaul int unit, error = 0, rid; 154245386Swpaul 154345386Swpaul s = splimp(); 154445386Swpaul 154549011Swpaul sc = device_get_softc(dev); 154649011Swpaul unit = device_get_unit(dev); 154745386Swpaul bzero(sc, sizeof(struct ti_softc)); 154845386Swpaul 154945386Swpaul /* 155045386Swpaul * Map control/status registers. 155145386Swpaul */ 155261041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 155345386Swpaul command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 155461041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 155561041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 155645386Swpaul 155745386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 155845386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 155949011Swpaul error = ENXIO; 156045386Swpaul goto fail; 156145386Swpaul } 156245386Swpaul 156349011Swpaul rid = TI_PCI_LOMEM; 156449011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 156549011Swpaul 0, ~0, 1, RF_ACTIVE); 156649011Swpaul 156749011Swpaul if (sc->ti_res == NULL) { 156845386Swpaul printf ("ti%d: couldn't map memory\n", unit); 156949011Swpaul error = ENXIO; 157045386Swpaul goto fail; 157145386Swpaul } 157245386Swpaul 157349035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 157449035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 157549133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 157649035Swpaul 157749133Swpaul /* 157849133Swpaul * XXX FIXME: rman_get_virtual() on the alpha is currently 157949133Swpaul * broken and returns a physical address instead of a kernel 158049133Swpaul * virtual address. Consequently, we need to do a little 158149133Swpaul * extra mangling of the vhandle on the alpha. This should 158249133Swpaul * eventually be fixed! The whole idea here is to get rid 158349133Swpaul * of platform dependencies. 158449133Swpaul */ 158549133Swpaul#ifdef __alpha__ 158649133Swpaul if (pci_cvt_to_bwx(sc->ti_vhandle)) 158749133Swpaul sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 158849133Swpaul else 158949133Swpaul sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 159049133Swpaul sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 159149133Swpaul#endif 159249133Swpaul 159349011Swpaul /* Allocate interrupt */ 159449011Swpaul rid = 0; 159549133Swpaul 159649011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 159749011Swpaul RF_SHAREABLE | RF_ACTIVE); 159845386Swpaul 159949011Swpaul if (sc->ti_irq == NULL) { 160049011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 160149011Swpaul error = ENXIO; 160245386Swpaul goto fail; 160345386Swpaul } 160445386Swpaul 160549011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 160649011Swpaul ti_intr, sc, &sc->ti_intrhand); 160749011Swpaul 160849011Swpaul if (error) { 160949011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 161049011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 161149011Swpaul TI_PCI_LOMEM, sc->ti_res); 161249011Swpaul printf("ti%d: couldn't set up irq\n", unit); 161345386Swpaul goto fail; 161445386Swpaul } 161545386Swpaul 161645386Swpaul sc->ti_unit = unit; 161745386Swpaul 161845386Swpaul if (ti_chipinit(sc)) { 161945386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 162049011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 162149011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 162249011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 162349011Swpaul TI_PCI_LOMEM, sc->ti_res); 162449011Swpaul error = ENXIO; 162545386Swpaul goto fail; 162645386Swpaul } 162745386Swpaul 162845386Swpaul /* Zero out the NIC's on-board SRAM. */ 162945386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 163045386Swpaul 163145386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 163245386Swpaul if (ti_chipinit(sc)) { 163345386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 163449011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 163549011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 163649011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 163749011Swpaul TI_PCI_LOMEM, sc->ti_res); 163849011Swpaul error = ENXIO; 163945386Swpaul goto fail; 164045386Swpaul } 164145386Swpaul 164245386Swpaul /* 164345386Swpaul * Get station address from the EEPROM. Note: the manual states 164445386Swpaul * that the MAC address is at offset 0x8c, however the data is 164545386Swpaul * stored as two longwords (since that's how it's loaded into 164645386Swpaul * the NIC). This means the MAC address is actually preceeded 164745386Swpaul * by two zero bytes. We need to skip over those. 164845386Swpaul */ 164945386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 165045386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 165145386Swpaul printf("ti%d: failed to read station address\n", unit); 165249011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 165349011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 165449011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 165549011Swpaul TI_PCI_LOMEM, sc->ti_res); 165649011Swpaul error = ENXIO; 165745386Swpaul goto fail; 165845386Swpaul } 165945386Swpaul 166045386Swpaul /* 166145386Swpaul * A Tigon chip was detected. Inform the world. 166245386Swpaul */ 166345386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 166445386Swpaul sc->arpcom.ac_enaddr, ":"); 166545386Swpaul 166645386Swpaul /* Allocate the general information block and ring buffers. */ 166749011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 166850548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 166945386Swpaul 167049011Swpaul if (sc->ti_rdata == NULL) { 167149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 167249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 167349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 167449011Swpaul TI_PCI_LOMEM, sc->ti_res); 167549011Swpaul error = ENXIO; 167645386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 167745386Swpaul goto fail; 167845386Swpaul } 167945386Swpaul 168045386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 168145386Swpaul 168245386Swpaul /* Try to allocate memory for jumbo buffers. */ 168345386Swpaul if (ti_alloc_jumbo_mem(sc)) { 168445386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 168549011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 168649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 168749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 168849011Swpaul TI_PCI_LOMEM, sc->ti_res); 168962793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 169062793Sgallatin M_DEVBUF); 169149011Swpaul error = ENXIO; 169245386Swpaul goto fail; 169345386Swpaul } 169445386Swpaul 169563699Swpaul /* 169663699Swpaul * We really need a better way to tell a 1000baseTX card 169763699Swpaul * from a 1000baseSX one, since in theory there could be 169863699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 169963699Swpaul * clever enough to change the PCI ID. For the moment 170063699Swpaul * though, the AceNIC is the only copper card available. 170163699Swpaul */ 170263699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 170363699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 170463699Swpaul sc->ti_copper = 1; 170564139Swpaul /* Ok, it's not the only copper card available. */ 170664139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 170764139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 170864139Swpaul sc->ti_copper = 1; 170963699Swpaul 171045386Swpaul /* Set default tuneable values. */ 171145386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 171245386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 171345386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 171445386Swpaul sc->ti_rx_max_coal_bds = 64; 171545386Swpaul sc->ti_tx_max_coal_bds = 128; 171645386Swpaul sc->ti_tx_buf_ratio = 21; 171745386Swpaul 171845386Swpaul /* Set up ifnet structure */ 171945386Swpaul ifp = &sc->arpcom.ac_if; 172045386Swpaul ifp->if_softc = sc; 172145386Swpaul ifp->if_unit = sc->ti_unit; 172245386Swpaul ifp->if_name = "ti"; 172345386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 172445386Swpaul ifp->if_ioctl = ti_ioctl; 172545386Swpaul ifp->if_output = ether_output; 172645386Swpaul ifp->if_start = ti_start; 172745386Swpaul ifp->if_watchdog = ti_watchdog; 172845386Swpaul ifp->if_init = ti_init; 172945386Swpaul ifp->if_mtu = ETHERMTU; 173045386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 173145386Swpaul 173245386Swpaul /* Set up ifmedia support. */ 173345386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 173463699Swpaul if (sc->ti_copper) { 173563699Swpaul /* 173663699Swpaul * Copper cards allow manual 10/100 mode selection, 173763699Swpaul * but not manual 1000baseTX mode selection. Why? 173863699Swpaul * Becuase currently there's no way to specify the 173963699Swpaul * master/slave setting through the firmware interface, 174063699Swpaul * so Alteon decided to just bag it and handle it 174163699Swpaul * via autonegotiation. 174263699Swpaul */ 174363699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 174463699Swpaul ifmedia_add(&sc->ifmedia, 174563699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 174663699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 174763699Swpaul ifmedia_add(&sc->ifmedia, 174863699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 174963699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 175063699Swpaul ifmedia_add(&sc->ifmedia, 175163699Swpaul IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 175263699Swpaul } else { 175363699Swpaul /* Fiber cards don't support 10/100 modes. */ 175463699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 175563699Swpaul ifmedia_add(&sc->ifmedia, 175663699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 175763699Swpaul } 175845386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 175945386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 176045386Swpaul 176145386Swpaul /* 176263090Sarchie * Call MI attach routine. 176345386Swpaul */ 176463090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 176545386Swpaul 176645386Swpaulfail: 176745386Swpaul splx(s); 176845386Swpaul 176949011Swpaul return(error); 177045386Swpaul} 177145386Swpaul 177249011Swpaulstatic int ti_detach(dev) 177349011Swpaul device_t dev; 177449011Swpaul{ 177549011Swpaul struct ti_softc *sc; 177649011Swpaul struct ifnet *ifp; 177749011Swpaul int s; 177849011Swpaul 177949011Swpaul s = splimp(); 178049011Swpaul 178149011Swpaul sc = device_get_softc(dev); 178249011Swpaul ifp = &sc->arpcom.ac_if; 178349011Swpaul 178463090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 178549011Swpaul ti_stop(sc); 178649011Swpaul 178749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 178849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 178949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 179049011Swpaul 179162793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 179262793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 179349011Swpaul ifmedia_removeall(&sc->ifmedia); 179449011Swpaul 179549011Swpaul splx(s); 179649011Swpaul 179749011Swpaul return(0); 179849011Swpaul} 179949011Swpaul 180045386Swpaul/* 180145386Swpaul * Frame reception handling. This is called if there's a frame 180245386Swpaul * on the receive return list. 180345386Swpaul * 180445386Swpaul * Note: we have to be able to handle three possibilities here: 180545386Swpaul * 1) the frame is from the mini receive ring (can only happen) 180645386Swpaul * on Tigon 2 boards) 180745386Swpaul * 2) the frame is from the jumbo recieve ring 180845386Swpaul * 3) the frame is from the standard receive ring 180945386Swpaul */ 181045386Swpaul 181145386Swpaulstatic void ti_rxeof(sc) 181245386Swpaul struct ti_softc *sc; 181345386Swpaul{ 181445386Swpaul struct ifnet *ifp; 181548597Swpaul struct ti_cmd_desc cmd; 181645386Swpaul 181745386Swpaul ifp = &sc->arpcom.ac_if; 181845386Swpaul 181945386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 182045386Swpaul struct ti_rx_desc *cur_rx; 182145386Swpaul u_int32_t rxidx; 182245386Swpaul struct ether_header *eh; 182345386Swpaul struct mbuf *m = NULL; 182445386Swpaul#if NVLAN > 0 182545386Swpaul u_int16_t vlan_tag = 0; 182645386Swpaul int have_tag = 0; 182745386Swpaul#endif 182845386Swpaul 182945386Swpaul cur_rx = 183045386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 183145386Swpaul rxidx = cur_rx->ti_idx; 183245386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 183345386Swpaul 183445386Swpaul#if NVLAN > 0 183545386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 183645386Swpaul have_tag = 1; 183745386Swpaul vlan_tag = cur_rx->ti_vlan_tag; 183845386Swpaul } 183945386Swpaul#endif 184045386Swpaul 184145386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 184245386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 184345386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 184445386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 184545386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 184645386Swpaul ifp->if_ierrors++; 184745386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 184845386Swpaul continue; 184945386Swpaul } 185048597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 185148597Swpaul ifp->if_ierrors++; 185248597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 185348597Swpaul continue; 185448597Swpaul } 185545386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 185645386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 185745386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 185845386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 185945386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 186045386Swpaul ifp->if_ierrors++; 186145386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 186245386Swpaul continue; 186345386Swpaul } 186448597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 186548597Swpaul ifp->if_ierrors++; 186648597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 186748597Swpaul continue; 186848597Swpaul } 186945386Swpaul } else { 187045386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 187145386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 187245386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 187345386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 187445386Swpaul ifp->if_ierrors++; 187545386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 187645386Swpaul continue; 187745386Swpaul } 187848597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 187948597Swpaul ifp->if_ierrors++; 188048597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 188148597Swpaul continue; 188248597Swpaul } 188345386Swpaul } 188445386Swpaul 188545386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 188645386Swpaul ifp->if_ipackets++; 188745386Swpaul eh = mtod(m, struct ether_header *); 188845386Swpaul m->m_pkthdr.rcvif = ifp; 188945386Swpaul 189045386Swpaul /* Remove header from mbuf and pass it on. */ 189145386Swpaul m_adj(m, sizeof(struct ether_header)); 189245386Swpaul 189358698Sjlemon if (ifp->if_hwassist) { 189458698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 189558698Sjlemon CSUM_DATA_VALID; 189658698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 189758698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 189858698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 189958698Sjlemon } 190045386Swpaul 190145386Swpaul#if NVLAN > 0 190245386Swpaul /* 190345386Swpaul * If we received a packet with a vlan tag, pass it 190445386Swpaul * to vlan_input() instead of ether_input(). 190545386Swpaul */ 190645386Swpaul if (have_tag) { 190745386Swpaul vlan_input_tag(eh, m, vlan_tag); 190845386Swpaul have_tag = vlan_tag = 0; 190945386Swpaul continue; 191045386Swpaul } 191145386Swpaul#endif 191245386Swpaul ether_input(ifp, eh, m); 191345386Swpaul } 191445386Swpaul 191545386Swpaul /* Only necessary on the Tigon 1. */ 191645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 191745386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 191845386Swpaul sc->ti_rx_saved_considx); 191945386Swpaul 192048597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 192148597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 192248597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 192345386Swpaul 192445386Swpaul return; 192545386Swpaul} 192645386Swpaul 192745386Swpaulstatic void ti_txeof(sc) 192845386Swpaul struct ti_softc *sc; 192945386Swpaul{ 193045386Swpaul struct ti_tx_desc *cur_tx = NULL; 193145386Swpaul struct ifnet *ifp; 193245386Swpaul 193345386Swpaul ifp = &sc->arpcom.ac_if; 193445386Swpaul 193545386Swpaul /* 193645386Swpaul * Go through our tx ring and free mbufs for those 193745386Swpaul * frames that have been sent. 193845386Swpaul */ 193945386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 194045386Swpaul u_int32_t idx = 0; 194145386Swpaul 194245386Swpaul idx = sc->ti_tx_saved_considx; 194345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 194445386Swpaul if (idx > 383) 194545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 194645386Swpaul TI_TX_RING_BASE + 6144); 194745386Swpaul else if (idx > 255) 194845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 194945386Swpaul TI_TX_RING_BASE + 4096); 195045386Swpaul else if (idx > 127) 195145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 195245386Swpaul TI_TX_RING_BASE + 2048); 195345386Swpaul else 195445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 195545386Swpaul TI_TX_RING_BASE); 195645386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 195745386Swpaul } else 195845386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 195945386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 196045386Swpaul ifp->if_opackets++; 196145386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 196245386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 196345386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 196445386Swpaul } 196548011Swpaul sc->ti_txcnt--; 196645386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 196745386Swpaul ifp->if_timer = 0; 196845386Swpaul } 196945386Swpaul 197045386Swpaul if (cur_tx != NULL) 197145386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 197245386Swpaul 197345386Swpaul return; 197445386Swpaul} 197545386Swpaul 197645386Swpaulstatic void ti_intr(xsc) 197745386Swpaul void *xsc; 197845386Swpaul{ 197945386Swpaul struct ti_softc *sc; 198045386Swpaul struct ifnet *ifp; 198145386Swpaul 198245386Swpaul sc = xsc; 198345386Swpaul ifp = &sc->arpcom.ac_if; 198445386Swpaul 198545386Swpaul#ifdef notdef 198645386Swpaul /* Avoid this for now -- checking this register is expensive. */ 198745386Swpaul /* Make sure this is really our interrupt. */ 198845386Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 198945386Swpaul return; 199045386Swpaul#endif 199145386Swpaul 199245386Swpaul /* Ack interrupt and stop others from occuring. */ 199345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 199445386Swpaul 199545386Swpaul if (ifp->if_flags & IFF_RUNNING) { 199645386Swpaul /* Check RX return ring producer/consumer */ 199745386Swpaul ti_rxeof(sc); 199845386Swpaul 199945386Swpaul /* Check TX ring producer/consumer */ 200045386Swpaul ti_txeof(sc); 200145386Swpaul } 200245386Swpaul 200345386Swpaul ti_handle_events(sc); 200445386Swpaul 200545386Swpaul /* Re-enable interrupts. */ 200645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 200745386Swpaul 200845386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 200945386Swpaul ti_start(ifp); 201045386Swpaul 201145386Swpaul return; 201245386Swpaul} 201345386Swpaul 201445386Swpaulstatic void ti_stats_update(sc) 201545386Swpaul struct ti_softc *sc; 201645386Swpaul{ 201745386Swpaul struct ifnet *ifp; 201845386Swpaul 201945386Swpaul ifp = &sc->arpcom.ac_if; 202045386Swpaul 202145386Swpaul ifp->if_collisions += 202245386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 202345386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 202445386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 202545386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 202645386Swpaul ifp->if_collisions; 202745386Swpaul 202845386Swpaul return; 202945386Swpaul} 203045386Swpaul 203145386Swpaul/* 203245386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 203345386Swpaul * pointers to descriptors. 203445386Swpaul */ 203545386Swpaulstatic int ti_encap(sc, m_head, txidx) 203645386Swpaul struct ti_softc *sc; 203745386Swpaul struct mbuf *m_head; 203845386Swpaul u_int32_t *txidx; 203945386Swpaul{ 204045386Swpaul struct ti_tx_desc *f = NULL; 204145386Swpaul struct mbuf *m; 204248011Swpaul u_int32_t frag, cur, cnt = 0; 204358698Sjlemon u_int16_t csum_flags = 0; 204445386Swpaul#if NVLAN > 0 204545386Swpaul struct ifvlan *ifv = NULL; 204645386Swpaul 204745386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 204845386Swpaul m_head->m_pkthdr.rcvif != NULL && 204945386Swpaul m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 205045386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 205145386Swpaul#endif 205245386Swpaul 205345386Swpaul m = m_head; 205445386Swpaul cur = frag = *txidx; 205545386Swpaul 205658698Sjlemon if (m_head->m_pkthdr.csum_flags) { 205758698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 205858698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 205958698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 206058698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 206158698Sjlemon if (m_head->m_flags & M_LASTFRAG) 206258698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 206358698Sjlemon else if (m_head->m_flags & M_FRAG) 206458698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 206558698Sjlemon } 206645386Swpaul /* 206745386Swpaul * Start packing the mbufs in this chain into 206845386Swpaul * the fragment pointers. Stop when we run out 206945386Swpaul * of fragments or hit the end of the mbuf chain. 207045386Swpaul */ 207145386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 207245386Swpaul if (m->m_len != 0) { 207345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 207445386Swpaul if (frag > 383) 207545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 207645386Swpaul TI_TX_RING_BASE + 6144); 207745386Swpaul else if (frag > 255) 207845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 207945386Swpaul TI_TX_RING_BASE + 4096); 208045386Swpaul else if (frag > 127) 208145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 208245386Swpaul TI_TX_RING_BASE + 2048); 208345386Swpaul else 208445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 208545386Swpaul TI_TX_RING_BASE); 208645386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 208745386Swpaul } else 208845386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 208945386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 209045386Swpaul break; 209145386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 209245386Swpaul f->ti_len = m->m_len; 209358698Sjlemon f->ti_flags = csum_flags; 209445386Swpaul#if NVLAN > 0 209545386Swpaul if (ifv != NULL) { 209645386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 209745386Swpaul f->ti_vlan_tag = ifv->ifv_tag; 209845386Swpaul } else { 209945386Swpaul f->ti_vlan_tag = 0; 210045386Swpaul } 210145386Swpaul#endif 210248011Swpaul /* 210348011Swpaul * Sanity check: avoid coming within 16 descriptors 210448011Swpaul * of the end of the ring. 210548011Swpaul */ 210648011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 210748011Swpaul return(ENOBUFS); 210845386Swpaul cur = frag; 210945386Swpaul TI_INC(frag, TI_TX_RING_CNT); 211048011Swpaul cnt++; 211145386Swpaul } 211245386Swpaul } 211345386Swpaul 211445386Swpaul if (m != NULL) 211545386Swpaul return(ENOBUFS); 211645386Swpaul 211746177Swpaul if (frag == sc->ti_tx_saved_considx) 211846177Swpaul return(ENOBUFS); 211946177Swpaul 212045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 212145386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 212245386Swpaul TI_BDFLAG_END; 212345386Swpaul else 212445386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 212547458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 212648011Swpaul sc->ti_txcnt += cnt; 212745386Swpaul 212845386Swpaul *txidx = frag; 212945386Swpaul 213045386Swpaul return(0); 213145386Swpaul} 213245386Swpaul 213345386Swpaul/* 213445386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 213545386Swpaul * to the mbuf data regions directly in the transmit descriptors. 213645386Swpaul */ 213745386Swpaulstatic void ti_start(ifp) 213845386Swpaul struct ifnet *ifp; 213945386Swpaul{ 214045386Swpaul struct ti_softc *sc; 214145386Swpaul struct mbuf *m_head = NULL; 214245386Swpaul u_int32_t prodidx = 0; 214345386Swpaul 214445386Swpaul sc = ifp->if_softc; 214545386Swpaul 214645386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 214745386Swpaul 214845386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 214945386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 215045386Swpaul if (m_head == NULL) 215145386Swpaul break; 215245386Swpaul 215345386Swpaul /* 215458698Sjlemon * XXX 215558698Sjlemon * safety overkill. If this is a fragmented packet chain 215658698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 215758698Sjlemon * it if we have enough descriptors to handle the entire 215858698Sjlemon * chain at once. 215958698Sjlemon * (paranoia -- may not actually be needed) 216058698Sjlemon */ 216158698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 216258698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 216358698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 216458698Sjlemon m_head->m_pkthdr.csum_data + 16) { 216558698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 216658698Sjlemon ifp->if_flags |= IFF_OACTIVE; 216758698Sjlemon break; 216858698Sjlemon } 216958698Sjlemon } 217058698Sjlemon 217158698Sjlemon /* 217245386Swpaul * Pack the data into the transmit ring. If we 217345386Swpaul * don't have room, set the OACTIVE flag and wait 217445386Swpaul * for the NIC to drain the ring. 217545386Swpaul */ 217645386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 217745386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 217845386Swpaul ifp->if_flags |= IFF_OACTIVE; 217945386Swpaul break; 218045386Swpaul } 218145386Swpaul 218245386Swpaul /* 218345386Swpaul * If there's a BPF listener, bounce a copy of this frame 218445386Swpaul * to him. 218545386Swpaul */ 218645386Swpaul if (ifp->if_bpf) 218745386Swpaul bpf_mtap(ifp, m_head); 218845386Swpaul } 218945386Swpaul 219045386Swpaul /* Transmit */ 219145386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 219245386Swpaul 219345386Swpaul /* 219445386Swpaul * Set a timeout in case the chip goes out to lunch. 219545386Swpaul */ 219645386Swpaul ifp->if_timer = 5; 219745386Swpaul 219845386Swpaul return; 219945386Swpaul} 220045386Swpaul 220145386Swpaulstatic void ti_init(xsc) 220245386Swpaul void *xsc; 220345386Swpaul{ 220445386Swpaul struct ti_softc *sc = xsc; 220545386Swpaul int s; 220645386Swpaul 220745386Swpaul s = splimp(); 220845386Swpaul 220945386Swpaul /* Cancel pending I/O and flush buffers. */ 221045386Swpaul ti_stop(sc); 221145386Swpaul 221245386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 221345386Swpaul if (ti_gibinit(sc)) { 221445386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 221545386Swpaul splx(s); 221645386Swpaul return; 221745386Swpaul } 221845386Swpaul 221945386Swpaul splx(s); 222045386Swpaul 222145386Swpaul return; 222245386Swpaul} 222345386Swpaul 222445386Swpaulstatic void ti_init2(sc) 222545386Swpaul struct ti_softc *sc; 222645386Swpaul{ 222745386Swpaul struct ti_cmd_desc cmd; 222845386Swpaul struct ifnet *ifp; 222945386Swpaul u_int16_t *m; 223045386Swpaul struct ifmedia *ifm; 223145386Swpaul int tmp; 223245386Swpaul 223345386Swpaul ifp = &sc->arpcom.ac_if; 223445386Swpaul 223545386Swpaul /* Specify MTU and interface index. */ 223645386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 223745386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 223845386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 223945386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 224045386Swpaul 224145386Swpaul /* Load our MAC address. */ 224245386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 224345386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 224445386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 224545386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 224645386Swpaul 224745386Swpaul /* Enable or disable promiscuous mode as needed. */ 224845386Swpaul if (ifp->if_flags & IFF_PROMISC) { 224945386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 225045386Swpaul } else { 225145386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 225245386Swpaul } 225345386Swpaul 225445386Swpaul /* Program multicast filter. */ 225545386Swpaul ti_setmulti(sc); 225645386Swpaul 225745386Swpaul /* 225845386Swpaul * If this is a Tigon 1, we should tell the 225945386Swpaul * firmware to use software packet filtering. 226045386Swpaul */ 226145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 226245386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 226345386Swpaul } 226445386Swpaul 226545386Swpaul /* Init RX ring. */ 226645386Swpaul ti_init_rx_ring_std(sc); 226745386Swpaul 226845386Swpaul /* Init jumbo RX ring. */ 226945386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 227045386Swpaul ti_init_rx_ring_jumbo(sc); 227145386Swpaul 227245386Swpaul /* 227345386Swpaul * If this is a Tigon 2, we can also configure the 227445386Swpaul * mini ring. 227545386Swpaul */ 227645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 227745386Swpaul ti_init_rx_ring_mini(sc); 227845386Swpaul 227945386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 228045386Swpaul sc->ti_rx_saved_considx = 0; 228145386Swpaul 228245386Swpaul /* Init TX ring. */ 228345386Swpaul ti_init_tx_ring(sc); 228445386Swpaul 228545386Swpaul /* Tell firmware we're alive. */ 228645386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 228745386Swpaul 228845386Swpaul /* Enable host interrupts. */ 228945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 229045386Swpaul 229145386Swpaul ifp->if_flags |= IFF_RUNNING; 229245386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 229345386Swpaul 229445386Swpaul /* 229545386Swpaul * Make sure to set media properly. We have to do this 229645386Swpaul * here since we have to issue commands in order to set 229745386Swpaul * the link negotiation and we can't issue commands until 229845386Swpaul * the firmware is running. 229945386Swpaul */ 230045386Swpaul ifm = &sc->ifmedia; 230145386Swpaul tmp = ifm->ifm_media; 230245386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 230345386Swpaul ti_ifmedia_upd(ifp); 230445386Swpaul ifm->ifm_media = tmp; 230545386Swpaul 230645386Swpaul return; 230745386Swpaul} 230845386Swpaul 230945386Swpaul/* 231045386Swpaul * Set media options. 231145386Swpaul */ 231245386Swpaulstatic int ti_ifmedia_upd(ifp) 231345386Swpaul struct ifnet *ifp; 231445386Swpaul{ 231545386Swpaul struct ti_softc *sc; 231645386Swpaul struct ifmedia *ifm; 231745386Swpaul struct ti_cmd_desc cmd; 231845386Swpaul 231945386Swpaul sc = ifp->if_softc; 232045386Swpaul ifm = &sc->ifmedia; 232145386Swpaul 232245386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 232345386Swpaul return(EINVAL); 232445386Swpaul 232545386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 232645386Swpaul case IFM_AUTO: 232745386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 232845386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 232945386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 233045386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 233145386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 233245386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 233345386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 233445386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 233545386Swpaul break; 233645386Swpaul case IFM_1000_SX: 233763699Swpaul case IFM_1000_TX: 233845386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 233963699Swpaul TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 234045386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 234163699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 234263699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 234363699Swpaul } 234445386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 234545386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 234645386Swpaul break; 234745386Swpaul case IFM_100_FX: 234845386Swpaul case IFM_10_FL: 234963699Swpaul case IFM_100_TX: 235063699Swpaul case IFM_10_T: 235145386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 235245386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 235363699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 235463699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 235545386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 235645386Swpaul } else { 235745386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 235845386Swpaul } 235945386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 236045386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 236145386Swpaul } else { 236245386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 236345386Swpaul } 236445386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 236545386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 236645386Swpaul break; 236745386Swpaul } 236845386Swpaul 236945386Swpaul return(0); 237045386Swpaul} 237145386Swpaul 237245386Swpaul/* 237345386Swpaul * Report current media status. 237445386Swpaul */ 237545386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 237645386Swpaul struct ifnet *ifp; 237745386Swpaul struct ifmediareq *ifmr; 237845386Swpaul{ 237945386Swpaul struct ti_softc *sc; 238063699Swpaul u_int32_t media = 0; 238145386Swpaul 238245386Swpaul sc = ifp->if_softc; 238345386Swpaul 238445386Swpaul ifmr->ifm_status = IFM_AVALID; 238545386Swpaul ifmr->ifm_active = IFM_ETHER; 238645386Swpaul 238745386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 238845386Swpaul return; 238945386Swpaul 239045386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 239145386Swpaul 239263699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 239363699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 239463699Swpaul if (sc->ti_copper) 239563699Swpaul ifmr->ifm_active |= IFM_1000_TX; 239663699Swpaul else 239763699Swpaul ifmr->ifm_active |= IFM_1000_SX; 239863699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 239963699Swpaul ifmr->ifm_active |= IFM_FDX; 240063699Swpaul else 240163699Swpaul ifmr->ifm_active |= IFM_HDX; 240263699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 240345386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 240463699Swpaul if (sc->ti_copper) { 240563699Swpaul if (media & TI_LNK_100MB) 240663699Swpaul ifmr->ifm_active |= IFM_100_TX; 240763699Swpaul if (media & TI_LNK_10MB) 240863699Swpaul ifmr->ifm_active |= IFM_10_T; 240963699Swpaul } else { 241063699Swpaul if (media & TI_LNK_100MB) 241163699Swpaul ifmr->ifm_active |= IFM_100_FX; 241263699Swpaul if (media & TI_LNK_10MB) 241363699Swpaul ifmr->ifm_active |= IFM_10_FL; 241463699Swpaul } 241545386Swpaul if (media & TI_LNK_FULL_DUPLEX) 241645386Swpaul ifmr->ifm_active |= IFM_FDX; 241745386Swpaul if (media & TI_LNK_HALF_DUPLEX) 241845386Swpaul ifmr->ifm_active |= IFM_HDX; 241945386Swpaul } 242045386Swpaul 242145386Swpaul return; 242245386Swpaul} 242345386Swpaul 242445386Swpaulstatic int ti_ioctl(ifp, command, data) 242545386Swpaul struct ifnet *ifp; 242645386Swpaul u_long command; 242745386Swpaul caddr_t data; 242845386Swpaul{ 242945386Swpaul struct ti_softc *sc = ifp->if_softc; 243045386Swpaul struct ifreq *ifr = (struct ifreq *) data; 243145386Swpaul int s, error = 0; 243245386Swpaul struct ti_cmd_desc cmd; 243345386Swpaul 243445386Swpaul s = splimp(); 243545386Swpaul 243645386Swpaul switch(command) { 243745386Swpaul case SIOCSIFADDR: 243845386Swpaul case SIOCGIFADDR: 243945386Swpaul error = ether_ioctl(ifp, command, data); 244045386Swpaul break; 244145386Swpaul case SIOCSIFMTU: 244245386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 244345386Swpaul error = EINVAL; 244445386Swpaul else { 244545386Swpaul ifp->if_mtu = ifr->ifr_mtu; 244645386Swpaul ti_init(sc); 244745386Swpaul } 244845386Swpaul break; 244945386Swpaul case SIOCSIFFLAGS: 245045386Swpaul if (ifp->if_flags & IFF_UP) { 245145386Swpaul /* 245245386Swpaul * If only the state of the PROMISC flag changed, 245345386Swpaul * then just use the 'set promisc mode' command 245445386Swpaul * instead of reinitializing the entire NIC. Doing 245545386Swpaul * a full re-init means reloading the firmware and 245645386Swpaul * waiting for it to start up, which may take a 245745386Swpaul * second or two. 245845386Swpaul */ 245945386Swpaul if (ifp->if_flags & IFF_RUNNING && 246045386Swpaul ifp->if_flags & IFF_PROMISC && 246145386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 246245386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 246345386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 246445386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 246545386Swpaul !(ifp->if_flags & IFF_PROMISC) && 246645386Swpaul sc->ti_if_flags & IFF_PROMISC) { 246745386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 246845386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 246945386Swpaul } else 247045386Swpaul ti_init(sc); 247145386Swpaul } else { 247245386Swpaul if (ifp->if_flags & IFF_RUNNING) { 247345386Swpaul ti_stop(sc); 247445386Swpaul } 247545386Swpaul } 247645386Swpaul sc->ti_if_flags = ifp->if_flags; 247745386Swpaul error = 0; 247845386Swpaul break; 247945386Swpaul case SIOCADDMULTI: 248045386Swpaul case SIOCDELMULTI: 248145386Swpaul if (ifp->if_flags & IFF_RUNNING) { 248245386Swpaul ti_setmulti(sc); 248345386Swpaul error = 0; 248445386Swpaul } 248545386Swpaul break; 248645386Swpaul case SIOCSIFMEDIA: 248745386Swpaul case SIOCGIFMEDIA: 248845386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 248945386Swpaul break; 249045386Swpaul default: 249145386Swpaul error = EINVAL; 249245386Swpaul break; 249345386Swpaul } 249445386Swpaul 249545386Swpaul (void)splx(s); 249645386Swpaul 249745386Swpaul return(error); 249845386Swpaul} 249945386Swpaul 250045386Swpaulstatic void ti_watchdog(ifp) 250145386Swpaul struct ifnet *ifp; 250245386Swpaul{ 250345386Swpaul struct ti_softc *sc; 250445386Swpaul 250545386Swpaul sc = ifp->if_softc; 250645386Swpaul 250745386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 250845386Swpaul ti_stop(sc); 250945386Swpaul ti_init(sc); 251045386Swpaul 251145386Swpaul ifp->if_oerrors++; 251245386Swpaul 251345386Swpaul return; 251445386Swpaul} 251545386Swpaul 251645386Swpaul/* 251745386Swpaul * Stop the adapter and free any mbufs allocated to the 251845386Swpaul * RX and TX lists. 251945386Swpaul */ 252045386Swpaulstatic void ti_stop(sc) 252145386Swpaul struct ti_softc *sc; 252245386Swpaul{ 252345386Swpaul struct ifnet *ifp; 252445386Swpaul struct ti_cmd_desc cmd; 252545386Swpaul 252645386Swpaul ifp = &sc->arpcom.ac_if; 252745386Swpaul 252845386Swpaul /* Disable host interrupts. */ 252945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 253045386Swpaul /* 253145386Swpaul * Tell firmware we're shutting down. 253245386Swpaul */ 253345386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 253445386Swpaul 253545386Swpaul /* Halt and reinitialize. */ 253645386Swpaul ti_chipinit(sc); 253745386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 253845386Swpaul ti_chipinit(sc); 253945386Swpaul 254045386Swpaul /* Free the RX lists. */ 254145386Swpaul ti_free_rx_ring_std(sc); 254245386Swpaul 254345386Swpaul /* Free jumbo RX list. */ 254445386Swpaul ti_free_rx_ring_jumbo(sc); 254545386Swpaul 254645386Swpaul /* Free mini RX list. */ 254745386Swpaul ti_free_rx_ring_mini(sc); 254845386Swpaul 254945386Swpaul /* Free TX buffers. */ 255045386Swpaul ti_free_tx_ring(sc); 255145386Swpaul 255245386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 255345386Swpaul sc->ti_return_prodidx.ti_idx = 0; 255445386Swpaul sc->ti_tx_considx.ti_idx = 0; 255545386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 255645386Swpaul 255745386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 255845386Swpaul 255945386Swpaul return; 256045386Swpaul} 256145386Swpaul 256245386Swpaul/* 256345386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 256445386Swpaul * get confused by errant DMAs when rebooting. 256545386Swpaul */ 256649011Swpaulstatic void ti_shutdown(dev) 256749011Swpaul device_t dev; 256845386Swpaul{ 256945386Swpaul struct ti_softc *sc; 257045386Swpaul 257149011Swpaul sc = device_get_softc(dev); 257245386Swpaul 257345386Swpaul ti_chipinit(sc); 257445386Swpaul 257545386Swpaul return; 257645386Swpaul} 2577