if_ti.c revision 62793
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 62793 2000-07-08 00:14:12Z gallatin $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include "vlan.h" 8245386Swpaul 8345386Swpaul#include <sys/param.h> 8445386Swpaul#include <sys/systm.h> 8545386Swpaul#include <sys/sockio.h> 8645386Swpaul#include <sys/mbuf.h> 8745386Swpaul#include <sys/malloc.h> 8845386Swpaul#include <sys/kernel.h> 8945386Swpaul#include <sys/socket.h> 9045386Swpaul#include <sys/queue.h> 9145386Swpaul 9245386Swpaul#include <net/if.h> 9345386Swpaul#include <net/if_arp.h> 9445386Swpaul#include <net/ethernet.h> 9545386Swpaul#include <net/if_dl.h> 9645386Swpaul#include <net/if_media.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#if NVLAN > 0 10145386Swpaul#include <net/if_types.h> 10245386Swpaul#include <net/if_vlan_var.h> 10345386Swpaul#endif 10445386Swpaul 10545386Swpaul#include <netinet/in_systm.h> 10645386Swpaul#include <netinet/in.h> 10745386Swpaul#include <netinet/ip.h> 10845386Swpaul 10945386Swpaul#include <vm/vm.h> /* for vtophys */ 11045386Swpaul#include <vm/pmap.h> /* for vtophys */ 11145386Swpaul#include <machine/clock.h> /* for DELAY */ 11245386Swpaul#include <machine/bus_memio.h> 11345386Swpaul#include <machine/bus.h> 11449011Swpaul#include <machine/resource.h> 11549011Swpaul#include <sys/bus.h> 11649011Swpaul#include <sys/rman.h> 11745386Swpaul 11845386Swpaul#include <pci/pcireg.h> 11945386Swpaul#include <pci/pcivar.h> 12045386Swpaul 12145386Swpaul#include <pci/if_tireg.h> 12245386Swpaul#include <pci/ti_fw.h> 12345386Swpaul#include <pci/ti_fw2.h> 12445386Swpaul 12558698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12645386Swpaul 12745386Swpaul#if !defined(lint) 12845386Swpaulstatic const char rcsid[] = 12950477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 62793 2000-07-08 00:14:12Z gallatin $"; 13045386Swpaul#endif 13145386Swpaul 13245386Swpaul/* 13345386Swpaul * Various supported device vendors/types and their names. 13445386Swpaul */ 13545386Swpaul 13645386Swpaulstatic struct ti_type ti_devs[] = { 13745386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13845386Swpaul "Alteon AceNIC Gigabit Ethernet" }, 13945386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 14045386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 14145386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 14245386Swpaul "Netgear GA620 Gigabit Ethernet" }, 14345386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14445386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14556206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 14656206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 14745386Swpaul { 0, 0, NULL } 14845386Swpaul}; 14945386Swpaul 15049011Swpaulstatic int ti_probe __P((device_t)); 15149011Swpaulstatic int ti_attach __P((device_t)); 15249011Swpaulstatic int ti_detach __P((device_t)); 15345386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15445386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15545386Swpaul 15645386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 15745386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 15845386Swpaul u_int32_t *)); 15945386Swpaul 16045386Swpaulstatic void ti_intr __P((void *)); 16145386Swpaulstatic void ti_start __P((struct ifnet *)); 16245386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16345386Swpaulstatic void ti_init __P((void *)); 16445386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16545386Swpaulstatic void ti_stop __P((struct ti_softc *)); 16645386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 16749011Swpaulstatic void ti_shutdown __P((device_t)); 16845386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 16945386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17045386Swpaul 17145386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17245386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17345386Swpaul int, u_int8_t *)); 17445386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17545386Swpaul 17645386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 17745386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 17845386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 17945386Swpaul 18045386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18145386Swpaul u_int32_t, caddr_t)); 18245386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18345386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18445386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18545386Swpaul caddr_t, int)); 18645386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 18745386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 18845386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 18945386Swpaulstatic void ti_jfree __P((caddr_t, u_int)); 19045386Swpaulstatic void ti_jref __P((caddr_t, u_int)); 19145386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19245386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19345386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19445386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19545386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19645386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 19745386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 19845386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 19945386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20045386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 20145386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 20245386Swpaul 20345386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20445386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20545386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 20645386Swpaul 20749011Swpaulstatic device_method_t ti_methods[] = { 20849011Swpaul /* Device interface */ 20949011Swpaul DEVMETHOD(device_probe, ti_probe), 21049011Swpaul DEVMETHOD(device_attach, ti_attach), 21149011Swpaul DEVMETHOD(device_detach, ti_detach), 21249011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 21349011Swpaul { 0, 0 } 21449011Swpaul}; 21549011Swpaul 21649011Swpaulstatic driver_t ti_driver = { 21751455Swpaul "ti", 21849011Swpaul ti_methods, 21949011Swpaul sizeof(struct ti_softc) 22049011Swpaul}; 22149011Swpaul 22249011Swpaulstatic devclass_t ti_devclass; 22349011Swpaul 22451533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22549011Swpaul 22645386Swpaul/* 22745386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 22845386Swpaul */ 22945386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 23045386Swpaul struct ti_softc *sc; 23145386Swpaul int byte; 23245386Swpaul{ 23345386Swpaul register int i, ack = 0; 23445386Swpaul 23545386Swpaul /* 23645386Swpaul * Make sure we're in TX mode. 23745386Swpaul */ 23845386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 23945386Swpaul 24045386Swpaul /* 24145386Swpaul * Feed in each bit and stobe the clock. 24245386Swpaul */ 24345386Swpaul for (i = 0x80; i; i >>= 1) { 24445386Swpaul if (byte & i) { 24545386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24645386Swpaul } else { 24745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24845386Swpaul } 24945386Swpaul DELAY(1); 25045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25145386Swpaul DELAY(1); 25245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25345386Swpaul } 25445386Swpaul 25545386Swpaul /* 25645386Swpaul * Turn off TX mode. 25745386Swpaul */ 25845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 25945386Swpaul 26045386Swpaul /* 26145386Swpaul * Check for ack. 26245386Swpaul */ 26345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26445386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26645386Swpaul 26745386Swpaul return(ack); 26845386Swpaul} 26945386Swpaul 27045386Swpaul/* 27145386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 27245386Swpaul * We have to send two address bytes since the EEPROM can hold 27345386Swpaul * more than 256 bytes of data. 27445386Swpaul */ 27545386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 27645386Swpaul struct ti_softc *sc; 27745386Swpaul int addr; 27845386Swpaul u_int8_t *dest; 27945386Swpaul{ 28045386Swpaul register int i; 28145386Swpaul u_int8_t byte = 0; 28245386Swpaul 28345386Swpaul EEPROM_START; 28445386Swpaul 28545386Swpaul /* 28645386Swpaul * Send write control code to EEPROM. 28745386Swpaul */ 28845386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 28945386Swpaul printf("ti%d: failed to send write command, status: %x\n", 29045386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29145386Swpaul return(1); 29245386Swpaul } 29345386Swpaul 29445386Swpaul /* 29545386Swpaul * Send first byte of address of byte we want to read. 29645386Swpaul */ 29745386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 29845386Swpaul printf("ti%d: failed to send address, status: %x\n", 29945386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30045386Swpaul return(1); 30145386Swpaul } 30245386Swpaul /* 30345386Swpaul * Send second byte address of byte we want to read. 30445386Swpaul */ 30545386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 30645386Swpaul printf("ti%d: failed to send address, status: %x\n", 30745386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30845386Swpaul return(1); 30945386Swpaul } 31045386Swpaul 31145386Swpaul EEPROM_STOP; 31245386Swpaul EEPROM_START; 31345386Swpaul /* 31445386Swpaul * Send read control code to EEPROM. 31545386Swpaul */ 31645386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 31745386Swpaul printf("ti%d: failed to send read command, status: %x\n", 31845386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31945386Swpaul return(1); 32045386Swpaul } 32145386Swpaul 32245386Swpaul /* 32345386Swpaul * Start reading bits from EEPROM. 32445386Swpaul */ 32545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 32645386Swpaul for (i = 0x80; i; i >>= 1) { 32745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 32845386Swpaul DELAY(1); 32945386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 33045386Swpaul byte |= i; 33145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33245386Swpaul DELAY(1); 33345386Swpaul } 33445386Swpaul 33545386Swpaul EEPROM_STOP; 33645386Swpaul 33745386Swpaul /* 33845386Swpaul * No ACK generated for read, so just return byte. 33945386Swpaul */ 34045386Swpaul 34145386Swpaul *dest = byte; 34245386Swpaul 34345386Swpaul return(0); 34445386Swpaul} 34545386Swpaul 34645386Swpaul/* 34745386Swpaul * Read a sequence of bytes from the EEPROM. 34845386Swpaul */ 34945386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 35045386Swpaul struct ti_softc *sc; 35145386Swpaul caddr_t dest; 35245386Swpaul int off; 35345386Swpaul int cnt; 35445386Swpaul{ 35545386Swpaul int err = 0, i; 35645386Swpaul u_int8_t byte = 0; 35745386Swpaul 35845386Swpaul for (i = 0; i < cnt; i++) { 35945386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 36045386Swpaul if (err) 36145386Swpaul break; 36245386Swpaul *(dest + i) = byte; 36345386Swpaul } 36445386Swpaul 36545386Swpaul return(err ? 1 : 0); 36645386Swpaul} 36745386Swpaul 36845386Swpaul/* 36945386Swpaul * NIC memory access function. Can be used to either clear a section 37045386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 37145386Swpaul */ 37245386Swpaulstatic void ti_mem(sc, addr, len, buf) 37345386Swpaul struct ti_softc *sc; 37445386Swpaul u_int32_t addr, len; 37545386Swpaul caddr_t buf; 37645386Swpaul{ 37745386Swpaul int segptr, segsize, cnt; 37845386Swpaul caddr_t ti_winbase, ptr; 37945386Swpaul 38045386Swpaul segptr = addr; 38145386Swpaul cnt = len; 38249133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 38345386Swpaul ptr = buf; 38445386Swpaul 38545386Swpaul while(cnt) { 38645386Swpaul if (cnt < TI_WINLEN) 38745386Swpaul segsize = cnt; 38845386Swpaul else 38945386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 39045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 39145386Swpaul if (buf == NULL) 39245386Swpaul bzero((char *)ti_winbase + (segptr & 39345386Swpaul (TI_WINLEN - 1)), segsize); 39445386Swpaul else { 39545386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 39645386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 39745386Swpaul ptr += segsize; 39845386Swpaul } 39945386Swpaul segptr += segsize; 40045386Swpaul cnt -= segsize; 40145386Swpaul } 40245386Swpaul 40345386Swpaul return; 40445386Swpaul} 40545386Swpaul 40645386Swpaul/* 40745386Swpaul * Load firmware image into the NIC. Check that the firmware revision 40845386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 40945386Swpaul * Tigon 2. 41045386Swpaul */ 41145386Swpaulstatic void ti_loadfw(sc) 41245386Swpaul struct ti_softc *sc; 41345386Swpaul{ 41445386Swpaul switch(sc->ti_hwrev) { 41545386Swpaul case TI_HWREV_TIGON: 41645386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 41745386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 41845386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 41945386Swpaul printf("ti%d: firmware revision mismatch; want " 42045386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 42145386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 42245386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 42345386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 42445386Swpaul return; 42545386Swpaul } 42645386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 42745386Swpaul (caddr_t)tigonFwText); 42845386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 42945386Swpaul (caddr_t)tigonFwData); 43045386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 43145386Swpaul (caddr_t)tigonFwRodata); 43245386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 43345386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 43445386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43545386Swpaul break; 43645386Swpaul case TI_HWREV_TIGON_II: 43745386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 43845386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 43945386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 44045386Swpaul printf("ti%d: firmware revision mismatch; want " 44145386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 44245386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 44345386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 44445386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44545386Swpaul return; 44645386Swpaul } 44745386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 44845386Swpaul (caddr_t)tigon2FwText); 44945386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 45045386Swpaul (caddr_t)tigon2FwData); 45145386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 45245386Swpaul (caddr_t)tigon2FwRodata); 45345386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 45445386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45545386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 45645386Swpaul break; 45745386Swpaul default: 45845386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 45945386Swpaul sc->ti_unit); 46045386Swpaul break; 46145386Swpaul } 46245386Swpaul 46345386Swpaul return; 46445386Swpaul} 46545386Swpaul 46645386Swpaul/* 46745386Swpaul * Send the NIC a command via the command ring. 46845386Swpaul */ 46945386Swpaulstatic void ti_cmd(sc, cmd) 47045386Swpaul struct ti_softc *sc; 47145386Swpaul struct ti_cmd_desc *cmd; 47245386Swpaul{ 47345386Swpaul u_int32_t index; 47445386Swpaul 47545386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 47645386Swpaul return; 47745386Swpaul 47845386Swpaul index = sc->ti_cmd_saved_prodidx; 47945386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 48045386Swpaul TI_INC(index, TI_CMD_RING_CNT); 48145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 48245386Swpaul sc->ti_cmd_saved_prodidx = index; 48345386Swpaul 48445386Swpaul return; 48545386Swpaul} 48645386Swpaul 48745386Swpaul/* 48845386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 48945386Swpaul * number of command slots to include after the initial command. 49045386Swpaul */ 49145386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 49245386Swpaul struct ti_softc *sc; 49345386Swpaul struct ti_cmd_desc *cmd; 49445386Swpaul caddr_t arg; 49545386Swpaul int len; 49645386Swpaul{ 49745386Swpaul u_int32_t index; 49845386Swpaul register int i; 49945386Swpaul 50045386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 50145386Swpaul return; 50245386Swpaul 50345386Swpaul index = sc->ti_cmd_saved_prodidx; 50445386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50545386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50645386Swpaul for (i = 0; i < len; i++) { 50745386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 50845386Swpaul *(u_int32_t *)(&arg[i * 4])); 50945386Swpaul TI_INC(index, TI_CMD_RING_CNT); 51045386Swpaul } 51145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 51245386Swpaul sc->ti_cmd_saved_prodidx = index; 51345386Swpaul 51445386Swpaul return; 51545386Swpaul} 51645386Swpaul 51745386Swpaul/* 51845386Swpaul * Handle events that have triggered interrupts. 51945386Swpaul */ 52045386Swpaulstatic void ti_handle_events(sc) 52145386Swpaul struct ti_softc *sc; 52245386Swpaul{ 52345386Swpaul struct ti_event_desc *e; 52445386Swpaul 52545386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 52645386Swpaul return; 52745386Swpaul 52845386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 52945386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 53045386Swpaul switch(e->ti_event) { 53145386Swpaul case TI_EV_LINKSTAT_CHANGED: 53245386Swpaul sc->ti_linkstat = e->ti_code; 53345386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 53445386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53545386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 53645386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 53745386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 53845386Swpaul printf("ti%d: link down\n", sc->ti_unit); 53945386Swpaul break; 54045386Swpaul case TI_EV_ERROR: 54145386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 54245386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 54345386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 54445386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54545386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 54645386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 54745386Swpaul break; 54845386Swpaul case TI_EV_FIRMWARE_UP: 54945386Swpaul ti_init2(sc); 55045386Swpaul break; 55145386Swpaul case TI_EV_STATS_UPDATED: 55245386Swpaul ti_stats_update(sc); 55345386Swpaul break; 55445386Swpaul case TI_EV_RESET_JUMBO_RING: 55545386Swpaul case TI_EV_MCAST_UPDATED: 55645386Swpaul /* Who cares. */ 55745386Swpaul break; 55845386Swpaul default: 55945386Swpaul printf("ti%d: unknown event: %d\n", 56045386Swpaul sc->ti_unit, e->ti_event); 56145386Swpaul break; 56245386Swpaul } 56345386Swpaul /* Advance the consumer index. */ 56445386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56545386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 56645386Swpaul } 56745386Swpaul 56845386Swpaul return; 56945386Swpaul} 57045386Swpaul 57145386Swpaul/* 57245386Swpaul * Memory management for the jumbo receive ring is a pain in the 57345386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 57445386Swpaul * _and_ it has to be contiguous (unless you use the extended 57545386Swpaul * jumbo descriptor format). Using malloc() all the time won't 57645386Swpaul * work: malloc() allocates memory in powers of two, which means we 57745386Swpaul * would end up wasting a considerable amount of space by allocating 57845386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 57945386Swpaul * to do our own memory management. 58045386Swpaul * 58145386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 58245386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 58345386Swpaul * as external mbuf storage. 58445386Swpaul * 58545386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 58645386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 58745386Swpaul * RAM. This is a bit much, especially considering we also need 58845386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 58945386Swpaul * save space, we only actually allocate enough memory for 64 slots 59045386Swpaul * by default, which works out to between 500 and 600K. This can 59145386Swpaul * be tuned by changing a #define in if_tireg.h. 59245386Swpaul */ 59345386Swpaul 59445386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59545386Swpaul struct ti_softc *sc; 59645386Swpaul{ 59745386Swpaul caddr_t ptr; 59845386Swpaul register int i; 59945386Swpaul struct ti_jpool_entry *entry; 60045386Swpaul 60145386Swpaul /* Grab a big chunk o' storage. */ 60245386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 60350548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 60445386Swpaul 60545386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 60645386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 60745386Swpaul return(ENOBUFS); 60845386Swpaul } 60945386Swpaul 61045386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 61145386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 61245386Swpaul 61345386Swpaul /* 61445386Swpaul * Now divide it up into 9K pieces and save the addresses 61545386Swpaul * in an array. Note that we play an evil trick here by using 61645386Swpaul * the first few bytes in the buffer to hold the the address 61745386Swpaul * of the softc structure for this interface. This is because 61845386Swpaul * ti_jfree() needs it, but it is called by the mbuf management 61945386Swpaul * code which will not pass it to us explicitly. 62045386Swpaul */ 62145386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 62245386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 62345386Swpaul u_int64_t **aptr; 62445386Swpaul aptr = (u_int64_t **)ptr; 62545386Swpaul aptr[0] = (u_int64_t *)sc; 62645386Swpaul ptr += sizeof(u_int64_t); 62745386Swpaul sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 62845386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 62945386Swpaul ptr += (TI_JLEN - sizeof(u_int64_t)); 63045386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 63145386Swpaul M_DEVBUF, M_NOWAIT); 63245386Swpaul if (entry == NULL) { 63362793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 63462793Sgallatin M_DEVBUF); 63545386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 63645386Swpaul printf("ti%d: no memory for jumbo " 63745386Swpaul "buffer queue!\n", sc->ti_unit); 63845386Swpaul return(ENOBUFS); 63945386Swpaul } 64045386Swpaul entry->slot = i; 64145386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 64245386Swpaul } 64345386Swpaul 64445386Swpaul return(0); 64545386Swpaul} 64645386Swpaul 64745386Swpaul/* 64845386Swpaul * Allocate a jumbo buffer. 64945386Swpaul */ 65045386Swpaulstatic void *ti_jalloc(sc) 65145386Swpaul struct ti_softc *sc; 65245386Swpaul{ 65345386Swpaul struct ti_jpool_entry *entry; 65445386Swpaul 65545386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 65645386Swpaul 65745386Swpaul if (entry == NULL) { 65845386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 65945386Swpaul return(NULL); 66045386Swpaul } 66145386Swpaul 66245386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 66345386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 66445386Swpaul sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 66545386Swpaul return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 66645386Swpaul} 66745386Swpaul 66845386Swpaul/* 66945386Swpaul * Adjust usage count on a jumbo buffer. In general this doesn't 67045386Swpaul * get used much because our jumbo buffers don't get passed around 67145386Swpaul * too much, but it's implemented for correctness. 67245386Swpaul */ 67345386Swpaulstatic void ti_jref(buf, size) 67445386Swpaul caddr_t buf; 67545386Swpaul u_int size; 67645386Swpaul{ 67745386Swpaul struct ti_softc *sc; 67845386Swpaul u_int64_t **aptr; 67945386Swpaul register int i; 68045386Swpaul 68145386Swpaul /* Extract the softc struct pointer. */ 68245386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 68345386Swpaul sc = (struct ti_softc *)(aptr[0]); 68445386Swpaul 68545386Swpaul if (sc == NULL) 68645386Swpaul panic("ti_jref: can't find softc pointer!"); 68745386Swpaul 68849036Swpaul if (size != TI_JUMBO_FRAMELEN) 68945386Swpaul panic("ti_jref: adjusting refcount of buf of wrong size!"); 69045386Swpaul 69145386Swpaul /* calculate the slot this buffer belongs to */ 69245386Swpaul 69345386Swpaul i = ((vm_offset_t)aptr 69445386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 69545386Swpaul 69645386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 69745386Swpaul panic("ti_jref: asked to reference buffer " 69845386Swpaul "that we don't manage!"); 69945386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 70045386Swpaul panic("ti_jref: buffer already free!"); 70145386Swpaul else 70245386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse++; 70345386Swpaul 70445386Swpaul return; 70545386Swpaul} 70645386Swpaul 70745386Swpaul/* 70845386Swpaul * Release a jumbo buffer. 70945386Swpaul */ 71045386Swpaulstatic void ti_jfree(buf, size) 71145386Swpaul caddr_t buf; 71245386Swpaul u_int size; 71345386Swpaul{ 71445386Swpaul struct ti_softc *sc; 71545386Swpaul u_int64_t **aptr; 71645386Swpaul int i; 71745386Swpaul struct ti_jpool_entry *entry; 71845386Swpaul 71945386Swpaul /* Extract the softc struct pointer. */ 72045386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 72145386Swpaul sc = (struct ti_softc *)(aptr[0]); 72245386Swpaul 72345386Swpaul if (sc == NULL) 72445386Swpaul panic("ti_jfree: can't find softc pointer!"); 72545386Swpaul 72649036Swpaul if (size != TI_JUMBO_FRAMELEN) 72745386Swpaul panic("ti_jfree: freeing buffer of wrong size!"); 72845386Swpaul 72945386Swpaul /* calculate the slot this buffer belongs to */ 73045386Swpaul 73145386Swpaul i = ((vm_offset_t)aptr 73245386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 73345386Swpaul 73445386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 73545386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 73645386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 73745386Swpaul panic("ti_jfree: buffer already free!"); 73845386Swpaul else { 73945386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse--; 74045386Swpaul if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 74145386Swpaul entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 74245386Swpaul if (entry == NULL) 74345386Swpaul panic("ti_jfree: buffer not in use!"); 74445386Swpaul entry->slot = i; 74545386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 74645386Swpaul jpool_entries); 74745386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 74845386Swpaul entry, jpool_entries); 74945386Swpaul } 75045386Swpaul } 75145386Swpaul 75245386Swpaul return; 75345386Swpaul} 75445386Swpaul 75545386Swpaul 75645386Swpaul/* 75745386Swpaul * Intialize a standard receive ring descriptor. 75845386Swpaul */ 75945386Swpaulstatic int ti_newbuf_std(sc, i, m) 76045386Swpaul struct ti_softc *sc; 76145386Swpaul int i; 76245386Swpaul struct mbuf *m; 76345386Swpaul{ 76445386Swpaul struct mbuf *m_new = NULL; 76545386Swpaul struct ti_rx_desc *r; 76645386Swpaul 76749036Swpaul if (m == NULL) { 76845386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 76945386Swpaul if (m_new == NULL) { 77045386Swpaul printf("ti%d: mbuf allocation failed " 77145386Swpaul "-- packet dropped!\n", sc->ti_unit); 77245386Swpaul return(ENOBUFS); 77345386Swpaul } 77445386Swpaul 77545386Swpaul MCLGET(m_new, M_DONTWAIT); 77645386Swpaul if (!(m_new->m_flags & M_EXT)) { 77745386Swpaul printf("ti%d: cluster allocation failed " 77845386Swpaul "-- packet dropped!\n", sc->ti_unit); 77945386Swpaul m_freem(m_new); 78045386Swpaul return(ENOBUFS); 78145386Swpaul } 78249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 78349036Swpaul } else { 78449036Swpaul m_new = m; 78549036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 78649036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 78745386Swpaul } 78845386Swpaul 78948597Swpaul m_adj(m_new, ETHER_ALIGN); 79045386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 79145386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 79245386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 79345386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 79445386Swpaul r->ti_flags = 0; 79558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 79658698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 79749036Swpaul r->ti_len = m_new->m_len; 79845386Swpaul r->ti_idx = i; 79945386Swpaul 80045386Swpaul return(0); 80145386Swpaul} 80245386Swpaul 80345386Swpaul/* 80445386Swpaul * Intialize a mini receive ring descriptor. This only applies to 80545386Swpaul * the Tigon 2. 80645386Swpaul */ 80745386Swpaulstatic int ti_newbuf_mini(sc, i, m) 80845386Swpaul struct ti_softc *sc; 80945386Swpaul int i; 81045386Swpaul struct mbuf *m; 81145386Swpaul{ 81245386Swpaul struct mbuf *m_new = NULL; 81345386Swpaul struct ti_rx_desc *r; 81445386Swpaul 81549036Swpaul if (m == NULL) { 81645386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 81745386Swpaul if (m_new == NULL) { 81845386Swpaul printf("ti%d: mbuf allocation failed " 81945386Swpaul "-- packet dropped!\n", sc->ti_unit); 82045386Swpaul return(ENOBUFS); 82145386Swpaul } 82249036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 82349036Swpaul } else { 82449036Swpaul m_new = m; 82549036Swpaul m_new->m_data = m_new->m_pktdat; 82649036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 82745386Swpaul } 82849036Swpaul 82948597Swpaul m_adj(m_new, ETHER_ALIGN); 83045386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 83145386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 83245386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 83345386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 83445386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 83558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 83658698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 83749036Swpaul r->ti_len = m_new->m_len; 83845386Swpaul r->ti_idx = i; 83945386Swpaul 84045386Swpaul return(0); 84145386Swpaul} 84245386Swpaul 84345386Swpaul/* 84445386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 84545386Swpaul * a jumbo buffer from the pool managed internally by the driver. 84645386Swpaul */ 84745386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 84845386Swpaul struct ti_softc *sc; 84945386Swpaul int i; 85045386Swpaul struct mbuf *m; 85145386Swpaul{ 85245386Swpaul struct mbuf *m_new = NULL; 85345386Swpaul struct ti_rx_desc *r; 85445386Swpaul 85549036Swpaul if (m == NULL) { 85645386Swpaul caddr_t *buf = NULL; 85745386Swpaul 85845386Swpaul /* Allocate the mbuf. */ 85945386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 86045386Swpaul if (m_new == NULL) { 86145386Swpaul printf("ti%d: mbuf allocation failed " 86245386Swpaul "-- packet dropped!\n", sc->ti_unit); 86345386Swpaul return(ENOBUFS); 86445386Swpaul } 86545386Swpaul 86645386Swpaul /* Allocate the jumbo buffer */ 86745386Swpaul buf = ti_jalloc(sc); 86845386Swpaul if (buf == NULL) { 86945386Swpaul m_freem(m_new); 87045386Swpaul printf("ti%d: jumbo allocation failed " 87145386Swpaul "-- packet dropped!\n", sc->ti_unit); 87245386Swpaul return(ENOBUFS); 87345386Swpaul } 87445386Swpaul 87545386Swpaul /* Attach the buffer to the mbuf. */ 87645386Swpaul m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 87745386Swpaul m_new->m_flags |= M_EXT; 87849036Swpaul m_new->m_len = m_new->m_pkthdr.len = 87949036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 88045386Swpaul m_new->m_ext.ext_free = ti_jfree; 88145386Swpaul m_new->m_ext.ext_ref = ti_jref; 88249036Swpaul } else { 88349036Swpaul m_new = m; 88449036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 88549036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 88645386Swpaul } 88745386Swpaul 88849780Swpaul m_adj(m_new, ETHER_ALIGN); 88945386Swpaul /* Set up the descriptor. */ 89045386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 89145386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 89245386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 89345386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 89445386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 89558698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 89658698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 89749036Swpaul r->ti_len = m_new->m_len; 89845386Swpaul r->ti_idx = i; 89945386Swpaul 90045386Swpaul return(0); 90145386Swpaul} 90245386Swpaul 90345386Swpaul/* 90445386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 90545386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 90645386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 90745386Swpaul * the NIC. 90845386Swpaul */ 90945386Swpaulstatic int ti_init_rx_ring_std(sc) 91045386Swpaul struct ti_softc *sc; 91145386Swpaul{ 91245386Swpaul register int i; 91345386Swpaul struct ti_cmd_desc cmd; 91445386Swpaul 91545386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 91645386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 91745386Swpaul return(ENOBUFS); 91845386Swpaul }; 91945386Swpaul 92045386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 92148597Swpaul sc->ti_std = i - 1; 92245386Swpaul 92345386Swpaul return(0); 92445386Swpaul} 92545386Swpaul 92645386Swpaulstatic void ti_free_rx_ring_std(sc) 92745386Swpaul struct ti_softc *sc; 92845386Swpaul{ 92945386Swpaul register int i; 93045386Swpaul 93145386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 93245386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 93345386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 93445386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 93545386Swpaul } 93645386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 93745386Swpaul sizeof(struct ti_rx_desc)); 93845386Swpaul } 93945386Swpaul 94045386Swpaul return; 94145386Swpaul} 94245386Swpaul 94345386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 94445386Swpaul struct ti_softc *sc; 94545386Swpaul{ 94645386Swpaul register int i; 94745386Swpaul struct ti_cmd_desc cmd; 94845386Swpaul 94945386Swpaul for (i = 0; i < (TI_JSLOTS - 20); i++) { 95045386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 95145386Swpaul return(ENOBUFS); 95245386Swpaul }; 95345386Swpaul 95445386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 95548597Swpaul sc->ti_jumbo = i - 1; 95645386Swpaul 95745386Swpaul return(0); 95845386Swpaul} 95945386Swpaul 96045386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 96145386Swpaul struct ti_softc *sc; 96245386Swpaul{ 96345386Swpaul register int i; 96445386Swpaul 96545386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 96645386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 96745386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 96845386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 96945386Swpaul } 97045386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 97145386Swpaul sizeof(struct ti_rx_desc)); 97245386Swpaul } 97345386Swpaul 97445386Swpaul return; 97545386Swpaul} 97645386Swpaul 97745386Swpaulstatic int ti_init_rx_ring_mini(sc) 97845386Swpaul struct ti_softc *sc; 97945386Swpaul{ 98045386Swpaul register int i; 98145386Swpaul 98245386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 98345386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 98445386Swpaul return(ENOBUFS); 98545386Swpaul }; 98645386Swpaul 98745386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 98848597Swpaul sc->ti_mini = i - 1; 98945386Swpaul 99045386Swpaul return(0); 99145386Swpaul} 99245386Swpaul 99345386Swpaulstatic void ti_free_rx_ring_mini(sc) 99445386Swpaul struct ti_softc *sc; 99545386Swpaul{ 99645386Swpaul register int i; 99745386Swpaul 99845386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 99945386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 100045386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 100145386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 100245386Swpaul } 100345386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 100445386Swpaul sizeof(struct ti_rx_desc)); 100545386Swpaul } 100645386Swpaul 100745386Swpaul return; 100845386Swpaul} 100945386Swpaul 101045386Swpaulstatic void ti_free_tx_ring(sc) 101145386Swpaul struct ti_softc *sc; 101245386Swpaul{ 101345386Swpaul register int i; 101445386Swpaul 101545386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 101645386Swpaul return; 101745386Swpaul 101845386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 101945386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 102045386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 102145386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 102245386Swpaul } 102345386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 102445386Swpaul sizeof(struct ti_tx_desc)); 102545386Swpaul } 102645386Swpaul 102745386Swpaul return; 102845386Swpaul} 102945386Swpaul 103045386Swpaulstatic int ti_init_tx_ring(sc) 103145386Swpaul struct ti_softc *sc; 103245386Swpaul{ 103348011Swpaul sc->ti_txcnt = 0; 103445386Swpaul sc->ti_tx_saved_considx = 0; 103545386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 103645386Swpaul return(0); 103745386Swpaul} 103845386Swpaul 103945386Swpaul/* 104045386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 104145386Swpaul * but we have to support the old way too so that Tigon 1 cards will 104245386Swpaul * work. 104345386Swpaul */ 104445386Swpaulvoid ti_add_mcast(sc, addr) 104545386Swpaul struct ti_softc *sc; 104645386Swpaul struct ether_addr *addr; 104745386Swpaul{ 104845386Swpaul struct ti_cmd_desc cmd; 104945386Swpaul u_int16_t *m; 105045386Swpaul u_int32_t ext[2] = {0, 0}; 105145386Swpaul 105245386Swpaul m = (u_int16_t *)&addr->octet[0]; 105345386Swpaul 105445386Swpaul switch(sc->ti_hwrev) { 105545386Swpaul case TI_HWREV_TIGON: 105645386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 105745386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 105845386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 105945386Swpaul break; 106045386Swpaul case TI_HWREV_TIGON_II: 106145386Swpaul ext[0] = htons(m[0]); 106245386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 106345386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 106445386Swpaul break; 106545386Swpaul default: 106645386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 106745386Swpaul break; 106845386Swpaul } 106945386Swpaul 107045386Swpaul return; 107145386Swpaul} 107245386Swpaul 107345386Swpaulvoid ti_del_mcast(sc, addr) 107445386Swpaul struct ti_softc *sc; 107545386Swpaul struct ether_addr *addr; 107645386Swpaul{ 107745386Swpaul struct ti_cmd_desc cmd; 107845386Swpaul u_int16_t *m; 107945386Swpaul u_int32_t ext[2] = {0, 0}; 108045386Swpaul 108145386Swpaul m = (u_int16_t *)&addr->octet[0]; 108245386Swpaul 108345386Swpaul switch(sc->ti_hwrev) { 108445386Swpaul case TI_HWREV_TIGON: 108545386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 108645386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 108745386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 108845386Swpaul break; 108945386Swpaul case TI_HWREV_TIGON_II: 109045386Swpaul ext[0] = htons(m[0]); 109145386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 109245386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 109345386Swpaul break; 109445386Swpaul default: 109545386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 109645386Swpaul break; 109745386Swpaul } 109845386Swpaul 109945386Swpaul return; 110045386Swpaul} 110145386Swpaul 110245386Swpaul/* 110345386Swpaul * Configure the Tigon's multicast address filter. 110445386Swpaul * 110545386Swpaul * The actual multicast table management is a bit of a pain, thanks to 110645386Swpaul * slight brain damage on the part of both Alteon and us. With our 110745386Swpaul * multicast code, we are only alerted when the multicast address table 110845386Swpaul * changes and at that point we only have the current list of addresses: 110945386Swpaul * we only know the current state, not the previous state, so we don't 111045386Swpaul * actually know what addresses were removed or added. The firmware has 111145386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 111245386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 111345386Swpaul * state so we know what addresses have been programmed into the NIC at 111445386Swpaul * any given time. 111545386Swpaul */ 111645386Swpaulstatic void ti_setmulti(sc) 111745386Swpaul struct ti_softc *sc; 111845386Swpaul{ 111945386Swpaul struct ifnet *ifp; 112045386Swpaul struct ifmultiaddr *ifma; 112145386Swpaul struct ti_cmd_desc cmd; 112245386Swpaul struct ti_mc_entry *mc; 112345386Swpaul u_int32_t intrs; 112445386Swpaul 112545386Swpaul ifp = &sc->arpcom.ac_if; 112645386Swpaul 112745386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 112845386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 112945386Swpaul return; 113045386Swpaul } else { 113145386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 113245386Swpaul } 113345386Swpaul 113445386Swpaul /* Disable interrupts. */ 113545386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 113645386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 113745386Swpaul 113845386Swpaul /* First, zot all the existing filters. */ 113945386Swpaul while (sc->ti_mc_listhead.slh_first != NULL) { 114045386Swpaul mc = sc->ti_mc_listhead.slh_first; 114145386Swpaul ti_del_mcast(sc, &mc->mc_addr); 114245386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 114345386Swpaul free(mc, M_DEVBUF); 114445386Swpaul } 114545386Swpaul 114645386Swpaul /* Now program new ones. */ 114745386Swpaul for (ifma = ifp->if_multiaddrs.lh_first; 114845386Swpaul ifma != NULL; ifma = ifma->ifma_link.le_next) { 114945386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 115045386Swpaul continue; 115145386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 115245386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 115345386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 115445386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 115545386Swpaul ti_add_mcast(sc, &mc->mc_addr); 115645386Swpaul } 115745386Swpaul 115845386Swpaul /* Re-enable interrupts. */ 115945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 116045386Swpaul 116145386Swpaul return; 116245386Swpaul} 116345386Swpaul 116445386Swpaul/* 116545386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 116645386Swpaul * we aren't actually in one. If we detect this condition, we can work 116745386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 116845386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 116945386Swpaul */ 117045386Swpaulstatic int ti_64bitslot_war(sc) 117145386Swpaul struct ti_softc *sc; 117245386Swpaul{ 117345386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 117445386Swpaul CSR_WRITE_4(sc, 0x600, 0); 117545386Swpaul CSR_WRITE_4(sc, 0x604, 0); 117645386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 117745386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 117845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 117945386Swpaul return(EINVAL); 118045386Swpaul else { 118145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 118245386Swpaul TI_PCISTATE_32BIT_BUS); 118345386Swpaul return(0); 118445386Swpaul } 118545386Swpaul } 118645386Swpaul } 118745386Swpaul 118845386Swpaul return(0); 118945386Swpaul} 119045386Swpaul 119145386Swpaul/* 119245386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 119345386Swpaul * self-test results. 119445386Swpaul */ 119545386Swpaulstatic int ti_chipinit(sc) 119645386Swpaul struct ti_softc *sc; 119745386Swpaul{ 119845386Swpaul u_int32_t cacheline; 119945386Swpaul u_int32_t pci_writemax = 0; 120045386Swpaul 120145386Swpaul /* Initialize link to down state. */ 120245386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 120345386Swpaul 120458698Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 120558698Sjlemon 120645386Swpaul /* Set endianness before we access any non-PCI registers. */ 120745386Swpaul#if BYTE_ORDER == BIG_ENDIAN 120845386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 120945386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 121045386Swpaul#else 121145386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 121245386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 121345386Swpaul#endif 121445386Swpaul 121545386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 121645386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 121745386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 121845386Swpaul return(ENODEV); 121945386Swpaul } 122045386Swpaul 122145386Swpaul /* Halt the CPU. */ 122245386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 122345386Swpaul 122445386Swpaul /* Figure out the hardware revision. */ 122545386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 122645386Swpaul case TI_REV_TIGON_I: 122745386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 122845386Swpaul break; 122945386Swpaul case TI_REV_TIGON_II: 123045386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 123145386Swpaul break; 123245386Swpaul default: 123345386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 123445386Swpaul return(ENODEV); 123545386Swpaul } 123645386Swpaul 123745386Swpaul /* Do special setup for Tigon 2. */ 123845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 123945386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 124045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 124145386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 124245386Swpaul } 124345386Swpaul 124445386Swpaul /* Set up the PCI state register. */ 124545386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 124645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 124745386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 124845386Swpaul } 124945386Swpaul 125045386Swpaul /* Clear the read/write max DMA parameters. */ 125145386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 125245386Swpaul TI_PCISTATE_READ_MAXDMA)); 125345386Swpaul 125445386Swpaul /* Get cache line size. */ 125545386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 125645386Swpaul 125745386Swpaul /* 125845386Swpaul * If the system has set enabled the PCI memory write 125945386Swpaul * and invalidate command in the command register, set 126045386Swpaul * the write max parameter accordingly. This is necessary 126145386Swpaul * to use MWI with the Tigon 2. 126245386Swpaul */ 126345386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 126445386Swpaul switch(cacheline) { 126545386Swpaul case 1: 126645386Swpaul case 4: 126745386Swpaul case 8: 126845386Swpaul case 16: 126945386Swpaul case 32: 127045386Swpaul case 64: 127145386Swpaul break; 127245386Swpaul default: 127345386Swpaul /* Disable PCI memory write and invalidate. */ 127445386Swpaul if (bootverbose) 127545386Swpaul printf("ti%d: cache line size %d not " 127645386Swpaul "supported; disabling PCI MWI\n", 127745386Swpaul sc->ti_unit, cacheline); 127845386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 127945386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 128045386Swpaul break; 128145386Swpaul } 128245386Swpaul } 128345386Swpaul 128445386Swpaul#ifdef __brokenalpha__ 128545386Swpaul /* 128645386Swpaul * From the Alteon sample driver: 128745386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 128845386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 128945386Swpaul * restriction on some ALPHA platforms with early revision 129045386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 129145386Swpaul */ 129245386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 129345386Swpaul#else 129445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 129545386Swpaul#endif 129645386Swpaul 129745386Swpaul /* This sets the min dma param all the way up (0xff). */ 129845386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 129945386Swpaul 130045386Swpaul /* Configure DMA variables. */ 130145386Swpaul#if BYTE_ORDER == BIG_ENDIAN 130245386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 130345386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 130445386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 130545386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 130645386Swpaul#else 130745386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 130845386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 130945386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 131045386Swpaul#endif 131145386Swpaul 131245386Swpaul /* 131345386Swpaul * Only allow 1 DMA channel to be active at a time. 131445386Swpaul * I don't think this is a good idea, but without it 131545386Swpaul * the firmware racks up lots of nicDmaReadRingFull 131658698Sjlemon * errors. This is not compatible with hardware checksums. 131745386Swpaul */ 131858698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 131958698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 132045386Swpaul 132145386Swpaul /* Recommended settings from Tigon manual. */ 132245386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 132345386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 132445386Swpaul 132545386Swpaul if (ti_64bitslot_war(sc)) { 132645386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 132745386Swpaul "but we aren't", sc->ti_unit); 132845386Swpaul return(EINVAL); 132945386Swpaul } 133045386Swpaul 133145386Swpaul return(0); 133245386Swpaul} 133345386Swpaul 133445386Swpaul/* 133545386Swpaul * Initialize the general information block and firmware, and 133645386Swpaul * start the CPU(s) running. 133745386Swpaul */ 133845386Swpaulstatic int ti_gibinit(sc) 133945386Swpaul struct ti_softc *sc; 134045386Swpaul{ 134145386Swpaul struct ti_rcb *rcb; 134245386Swpaul int i; 134345386Swpaul struct ifnet *ifp; 134445386Swpaul 134545386Swpaul ifp = &sc->arpcom.ac_if; 134645386Swpaul 134745386Swpaul /* Disable interrupts for now. */ 134845386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 134945386Swpaul 135045386Swpaul /* Tell the chip where to find the general information block. */ 135145386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 135245386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 135345386Swpaul 135445386Swpaul /* Load the firmware into SRAM. */ 135545386Swpaul ti_loadfw(sc); 135645386Swpaul 135745386Swpaul /* Set up the contents of the general info and ring control blocks. */ 135845386Swpaul 135945386Swpaul /* Set up the event ring and producer pointer. */ 136045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 136145386Swpaul 136245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 136345386Swpaul rcb->ti_flags = 0; 136445386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 136545386Swpaul vtophys(&sc->ti_ev_prodidx); 136645386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 136745386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 136845386Swpaul sc->ti_ev_saved_considx = 0; 136945386Swpaul 137045386Swpaul /* Set up the command ring and producer mailbox. */ 137145386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 137245386Swpaul 137345386Swpaul sc->ti_rdata->ti_cmd_ring = 137449133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 137545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 137645386Swpaul rcb->ti_flags = 0; 137745386Swpaul rcb->ti_max_len = 0; 137845386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 137945386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 138045386Swpaul } 138145386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 138245386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 138345386Swpaul sc->ti_cmd_saved_prodidx = 0; 138445386Swpaul 138545386Swpaul /* 138645386Swpaul * Assign the address of the stats refresh buffer. 138745386Swpaul * We re-use the current stats buffer for this to 138845386Swpaul * conserve memory. 138945386Swpaul */ 139045386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 139145386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 139245386Swpaul 139345386Swpaul /* Set up the standard receive ring. */ 139445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 139545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 139645386Swpaul rcb->ti_max_len = TI_FRAMELEN; 139745386Swpaul rcb->ti_flags = 0; 139858698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 139958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 140058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 140145386Swpaul#if NVLAN > 0 140245386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 140345386Swpaul#endif 140445386Swpaul 140545386Swpaul /* Set up the jumbo receive ring. */ 140645386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 140745386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 140845386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 140949036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 141045386Swpaul rcb->ti_flags = 0; 141158698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 141258698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 141358698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 141445386Swpaul#if NVLAN > 0 141545386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 141645386Swpaul#endif 141745386Swpaul 141845386Swpaul /* 141945386Swpaul * Set up the mini ring. Only activated on the 142045386Swpaul * Tigon 2 but the slot in the config block is 142145386Swpaul * still there on the Tigon 1. 142245386Swpaul */ 142345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 142445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 142545386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 142651352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 142745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 142845386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 142945386Swpaul else 143045386Swpaul rcb->ti_flags = 0; 143158698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 143258698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 143358698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 143445386Swpaul#if NVLAN > 0 143545386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 143645386Swpaul#endif 143745386Swpaul 143845386Swpaul /* 143945386Swpaul * Set up the receive return ring. 144045386Swpaul */ 144145386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 144245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 144345386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 144445386Swpaul rcb->ti_flags = 0; 144545386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 144645386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 144745386Swpaul vtophys(&sc->ti_return_prodidx); 144845386Swpaul 144945386Swpaul /* 145045386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 145145386Swpaul * of putting the transmit ring in the host's address space and 145245386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 145345386Swpaul * memory and accessing it through the shared memory region. We 145445386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 145545386Swpaul * so we have to revert to the shared memory scheme if we detect 145645386Swpaul * a Tigon 1 chip. 145745386Swpaul */ 145845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 145945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 146045386Swpaul sc->ti_rdata->ti_tx_ring_nic = 146149133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 146245386Swpaul } 146345386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 146445386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 146545386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 146645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 146745386Swpaul rcb->ti_flags = 0; 146845386Swpaul else 146945386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 147045386Swpaul#if NVLAN > 0 147145386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 147245386Swpaul#endif 147358698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 147458698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 147558698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 147645386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 147745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 147845386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 147945386Swpaul else 148045386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 148145386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 148245386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 148345386Swpaul vtophys(&sc->ti_tx_considx); 148445386Swpaul 148545386Swpaul /* Set up tuneables */ 148645386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 148745386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 148845386Swpaul (sc->ti_rx_coal_ticks / 10)); 148945386Swpaul else 149045386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 149145386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 149245386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 149345386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 149445386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 149545386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 149645386Swpaul 149745386Swpaul /* Turn interrupts on. */ 149845386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 149945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 150045386Swpaul 150145386Swpaul /* Start CPU. */ 150245386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 150345386Swpaul 150445386Swpaul return(0); 150545386Swpaul} 150645386Swpaul 150745386Swpaul/* 150845386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 150945386Swpaul * against our list and return its name if we find a match. 151045386Swpaul */ 151149011Swpaulstatic int ti_probe(dev) 151249011Swpaul device_t dev; 151345386Swpaul{ 151445386Swpaul struct ti_type *t; 151545386Swpaul 151645386Swpaul t = ti_devs; 151745386Swpaul 151845386Swpaul while(t->ti_name != NULL) { 151949011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 152049011Swpaul (pci_get_device(dev) == t->ti_did)) { 152149011Swpaul device_set_desc(dev, t->ti_name); 152249011Swpaul return(0); 152349011Swpaul } 152445386Swpaul t++; 152545386Swpaul } 152645386Swpaul 152749011Swpaul return(ENXIO); 152845386Swpaul} 152945386Swpaul 153049011Swpaulstatic int ti_attach(dev) 153149011Swpaul device_t dev; 153245386Swpaul{ 153345386Swpaul int s; 153445386Swpaul u_int32_t command; 153545386Swpaul struct ifnet *ifp; 153645386Swpaul struct ti_softc *sc; 153749011Swpaul int unit, error = 0, rid; 153845386Swpaul 153945386Swpaul s = splimp(); 154045386Swpaul 154149011Swpaul sc = device_get_softc(dev); 154249011Swpaul unit = device_get_unit(dev); 154345386Swpaul bzero(sc, sizeof(struct ti_softc)); 154445386Swpaul 154545386Swpaul /* 154645386Swpaul * Map control/status registers. 154745386Swpaul */ 154861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 154945386Swpaul command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 155061041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 155161041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 155245386Swpaul 155345386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 155445386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 155549011Swpaul error = ENXIO; 155645386Swpaul goto fail; 155745386Swpaul } 155845386Swpaul 155949011Swpaul rid = TI_PCI_LOMEM; 156049011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 156149011Swpaul 0, ~0, 1, RF_ACTIVE); 156249011Swpaul 156349011Swpaul if (sc->ti_res == NULL) { 156445386Swpaul printf ("ti%d: couldn't map memory\n", unit); 156549011Swpaul error = ENXIO; 156645386Swpaul goto fail; 156745386Swpaul } 156845386Swpaul 156949035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 157049035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 157149133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 157249035Swpaul 157349133Swpaul /* 157449133Swpaul * XXX FIXME: rman_get_virtual() on the alpha is currently 157549133Swpaul * broken and returns a physical address instead of a kernel 157649133Swpaul * virtual address. Consequently, we need to do a little 157749133Swpaul * extra mangling of the vhandle on the alpha. This should 157849133Swpaul * eventually be fixed! The whole idea here is to get rid 157949133Swpaul * of platform dependencies. 158049133Swpaul */ 158149133Swpaul#ifdef __alpha__ 158249133Swpaul if (pci_cvt_to_bwx(sc->ti_vhandle)) 158349133Swpaul sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 158449133Swpaul else 158549133Swpaul sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 158649133Swpaul sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 158749133Swpaul#endif 158849133Swpaul 158949011Swpaul /* Allocate interrupt */ 159049011Swpaul rid = 0; 159149133Swpaul 159249011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 159349011Swpaul RF_SHAREABLE | RF_ACTIVE); 159445386Swpaul 159549011Swpaul if (sc->ti_irq == NULL) { 159649011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 159749011Swpaul error = ENXIO; 159845386Swpaul goto fail; 159945386Swpaul } 160045386Swpaul 160149011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 160249011Swpaul ti_intr, sc, &sc->ti_intrhand); 160349011Swpaul 160449011Swpaul if (error) { 160549011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 160649011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 160749011Swpaul TI_PCI_LOMEM, sc->ti_res); 160849011Swpaul printf("ti%d: couldn't set up irq\n", unit); 160945386Swpaul goto fail; 161045386Swpaul } 161145386Swpaul 161245386Swpaul sc->ti_unit = unit; 161345386Swpaul 161445386Swpaul if (ti_chipinit(sc)) { 161545386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 161649011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 161749011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 161849011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 161949011Swpaul TI_PCI_LOMEM, sc->ti_res); 162049011Swpaul error = ENXIO; 162145386Swpaul goto fail; 162245386Swpaul } 162345386Swpaul 162445386Swpaul /* Zero out the NIC's on-board SRAM. */ 162545386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 162645386Swpaul 162745386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 162845386Swpaul if (ti_chipinit(sc)) { 162945386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 163049011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 163149011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 163249011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 163349011Swpaul TI_PCI_LOMEM, sc->ti_res); 163449011Swpaul error = ENXIO; 163545386Swpaul goto fail; 163645386Swpaul } 163745386Swpaul 163845386Swpaul /* 163945386Swpaul * Get station address from the EEPROM. Note: the manual states 164045386Swpaul * that the MAC address is at offset 0x8c, however the data is 164145386Swpaul * stored as two longwords (since that's how it's loaded into 164245386Swpaul * the NIC). This means the MAC address is actually preceeded 164345386Swpaul * by two zero bytes. We need to skip over those. 164445386Swpaul */ 164545386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 164645386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 164745386Swpaul printf("ti%d: failed to read station address\n", unit); 164849011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 164949011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 165049011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 165149011Swpaul TI_PCI_LOMEM, sc->ti_res); 165249011Swpaul error = ENXIO; 165345386Swpaul goto fail; 165445386Swpaul } 165545386Swpaul 165645386Swpaul /* 165745386Swpaul * A Tigon chip was detected. Inform the world. 165845386Swpaul */ 165945386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 166045386Swpaul sc->arpcom.ac_enaddr, ":"); 166145386Swpaul 166245386Swpaul /* Allocate the general information block and ring buffers. */ 166349011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 166450548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 166545386Swpaul 166649011Swpaul if (sc->ti_rdata == NULL) { 166749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 166849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 166949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 167049011Swpaul TI_PCI_LOMEM, sc->ti_res); 167149011Swpaul error = ENXIO; 167245386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 167345386Swpaul goto fail; 167445386Swpaul } 167545386Swpaul 167645386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 167745386Swpaul 167845386Swpaul /* Try to allocate memory for jumbo buffers. */ 167945386Swpaul if (ti_alloc_jumbo_mem(sc)) { 168045386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 168149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 168249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 168349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 168449011Swpaul TI_PCI_LOMEM, sc->ti_res); 168562793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 168662793Sgallatin M_DEVBUF); 168749011Swpaul error = ENXIO; 168845386Swpaul goto fail; 168945386Swpaul } 169045386Swpaul 169145386Swpaul /* Set default tuneable values. */ 169245386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 169345386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 169445386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 169545386Swpaul sc->ti_rx_max_coal_bds = 64; 169645386Swpaul sc->ti_tx_max_coal_bds = 128; 169745386Swpaul sc->ti_tx_buf_ratio = 21; 169845386Swpaul 169945386Swpaul /* Set up ifnet structure */ 170045386Swpaul ifp = &sc->arpcom.ac_if; 170145386Swpaul ifp->if_softc = sc; 170245386Swpaul ifp->if_unit = sc->ti_unit; 170345386Swpaul ifp->if_name = "ti"; 170445386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 170545386Swpaul ifp->if_ioctl = ti_ioctl; 170645386Swpaul ifp->if_output = ether_output; 170745386Swpaul ifp->if_start = ti_start; 170845386Swpaul ifp->if_watchdog = ti_watchdog; 170945386Swpaul ifp->if_init = ti_init; 171045386Swpaul ifp->if_mtu = ETHERMTU; 171145386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 171245386Swpaul 171345386Swpaul /* Set up ifmedia support. */ 171445386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 171545386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 171645386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 171745386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 171845386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 171945386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 172045386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 172145386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 172245386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 172345386Swpaul 172445386Swpaul /* 172545386Swpaul * Call MI attach routines. 172645386Swpaul */ 172745386Swpaul if_attach(ifp); 172845386Swpaul ether_ifattach(ifp); 172945386Swpaul 173045386Swpaul bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 173145386Swpaul 173245386Swpaulfail: 173345386Swpaul splx(s); 173445386Swpaul 173549011Swpaul return(error); 173645386Swpaul} 173745386Swpaul 173849011Swpaulstatic int ti_detach(dev) 173949011Swpaul device_t dev; 174049011Swpaul{ 174149011Swpaul struct ti_softc *sc; 174249011Swpaul struct ifnet *ifp; 174349011Swpaul int s; 174449011Swpaul 174549011Swpaul s = splimp(); 174649011Swpaul 174749011Swpaul sc = device_get_softc(dev); 174849011Swpaul ifp = &sc->arpcom.ac_if; 174949011Swpaul 175049011Swpaul if_detach(ifp); 175149011Swpaul ti_stop(sc); 175249011Swpaul 175349011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 175449011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 175549011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 175649011Swpaul 175762793Sgallatin contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 175862793Sgallatin contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 175949011Swpaul ifmedia_removeall(&sc->ifmedia); 176049011Swpaul 176149011Swpaul splx(s); 176249011Swpaul 176349011Swpaul return(0); 176449011Swpaul} 176549011Swpaul 176645386Swpaul/* 176745386Swpaul * Frame reception handling. This is called if there's a frame 176845386Swpaul * on the receive return list. 176945386Swpaul * 177045386Swpaul * Note: we have to be able to handle three possibilities here: 177145386Swpaul * 1) the frame is from the mini receive ring (can only happen) 177245386Swpaul * on Tigon 2 boards) 177345386Swpaul * 2) the frame is from the jumbo recieve ring 177445386Swpaul * 3) the frame is from the standard receive ring 177545386Swpaul */ 177645386Swpaul 177745386Swpaulstatic void ti_rxeof(sc) 177845386Swpaul struct ti_softc *sc; 177945386Swpaul{ 178045386Swpaul struct ifnet *ifp; 178148597Swpaul struct ti_cmd_desc cmd; 178245386Swpaul 178345386Swpaul ifp = &sc->arpcom.ac_if; 178445386Swpaul 178545386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 178645386Swpaul struct ti_rx_desc *cur_rx; 178745386Swpaul u_int32_t rxidx; 178845386Swpaul struct ether_header *eh; 178945386Swpaul struct mbuf *m = NULL; 179045386Swpaul#if NVLAN > 0 179145386Swpaul u_int16_t vlan_tag = 0; 179245386Swpaul int have_tag = 0; 179345386Swpaul#endif 179445386Swpaul 179545386Swpaul cur_rx = 179645386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 179745386Swpaul rxidx = cur_rx->ti_idx; 179845386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 179945386Swpaul 180045386Swpaul#if NVLAN > 0 180145386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 180245386Swpaul have_tag = 1; 180345386Swpaul vlan_tag = cur_rx->ti_vlan_tag; 180445386Swpaul } 180545386Swpaul#endif 180645386Swpaul 180745386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 180845386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 180945386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 181045386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 181145386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 181245386Swpaul ifp->if_ierrors++; 181345386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 181445386Swpaul continue; 181545386Swpaul } 181648597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 181748597Swpaul ifp->if_ierrors++; 181848597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 181948597Swpaul continue; 182048597Swpaul } 182145386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 182245386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 182345386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 182445386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 182545386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 182645386Swpaul ifp->if_ierrors++; 182745386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 182845386Swpaul continue; 182945386Swpaul } 183048597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 183148597Swpaul ifp->if_ierrors++; 183248597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 183348597Swpaul continue; 183448597Swpaul } 183545386Swpaul } else { 183645386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 183745386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 183845386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 183945386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 184045386Swpaul ifp->if_ierrors++; 184145386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 184245386Swpaul continue; 184345386Swpaul } 184448597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 184548597Swpaul ifp->if_ierrors++; 184648597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 184748597Swpaul continue; 184848597Swpaul } 184945386Swpaul } 185045386Swpaul 185145386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 185245386Swpaul ifp->if_ipackets++; 185345386Swpaul eh = mtod(m, struct ether_header *); 185445386Swpaul m->m_pkthdr.rcvif = ifp; 185545386Swpaul 185645386Swpaul /* Remove header from mbuf and pass it on. */ 185745386Swpaul m_adj(m, sizeof(struct ether_header)); 185845386Swpaul 185958698Sjlemon if (ifp->if_hwassist) { 186058698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 186158698Sjlemon CSUM_DATA_VALID; 186258698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 186358698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 186458698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 186558698Sjlemon } 186645386Swpaul 186745386Swpaul#if NVLAN > 0 186845386Swpaul /* 186945386Swpaul * If we received a packet with a vlan tag, pass it 187045386Swpaul * to vlan_input() instead of ether_input(). 187145386Swpaul */ 187245386Swpaul if (have_tag) { 187345386Swpaul vlan_input_tag(eh, m, vlan_tag); 187445386Swpaul have_tag = vlan_tag = 0; 187545386Swpaul continue; 187645386Swpaul } 187745386Swpaul#endif 187845386Swpaul ether_input(ifp, eh, m); 187945386Swpaul } 188045386Swpaul 188145386Swpaul /* Only necessary on the Tigon 1. */ 188245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 188345386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 188445386Swpaul sc->ti_rx_saved_considx); 188545386Swpaul 188648597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 188748597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 188848597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 188945386Swpaul 189045386Swpaul return; 189145386Swpaul} 189245386Swpaul 189345386Swpaulstatic void ti_txeof(sc) 189445386Swpaul struct ti_softc *sc; 189545386Swpaul{ 189645386Swpaul struct ti_tx_desc *cur_tx = NULL; 189745386Swpaul struct ifnet *ifp; 189845386Swpaul 189945386Swpaul ifp = &sc->arpcom.ac_if; 190045386Swpaul 190145386Swpaul /* 190245386Swpaul * Go through our tx ring and free mbufs for those 190345386Swpaul * frames that have been sent. 190445386Swpaul */ 190545386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 190645386Swpaul u_int32_t idx = 0; 190745386Swpaul 190845386Swpaul idx = sc->ti_tx_saved_considx; 190945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 191045386Swpaul if (idx > 383) 191145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191245386Swpaul TI_TX_RING_BASE + 6144); 191345386Swpaul else if (idx > 255) 191445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191545386Swpaul TI_TX_RING_BASE + 4096); 191645386Swpaul else if (idx > 127) 191745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191845386Swpaul TI_TX_RING_BASE + 2048); 191945386Swpaul else 192045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 192145386Swpaul TI_TX_RING_BASE); 192245386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 192345386Swpaul } else 192445386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 192545386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 192645386Swpaul ifp->if_opackets++; 192745386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 192845386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 192945386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 193045386Swpaul } 193148011Swpaul sc->ti_txcnt--; 193245386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 193345386Swpaul ifp->if_timer = 0; 193445386Swpaul } 193545386Swpaul 193645386Swpaul if (cur_tx != NULL) 193745386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 193845386Swpaul 193945386Swpaul return; 194045386Swpaul} 194145386Swpaul 194245386Swpaulstatic void ti_intr(xsc) 194345386Swpaul void *xsc; 194445386Swpaul{ 194545386Swpaul struct ti_softc *sc; 194645386Swpaul struct ifnet *ifp; 194745386Swpaul 194845386Swpaul sc = xsc; 194945386Swpaul ifp = &sc->arpcom.ac_if; 195045386Swpaul 195145386Swpaul#ifdef notdef 195245386Swpaul /* Avoid this for now -- checking this register is expensive. */ 195345386Swpaul /* Make sure this is really our interrupt. */ 195445386Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 195545386Swpaul return; 195645386Swpaul#endif 195745386Swpaul 195845386Swpaul /* Ack interrupt and stop others from occuring. */ 195945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 196045386Swpaul 196145386Swpaul if (ifp->if_flags & IFF_RUNNING) { 196245386Swpaul /* Check RX return ring producer/consumer */ 196345386Swpaul ti_rxeof(sc); 196445386Swpaul 196545386Swpaul /* Check TX ring producer/consumer */ 196645386Swpaul ti_txeof(sc); 196745386Swpaul } 196845386Swpaul 196945386Swpaul ti_handle_events(sc); 197045386Swpaul 197145386Swpaul /* Re-enable interrupts. */ 197245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 197345386Swpaul 197445386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 197545386Swpaul ti_start(ifp); 197645386Swpaul 197745386Swpaul return; 197845386Swpaul} 197945386Swpaul 198045386Swpaulstatic void ti_stats_update(sc) 198145386Swpaul struct ti_softc *sc; 198245386Swpaul{ 198345386Swpaul struct ifnet *ifp; 198445386Swpaul 198545386Swpaul ifp = &sc->arpcom.ac_if; 198645386Swpaul 198745386Swpaul ifp->if_collisions += 198845386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 198945386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 199045386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 199145386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 199245386Swpaul ifp->if_collisions; 199345386Swpaul 199445386Swpaul return; 199545386Swpaul} 199645386Swpaul 199745386Swpaul/* 199845386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 199945386Swpaul * pointers to descriptors. 200045386Swpaul */ 200145386Swpaulstatic int ti_encap(sc, m_head, txidx) 200245386Swpaul struct ti_softc *sc; 200345386Swpaul struct mbuf *m_head; 200445386Swpaul u_int32_t *txidx; 200545386Swpaul{ 200645386Swpaul struct ti_tx_desc *f = NULL; 200745386Swpaul struct mbuf *m; 200848011Swpaul u_int32_t frag, cur, cnt = 0; 200958698Sjlemon u_int16_t csum_flags = 0; 201045386Swpaul#if NVLAN > 0 201145386Swpaul struct ifvlan *ifv = NULL; 201245386Swpaul 201345386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 201445386Swpaul m_head->m_pkthdr.rcvif != NULL && 201545386Swpaul m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 201645386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 201745386Swpaul#endif 201845386Swpaul 201945386Swpaul m = m_head; 202045386Swpaul cur = frag = *txidx; 202145386Swpaul 202258698Sjlemon if (m_head->m_pkthdr.csum_flags) { 202358698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 202458698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 202558698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 202658698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 202758698Sjlemon if (m_head->m_flags & M_LASTFRAG) 202858698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 202958698Sjlemon else if (m_head->m_flags & M_FRAG) 203058698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 203158698Sjlemon } 203245386Swpaul /* 203345386Swpaul * Start packing the mbufs in this chain into 203445386Swpaul * the fragment pointers. Stop when we run out 203545386Swpaul * of fragments or hit the end of the mbuf chain. 203645386Swpaul */ 203745386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 203845386Swpaul if (m->m_len != 0) { 203945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 204045386Swpaul if (frag > 383) 204145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204245386Swpaul TI_TX_RING_BASE + 6144); 204345386Swpaul else if (frag > 255) 204445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204545386Swpaul TI_TX_RING_BASE + 4096); 204645386Swpaul else if (frag > 127) 204745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204845386Swpaul TI_TX_RING_BASE + 2048); 204945386Swpaul else 205045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 205145386Swpaul TI_TX_RING_BASE); 205245386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 205345386Swpaul } else 205445386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 205545386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 205645386Swpaul break; 205745386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 205845386Swpaul f->ti_len = m->m_len; 205958698Sjlemon f->ti_flags = csum_flags; 206045386Swpaul#if NVLAN > 0 206145386Swpaul if (ifv != NULL) { 206245386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 206345386Swpaul f->ti_vlan_tag = ifv->ifv_tag; 206445386Swpaul } else { 206545386Swpaul f->ti_vlan_tag = 0; 206645386Swpaul } 206745386Swpaul#endif 206848011Swpaul /* 206948011Swpaul * Sanity check: avoid coming within 16 descriptors 207048011Swpaul * of the end of the ring. 207148011Swpaul */ 207248011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 207348011Swpaul return(ENOBUFS); 207445386Swpaul cur = frag; 207545386Swpaul TI_INC(frag, TI_TX_RING_CNT); 207648011Swpaul cnt++; 207745386Swpaul } 207845386Swpaul } 207945386Swpaul 208045386Swpaul if (m != NULL) 208145386Swpaul return(ENOBUFS); 208245386Swpaul 208346177Swpaul if (frag == sc->ti_tx_saved_considx) 208446177Swpaul return(ENOBUFS); 208546177Swpaul 208645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 208745386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 208845386Swpaul TI_BDFLAG_END; 208945386Swpaul else 209045386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 209147458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 209248011Swpaul sc->ti_txcnt += cnt; 209345386Swpaul 209445386Swpaul *txidx = frag; 209545386Swpaul 209645386Swpaul return(0); 209745386Swpaul} 209845386Swpaul 209945386Swpaul/* 210045386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 210145386Swpaul * to the mbuf data regions directly in the transmit descriptors. 210245386Swpaul */ 210345386Swpaulstatic void ti_start(ifp) 210445386Swpaul struct ifnet *ifp; 210545386Swpaul{ 210645386Swpaul struct ti_softc *sc; 210745386Swpaul struct mbuf *m_head = NULL; 210845386Swpaul u_int32_t prodidx = 0; 210945386Swpaul 211045386Swpaul sc = ifp->if_softc; 211145386Swpaul 211245386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 211345386Swpaul 211445386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 211545386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 211645386Swpaul if (m_head == NULL) 211745386Swpaul break; 211845386Swpaul 211945386Swpaul /* 212058698Sjlemon * XXX 212158698Sjlemon * safety overkill. If this is a fragmented packet chain 212258698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 212358698Sjlemon * it if we have enough descriptors to handle the entire 212458698Sjlemon * chain at once. 212558698Sjlemon * (paranoia -- may not actually be needed) 212658698Sjlemon */ 212758698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 212858698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 212958698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 213058698Sjlemon m_head->m_pkthdr.csum_data + 16) { 213158698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 213258698Sjlemon ifp->if_flags |= IFF_OACTIVE; 213358698Sjlemon break; 213458698Sjlemon } 213558698Sjlemon } 213658698Sjlemon 213758698Sjlemon /* 213845386Swpaul * Pack the data into the transmit ring. If we 213945386Swpaul * don't have room, set the OACTIVE flag and wait 214045386Swpaul * for the NIC to drain the ring. 214145386Swpaul */ 214245386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 214345386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 214445386Swpaul ifp->if_flags |= IFF_OACTIVE; 214545386Swpaul break; 214645386Swpaul } 214745386Swpaul 214845386Swpaul /* 214945386Swpaul * If there's a BPF listener, bounce a copy of this frame 215045386Swpaul * to him. 215145386Swpaul */ 215245386Swpaul if (ifp->if_bpf) 215345386Swpaul bpf_mtap(ifp, m_head); 215445386Swpaul } 215545386Swpaul 215645386Swpaul /* Transmit */ 215745386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 215845386Swpaul 215945386Swpaul /* 216045386Swpaul * Set a timeout in case the chip goes out to lunch. 216145386Swpaul */ 216245386Swpaul ifp->if_timer = 5; 216345386Swpaul 216445386Swpaul return; 216545386Swpaul} 216645386Swpaul 216745386Swpaulstatic void ti_init(xsc) 216845386Swpaul void *xsc; 216945386Swpaul{ 217045386Swpaul struct ti_softc *sc = xsc; 217145386Swpaul int s; 217245386Swpaul 217345386Swpaul s = splimp(); 217445386Swpaul 217545386Swpaul /* Cancel pending I/O and flush buffers. */ 217645386Swpaul ti_stop(sc); 217745386Swpaul 217845386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 217945386Swpaul if (ti_gibinit(sc)) { 218045386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 218145386Swpaul splx(s); 218245386Swpaul return; 218345386Swpaul } 218445386Swpaul 218545386Swpaul splx(s); 218645386Swpaul 218745386Swpaul return; 218845386Swpaul} 218945386Swpaul 219045386Swpaulstatic void ti_init2(sc) 219145386Swpaul struct ti_softc *sc; 219245386Swpaul{ 219345386Swpaul struct ti_cmd_desc cmd; 219445386Swpaul struct ifnet *ifp; 219545386Swpaul u_int16_t *m; 219645386Swpaul struct ifmedia *ifm; 219745386Swpaul int tmp; 219845386Swpaul 219945386Swpaul ifp = &sc->arpcom.ac_if; 220045386Swpaul 220145386Swpaul /* Specify MTU and interface index. */ 220245386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 220345386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 220445386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 220545386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 220645386Swpaul 220745386Swpaul /* Load our MAC address. */ 220845386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 220945386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 221045386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 221145386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 221245386Swpaul 221345386Swpaul /* Enable or disable promiscuous mode as needed. */ 221445386Swpaul if (ifp->if_flags & IFF_PROMISC) { 221545386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 221645386Swpaul } else { 221745386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 221845386Swpaul } 221945386Swpaul 222045386Swpaul /* Program multicast filter. */ 222145386Swpaul ti_setmulti(sc); 222245386Swpaul 222345386Swpaul /* 222445386Swpaul * If this is a Tigon 1, we should tell the 222545386Swpaul * firmware to use software packet filtering. 222645386Swpaul */ 222745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 222845386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 222945386Swpaul } 223045386Swpaul 223145386Swpaul /* Init RX ring. */ 223245386Swpaul ti_init_rx_ring_std(sc); 223345386Swpaul 223445386Swpaul /* Init jumbo RX ring. */ 223545386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 223645386Swpaul ti_init_rx_ring_jumbo(sc); 223745386Swpaul 223845386Swpaul /* 223945386Swpaul * If this is a Tigon 2, we can also configure the 224045386Swpaul * mini ring. 224145386Swpaul */ 224245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 224345386Swpaul ti_init_rx_ring_mini(sc); 224445386Swpaul 224545386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 224645386Swpaul sc->ti_rx_saved_considx = 0; 224745386Swpaul 224845386Swpaul /* Init TX ring. */ 224945386Swpaul ti_init_tx_ring(sc); 225045386Swpaul 225145386Swpaul /* Tell firmware we're alive. */ 225245386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 225345386Swpaul 225445386Swpaul /* Enable host interrupts. */ 225545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 225645386Swpaul 225745386Swpaul ifp->if_flags |= IFF_RUNNING; 225845386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 225945386Swpaul 226045386Swpaul /* 226145386Swpaul * Make sure to set media properly. We have to do this 226245386Swpaul * here since we have to issue commands in order to set 226345386Swpaul * the link negotiation and we can't issue commands until 226445386Swpaul * the firmware is running. 226545386Swpaul */ 226645386Swpaul ifm = &sc->ifmedia; 226745386Swpaul tmp = ifm->ifm_media; 226845386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 226945386Swpaul ti_ifmedia_upd(ifp); 227045386Swpaul ifm->ifm_media = tmp; 227145386Swpaul 227245386Swpaul return; 227345386Swpaul} 227445386Swpaul 227545386Swpaul/* 227645386Swpaul * Set media options. 227745386Swpaul */ 227845386Swpaulstatic int ti_ifmedia_upd(ifp) 227945386Swpaul struct ifnet *ifp; 228045386Swpaul{ 228145386Swpaul struct ti_softc *sc; 228245386Swpaul struct ifmedia *ifm; 228345386Swpaul struct ti_cmd_desc cmd; 228445386Swpaul 228545386Swpaul sc = ifp->if_softc; 228645386Swpaul ifm = &sc->ifmedia; 228745386Swpaul 228845386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 228945386Swpaul return(EINVAL); 229045386Swpaul 229145386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 229245386Swpaul case IFM_AUTO: 229345386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 229445386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 229545386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 229645386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 229745386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 229845386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 229945386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 230045386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 230145386Swpaul break; 230245386Swpaul case IFM_1000_SX: 230345386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 230445386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 230545386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 230645386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 230745386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 230845386Swpaul break; 230945386Swpaul case IFM_100_FX: 231045386Swpaul case IFM_10_FL: 231145386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 231245386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 231345386Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 231445386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 231545386Swpaul } else { 231645386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 231745386Swpaul } 231845386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 231945386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 232045386Swpaul } else { 232145386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 232245386Swpaul } 232345386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 232445386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 232545386Swpaul break; 232645386Swpaul } 232745386Swpaul 232845386Swpaul return(0); 232945386Swpaul} 233045386Swpaul 233145386Swpaul/* 233245386Swpaul * Report current media status. 233345386Swpaul */ 233445386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 233545386Swpaul struct ifnet *ifp; 233645386Swpaul struct ifmediareq *ifmr; 233745386Swpaul{ 233845386Swpaul struct ti_softc *sc; 233945386Swpaul 234045386Swpaul sc = ifp->if_softc; 234145386Swpaul 234245386Swpaul ifmr->ifm_status = IFM_AVALID; 234345386Swpaul ifmr->ifm_active = IFM_ETHER; 234445386Swpaul 234545386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 234645386Swpaul return; 234745386Swpaul 234845386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 234945386Swpaul 235045386Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 235145386Swpaul ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 235245386Swpaul else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 235345386Swpaul u_int32_t media; 235445386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 235545386Swpaul if (media & TI_LNK_100MB) 235645386Swpaul ifmr->ifm_active |= IFM_100_FX; 235745386Swpaul if (media & TI_LNK_10MB) 235845386Swpaul ifmr->ifm_active |= IFM_10_FL; 235945386Swpaul if (media & TI_LNK_FULL_DUPLEX) 236045386Swpaul ifmr->ifm_active |= IFM_FDX; 236145386Swpaul if (media & TI_LNK_HALF_DUPLEX) 236245386Swpaul ifmr->ifm_active |= IFM_HDX; 236345386Swpaul } 236445386Swpaul 236545386Swpaul return; 236645386Swpaul} 236745386Swpaul 236845386Swpaulstatic int ti_ioctl(ifp, command, data) 236945386Swpaul struct ifnet *ifp; 237045386Swpaul u_long command; 237145386Swpaul caddr_t data; 237245386Swpaul{ 237345386Swpaul struct ti_softc *sc = ifp->if_softc; 237445386Swpaul struct ifreq *ifr = (struct ifreq *) data; 237545386Swpaul int s, error = 0; 237645386Swpaul struct ti_cmd_desc cmd; 237745386Swpaul 237845386Swpaul s = splimp(); 237945386Swpaul 238045386Swpaul switch(command) { 238145386Swpaul case SIOCSIFADDR: 238245386Swpaul case SIOCGIFADDR: 238345386Swpaul error = ether_ioctl(ifp, command, data); 238445386Swpaul break; 238545386Swpaul case SIOCSIFMTU: 238645386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 238745386Swpaul error = EINVAL; 238845386Swpaul else { 238945386Swpaul ifp->if_mtu = ifr->ifr_mtu; 239045386Swpaul ti_init(sc); 239145386Swpaul } 239245386Swpaul break; 239345386Swpaul case SIOCSIFFLAGS: 239445386Swpaul if (ifp->if_flags & IFF_UP) { 239545386Swpaul /* 239645386Swpaul * If only the state of the PROMISC flag changed, 239745386Swpaul * then just use the 'set promisc mode' command 239845386Swpaul * instead of reinitializing the entire NIC. Doing 239945386Swpaul * a full re-init means reloading the firmware and 240045386Swpaul * waiting for it to start up, which may take a 240145386Swpaul * second or two. 240245386Swpaul */ 240345386Swpaul if (ifp->if_flags & IFF_RUNNING && 240445386Swpaul ifp->if_flags & IFF_PROMISC && 240545386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 240645386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 240745386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 240845386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 240945386Swpaul !(ifp->if_flags & IFF_PROMISC) && 241045386Swpaul sc->ti_if_flags & IFF_PROMISC) { 241145386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 241245386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 241345386Swpaul } else 241445386Swpaul ti_init(sc); 241545386Swpaul } else { 241645386Swpaul if (ifp->if_flags & IFF_RUNNING) { 241745386Swpaul ti_stop(sc); 241845386Swpaul } 241945386Swpaul } 242045386Swpaul sc->ti_if_flags = ifp->if_flags; 242145386Swpaul error = 0; 242245386Swpaul break; 242345386Swpaul case SIOCADDMULTI: 242445386Swpaul case SIOCDELMULTI: 242545386Swpaul if (ifp->if_flags & IFF_RUNNING) { 242645386Swpaul ti_setmulti(sc); 242745386Swpaul error = 0; 242845386Swpaul } 242945386Swpaul break; 243045386Swpaul case SIOCSIFMEDIA: 243145386Swpaul case SIOCGIFMEDIA: 243245386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 243345386Swpaul break; 243445386Swpaul default: 243545386Swpaul error = EINVAL; 243645386Swpaul break; 243745386Swpaul } 243845386Swpaul 243945386Swpaul (void)splx(s); 244045386Swpaul 244145386Swpaul return(error); 244245386Swpaul} 244345386Swpaul 244445386Swpaulstatic void ti_watchdog(ifp) 244545386Swpaul struct ifnet *ifp; 244645386Swpaul{ 244745386Swpaul struct ti_softc *sc; 244845386Swpaul 244945386Swpaul sc = ifp->if_softc; 245045386Swpaul 245145386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 245245386Swpaul ti_stop(sc); 245345386Swpaul ti_init(sc); 245445386Swpaul 245545386Swpaul ifp->if_oerrors++; 245645386Swpaul 245745386Swpaul return; 245845386Swpaul} 245945386Swpaul 246045386Swpaul/* 246145386Swpaul * Stop the adapter and free any mbufs allocated to the 246245386Swpaul * RX and TX lists. 246345386Swpaul */ 246445386Swpaulstatic void ti_stop(sc) 246545386Swpaul struct ti_softc *sc; 246645386Swpaul{ 246745386Swpaul struct ifnet *ifp; 246845386Swpaul struct ti_cmd_desc cmd; 246945386Swpaul 247045386Swpaul ifp = &sc->arpcom.ac_if; 247145386Swpaul 247245386Swpaul /* Disable host interrupts. */ 247345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 247445386Swpaul /* 247545386Swpaul * Tell firmware we're shutting down. 247645386Swpaul */ 247745386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 247845386Swpaul 247945386Swpaul /* Halt and reinitialize. */ 248045386Swpaul ti_chipinit(sc); 248145386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 248245386Swpaul ti_chipinit(sc); 248345386Swpaul 248445386Swpaul /* Free the RX lists. */ 248545386Swpaul ti_free_rx_ring_std(sc); 248645386Swpaul 248745386Swpaul /* Free jumbo RX list. */ 248845386Swpaul ti_free_rx_ring_jumbo(sc); 248945386Swpaul 249045386Swpaul /* Free mini RX list. */ 249145386Swpaul ti_free_rx_ring_mini(sc); 249245386Swpaul 249345386Swpaul /* Free TX buffers. */ 249445386Swpaul ti_free_tx_ring(sc); 249545386Swpaul 249645386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 249745386Swpaul sc->ti_return_prodidx.ti_idx = 0; 249845386Swpaul sc->ti_tx_considx.ti_idx = 0; 249945386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 250045386Swpaul 250145386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 250245386Swpaul 250345386Swpaul return; 250445386Swpaul} 250545386Swpaul 250645386Swpaul/* 250745386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 250845386Swpaul * get confused by errant DMAs when rebooting. 250945386Swpaul */ 251049011Swpaulstatic void ti_shutdown(dev) 251149011Swpaul device_t dev; 251245386Swpaul{ 251345386Swpaul struct ti_softc *sc; 251445386Swpaul 251549011Swpaul sc = device_get_softc(dev); 251645386Swpaul 251745386Swpaul ti_chipinit(sc); 251845386Swpaul 251945386Swpaul return; 252045386Swpaul} 2521