if_ti.c revision 61041
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ti/if_ti.c 61041 2000-05-28 16:13:43Z peter $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include "vlan.h" 8245386Swpaul 8345386Swpaul#include <sys/param.h> 8445386Swpaul#include <sys/systm.h> 8545386Swpaul#include <sys/sockio.h> 8645386Swpaul#include <sys/mbuf.h> 8745386Swpaul#include <sys/malloc.h> 8845386Swpaul#include <sys/kernel.h> 8945386Swpaul#include <sys/socket.h> 9045386Swpaul#include <sys/queue.h> 9145386Swpaul 9245386Swpaul#include <net/if.h> 9345386Swpaul#include <net/if_arp.h> 9445386Swpaul#include <net/ethernet.h> 9545386Swpaul#include <net/if_dl.h> 9645386Swpaul#include <net/if_media.h> 9745386Swpaul 9845386Swpaul#include <net/bpf.h> 9945386Swpaul 10045386Swpaul#if NVLAN > 0 10145386Swpaul#include <net/if_types.h> 10245386Swpaul#include <net/if_vlan_var.h> 10345386Swpaul#endif 10445386Swpaul 10545386Swpaul#include <netinet/in_systm.h> 10645386Swpaul#include <netinet/in.h> 10745386Swpaul#include <netinet/ip.h> 10845386Swpaul 10945386Swpaul#include <vm/vm.h> /* for vtophys */ 11045386Swpaul#include <vm/pmap.h> /* for vtophys */ 11145386Swpaul#include <machine/clock.h> /* for DELAY */ 11245386Swpaul#include <machine/bus_memio.h> 11345386Swpaul#include <machine/bus.h> 11449011Swpaul#include <machine/resource.h> 11549011Swpaul#include <sys/bus.h> 11649011Swpaul#include <sys/rman.h> 11745386Swpaul 11845386Swpaul#include <pci/pcireg.h> 11945386Swpaul#include <pci/pcivar.h> 12045386Swpaul 12145386Swpaul#include <pci/if_tireg.h> 12245386Swpaul#include <pci/ti_fw.h> 12345386Swpaul#include <pci/ti_fw2.h> 12445386Swpaul 12558698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 12645386Swpaul 12745386Swpaul#if !defined(lint) 12845386Swpaulstatic const char rcsid[] = 12950477Speter "$FreeBSD: head/sys/dev/ti/if_ti.c 61041 2000-05-28 16:13:43Z peter $"; 13045386Swpaul#endif 13145386Swpaul 13245386Swpaul/* 13345386Swpaul * Various supported device vendors/types and their names. 13445386Swpaul */ 13545386Swpaul 13645386Swpaulstatic struct ti_type ti_devs[] = { 13745386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 13845386Swpaul "Alteon AceNIC Gigabit Ethernet" }, 13945386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 14045386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 14145386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 14245386Swpaul "Netgear GA620 Gigabit Ethernet" }, 14345386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14445386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14556206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 14656206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 14745386Swpaul { 0, 0, NULL } 14845386Swpaul}; 14945386Swpaul 15049011Swpaulstatic int ti_probe __P((device_t)); 15149011Swpaulstatic int ti_attach __P((device_t)); 15249011Swpaulstatic int ti_detach __P((device_t)); 15345386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15445386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15545386Swpaul 15645386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 15745386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 15845386Swpaul u_int32_t *)); 15945386Swpaul 16045386Swpaulstatic void ti_intr __P((void *)); 16145386Swpaulstatic void ti_start __P((struct ifnet *)); 16245386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16345386Swpaulstatic void ti_init __P((void *)); 16445386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16545386Swpaulstatic void ti_stop __P((struct ti_softc *)); 16645386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 16749011Swpaulstatic void ti_shutdown __P((device_t)); 16845386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 16945386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17045386Swpaul 17145386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17245386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17345386Swpaul int, u_int8_t *)); 17445386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17545386Swpaul 17645386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 17745386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 17845386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 17945386Swpaul 18045386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18145386Swpaul u_int32_t, caddr_t)); 18245386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18345386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18445386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18545386Swpaul caddr_t, int)); 18645386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 18745386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 18845386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 18945386Swpaulstatic void ti_jfree __P((caddr_t, u_int)); 19045386Swpaulstatic void ti_jref __P((caddr_t, u_int)); 19145386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19245386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19345386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19445386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19545386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19645386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 19745386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 19845386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 19945386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20045386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 20145386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 20245386Swpaul 20345386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20445386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20545386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 20645386Swpaul 20749011Swpaulstatic device_method_t ti_methods[] = { 20849011Swpaul /* Device interface */ 20949011Swpaul DEVMETHOD(device_probe, ti_probe), 21049011Swpaul DEVMETHOD(device_attach, ti_attach), 21149011Swpaul DEVMETHOD(device_detach, ti_detach), 21249011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 21349011Swpaul { 0, 0 } 21449011Swpaul}; 21549011Swpaul 21649011Swpaulstatic driver_t ti_driver = { 21751455Swpaul "ti", 21849011Swpaul ti_methods, 21949011Swpaul sizeof(struct ti_softc) 22049011Swpaul}; 22149011Swpaul 22249011Swpaulstatic devclass_t ti_devclass; 22349011Swpaul 22451533SwpaulDRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 22549011Swpaul 22645386Swpaul/* 22745386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 22845386Swpaul */ 22945386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 23045386Swpaul struct ti_softc *sc; 23145386Swpaul int byte; 23245386Swpaul{ 23345386Swpaul register int i, ack = 0; 23445386Swpaul 23545386Swpaul /* 23645386Swpaul * Make sure we're in TX mode. 23745386Swpaul */ 23845386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 23945386Swpaul 24045386Swpaul /* 24145386Swpaul * Feed in each bit and stobe the clock. 24245386Swpaul */ 24345386Swpaul for (i = 0x80; i; i >>= 1) { 24445386Swpaul if (byte & i) { 24545386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24645386Swpaul } else { 24745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 24845386Swpaul } 24945386Swpaul DELAY(1); 25045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25145386Swpaul DELAY(1); 25245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 25345386Swpaul } 25445386Swpaul 25545386Swpaul /* 25645386Swpaul * Turn off TX mode. 25745386Swpaul */ 25845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 25945386Swpaul 26045386Swpaul /* 26145386Swpaul * Check for ack. 26245386Swpaul */ 26345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26445386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 26545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 26645386Swpaul 26745386Swpaul return(ack); 26845386Swpaul} 26945386Swpaul 27045386Swpaul/* 27145386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 27245386Swpaul * We have to send two address bytes since the EEPROM can hold 27345386Swpaul * more than 256 bytes of data. 27445386Swpaul */ 27545386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 27645386Swpaul struct ti_softc *sc; 27745386Swpaul int addr; 27845386Swpaul u_int8_t *dest; 27945386Swpaul{ 28045386Swpaul register int i; 28145386Swpaul u_int8_t byte = 0; 28245386Swpaul 28345386Swpaul EEPROM_START; 28445386Swpaul 28545386Swpaul /* 28645386Swpaul * Send write control code to EEPROM. 28745386Swpaul */ 28845386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 28945386Swpaul printf("ti%d: failed to send write command, status: %x\n", 29045386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29145386Swpaul return(1); 29245386Swpaul } 29345386Swpaul 29445386Swpaul /* 29545386Swpaul * Send first byte of address of byte we want to read. 29645386Swpaul */ 29745386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 29845386Swpaul printf("ti%d: failed to send address, status: %x\n", 29945386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30045386Swpaul return(1); 30145386Swpaul } 30245386Swpaul /* 30345386Swpaul * Send second byte address of byte we want to read. 30445386Swpaul */ 30545386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 30645386Swpaul printf("ti%d: failed to send address, status: %x\n", 30745386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30845386Swpaul return(1); 30945386Swpaul } 31045386Swpaul 31145386Swpaul EEPROM_STOP; 31245386Swpaul EEPROM_START; 31345386Swpaul /* 31445386Swpaul * Send read control code to EEPROM. 31545386Swpaul */ 31645386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 31745386Swpaul printf("ti%d: failed to send read command, status: %x\n", 31845386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 31945386Swpaul return(1); 32045386Swpaul } 32145386Swpaul 32245386Swpaul /* 32345386Swpaul * Start reading bits from EEPROM. 32445386Swpaul */ 32545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 32645386Swpaul for (i = 0x80; i; i >>= 1) { 32745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 32845386Swpaul DELAY(1); 32945386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 33045386Swpaul byte |= i; 33145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 33245386Swpaul DELAY(1); 33345386Swpaul } 33445386Swpaul 33545386Swpaul EEPROM_STOP; 33645386Swpaul 33745386Swpaul /* 33845386Swpaul * No ACK generated for read, so just return byte. 33945386Swpaul */ 34045386Swpaul 34145386Swpaul *dest = byte; 34245386Swpaul 34345386Swpaul return(0); 34445386Swpaul} 34545386Swpaul 34645386Swpaul/* 34745386Swpaul * Read a sequence of bytes from the EEPROM. 34845386Swpaul */ 34945386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 35045386Swpaul struct ti_softc *sc; 35145386Swpaul caddr_t dest; 35245386Swpaul int off; 35345386Swpaul int cnt; 35445386Swpaul{ 35545386Swpaul int err = 0, i; 35645386Swpaul u_int8_t byte = 0; 35745386Swpaul 35845386Swpaul for (i = 0; i < cnt; i++) { 35945386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 36045386Swpaul if (err) 36145386Swpaul break; 36245386Swpaul *(dest + i) = byte; 36345386Swpaul } 36445386Swpaul 36545386Swpaul return(err ? 1 : 0); 36645386Swpaul} 36745386Swpaul 36845386Swpaul/* 36945386Swpaul * NIC memory access function. Can be used to either clear a section 37045386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 37145386Swpaul */ 37245386Swpaulstatic void ti_mem(sc, addr, len, buf) 37345386Swpaul struct ti_softc *sc; 37445386Swpaul u_int32_t addr, len; 37545386Swpaul caddr_t buf; 37645386Swpaul{ 37745386Swpaul int segptr, segsize, cnt; 37845386Swpaul caddr_t ti_winbase, ptr; 37945386Swpaul 38045386Swpaul segptr = addr; 38145386Swpaul cnt = len; 38249133Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 38345386Swpaul ptr = buf; 38445386Swpaul 38545386Swpaul while(cnt) { 38645386Swpaul if (cnt < TI_WINLEN) 38745386Swpaul segsize = cnt; 38845386Swpaul else 38945386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 39045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 39145386Swpaul if (buf == NULL) 39245386Swpaul bzero((char *)ti_winbase + (segptr & 39345386Swpaul (TI_WINLEN - 1)), segsize); 39445386Swpaul else { 39545386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 39645386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 39745386Swpaul ptr += segsize; 39845386Swpaul } 39945386Swpaul segptr += segsize; 40045386Swpaul cnt -= segsize; 40145386Swpaul } 40245386Swpaul 40345386Swpaul return; 40445386Swpaul} 40545386Swpaul 40645386Swpaul/* 40745386Swpaul * Load firmware image into the NIC. Check that the firmware revision 40845386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 40945386Swpaul * Tigon 2. 41045386Swpaul */ 41145386Swpaulstatic void ti_loadfw(sc) 41245386Swpaul struct ti_softc *sc; 41345386Swpaul{ 41445386Swpaul switch(sc->ti_hwrev) { 41545386Swpaul case TI_HWREV_TIGON: 41645386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 41745386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 41845386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 41945386Swpaul printf("ti%d: firmware revision mismatch; want " 42045386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 42145386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 42245386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 42345386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 42445386Swpaul return; 42545386Swpaul } 42645386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 42745386Swpaul (caddr_t)tigonFwText); 42845386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 42945386Swpaul (caddr_t)tigonFwData); 43045386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 43145386Swpaul (caddr_t)tigonFwRodata); 43245386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 43345386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 43445386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 43545386Swpaul break; 43645386Swpaul case TI_HWREV_TIGON_II: 43745386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 43845386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 43945386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 44045386Swpaul printf("ti%d: firmware revision mismatch; want " 44145386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 44245386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 44345386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 44445386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 44545386Swpaul return; 44645386Swpaul } 44745386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 44845386Swpaul (caddr_t)tigon2FwText); 44945386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 45045386Swpaul (caddr_t)tigon2FwData); 45145386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 45245386Swpaul (caddr_t)tigon2FwRodata); 45345386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 45445386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 45545386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 45645386Swpaul break; 45745386Swpaul default: 45845386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 45945386Swpaul sc->ti_unit); 46045386Swpaul break; 46145386Swpaul } 46245386Swpaul 46345386Swpaul return; 46445386Swpaul} 46545386Swpaul 46645386Swpaul/* 46745386Swpaul * Send the NIC a command via the command ring. 46845386Swpaul */ 46945386Swpaulstatic void ti_cmd(sc, cmd) 47045386Swpaul struct ti_softc *sc; 47145386Swpaul struct ti_cmd_desc *cmd; 47245386Swpaul{ 47345386Swpaul u_int32_t index; 47445386Swpaul 47545386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 47645386Swpaul return; 47745386Swpaul 47845386Swpaul index = sc->ti_cmd_saved_prodidx; 47945386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 48045386Swpaul TI_INC(index, TI_CMD_RING_CNT); 48145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 48245386Swpaul sc->ti_cmd_saved_prodidx = index; 48345386Swpaul 48445386Swpaul return; 48545386Swpaul} 48645386Swpaul 48745386Swpaul/* 48845386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 48945386Swpaul * number of command slots to include after the initial command. 49045386Swpaul */ 49145386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 49245386Swpaul struct ti_softc *sc; 49345386Swpaul struct ti_cmd_desc *cmd; 49445386Swpaul caddr_t arg; 49545386Swpaul int len; 49645386Swpaul{ 49745386Swpaul u_int32_t index; 49845386Swpaul register int i; 49945386Swpaul 50045386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 50145386Swpaul return; 50245386Swpaul 50345386Swpaul index = sc->ti_cmd_saved_prodidx; 50445386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 50545386Swpaul TI_INC(index, TI_CMD_RING_CNT); 50645386Swpaul for (i = 0; i < len; i++) { 50745386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 50845386Swpaul *(u_int32_t *)(&arg[i * 4])); 50945386Swpaul TI_INC(index, TI_CMD_RING_CNT); 51045386Swpaul } 51145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 51245386Swpaul sc->ti_cmd_saved_prodidx = index; 51345386Swpaul 51445386Swpaul return; 51545386Swpaul} 51645386Swpaul 51745386Swpaul/* 51845386Swpaul * Handle events that have triggered interrupts. 51945386Swpaul */ 52045386Swpaulstatic void ti_handle_events(sc) 52145386Swpaul struct ti_softc *sc; 52245386Swpaul{ 52345386Swpaul struct ti_event_desc *e; 52445386Swpaul 52545386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 52645386Swpaul return; 52745386Swpaul 52845386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 52945386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 53045386Swpaul switch(e->ti_event) { 53145386Swpaul case TI_EV_LINKSTAT_CHANGED: 53245386Swpaul sc->ti_linkstat = e->ti_code; 53345386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 53445386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 53545386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 53645386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 53745386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 53845386Swpaul printf("ti%d: link down\n", sc->ti_unit); 53945386Swpaul break; 54045386Swpaul case TI_EV_ERROR: 54145386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 54245386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 54345386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 54445386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 54545386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 54645386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 54745386Swpaul break; 54845386Swpaul case TI_EV_FIRMWARE_UP: 54945386Swpaul ti_init2(sc); 55045386Swpaul break; 55145386Swpaul case TI_EV_STATS_UPDATED: 55245386Swpaul ti_stats_update(sc); 55345386Swpaul break; 55445386Swpaul case TI_EV_RESET_JUMBO_RING: 55545386Swpaul case TI_EV_MCAST_UPDATED: 55645386Swpaul /* Who cares. */ 55745386Swpaul break; 55845386Swpaul default: 55945386Swpaul printf("ti%d: unknown event: %d\n", 56045386Swpaul sc->ti_unit, e->ti_event); 56145386Swpaul break; 56245386Swpaul } 56345386Swpaul /* Advance the consumer index. */ 56445386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 56545386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 56645386Swpaul } 56745386Swpaul 56845386Swpaul return; 56945386Swpaul} 57045386Swpaul 57145386Swpaul/* 57245386Swpaul * Memory management for the jumbo receive ring is a pain in the 57345386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 57445386Swpaul * _and_ it has to be contiguous (unless you use the extended 57545386Swpaul * jumbo descriptor format). Using malloc() all the time won't 57645386Swpaul * work: malloc() allocates memory in powers of two, which means we 57745386Swpaul * would end up wasting a considerable amount of space by allocating 57845386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 57945386Swpaul * to do our own memory management. 58045386Swpaul * 58145386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 58245386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 58345386Swpaul * as external mbuf storage. 58445386Swpaul * 58545386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 58645386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 58745386Swpaul * RAM. This is a bit much, especially considering we also need 58845386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 58945386Swpaul * save space, we only actually allocate enough memory for 64 slots 59045386Swpaul * by default, which works out to between 500 and 600K. This can 59145386Swpaul * be tuned by changing a #define in if_tireg.h. 59245386Swpaul */ 59345386Swpaul 59445386Swpaulstatic int ti_alloc_jumbo_mem(sc) 59545386Swpaul struct ti_softc *sc; 59645386Swpaul{ 59745386Swpaul caddr_t ptr; 59845386Swpaul register int i; 59945386Swpaul struct ti_jpool_entry *entry; 60045386Swpaul 60145386Swpaul /* Grab a big chunk o' storage. */ 60245386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 60350548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 60445386Swpaul 60545386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 60645386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 60745386Swpaul return(ENOBUFS); 60845386Swpaul } 60945386Swpaul 61045386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 61145386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 61245386Swpaul 61345386Swpaul /* 61445386Swpaul * Now divide it up into 9K pieces and save the addresses 61545386Swpaul * in an array. Note that we play an evil trick here by using 61645386Swpaul * the first few bytes in the buffer to hold the the address 61745386Swpaul * of the softc structure for this interface. This is because 61845386Swpaul * ti_jfree() needs it, but it is called by the mbuf management 61945386Swpaul * code which will not pass it to us explicitly. 62045386Swpaul */ 62145386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 62245386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 62345386Swpaul u_int64_t **aptr; 62445386Swpaul aptr = (u_int64_t **)ptr; 62545386Swpaul aptr[0] = (u_int64_t *)sc; 62645386Swpaul ptr += sizeof(u_int64_t); 62745386Swpaul sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 62845386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 62945386Swpaul ptr += (TI_JLEN - sizeof(u_int64_t)); 63045386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 63145386Swpaul M_DEVBUF, M_NOWAIT); 63245386Swpaul if (entry == NULL) { 63345386Swpaul free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 63445386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 63545386Swpaul printf("ti%d: no memory for jumbo " 63645386Swpaul "buffer queue!\n", sc->ti_unit); 63745386Swpaul return(ENOBUFS); 63845386Swpaul } 63945386Swpaul entry->slot = i; 64045386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 64145386Swpaul } 64245386Swpaul 64345386Swpaul return(0); 64445386Swpaul} 64545386Swpaul 64645386Swpaul/* 64745386Swpaul * Allocate a jumbo buffer. 64845386Swpaul */ 64945386Swpaulstatic void *ti_jalloc(sc) 65045386Swpaul struct ti_softc *sc; 65145386Swpaul{ 65245386Swpaul struct ti_jpool_entry *entry; 65345386Swpaul 65445386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 65545386Swpaul 65645386Swpaul if (entry == NULL) { 65745386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 65845386Swpaul return(NULL); 65945386Swpaul } 66045386Swpaul 66145386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 66245386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 66345386Swpaul sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 66445386Swpaul return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 66545386Swpaul} 66645386Swpaul 66745386Swpaul/* 66845386Swpaul * Adjust usage count on a jumbo buffer. In general this doesn't 66945386Swpaul * get used much because our jumbo buffers don't get passed around 67045386Swpaul * too much, but it's implemented for correctness. 67145386Swpaul */ 67245386Swpaulstatic void ti_jref(buf, size) 67345386Swpaul caddr_t buf; 67445386Swpaul u_int size; 67545386Swpaul{ 67645386Swpaul struct ti_softc *sc; 67745386Swpaul u_int64_t **aptr; 67845386Swpaul register int i; 67945386Swpaul 68045386Swpaul /* Extract the softc struct pointer. */ 68145386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 68245386Swpaul sc = (struct ti_softc *)(aptr[0]); 68345386Swpaul 68445386Swpaul if (sc == NULL) 68545386Swpaul panic("ti_jref: can't find softc pointer!"); 68645386Swpaul 68749036Swpaul if (size != TI_JUMBO_FRAMELEN) 68845386Swpaul panic("ti_jref: adjusting refcount of buf of wrong size!"); 68945386Swpaul 69045386Swpaul /* calculate the slot this buffer belongs to */ 69145386Swpaul 69245386Swpaul i = ((vm_offset_t)aptr 69345386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 69445386Swpaul 69545386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 69645386Swpaul panic("ti_jref: asked to reference buffer " 69745386Swpaul "that we don't manage!"); 69845386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 69945386Swpaul panic("ti_jref: buffer already free!"); 70045386Swpaul else 70145386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse++; 70245386Swpaul 70345386Swpaul return; 70445386Swpaul} 70545386Swpaul 70645386Swpaul/* 70745386Swpaul * Release a jumbo buffer. 70845386Swpaul */ 70945386Swpaulstatic void ti_jfree(buf, size) 71045386Swpaul caddr_t buf; 71145386Swpaul u_int size; 71245386Swpaul{ 71345386Swpaul struct ti_softc *sc; 71445386Swpaul u_int64_t **aptr; 71545386Swpaul int i; 71645386Swpaul struct ti_jpool_entry *entry; 71745386Swpaul 71845386Swpaul /* Extract the softc struct pointer. */ 71945386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 72045386Swpaul sc = (struct ti_softc *)(aptr[0]); 72145386Swpaul 72245386Swpaul if (sc == NULL) 72345386Swpaul panic("ti_jfree: can't find softc pointer!"); 72445386Swpaul 72549036Swpaul if (size != TI_JUMBO_FRAMELEN) 72645386Swpaul panic("ti_jfree: freeing buffer of wrong size!"); 72745386Swpaul 72845386Swpaul /* calculate the slot this buffer belongs to */ 72945386Swpaul 73045386Swpaul i = ((vm_offset_t)aptr 73145386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 73245386Swpaul 73345386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 73445386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 73545386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 73645386Swpaul panic("ti_jfree: buffer already free!"); 73745386Swpaul else { 73845386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse--; 73945386Swpaul if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 74045386Swpaul entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 74145386Swpaul if (entry == NULL) 74245386Swpaul panic("ti_jfree: buffer not in use!"); 74345386Swpaul entry->slot = i; 74445386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 74545386Swpaul jpool_entries); 74645386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 74745386Swpaul entry, jpool_entries); 74845386Swpaul } 74945386Swpaul } 75045386Swpaul 75145386Swpaul return; 75245386Swpaul} 75345386Swpaul 75445386Swpaul 75545386Swpaul/* 75645386Swpaul * Intialize a standard receive ring descriptor. 75745386Swpaul */ 75845386Swpaulstatic int ti_newbuf_std(sc, i, m) 75945386Swpaul struct ti_softc *sc; 76045386Swpaul int i; 76145386Swpaul struct mbuf *m; 76245386Swpaul{ 76345386Swpaul struct mbuf *m_new = NULL; 76445386Swpaul struct ti_rx_desc *r; 76545386Swpaul 76649036Swpaul if (m == NULL) { 76745386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 76845386Swpaul if (m_new == NULL) { 76945386Swpaul printf("ti%d: mbuf allocation failed " 77045386Swpaul "-- packet dropped!\n", sc->ti_unit); 77145386Swpaul return(ENOBUFS); 77245386Swpaul } 77345386Swpaul 77445386Swpaul MCLGET(m_new, M_DONTWAIT); 77545386Swpaul if (!(m_new->m_flags & M_EXT)) { 77645386Swpaul printf("ti%d: cluster allocation failed " 77745386Swpaul "-- packet dropped!\n", sc->ti_unit); 77845386Swpaul m_freem(m_new); 77945386Swpaul return(ENOBUFS); 78045386Swpaul } 78149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 78249036Swpaul } else { 78349036Swpaul m_new = m; 78449036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 78549036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 78645386Swpaul } 78745386Swpaul 78848597Swpaul m_adj(m_new, ETHER_ALIGN); 78945386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 79045386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 79145386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 79245386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 79345386Swpaul r->ti_flags = 0; 79458698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 79558698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 79649036Swpaul r->ti_len = m_new->m_len; 79745386Swpaul r->ti_idx = i; 79845386Swpaul 79945386Swpaul return(0); 80045386Swpaul} 80145386Swpaul 80245386Swpaul/* 80345386Swpaul * Intialize a mini receive ring descriptor. This only applies to 80445386Swpaul * the Tigon 2. 80545386Swpaul */ 80645386Swpaulstatic int ti_newbuf_mini(sc, i, m) 80745386Swpaul struct ti_softc *sc; 80845386Swpaul int i; 80945386Swpaul struct mbuf *m; 81045386Swpaul{ 81145386Swpaul struct mbuf *m_new = NULL; 81245386Swpaul struct ti_rx_desc *r; 81345386Swpaul 81449036Swpaul if (m == NULL) { 81545386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 81645386Swpaul if (m_new == NULL) { 81745386Swpaul printf("ti%d: mbuf allocation failed " 81845386Swpaul "-- packet dropped!\n", sc->ti_unit); 81945386Swpaul return(ENOBUFS); 82045386Swpaul } 82149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 82249036Swpaul } else { 82349036Swpaul m_new = m; 82449036Swpaul m_new->m_data = m_new->m_pktdat; 82549036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 82645386Swpaul } 82749036Swpaul 82848597Swpaul m_adj(m_new, ETHER_ALIGN); 82945386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 83045386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 83145386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 83245386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 83345386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 83458698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 83558698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 83649036Swpaul r->ti_len = m_new->m_len; 83745386Swpaul r->ti_idx = i; 83845386Swpaul 83945386Swpaul return(0); 84045386Swpaul} 84145386Swpaul 84245386Swpaul/* 84345386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 84445386Swpaul * a jumbo buffer from the pool managed internally by the driver. 84545386Swpaul */ 84645386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 84745386Swpaul struct ti_softc *sc; 84845386Swpaul int i; 84945386Swpaul struct mbuf *m; 85045386Swpaul{ 85145386Swpaul struct mbuf *m_new = NULL; 85245386Swpaul struct ti_rx_desc *r; 85345386Swpaul 85449036Swpaul if (m == NULL) { 85545386Swpaul caddr_t *buf = NULL; 85645386Swpaul 85745386Swpaul /* Allocate the mbuf. */ 85845386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 85945386Swpaul if (m_new == NULL) { 86045386Swpaul printf("ti%d: mbuf allocation failed " 86145386Swpaul "-- packet dropped!\n", sc->ti_unit); 86245386Swpaul return(ENOBUFS); 86345386Swpaul } 86445386Swpaul 86545386Swpaul /* Allocate the jumbo buffer */ 86645386Swpaul buf = ti_jalloc(sc); 86745386Swpaul if (buf == NULL) { 86845386Swpaul m_freem(m_new); 86945386Swpaul printf("ti%d: jumbo allocation failed " 87045386Swpaul "-- packet dropped!\n", sc->ti_unit); 87145386Swpaul return(ENOBUFS); 87245386Swpaul } 87345386Swpaul 87445386Swpaul /* Attach the buffer to the mbuf. */ 87545386Swpaul m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 87645386Swpaul m_new->m_flags |= M_EXT; 87749036Swpaul m_new->m_len = m_new->m_pkthdr.len = 87849036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 87945386Swpaul m_new->m_ext.ext_free = ti_jfree; 88045386Swpaul m_new->m_ext.ext_ref = ti_jref; 88149036Swpaul } else { 88249036Swpaul m_new = m; 88349036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 88449036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 88545386Swpaul } 88645386Swpaul 88749780Swpaul m_adj(m_new, ETHER_ALIGN); 88845386Swpaul /* Set up the descriptor. */ 88945386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 89045386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 89145386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 89245386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 89345386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 89458698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 89558698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 89649036Swpaul r->ti_len = m_new->m_len; 89745386Swpaul r->ti_idx = i; 89845386Swpaul 89945386Swpaul return(0); 90045386Swpaul} 90145386Swpaul 90245386Swpaul/* 90345386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 90445386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 90545386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 90645386Swpaul * the NIC. 90745386Swpaul */ 90845386Swpaulstatic int ti_init_rx_ring_std(sc) 90945386Swpaul struct ti_softc *sc; 91045386Swpaul{ 91145386Swpaul register int i; 91245386Swpaul struct ti_cmd_desc cmd; 91345386Swpaul 91445386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 91545386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 91645386Swpaul return(ENOBUFS); 91745386Swpaul }; 91845386Swpaul 91945386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 92048597Swpaul sc->ti_std = i - 1; 92145386Swpaul 92245386Swpaul return(0); 92345386Swpaul} 92445386Swpaul 92545386Swpaulstatic void ti_free_rx_ring_std(sc) 92645386Swpaul struct ti_softc *sc; 92745386Swpaul{ 92845386Swpaul register int i; 92945386Swpaul 93045386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 93145386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 93245386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 93345386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 93445386Swpaul } 93545386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 93645386Swpaul sizeof(struct ti_rx_desc)); 93745386Swpaul } 93845386Swpaul 93945386Swpaul return; 94045386Swpaul} 94145386Swpaul 94245386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 94345386Swpaul struct ti_softc *sc; 94445386Swpaul{ 94545386Swpaul register int i; 94645386Swpaul struct ti_cmd_desc cmd; 94745386Swpaul 94845386Swpaul for (i = 0; i < (TI_JSLOTS - 20); i++) { 94945386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 95045386Swpaul return(ENOBUFS); 95145386Swpaul }; 95245386Swpaul 95345386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 95448597Swpaul sc->ti_jumbo = i - 1; 95545386Swpaul 95645386Swpaul return(0); 95745386Swpaul} 95845386Swpaul 95945386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 96045386Swpaul struct ti_softc *sc; 96145386Swpaul{ 96245386Swpaul register int i; 96345386Swpaul 96445386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 96545386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 96645386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 96745386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 96845386Swpaul } 96945386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 97045386Swpaul sizeof(struct ti_rx_desc)); 97145386Swpaul } 97245386Swpaul 97345386Swpaul return; 97445386Swpaul} 97545386Swpaul 97645386Swpaulstatic int ti_init_rx_ring_mini(sc) 97745386Swpaul struct ti_softc *sc; 97845386Swpaul{ 97945386Swpaul register int i; 98045386Swpaul 98145386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 98245386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 98345386Swpaul return(ENOBUFS); 98445386Swpaul }; 98545386Swpaul 98645386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 98748597Swpaul sc->ti_mini = i - 1; 98845386Swpaul 98945386Swpaul return(0); 99045386Swpaul} 99145386Swpaul 99245386Swpaulstatic void ti_free_rx_ring_mini(sc) 99345386Swpaul struct ti_softc *sc; 99445386Swpaul{ 99545386Swpaul register int i; 99645386Swpaul 99745386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 99845386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 99945386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 100045386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 100145386Swpaul } 100245386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 100345386Swpaul sizeof(struct ti_rx_desc)); 100445386Swpaul } 100545386Swpaul 100645386Swpaul return; 100745386Swpaul} 100845386Swpaul 100945386Swpaulstatic void ti_free_tx_ring(sc) 101045386Swpaul struct ti_softc *sc; 101145386Swpaul{ 101245386Swpaul register int i; 101345386Swpaul 101445386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 101545386Swpaul return; 101645386Swpaul 101745386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 101845386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 101945386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 102045386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 102145386Swpaul } 102245386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 102345386Swpaul sizeof(struct ti_tx_desc)); 102445386Swpaul } 102545386Swpaul 102645386Swpaul return; 102745386Swpaul} 102845386Swpaul 102945386Swpaulstatic int ti_init_tx_ring(sc) 103045386Swpaul struct ti_softc *sc; 103145386Swpaul{ 103248011Swpaul sc->ti_txcnt = 0; 103345386Swpaul sc->ti_tx_saved_considx = 0; 103445386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 103545386Swpaul return(0); 103645386Swpaul} 103745386Swpaul 103845386Swpaul/* 103945386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 104045386Swpaul * but we have to support the old way too so that Tigon 1 cards will 104145386Swpaul * work. 104245386Swpaul */ 104345386Swpaulvoid ti_add_mcast(sc, addr) 104445386Swpaul struct ti_softc *sc; 104545386Swpaul struct ether_addr *addr; 104645386Swpaul{ 104745386Swpaul struct ti_cmd_desc cmd; 104845386Swpaul u_int16_t *m; 104945386Swpaul u_int32_t ext[2] = {0, 0}; 105045386Swpaul 105145386Swpaul m = (u_int16_t *)&addr->octet[0]; 105245386Swpaul 105345386Swpaul switch(sc->ti_hwrev) { 105445386Swpaul case TI_HWREV_TIGON: 105545386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 105645386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 105745386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 105845386Swpaul break; 105945386Swpaul case TI_HWREV_TIGON_II: 106045386Swpaul ext[0] = htons(m[0]); 106145386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 106245386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 106345386Swpaul break; 106445386Swpaul default: 106545386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 106645386Swpaul break; 106745386Swpaul } 106845386Swpaul 106945386Swpaul return; 107045386Swpaul} 107145386Swpaul 107245386Swpaulvoid ti_del_mcast(sc, addr) 107345386Swpaul struct ti_softc *sc; 107445386Swpaul struct ether_addr *addr; 107545386Swpaul{ 107645386Swpaul struct ti_cmd_desc cmd; 107745386Swpaul u_int16_t *m; 107845386Swpaul u_int32_t ext[2] = {0, 0}; 107945386Swpaul 108045386Swpaul m = (u_int16_t *)&addr->octet[0]; 108145386Swpaul 108245386Swpaul switch(sc->ti_hwrev) { 108345386Swpaul case TI_HWREV_TIGON: 108445386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 108545386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 108645386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 108745386Swpaul break; 108845386Swpaul case TI_HWREV_TIGON_II: 108945386Swpaul ext[0] = htons(m[0]); 109045386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 109145386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 109245386Swpaul break; 109345386Swpaul default: 109445386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 109545386Swpaul break; 109645386Swpaul } 109745386Swpaul 109845386Swpaul return; 109945386Swpaul} 110045386Swpaul 110145386Swpaul/* 110245386Swpaul * Configure the Tigon's multicast address filter. 110345386Swpaul * 110445386Swpaul * The actual multicast table management is a bit of a pain, thanks to 110545386Swpaul * slight brain damage on the part of both Alteon and us. With our 110645386Swpaul * multicast code, we are only alerted when the multicast address table 110745386Swpaul * changes and at that point we only have the current list of addresses: 110845386Swpaul * we only know the current state, not the previous state, so we don't 110945386Swpaul * actually know what addresses were removed or added. The firmware has 111045386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 111145386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 111245386Swpaul * state so we know what addresses have been programmed into the NIC at 111345386Swpaul * any given time. 111445386Swpaul */ 111545386Swpaulstatic void ti_setmulti(sc) 111645386Swpaul struct ti_softc *sc; 111745386Swpaul{ 111845386Swpaul struct ifnet *ifp; 111945386Swpaul struct ifmultiaddr *ifma; 112045386Swpaul struct ti_cmd_desc cmd; 112145386Swpaul struct ti_mc_entry *mc; 112245386Swpaul u_int32_t intrs; 112345386Swpaul 112445386Swpaul ifp = &sc->arpcom.ac_if; 112545386Swpaul 112645386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 112745386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 112845386Swpaul return; 112945386Swpaul } else { 113045386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 113145386Swpaul } 113245386Swpaul 113345386Swpaul /* Disable interrupts. */ 113445386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 113545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 113645386Swpaul 113745386Swpaul /* First, zot all the existing filters. */ 113845386Swpaul while (sc->ti_mc_listhead.slh_first != NULL) { 113945386Swpaul mc = sc->ti_mc_listhead.slh_first; 114045386Swpaul ti_del_mcast(sc, &mc->mc_addr); 114145386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 114245386Swpaul free(mc, M_DEVBUF); 114345386Swpaul } 114445386Swpaul 114545386Swpaul /* Now program new ones. */ 114645386Swpaul for (ifma = ifp->if_multiaddrs.lh_first; 114745386Swpaul ifma != NULL; ifma = ifma->ifma_link.le_next) { 114845386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 114945386Swpaul continue; 115045386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 115145386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 115245386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 115345386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 115445386Swpaul ti_add_mcast(sc, &mc->mc_addr); 115545386Swpaul } 115645386Swpaul 115745386Swpaul /* Re-enable interrupts. */ 115845386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 115945386Swpaul 116045386Swpaul return; 116145386Swpaul} 116245386Swpaul 116345386Swpaul/* 116445386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 116545386Swpaul * we aren't actually in one. If we detect this condition, we can work 116645386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 116745386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 116845386Swpaul */ 116945386Swpaulstatic int ti_64bitslot_war(sc) 117045386Swpaul struct ti_softc *sc; 117145386Swpaul{ 117245386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 117345386Swpaul CSR_WRITE_4(sc, 0x600, 0); 117445386Swpaul CSR_WRITE_4(sc, 0x604, 0); 117545386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 117645386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 117745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 117845386Swpaul return(EINVAL); 117945386Swpaul else { 118045386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 118145386Swpaul TI_PCISTATE_32BIT_BUS); 118245386Swpaul return(0); 118345386Swpaul } 118445386Swpaul } 118545386Swpaul } 118645386Swpaul 118745386Swpaul return(0); 118845386Swpaul} 118945386Swpaul 119045386Swpaul/* 119145386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 119245386Swpaul * self-test results. 119345386Swpaul */ 119445386Swpaulstatic int ti_chipinit(sc) 119545386Swpaul struct ti_softc *sc; 119645386Swpaul{ 119745386Swpaul u_int32_t cacheline; 119845386Swpaul u_int32_t pci_writemax = 0; 119945386Swpaul 120045386Swpaul /* Initialize link to down state. */ 120145386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 120245386Swpaul 120358698Sjlemon sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 120458698Sjlemon 120545386Swpaul /* Set endianness before we access any non-PCI registers. */ 120645386Swpaul#if BYTE_ORDER == BIG_ENDIAN 120745386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 120845386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 120945386Swpaul#else 121045386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 121145386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 121245386Swpaul#endif 121345386Swpaul 121445386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 121545386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 121645386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 121745386Swpaul return(ENODEV); 121845386Swpaul } 121945386Swpaul 122045386Swpaul /* Halt the CPU. */ 122145386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 122245386Swpaul 122345386Swpaul /* Figure out the hardware revision. */ 122445386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 122545386Swpaul case TI_REV_TIGON_I: 122645386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 122745386Swpaul break; 122845386Swpaul case TI_REV_TIGON_II: 122945386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 123045386Swpaul break; 123145386Swpaul default: 123245386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 123345386Swpaul return(ENODEV); 123445386Swpaul } 123545386Swpaul 123645386Swpaul /* Do special setup for Tigon 2. */ 123745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 123845386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 123945386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 124045386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 124145386Swpaul } 124245386Swpaul 124345386Swpaul /* Set up the PCI state register. */ 124445386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 124545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 124645386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 124745386Swpaul } 124845386Swpaul 124945386Swpaul /* Clear the read/write max DMA parameters. */ 125045386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 125145386Swpaul TI_PCISTATE_READ_MAXDMA)); 125245386Swpaul 125345386Swpaul /* Get cache line size. */ 125445386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 125545386Swpaul 125645386Swpaul /* 125745386Swpaul * If the system has set enabled the PCI memory write 125845386Swpaul * and invalidate command in the command register, set 125945386Swpaul * the write max parameter accordingly. This is necessary 126045386Swpaul * to use MWI with the Tigon 2. 126145386Swpaul */ 126245386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 126345386Swpaul switch(cacheline) { 126445386Swpaul case 1: 126545386Swpaul case 4: 126645386Swpaul case 8: 126745386Swpaul case 16: 126845386Swpaul case 32: 126945386Swpaul case 64: 127045386Swpaul break; 127145386Swpaul default: 127245386Swpaul /* Disable PCI memory write and invalidate. */ 127345386Swpaul if (bootverbose) 127445386Swpaul printf("ti%d: cache line size %d not " 127545386Swpaul "supported; disabling PCI MWI\n", 127645386Swpaul sc->ti_unit, cacheline); 127745386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 127845386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 127945386Swpaul break; 128045386Swpaul } 128145386Swpaul } 128245386Swpaul 128345386Swpaul#ifdef __brokenalpha__ 128445386Swpaul /* 128545386Swpaul * From the Alteon sample driver: 128645386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 128745386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 128845386Swpaul * restriction on some ALPHA platforms with early revision 128945386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 129045386Swpaul */ 129145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 129245386Swpaul#else 129345386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 129445386Swpaul#endif 129545386Swpaul 129645386Swpaul /* This sets the min dma param all the way up (0xff). */ 129745386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 129845386Swpaul 129945386Swpaul /* Configure DMA variables. */ 130045386Swpaul#if BYTE_ORDER == BIG_ENDIAN 130145386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 130245386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 130345386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 130445386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 130545386Swpaul#else 130645386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 130745386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 130845386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 130945386Swpaul#endif 131045386Swpaul 131145386Swpaul /* 131245386Swpaul * Only allow 1 DMA channel to be active at a time. 131345386Swpaul * I don't think this is a good idea, but without it 131445386Swpaul * the firmware racks up lots of nicDmaReadRingFull 131558698Sjlemon * errors. This is not compatible with hardware checksums. 131645386Swpaul */ 131758698Sjlemon if (sc->arpcom.ac_if.if_hwassist == 0) 131858698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 131945386Swpaul 132045386Swpaul /* Recommended settings from Tigon manual. */ 132145386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 132245386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 132345386Swpaul 132445386Swpaul if (ti_64bitslot_war(sc)) { 132545386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 132645386Swpaul "but we aren't", sc->ti_unit); 132745386Swpaul return(EINVAL); 132845386Swpaul } 132945386Swpaul 133045386Swpaul return(0); 133145386Swpaul} 133245386Swpaul 133345386Swpaul/* 133445386Swpaul * Initialize the general information block and firmware, and 133545386Swpaul * start the CPU(s) running. 133645386Swpaul */ 133745386Swpaulstatic int ti_gibinit(sc) 133845386Swpaul struct ti_softc *sc; 133945386Swpaul{ 134045386Swpaul struct ti_rcb *rcb; 134145386Swpaul int i; 134245386Swpaul struct ifnet *ifp; 134345386Swpaul 134445386Swpaul ifp = &sc->arpcom.ac_if; 134545386Swpaul 134645386Swpaul /* Disable interrupts for now. */ 134745386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 134845386Swpaul 134945386Swpaul /* Tell the chip where to find the general information block. */ 135045386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 135145386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 135245386Swpaul 135345386Swpaul /* Load the firmware into SRAM. */ 135445386Swpaul ti_loadfw(sc); 135545386Swpaul 135645386Swpaul /* Set up the contents of the general info and ring control blocks. */ 135745386Swpaul 135845386Swpaul /* Set up the event ring and producer pointer. */ 135945386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 136045386Swpaul 136145386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 136245386Swpaul rcb->ti_flags = 0; 136345386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 136445386Swpaul vtophys(&sc->ti_ev_prodidx); 136545386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 136645386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 136745386Swpaul sc->ti_ev_saved_considx = 0; 136845386Swpaul 136945386Swpaul /* Set up the command ring and producer mailbox. */ 137045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 137145386Swpaul 137245386Swpaul sc->ti_rdata->ti_cmd_ring = 137349133Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 137445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 137545386Swpaul rcb->ti_flags = 0; 137645386Swpaul rcb->ti_max_len = 0; 137745386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 137845386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 137945386Swpaul } 138045386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 138145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 138245386Swpaul sc->ti_cmd_saved_prodidx = 0; 138345386Swpaul 138445386Swpaul /* 138545386Swpaul * Assign the address of the stats refresh buffer. 138645386Swpaul * We re-use the current stats buffer for this to 138745386Swpaul * conserve memory. 138845386Swpaul */ 138945386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 139045386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 139145386Swpaul 139245386Swpaul /* Set up the standard receive ring. */ 139345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 139445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 139545386Swpaul rcb->ti_max_len = TI_FRAMELEN; 139645386Swpaul rcb->ti_flags = 0; 139758698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 139858698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 139958698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 140045386Swpaul#if NVLAN > 0 140145386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 140245386Swpaul#endif 140345386Swpaul 140445386Swpaul /* Set up the jumbo receive ring. */ 140545386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 140645386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 140745386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 140849036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 140945386Swpaul rcb->ti_flags = 0; 141058698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 141158698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 141258698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 141345386Swpaul#if NVLAN > 0 141445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 141545386Swpaul#endif 141645386Swpaul 141745386Swpaul /* 141845386Swpaul * Set up the mini ring. Only activated on the 141945386Swpaul * Tigon 2 but the slot in the config block is 142045386Swpaul * still there on the Tigon 1. 142145386Swpaul */ 142245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 142345386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 142445386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 142551352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 142645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 142745386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 142845386Swpaul else 142945386Swpaul rcb->ti_flags = 0; 143058698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 143158698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 143258698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 143345386Swpaul#if NVLAN > 0 143445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 143545386Swpaul#endif 143645386Swpaul 143745386Swpaul /* 143845386Swpaul * Set up the receive return ring. 143945386Swpaul */ 144045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 144145386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 144245386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 144345386Swpaul rcb->ti_flags = 0; 144445386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 144545386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 144645386Swpaul vtophys(&sc->ti_return_prodidx); 144745386Swpaul 144845386Swpaul /* 144945386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 145045386Swpaul * of putting the transmit ring in the host's address space and 145145386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 145245386Swpaul * memory and accessing it through the shared memory region. We 145345386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 145445386Swpaul * so we have to revert to the shared memory scheme if we detect 145545386Swpaul * a Tigon 1 chip. 145645386Swpaul */ 145745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 145845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 145945386Swpaul sc->ti_rdata->ti_tx_ring_nic = 146049133Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 146145386Swpaul } 146245386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 146345386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 146445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 146545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 146645386Swpaul rcb->ti_flags = 0; 146745386Swpaul else 146845386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 146945386Swpaul#if NVLAN > 0 147045386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 147145386Swpaul#endif 147258698Sjlemon if (sc->arpcom.ac_if.if_hwassist) 147358698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 147458698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 147545386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 147645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 147745386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 147845386Swpaul else 147945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 148045386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 148145386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 148245386Swpaul vtophys(&sc->ti_tx_considx); 148345386Swpaul 148445386Swpaul /* Set up tuneables */ 148545386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 148645386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 148745386Swpaul (sc->ti_rx_coal_ticks / 10)); 148845386Swpaul else 148945386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 149045386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 149145386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 149245386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 149345386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 149445386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 149545386Swpaul 149645386Swpaul /* Turn interrupts on. */ 149745386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 149845386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 149945386Swpaul 150045386Swpaul /* Start CPU. */ 150145386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 150245386Swpaul 150345386Swpaul return(0); 150445386Swpaul} 150545386Swpaul 150645386Swpaul/* 150745386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 150845386Swpaul * against our list and return its name if we find a match. 150945386Swpaul */ 151049011Swpaulstatic int ti_probe(dev) 151149011Swpaul device_t dev; 151245386Swpaul{ 151345386Swpaul struct ti_type *t; 151445386Swpaul 151545386Swpaul t = ti_devs; 151645386Swpaul 151745386Swpaul while(t->ti_name != NULL) { 151849011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 151949011Swpaul (pci_get_device(dev) == t->ti_did)) { 152049011Swpaul device_set_desc(dev, t->ti_name); 152149011Swpaul return(0); 152249011Swpaul } 152345386Swpaul t++; 152445386Swpaul } 152545386Swpaul 152649011Swpaul return(ENXIO); 152745386Swpaul} 152845386Swpaul 152949011Swpaulstatic int ti_attach(dev) 153049011Swpaul device_t dev; 153145386Swpaul{ 153245386Swpaul int s; 153345386Swpaul u_int32_t command; 153445386Swpaul struct ifnet *ifp; 153545386Swpaul struct ti_softc *sc; 153649011Swpaul int unit, error = 0, rid; 153745386Swpaul 153845386Swpaul s = splimp(); 153945386Swpaul 154049011Swpaul sc = device_get_softc(dev); 154149011Swpaul unit = device_get_unit(dev); 154245386Swpaul bzero(sc, sizeof(struct ti_softc)); 154345386Swpaul 154445386Swpaul /* 154545386Swpaul * Map control/status registers. 154645386Swpaul */ 154761041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 154845386Swpaul command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 154961041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 155061041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 155145386Swpaul 155245386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 155345386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 155449011Swpaul error = ENXIO; 155545386Swpaul goto fail; 155645386Swpaul } 155745386Swpaul 155849011Swpaul rid = TI_PCI_LOMEM; 155949011Swpaul sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 156049011Swpaul 0, ~0, 1, RF_ACTIVE); 156149011Swpaul 156249011Swpaul if (sc->ti_res == NULL) { 156345386Swpaul printf ("ti%d: couldn't map memory\n", unit); 156449011Swpaul error = ENXIO; 156545386Swpaul goto fail; 156645386Swpaul } 156745386Swpaul 156849035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 156949035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 157049133Swpaul sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 157149035Swpaul 157249133Swpaul /* 157349133Swpaul * XXX FIXME: rman_get_virtual() on the alpha is currently 157449133Swpaul * broken and returns a physical address instead of a kernel 157549133Swpaul * virtual address. Consequently, we need to do a little 157649133Swpaul * extra mangling of the vhandle on the alpha. This should 157749133Swpaul * eventually be fixed! The whole idea here is to get rid 157849133Swpaul * of platform dependencies. 157949133Swpaul */ 158049133Swpaul#ifdef __alpha__ 158149133Swpaul if (pci_cvt_to_bwx(sc->ti_vhandle)) 158249133Swpaul sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 158349133Swpaul else 158449133Swpaul sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 158549133Swpaul sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 158649133Swpaul#endif 158749133Swpaul 158849011Swpaul /* Allocate interrupt */ 158949011Swpaul rid = 0; 159049133Swpaul 159149011Swpaul sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 159249011Swpaul RF_SHAREABLE | RF_ACTIVE); 159345386Swpaul 159449011Swpaul if (sc->ti_irq == NULL) { 159549011Swpaul printf("ti%d: couldn't map interrupt\n", unit); 159649011Swpaul error = ENXIO; 159745386Swpaul goto fail; 159845386Swpaul } 159945386Swpaul 160049011Swpaul error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 160149011Swpaul ti_intr, sc, &sc->ti_intrhand); 160249011Swpaul 160349011Swpaul if (error) { 160449011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 160549011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 160649011Swpaul TI_PCI_LOMEM, sc->ti_res); 160749011Swpaul printf("ti%d: couldn't set up irq\n", unit); 160845386Swpaul goto fail; 160945386Swpaul } 161045386Swpaul 161145386Swpaul sc->ti_unit = unit; 161245386Swpaul 161345386Swpaul if (ti_chipinit(sc)) { 161445386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 161549011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 161649011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 161749011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 161849011Swpaul TI_PCI_LOMEM, sc->ti_res); 161949011Swpaul error = ENXIO; 162045386Swpaul goto fail; 162145386Swpaul } 162245386Swpaul 162345386Swpaul /* Zero out the NIC's on-board SRAM. */ 162445386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 162545386Swpaul 162645386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 162745386Swpaul if (ti_chipinit(sc)) { 162845386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 162949011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 163049011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 163149011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 163249011Swpaul TI_PCI_LOMEM, sc->ti_res); 163349011Swpaul error = ENXIO; 163445386Swpaul goto fail; 163545386Swpaul } 163645386Swpaul 163745386Swpaul /* 163845386Swpaul * Get station address from the EEPROM. Note: the manual states 163945386Swpaul * that the MAC address is at offset 0x8c, however the data is 164045386Swpaul * stored as two longwords (since that's how it's loaded into 164145386Swpaul * the NIC). This means the MAC address is actually preceeded 164245386Swpaul * by two zero bytes. We need to skip over those. 164345386Swpaul */ 164445386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 164545386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 164645386Swpaul printf("ti%d: failed to read station address\n", unit); 164749011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 164849011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 164949011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 165049011Swpaul TI_PCI_LOMEM, sc->ti_res); 165149011Swpaul error = ENXIO; 165245386Swpaul goto fail; 165345386Swpaul } 165445386Swpaul 165545386Swpaul /* 165645386Swpaul * A Tigon chip was detected. Inform the world. 165745386Swpaul */ 165845386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 165945386Swpaul sc->arpcom.ac_enaddr, ":"); 166045386Swpaul 166145386Swpaul /* Allocate the general information block and ring buffers. */ 166249011Swpaul sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 166350548Sbde M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 166445386Swpaul 166549011Swpaul if (sc->ti_rdata == NULL) { 166649011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 166749011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 166849011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 166949011Swpaul TI_PCI_LOMEM, sc->ti_res); 167049011Swpaul error = ENXIO; 167145386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 167245386Swpaul goto fail; 167345386Swpaul } 167445386Swpaul 167545386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 167645386Swpaul 167745386Swpaul /* Try to allocate memory for jumbo buffers. */ 167845386Swpaul if (ti_alloc_jumbo_mem(sc)) { 167945386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 168049011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 168149011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 168249011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 168349011Swpaul TI_PCI_LOMEM, sc->ti_res); 168449011Swpaul free(sc->ti_rdata, M_DEVBUF); 168549011Swpaul error = ENXIO; 168645386Swpaul goto fail; 168745386Swpaul } 168845386Swpaul 168945386Swpaul /* Set default tuneable values. */ 169045386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 169145386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 169245386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 169345386Swpaul sc->ti_rx_max_coal_bds = 64; 169445386Swpaul sc->ti_tx_max_coal_bds = 128; 169545386Swpaul sc->ti_tx_buf_ratio = 21; 169645386Swpaul 169745386Swpaul /* Set up ifnet structure */ 169845386Swpaul ifp = &sc->arpcom.ac_if; 169945386Swpaul ifp->if_softc = sc; 170045386Swpaul ifp->if_unit = sc->ti_unit; 170145386Swpaul ifp->if_name = "ti"; 170245386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 170345386Swpaul ifp->if_ioctl = ti_ioctl; 170445386Swpaul ifp->if_output = ether_output; 170545386Swpaul ifp->if_start = ti_start; 170645386Swpaul ifp->if_watchdog = ti_watchdog; 170745386Swpaul ifp->if_init = ti_init; 170845386Swpaul ifp->if_mtu = ETHERMTU; 170945386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 171045386Swpaul 171145386Swpaul /* Set up ifmedia support. */ 171245386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 171345386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 171445386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 171545386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 171645386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 171745386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 171845386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 171945386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 172045386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 172145386Swpaul 172245386Swpaul /* 172345386Swpaul * Call MI attach routines. 172445386Swpaul */ 172545386Swpaul if_attach(ifp); 172645386Swpaul ether_ifattach(ifp); 172745386Swpaul 172845386Swpaul bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 172945386Swpaul 173045386Swpaulfail: 173145386Swpaul splx(s); 173245386Swpaul 173349011Swpaul return(error); 173445386Swpaul} 173545386Swpaul 173649011Swpaulstatic int ti_detach(dev) 173749011Swpaul device_t dev; 173849011Swpaul{ 173949011Swpaul struct ti_softc *sc; 174049011Swpaul struct ifnet *ifp; 174149011Swpaul int s; 174249011Swpaul 174349011Swpaul s = splimp(); 174449011Swpaul 174549011Swpaul sc = device_get_softc(dev); 174649011Swpaul ifp = &sc->arpcom.ac_if; 174749011Swpaul 174849011Swpaul if_detach(ifp); 174949011Swpaul ti_stop(sc); 175049011Swpaul 175149011Swpaul bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 175249011Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 175349011Swpaul bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 175449011Swpaul 175549011Swpaul free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 175649011Swpaul free(sc->ti_rdata, M_DEVBUF); 175749011Swpaul ifmedia_removeall(&sc->ifmedia); 175849011Swpaul 175949011Swpaul splx(s); 176049011Swpaul 176149011Swpaul return(0); 176249011Swpaul} 176349011Swpaul 176445386Swpaul/* 176545386Swpaul * Frame reception handling. This is called if there's a frame 176645386Swpaul * on the receive return list. 176745386Swpaul * 176845386Swpaul * Note: we have to be able to handle three possibilities here: 176945386Swpaul * 1) the frame is from the mini receive ring (can only happen) 177045386Swpaul * on Tigon 2 boards) 177145386Swpaul * 2) the frame is from the jumbo recieve ring 177245386Swpaul * 3) the frame is from the standard receive ring 177345386Swpaul */ 177445386Swpaul 177545386Swpaulstatic void ti_rxeof(sc) 177645386Swpaul struct ti_softc *sc; 177745386Swpaul{ 177845386Swpaul struct ifnet *ifp; 177948597Swpaul struct ti_cmd_desc cmd; 178045386Swpaul 178145386Swpaul ifp = &sc->arpcom.ac_if; 178245386Swpaul 178345386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 178445386Swpaul struct ti_rx_desc *cur_rx; 178545386Swpaul u_int32_t rxidx; 178645386Swpaul struct ether_header *eh; 178745386Swpaul struct mbuf *m = NULL; 178845386Swpaul#if NVLAN > 0 178945386Swpaul u_int16_t vlan_tag = 0; 179045386Swpaul int have_tag = 0; 179145386Swpaul#endif 179245386Swpaul 179345386Swpaul cur_rx = 179445386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 179545386Swpaul rxidx = cur_rx->ti_idx; 179645386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 179745386Swpaul 179845386Swpaul#if NVLAN > 0 179945386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 180045386Swpaul have_tag = 1; 180145386Swpaul vlan_tag = cur_rx->ti_vlan_tag; 180245386Swpaul } 180345386Swpaul#endif 180445386Swpaul 180545386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 180645386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 180745386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 180845386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 180945386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 181045386Swpaul ifp->if_ierrors++; 181145386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 181245386Swpaul continue; 181345386Swpaul } 181448597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 181548597Swpaul ifp->if_ierrors++; 181648597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 181748597Swpaul continue; 181848597Swpaul } 181945386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 182045386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 182145386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 182245386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 182345386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 182445386Swpaul ifp->if_ierrors++; 182545386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 182645386Swpaul continue; 182745386Swpaul } 182848597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 182948597Swpaul ifp->if_ierrors++; 183048597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 183148597Swpaul continue; 183248597Swpaul } 183345386Swpaul } else { 183445386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 183545386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 183645386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 183745386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 183845386Swpaul ifp->if_ierrors++; 183945386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 184045386Swpaul continue; 184145386Swpaul } 184248597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 184348597Swpaul ifp->if_ierrors++; 184448597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 184548597Swpaul continue; 184648597Swpaul } 184745386Swpaul } 184845386Swpaul 184945386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 185045386Swpaul ifp->if_ipackets++; 185145386Swpaul eh = mtod(m, struct ether_header *); 185245386Swpaul m->m_pkthdr.rcvif = ifp; 185345386Swpaul 185445386Swpaul /* Remove header from mbuf and pass it on. */ 185545386Swpaul m_adj(m, sizeof(struct ether_header)); 185645386Swpaul 185758698Sjlemon if (ifp->if_hwassist) { 185858698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 185958698Sjlemon CSUM_DATA_VALID; 186058698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 186158698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 186258698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 186358698Sjlemon } 186445386Swpaul 186545386Swpaul#if NVLAN > 0 186645386Swpaul /* 186745386Swpaul * If we received a packet with a vlan tag, pass it 186845386Swpaul * to vlan_input() instead of ether_input(). 186945386Swpaul */ 187045386Swpaul if (have_tag) { 187145386Swpaul vlan_input_tag(eh, m, vlan_tag); 187245386Swpaul have_tag = vlan_tag = 0; 187345386Swpaul continue; 187445386Swpaul } 187545386Swpaul#endif 187645386Swpaul ether_input(ifp, eh, m); 187745386Swpaul } 187845386Swpaul 187945386Swpaul /* Only necessary on the Tigon 1. */ 188045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 188145386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 188245386Swpaul sc->ti_rx_saved_considx); 188345386Swpaul 188448597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 188548597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 188648597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 188745386Swpaul 188845386Swpaul return; 188945386Swpaul} 189045386Swpaul 189145386Swpaulstatic void ti_txeof(sc) 189245386Swpaul struct ti_softc *sc; 189345386Swpaul{ 189445386Swpaul struct ti_tx_desc *cur_tx = NULL; 189545386Swpaul struct ifnet *ifp; 189645386Swpaul 189745386Swpaul ifp = &sc->arpcom.ac_if; 189845386Swpaul 189945386Swpaul /* 190045386Swpaul * Go through our tx ring and free mbufs for those 190145386Swpaul * frames that have been sent. 190245386Swpaul */ 190345386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 190445386Swpaul u_int32_t idx = 0; 190545386Swpaul 190645386Swpaul idx = sc->ti_tx_saved_considx; 190745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 190845386Swpaul if (idx > 383) 190945386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191045386Swpaul TI_TX_RING_BASE + 6144); 191145386Swpaul else if (idx > 255) 191245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191345386Swpaul TI_TX_RING_BASE + 4096); 191445386Swpaul else if (idx > 127) 191545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191645386Swpaul TI_TX_RING_BASE + 2048); 191745386Swpaul else 191845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191945386Swpaul TI_TX_RING_BASE); 192045386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 192145386Swpaul } else 192245386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 192345386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 192445386Swpaul ifp->if_opackets++; 192545386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 192645386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 192745386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 192845386Swpaul } 192948011Swpaul sc->ti_txcnt--; 193045386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 193145386Swpaul ifp->if_timer = 0; 193245386Swpaul } 193345386Swpaul 193445386Swpaul if (cur_tx != NULL) 193545386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 193645386Swpaul 193745386Swpaul return; 193845386Swpaul} 193945386Swpaul 194045386Swpaulstatic void ti_intr(xsc) 194145386Swpaul void *xsc; 194245386Swpaul{ 194345386Swpaul struct ti_softc *sc; 194445386Swpaul struct ifnet *ifp; 194545386Swpaul 194645386Swpaul sc = xsc; 194745386Swpaul ifp = &sc->arpcom.ac_if; 194845386Swpaul 194945386Swpaul#ifdef notdef 195045386Swpaul /* Avoid this for now -- checking this register is expensive. */ 195145386Swpaul /* Make sure this is really our interrupt. */ 195245386Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 195345386Swpaul return; 195445386Swpaul#endif 195545386Swpaul 195645386Swpaul /* Ack interrupt and stop others from occuring. */ 195745386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 195845386Swpaul 195945386Swpaul if (ifp->if_flags & IFF_RUNNING) { 196045386Swpaul /* Check RX return ring producer/consumer */ 196145386Swpaul ti_rxeof(sc); 196245386Swpaul 196345386Swpaul /* Check TX ring producer/consumer */ 196445386Swpaul ti_txeof(sc); 196545386Swpaul } 196645386Swpaul 196745386Swpaul ti_handle_events(sc); 196845386Swpaul 196945386Swpaul /* Re-enable interrupts. */ 197045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 197145386Swpaul 197245386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 197345386Swpaul ti_start(ifp); 197445386Swpaul 197545386Swpaul return; 197645386Swpaul} 197745386Swpaul 197845386Swpaulstatic void ti_stats_update(sc) 197945386Swpaul struct ti_softc *sc; 198045386Swpaul{ 198145386Swpaul struct ifnet *ifp; 198245386Swpaul 198345386Swpaul ifp = &sc->arpcom.ac_if; 198445386Swpaul 198545386Swpaul ifp->if_collisions += 198645386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 198745386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 198845386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 198945386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 199045386Swpaul ifp->if_collisions; 199145386Swpaul 199245386Swpaul return; 199345386Swpaul} 199445386Swpaul 199545386Swpaul/* 199645386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 199745386Swpaul * pointers to descriptors. 199845386Swpaul */ 199945386Swpaulstatic int ti_encap(sc, m_head, txidx) 200045386Swpaul struct ti_softc *sc; 200145386Swpaul struct mbuf *m_head; 200245386Swpaul u_int32_t *txidx; 200345386Swpaul{ 200445386Swpaul struct ti_tx_desc *f = NULL; 200545386Swpaul struct mbuf *m; 200648011Swpaul u_int32_t frag, cur, cnt = 0; 200758698Sjlemon u_int16_t csum_flags = 0; 200845386Swpaul#if NVLAN > 0 200945386Swpaul struct ifvlan *ifv = NULL; 201045386Swpaul 201145386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 201245386Swpaul m_head->m_pkthdr.rcvif != NULL && 201345386Swpaul m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 201445386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 201545386Swpaul#endif 201645386Swpaul 201745386Swpaul m = m_head; 201845386Swpaul cur = frag = *txidx; 201945386Swpaul 202058698Sjlemon if (m_head->m_pkthdr.csum_flags) { 202158698Sjlemon if (m_head->m_pkthdr.csum_flags & CSUM_IP) 202258698Sjlemon csum_flags |= TI_BDFLAG_IP_CKSUM; 202358698Sjlemon if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 202458698Sjlemon csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 202558698Sjlemon if (m_head->m_flags & M_LASTFRAG) 202658698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG_END; 202758698Sjlemon else if (m_head->m_flags & M_FRAG) 202858698Sjlemon csum_flags |= TI_BDFLAG_IP_FRAG; 202958698Sjlemon } 203045386Swpaul /* 203145386Swpaul * Start packing the mbufs in this chain into 203245386Swpaul * the fragment pointers. Stop when we run out 203345386Swpaul * of fragments or hit the end of the mbuf chain. 203445386Swpaul */ 203545386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 203645386Swpaul if (m->m_len != 0) { 203745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 203845386Swpaul if (frag > 383) 203945386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204045386Swpaul TI_TX_RING_BASE + 6144); 204145386Swpaul else if (frag > 255) 204245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204345386Swpaul TI_TX_RING_BASE + 4096); 204445386Swpaul else if (frag > 127) 204545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204645386Swpaul TI_TX_RING_BASE + 2048); 204745386Swpaul else 204845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 204945386Swpaul TI_TX_RING_BASE); 205045386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 205145386Swpaul } else 205245386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 205345386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 205445386Swpaul break; 205545386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 205645386Swpaul f->ti_len = m->m_len; 205758698Sjlemon f->ti_flags = csum_flags; 205845386Swpaul#if NVLAN > 0 205945386Swpaul if (ifv != NULL) { 206045386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 206145386Swpaul f->ti_vlan_tag = ifv->ifv_tag; 206245386Swpaul } else { 206345386Swpaul f->ti_vlan_tag = 0; 206445386Swpaul } 206545386Swpaul#endif 206648011Swpaul /* 206748011Swpaul * Sanity check: avoid coming within 16 descriptors 206848011Swpaul * of the end of the ring. 206948011Swpaul */ 207048011Swpaul if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 207148011Swpaul return(ENOBUFS); 207245386Swpaul cur = frag; 207345386Swpaul TI_INC(frag, TI_TX_RING_CNT); 207448011Swpaul cnt++; 207545386Swpaul } 207645386Swpaul } 207745386Swpaul 207845386Swpaul if (m != NULL) 207945386Swpaul return(ENOBUFS); 208045386Swpaul 208146177Swpaul if (frag == sc->ti_tx_saved_considx) 208246177Swpaul return(ENOBUFS); 208346177Swpaul 208445386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 208545386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 208645386Swpaul TI_BDFLAG_END; 208745386Swpaul else 208845386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 208947458Swpaul sc->ti_cdata.ti_tx_chain[cur] = m_head; 209048011Swpaul sc->ti_txcnt += cnt; 209145386Swpaul 209245386Swpaul *txidx = frag; 209345386Swpaul 209445386Swpaul return(0); 209545386Swpaul} 209645386Swpaul 209745386Swpaul/* 209845386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 209945386Swpaul * to the mbuf data regions directly in the transmit descriptors. 210045386Swpaul */ 210145386Swpaulstatic void ti_start(ifp) 210245386Swpaul struct ifnet *ifp; 210345386Swpaul{ 210445386Swpaul struct ti_softc *sc; 210545386Swpaul struct mbuf *m_head = NULL; 210645386Swpaul u_int32_t prodidx = 0; 210745386Swpaul 210845386Swpaul sc = ifp->if_softc; 210945386Swpaul 211045386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 211145386Swpaul 211245386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 211345386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 211445386Swpaul if (m_head == NULL) 211545386Swpaul break; 211645386Swpaul 211745386Swpaul /* 211858698Sjlemon * XXX 211958698Sjlemon * safety overkill. If this is a fragmented packet chain 212058698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 212158698Sjlemon * it if we have enough descriptors to handle the entire 212258698Sjlemon * chain at once. 212358698Sjlemon * (paranoia -- may not actually be needed) 212458698Sjlemon */ 212558698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 212658698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 212758698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 212858698Sjlemon m_head->m_pkthdr.csum_data + 16) { 212958698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 213058698Sjlemon ifp->if_flags |= IFF_OACTIVE; 213158698Sjlemon break; 213258698Sjlemon } 213358698Sjlemon } 213458698Sjlemon 213558698Sjlemon /* 213645386Swpaul * Pack the data into the transmit ring. If we 213745386Swpaul * don't have room, set the OACTIVE flag and wait 213845386Swpaul * for the NIC to drain the ring. 213945386Swpaul */ 214045386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 214145386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 214245386Swpaul ifp->if_flags |= IFF_OACTIVE; 214345386Swpaul break; 214445386Swpaul } 214545386Swpaul 214645386Swpaul /* 214745386Swpaul * If there's a BPF listener, bounce a copy of this frame 214845386Swpaul * to him. 214945386Swpaul */ 215045386Swpaul if (ifp->if_bpf) 215145386Swpaul bpf_mtap(ifp, m_head); 215245386Swpaul } 215345386Swpaul 215445386Swpaul /* Transmit */ 215545386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 215645386Swpaul 215745386Swpaul /* 215845386Swpaul * Set a timeout in case the chip goes out to lunch. 215945386Swpaul */ 216045386Swpaul ifp->if_timer = 5; 216145386Swpaul 216245386Swpaul return; 216345386Swpaul} 216445386Swpaul 216545386Swpaulstatic void ti_init(xsc) 216645386Swpaul void *xsc; 216745386Swpaul{ 216845386Swpaul struct ti_softc *sc = xsc; 216945386Swpaul int s; 217045386Swpaul 217145386Swpaul s = splimp(); 217245386Swpaul 217345386Swpaul /* Cancel pending I/O and flush buffers. */ 217445386Swpaul ti_stop(sc); 217545386Swpaul 217645386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 217745386Swpaul if (ti_gibinit(sc)) { 217845386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 217945386Swpaul splx(s); 218045386Swpaul return; 218145386Swpaul } 218245386Swpaul 218345386Swpaul splx(s); 218445386Swpaul 218545386Swpaul return; 218645386Swpaul} 218745386Swpaul 218845386Swpaulstatic void ti_init2(sc) 218945386Swpaul struct ti_softc *sc; 219045386Swpaul{ 219145386Swpaul struct ti_cmd_desc cmd; 219245386Swpaul struct ifnet *ifp; 219345386Swpaul u_int16_t *m; 219445386Swpaul struct ifmedia *ifm; 219545386Swpaul int tmp; 219645386Swpaul 219745386Swpaul ifp = &sc->arpcom.ac_if; 219845386Swpaul 219945386Swpaul /* Specify MTU and interface index. */ 220045386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 220145386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 220245386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 220345386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 220445386Swpaul 220545386Swpaul /* Load our MAC address. */ 220645386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 220745386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 220845386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 220945386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 221045386Swpaul 221145386Swpaul /* Enable or disable promiscuous mode as needed. */ 221245386Swpaul if (ifp->if_flags & IFF_PROMISC) { 221345386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 221445386Swpaul } else { 221545386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 221645386Swpaul } 221745386Swpaul 221845386Swpaul /* Program multicast filter. */ 221945386Swpaul ti_setmulti(sc); 222045386Swpaul 222145386Swpaul /* 222245386Swpaul * If this is a Tigon 1, we should tell the 222345386Swpaul * firmware to use software packet filtering. 222445386Swpaul */ 222545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 222645386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 222745386Swpaul } 222845386Swpaul 222945386Swpaul /* Init RX ring. */ 223045386Swpaul ti_init_rx_ring_std(sc); 223145386Swpaul 223245386Swpaul /* Init jumbo RX ring. */ 223345386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 223445386Swpaul ti_init_rx_ring_jumbo(sc); 223545386Swpaul 223645386Swpaul /* 223745386Swpaul * If this is a Tigon 2, we can also configure the 223845386Swpaul * mini ring. 223945386Swpaul */ 224045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 224145386Swpaul ti_init_rx_ring_mini(sc); 224245386Swpaul 224345386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 224445386Swpaul sc->ti_rx_saved_considx = 0; 224545386Swpaul 224645386Swpaul /* Init TX ring. */ 224745386Swpaul ti_init_tx_ring(sc); 224845386Swpaul 224945386Swpaul /* Tell firmware we're alive. */ 225045386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 225145386Swpaul 225245386Swpaul /* Enable host interrupts. */ 225345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 225445386Swpaul 225545386Swpaul ifp->if_flags |= IFF_RUNNING; 225645386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 225745386Swpaul 225845386Swpaul /* 225945386Swpaul * Make sure to set media properly. We have to do this 226045386Swpaul * here since we have to issue commands in order to set 226145386Swpaul * the link negotiation and we can't issue commands until 226245386Swpaul * the firmware is running. 226345386Swpaul */ 226445386Swpaul ifm = &sc->ifmedia; 226545386Swpaul tmp = ifm->ifm_media; 226645386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 226745386Swpaul ti_ifmedia_upd(ifp); 226845386Swpaul ifm->ifm_media = tmp; 226945386Swpaul 227045386Swpaul return; 227145386Swpaul} 227245386Swpaul 227345386Swpaul/* 227445386Swpaul * Set media options. 227545386Swpaul */ 227645386Swpaulstatic int ti_ifmedia_upd(ifp) 227745386Swpaul struct ifnet *ifp; 227845386Swpaul{ 227945386Swpaul struct ti_softc *sc; 228045386Swpaul struct ifmedia *ifm; 228145386Swpaul struct ti_cmd_desc cmd; 228245386Swpaul 228345386Swpaul sc = ifp->if_softc; 228445386Swpaul ifm = &sc->ifmedia; 228545386Swpaul 228645386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 228745386Swpaul return(EINVAL); 228845386Swpaul 228945386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 229045386Swpaul case IFM_AUTO: 229145386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 229245386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 229345386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 229445386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 229545386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 229645386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 229745386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 229845386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 229945386Swpaul break; 230045386Swpaul case IFM_1000_SX: 230145386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 230245386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 230345386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 230445386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 230545386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 230645386Swpaul break; 230745386Swpaul case IFM_100_FX: 230845386Swpaul case IFM_10_FL: 230945386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 231045386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 231145386Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 231245386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 231345386Swpaul } else { 231445386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 231545386Swpaul } 231645386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 231745386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 231845386Swpaul } else { 231945386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 232045386Swpaul } 232145386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 232245386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 232345386Swpaul break; 232445386Swpaul } 232545386Swpaul 232645386Swpaul return(0); 232745386Swpaul} 232845386Swpaul 232945386Swpaul/* 233045386Swpaul * Report current media status. 233145386Swpaul */ 233245386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 233345386Swpaul struct ifnet *ifp; 233445386Swpaul struct ifmediareq *ifmr; 233545386Swpaul{ 233645386Swpaul struct ti_softc *sc; 233745386Swpaul 233845386Swpaul sc = ifp->if_softc; 233945386Swpaul 234045386Swpaul ifmr->ifm_status = IFM_AVALID; 234145386Swpaul ifmr->ifm_active = IFM_ETHER; 234245386Swpaul 234345386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 234445386Swpaul return; 234545386Swpaul 234645386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 234745386Swpaul 234845386Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 234945386Swpaul ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 235045386Swpaul else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 235145386Swpaul u_int32_t media; 235245386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 235345386Swpaul if (media & TI_LNK_100MB) 235445386Swpaul ifmr->ifm_active |= IFM_100_FX; 235545386Swpaul if (media & TI_LNK_10MB) 235645386Swpaul ifmr->ifm_active |= IFM_10_FL; 235745386Swpaul if (media & TI_LNK_FULL_DUPLEX) 235845386Swpaul ifmr->ifm_active |= IFM_FDX; 235945386Swpaul if (media & TI_LNK_HALF_DUPLEX) 236045386Swpaul ifmr->ifm_active |= IFM_HDX; 236145386Swpaul } 236245386Swpaul 236345386Swpaul return; 236445386Swpaul} 236545386Swpaul 236645386Swpaulstatic int ti_ioctl(ifp, command, data) 236745386Swpaul struct ifnet *ifp; 236845386Swpaul u_long command; 236945386Swpaul caddr_t data; 237045386Swpaul{ 237145386Swpaul struct ti_softc *sc = ifp->if_softc; 237245386Swpaul struct ifreq *ifr = (struct ifreq *) data; 237345386Swpaul int s, error = 0; 237445386Swpaul struct ti_cmd_desc cmd; 237545386Swpaul 237645386Swpaul s = splimp(); 237745386Swpaul 237845386Swpaul switch(command) { 237945386Swpaul case SIOCSIFADDR: 238045386Swpaul case SIOCGIFADDR: 238145386Swpaul error = ether_ioctl(ifp, command, data); 238245386Swpaul break; 238345386Swpaul case SIOCSIFMTU: 238445386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 238545386Swpaul error = EINVAL; 238645386Swpaul else { 238745386Swpaul ifp->if_mtu = ifr->ifr_mtu; 238845386Swpaul ti_init(sc); 238945386Swpaul } 239045386Swpaul break; 239145386Swpaul case SIOCSIFFLAGS: 239245386Swpaul if (ifp->if_flags & IFF_UP) { 239345386Swpaul /* 239445386Swpaul * If only the state of the PROMISC flag changed, 239545386Swpaul * then just use the 'set promisc mode' command 239645386Swpaul * instead of reinitializing the entire NIC. Doing 239745386Swpaul * a full re-init means reloading the firmware and 239845386Swpaul * waiting for it to start up, which may take a 239945386Swpaul * second or two. 240045386Swpaul */ 240145386Swpaul if (ifp->if_flags & IFF_RUNNING && 240245386Swpaul ifp->if_flags & IFF_PROMISC && 240345386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 240445386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 240545386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 240645386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 240745386Swpaul !(ifp->if_flags & IFF_PROMISC) && 240845386Swpaul sc->ti_if_flags & IFF_PROMISC) { 240945386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 241045386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 241145386Swpaul } else 241245386Swpaul ti_init(sc); 241345386Swpaul } else { 241445386Swpaul if (ifp->if_flags & IFF_RUNNING) { 241545386Swpaul ti_stop(sc); 241645386Swpaul } 241745386Swpaul } 241845386Swpaul sc->ti_if_flags = ifp->if_flags; 241945386Swpaul error = 0; 242045386Swpaul break; 242145386Swpaul case SIOCADDMULTI: 242245386Swpaul case SIOCDELMULTI: 242345386Swpaul if (ifp->if_flags & IFF_RUNNING) { 242445386Swpaul ti_setmulti(sc); 242545386Swpaul error = 0; 242645386Swpaul } 242745386Swpaul break; 242845386Swpaul case SIOCSIFMEDIA: 242945386Swpaul case SIOCGIFMEDIA: 243045386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 243145386Swpaul break; 243245386Swpaul default: 243345386Swpaul error = EINVAL; 243445386Swpaul break; 243545386Swpaul } 243645386Swpaul 243745386Swpaul (void)splx(s); 243845386Swpaul 243945386Swpaul return(error); 244045386Swpaul} 244145386Swpaul 244245386Swpaulstatic void ti_watchdog(ifp) 244345386Swpaul struct ifnet *ifp; 244445386Swpaul{ 244545386Swpaul struct ti_softc *sc; 244645386Swpaul 244745386Swpaul sc = ifp->if_softc; 244845386Swpaul 244945386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 245045386Swpaul ti_stop(sc); 245145386Swpaul ti_init(sc); 245245386Swpaul 245345386Swpaul ifp->if_oerrors++; 245445386Swpaul 245545386Swpaul return; 245645386Swpaul} 245745386Swpaul 245845386Swpaul/* 245945386Swpaul * Stop the adapter and free any mbufs allocated to the 246045386Swpaul * RX and TX lists. 246145386Swpaul */ 246245386Swpaulstatic void ti_stop(sc) 246345386Swpaul struct ti_softc *sc; 246445386Swpaul{ 246545386Swpaul struct ifnet *ifp; 246645386Swpaul struct ti_cmd_desc cmd; 246745386Swpaul 246845386Swpaul ifp = &sc->arpcom.ac_if; 246945386Swpaul 247045386Swpaul /* Disable host interrupts. */ 247145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 247245386Swpaul /* 247345386Swpaul * Tell firmware we're shutting down. 247445386Swpaul */ 247545386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 247645386Swpaul 247745386Swpaul /* Halt and reinitialize. */ 247845386Swpaul ti_chipinit(sc); 247945386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 248045386Swpaul ti_chipinit(sc); 248145386Swpaul 248245386Swpaul /* Free the RX lists. */ 248345386Swpaul ti_free_rx_ring_std(sc); 248445386Swpaul 248545386Swpaul /* Free jumbo RX list. */ 248645386Swpaul ti_free_rx_ring_jumbo(sc); 248745386Swpaul 248845386Swpaul /* Free mini RX list. */ 248945386Swpaul ti_free_rx_ring_mini(sc); 249045386Swpaul 249145386Swpaul /* Free TX buffers. */ 249245386Swpaul ti_free_tx_ring(sc); 249345386Swpaul 249445386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 249545386Swpaul sc->ti_return_prodidx.ti_idx = 0; 249645386Swpaul sc->ti_tx_considx.ti_idx = 0; 249745386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 249845386Swpaul 249945386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 250045386Swpaul 250145386Swpaul return; 250245386Swpaul} 250345386Swpaul 250445386Swpaul/* 250545386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 250645386Swpaul * get confused by errant DMAs when rebooting. 250745386Swpaul */ 250849011Swpaulstatic void ti_shutdown(dev) 250949011Swpaul device_t dev; 251045386Swpaul{ 251145386Swpaul struct ti_softc *sc; 251245386Swpaul 251349011Swpaul sc = device_get_softc(dev); 251445386Swpaul 251545386Swpaul ti_chipinit(sc); 251645386Swpaul 251745386Swpaul return; 251845386Swpaul} 2519