if_ti.c revision 46177
145386Swpaul/* 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul * 3246177Swpaul * $Id: if_ti.c,v 1.109 1999/04/29 16:22:07 wpaul Exp $ 3345386Swpaul */ 3445386Swpaul 3545386Swpaul/* 3645386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3745386Swpaul * Manuals, sample driver and firmware source kits are available 3845386Swpaul * from http://www.alteon.com/support/openkits. 3945386Swpaul * 4045386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4145386Swpaul * Electrical Engineering Department 4245386Swpaul * Columbia University, New York City 4345386Swpaul */ 4445386Swpaul 4545386Swpaul/* 4645386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4745386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4845386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4945386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5045386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 5145386Swpaul * controlled by firmware, which must be loaded into the NIC during 5245386Swpaul * initialization. 5345386Swpaul * 5445386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5545386Swpaul * revision, which supports new features such as extended commands, 5645386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5745386Swpaul * 5845386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5945386Swpaul * of development material for the Tigon NIC without requiring an NDA 6045386Swpaul * (although they really should have done it a long time ago). With 6145386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6245386Swpaul * stellar example. 6345386Swpaul * 6445386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6545386Swpaul * this driver by #including it as a C header file. This bloats the 6645386Swpaul * driver somewhat, but it's the easiest method considering that the 6745386Swpaul * driver code and firmware code need to be kept in sync. The source 6845386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6945386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7045386Swpaul * 7145386Swpaul * The following people deserve special thanks: 7245386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7345386Swpaul * for testing 7445386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7545386Swpaul * GA620 Tigon 2 boards for testing 7645386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7745386Swpaul * convincing me to write this driver. 7845386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7945386Swpaul */ 8045386Swpaul 8145386Swpaul#include "bpfilter.h" 8245386Swpaul#include "vlan.h" 8345386Swpaul 8445386Swpaul#include <sys/param.h> 8545386Swpaul#include <sys/systm.h> 8645386Swpaul#include <sys/sockio.h> 8745386Swpaul#include <sys/mbuf.h> 8845386Swpaul#include <sys/malloc.h> 8945386Swpaul#include <sys/kernel.h> 9045386Swpaul#include <sys/socket.h> 9145386Swpaul#include <sys/queue.h> 9245386Swpaul 9345386Swpaul#include <net/if.h> 9445386Swpaul#include <net/if_arp.h> 9545386Swpaul#include <net/ethernet.h> 9645386Swpaul#include <net/if_dl.h> 9745386Swpaul#include <net/if_media.h> 9845386Swpaul 9945386Swpaul#if NBPFILTER > 0 10045386Swpaul#include <net/bpf.h> 10145386Swpaul#endif 10245386Swpaul 10345386Swpaul#if NVLAN > 0 10445386Swpaul#include <net/if_types.h> 10545386Swpaul#include <net/if_vlan_var.h> 10645386Swpaul#endif 10745386Swpaul 10845386Swpaul#include <netinet/in_systm.h> 10945386Swpaul#include <netinet/in.h> 11045386Swpaul#include <netinet/ip.h> 11145386Swpaul 11245386Swpaul#include <vm/vm.h> /* for vtophys */ 11345386Swpaul#include <vm/pmap.h> /* for vtophys */ 11445386Swpaul#include <machine/clock.h> /* for DELAY */ 11545386Swpaul#include <machine/bus_memio.h> 11645386Swpaul#include <machine/bus.h> 11745386Swpaul 11845386Swpaul#include <pci/pcireg.h> 11945386Swpaul#include <pci/pcivar.h> 12045386Swpaul 12145386Swpaul#include <pci/if_tireg.h> 12245386Swpaul#include <pci/ti_fw.h> 12345386Swpaul#include <pci/ti_fw2.h> 12445386Swpaul 12545386Swpaul#ifdef M_HWCKSUM 12645386Swpaul/*#define TI_CSUM_OFFLOAD*/ 12745386Swpaul#endif 12845386Swpaul 12945386Swpaul#if !defined(lint) 13045386Swpaulstatic const char rcsid[] = 13146177Swpaul "$Id: if_ti.c,v 1.109 1999/04/29 16:22:07 wpaul Exp $"; 13245386Swpaul#endif 13345386Swpaul 13445386Swpaul/* 13545386Swpaul * Various supported device vendors/types and their names. 13645386Swpaul */ 13745386Swpaul 13845386Swpaulstatic struct ti_type ti_devs[] = { 13945386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 14045386Swpaul "Alteon AceNIC Gigabit Ethernet" }, 14145386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 14245386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 14345386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 14445386Swpaul "Netgear GA620 Gigabit Ethernet" }, 14545386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 14645386Swpaul "Silicon Graphics Gigabit Ethernet" }, 14745386Swpaul { 0, 0, NULL } 14845386Swpaul}; 14945386Swpaul 15045386Swpaulstatic unsigned long ti_count; 15145386Swpaul 15245386Swpaulstatic const char *ti_probe __P((pcici_t, pcidi_t)); 15345386Swpaulstatic void ti_attach __P((pcici_t, int)); 15445386Swpaulstatic void ti_txeof __P((struct ti_softc *)); 15545386Swpaulstatic void ti_rxeof __P((struct ti_softc *)); 15645386Swpaul 15745386Swpaulstatic void ti_stats_update __P((struct ti_softc *)); 15845386Swpaulstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 15945386Swpaul u_int32_t *)); 16045386Swpaul 16145386Swpaulstatic void ti_intr __P((void *)); 16245386Swpaulstatic void ti_start __P((struct ifnet *)); 16345386Swpaulstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16445386Swpaulstatic void ti_init __P((void *)); 16545386Swpaulstatic void ti_init2 __P((struct ti_softc *)); 16645386Swpaulstatic void ti_stop __P((struct ti_softc *)); 16745386Swpaulstatic void ti_watchdog __P((struct ifnet *)); 16845386Swpaulstatic void ti_shutdown __P((int, void *)); 16945386Swpaulstatic int ti_ifmedia_upd __P((struct ifnet *)); 17045386Swpaulstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17145386Swpaul 17245386Swpaulstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17345386Swpaulstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17445386Swpaul int, u_int8_t *)); 17545386Swpaulstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17645386Swpaul 17745386Swpaulstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 17845386Swpaulstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 17945386Swpaulstatic void ti_setmulti __P((struct ti_softc *)); 18045386Swpaul 18145386Swpaulstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18245386Swpaul u_int32_t, caddr_t)); 18345386Swpaulstatic void ti_loadfw __P((struct ti_softc *)); 18445386Swpaulstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18545386Swpaulstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18645386Swpaul caddr_t, int)); 18745386Swpaulstatic void ti_handle_events __P((struct ti_softc *)); 18845386Swpaulstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 18945386Swpaulstatic void *ti_jalloc __P((struct ti_softc *)); 19045386Swpaulstatic void ti_jfree __P((caddr_t, u_int)); 19145386Swpaulstatic void ti_jref __P((caddr_t, u_int)); 19245386Swpaulstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19345386Swpaulstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19445386Swpaulstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19545386Swpaulstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19645386Swpaulstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19745386Swpaulstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 19845386Swpaulstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 19945386Swpaulstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 20045386Swpaulstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20145386Swpaulstatic void ti_refill_rx_rings __P((struct ti_softc *)); 20245386Swpaulstatic void ti_free_tx_ring __P((struct ti_softc *)); 20345386Swpaulstatic int ti_init_tx_ring __P((struct ti_softc *)); 20445386Swpaul 20545386Swpaulstatic int ti_64bitslot_war __P((struct ti_softc *)); 20645386Swpaulstatic int ti_chipinit __P((struct ti_softc *)); 20745386Swpaulstatic int ti_gibinit __P((struct ti_softc *)); 20845386Swpaul 20945386Swpaul/* 21045386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 21145386Swpaul */ 21245386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 21345386Swpaul struct ti_softc *sc; 21445386Swpaul int byte; 21545386Swpaul{ 21645386Swpaul register int i, ack = 0; 21745386Swpaul 21845386Swpaul /* 21945386Swpaul * Make sure we're in TX mode. 22045386Swpaul */ 22145386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 22245386Swpaul 22345386Swpaul /* 22445386Swpaul * Feed in each bit and stobe the clock. 22545386Swpaul */ 22645386Swpaul for (i = 0x80; i; i >>= 1) { 22745386Swpaul if (byte & i) { 22845386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 22945386Swpaul } else { 23045386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 23145386Swpaul } 23245386Swpaul DELAY(1); 23345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 23445386Swpaul DELAY(1); 23545386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 23645386Swpaul } 23745386Swpaul 23845386Swpaul /* 23945386Swpaul * Turn off TX mode. 24045386Swpaul */ 24145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 24245386Swpaul 24345386Swpaul /* 24445386Swpaul * Check for ack. 24545386Swpaul */ 24645386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24745386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 24845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24945386Swpaul 25045386Swpaul return(ack); 25145386Swpaul} 25245386Swpaul 25345386Swpaul/* 25445386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 25545386Swpaul * We have to send two address bytes since the EEPROM can hold 25645386Swpaul * more than 256 bytes of data. 25745386Swpaul */ 25845386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 25945386Swpaul struct ti_softc *sc; 26045386Swpaul int addr; 26145386Swpaul u_int8_t *dest; 26245386Swpaul{ 26345386Swpaul register int i; 26445386Swpaul u_int8_t byte = 0; 26545386Swpaul 26645386Swpaul EEPROM_START; 26745386Swpaul 26845386Swpaul /* 26945386Swpaul * Send write control code to EEPROM. 27045386Swpaul */ 27145386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 27245386Swpaul printf("ti%d: failed to send write command, status: %x\n", 27345386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 27445386Swpaul return(1); 27545386Swpaul } 27645386Swpaul 27745386Swpaul /* 27845386Swpaul * Send first byte of address of byte we want to read. 27945386Swpaul */ 28045386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 28145386Swpaul printf("ti%d: failed to send address, status: %x\n", 28245386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 28345386Swpaul return(1); 28445386Swpaul } 28545386Swpaul /* 28645386Swpaul * Send second byte address of byte we want to read. 28745386Swpaul */ 28845386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 28945386Swpaul printf("ti%d: failed to send address, status: %x\n", 29045386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29145386Swpaul return(1); 29245386Swpaul } 29345386Swpaul 29445386Swpaul EEPROM_STOP; 29545386Swpaul EEPROM_START; 29645386Swpaul /* 29745386Swpaul * Send read control code to EEPROM. 29845386Swpaul */ 29945386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 30045386Swpaul printf("ti%d: failed to send read command, status: %x\n", 30145386Swpaul sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30245386Swpaul return(1); 30345386Swpaul } 30445386Swpaul 30545386Swpaul /* 30645386Swpaul * Start reading bits from EEPROM. 30745386Swpaul */ 30845386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 30945386Swpaul for (i = 0x80; i; i >>= 1) { 31045386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 31145386Swpaul DELAY(1); 31245386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 31345386Swpaul byte |= i; 31445386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 31545386Swpaul DELAY(1); 31645386Swpaul } 31745386Swpaul 31845386Swpaul EEPROM_STOP; 31945386Swpaul 32045386Swpaul /* 32145386Swpaul * No ACK generated for read, so just return byte. 32245386Swpaul */ 32345386Swpaul 32445386Swpaul *dest = byte; 32545386Swpaul 32645386Swpaul return(0); 32745386Swpaul} 32845386Swpaul 32945386Swpaul/* 33045386Swpaul * Read a sequence of bytes from the EEPROM. 33145386Swpaul */ 33245386Swpaulstatic int ti_read_eeprom(sc, dest, off, cnt) 33345386Swpaul struct ti_softc *sc; 33445386Swpaul caddr_t dest; 33545386Swpaul int off; 33645386Swpaul int cnt; 33745386Swpaul{ 33845386Swpaul int err = 0, i; 33945386Swpaul u_int8_t byte = 0; 34045386Swpaul 34145386Swpaul for (i = 0; i < cnt; i++) { 34245386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 34345386Swpaul if (err) 34445386Swpaul break; 34545386Swpaul *(dest + i) = byte; 34645386Swpaul } 34745386Swpaul 34845386Swpaul return(err ? 1 : 0); 34945386Swpaul} 35045386Swpaul 35145386Swpaul/* 35245386Swpaul * NIC memory access function. Can be used to either clear a section 35345386Swpaul * of NIC local memory or (if buf is non-NULL) copy data into it. 35445386Swpaul */ 35545386Swpaulstatic void ti_mem(sc, addr, len, buf) 35645386Swpaul struct ti_softc *sc; 35745386Swpaul u_int32_t addr, len; 35845386Swpaul caddr_t buf; 35945386Swpaul{ 36045386Swpaul int segptr, segsize, cnt; 36145386Swpaul caddr_t ti_winbase, ptr; 36245386Swpaul 36345386Swpaul segptr = addr; 36445386Swpaul cnt = len; 36545386Swpaul#ifdef __i386__ 36645386Swpaul ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW); 36745386Swpaul#endif 36845386Swpaul#ifdef __alpha__ 36945386Swpaul ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 37045386Swpaul#endif 37145386Swpaul ptr = buf; 37245386Swpaul 37345386Swpaul while(cnt) { 37445386Swpaul if (cnt < TI_WINLEN) 37545386Swpaul segsize = cnt; 37645386Swpaul else 37745386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 37845386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 37945386Swpaul if (buf == NULL) 38045386Swpaul bzero((char *)ti_winbase + (segptr & 38145386Swpaul (TI_WINLEN - 1)), segsize); 38245386Swpaul else { 38345386Swpaul bcopy((char *)ptr, (char *)ti_winbase + 38445386Swpaul (segptr & (TI_WINLEN - 1)), segsize); 38545386Swpaul ptr += segsize; 38645386Swpaul } 38745386Swpaul segptr += segsize; 38845386Swpaul cnt -= segsize; 38945386Swpaul } 39045386Swpaul 39145386Swpaul return; 39245386Swpaul} 39345386Swpaul 39445386Swpaul/* 39545386Swpaul * Load firmware image into the NIC. Check that the firmware revision 39645386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 39745386Swpaul * Tigon 2. 39845386Swpaul */ 39945386Swpaulstatic void ti_loadfw(sc) 40045386Swpaul struct ti_softc *sc; 40145386Swpaul{ 40245386Swpaul switch(sc->ti_hwrev) { 40345386Swpaul case TI_HWREV_TIGON: 40445386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 40545386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 40645386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 40745386Swpaul printf("ti%d: firmware revision mismatch; want " 40845386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 40945386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 41045386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 41145386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 41245386Swpaul return; 41345386Swpaul } 41445386Swpaul ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 41545386Swpaul (caddr_t)tigonFwText); 41645386Swpaul ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 41745386Swpaul (caddr_t)tigonFwData); 41845386Swpaul ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 41945386Swpaul (caddr_t)tigonFwRodata); 42045386Swpaul ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 42145386Swpaul ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 42245386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 42345386Swpaul break; 42445386Swpaul case TI_HWREV_TIGON_II: 42545386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 42645386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 42745386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 42845386Swpaul printf("ti%d: firmware revision mismatch; want " 42945386Swpaul "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 43045386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 43145386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 43245386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 43345386Swpaul return; 43445386Swpaul } 43545386Swpaul ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 43645386Swpaul (caddr_t)tigon2FwText); 43745386Swpaul ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 43845386Swpaul (caddr_t)tigon2FwData); 43945386Swpaul ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 44045386Swpaul (caddr_t)tigon2FwRodata); 44145386Swpaul ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 44245386Swpaul ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 44345386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 44445386Swpaul break; 44545386Swpaul default: 44645386Swpaul printf("ti%d: can't load firmware: unknown hardware rev\n", 44745386Swpaul sc->ti_unit); 44845386Swpaul break; 44945386Swpaul } 45045386Swpaul 45145386Swpaul return; 45245386Swpaul} 45345386Swpaul 45445386Swpaul/* 45545386Swpaul * Send the NIC a command via the command ring. 45645386Swpaul */ 45745386Swpaulstatic void ti_cmd(sc, cmd) 45845386Swpaul struct ti_softc *sc; 45945386Swpaul struct ti_cmd_desc *cmd; 46045386Swpaul{ 46145386Swpaul u_int32_t index; 46245386Swpaul 46345386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 46445386Swpaul return; 46545386Swpaul 46645386Swpaul index = sc->ti_cmd_saved_prodidx; 46745386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 46845386Swpaul TI_INC(index, TI_CMD_RING_CNT); 46945386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 47045386Swpaul sc->ti_cmd_saved_prodidx = index; 47145386Swpaul 47245386Swpaul return; 47345386Swpaul} 47445386Swpaul 47545386Swpaul/* 47645386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 47745386Swpaul * number of command slots to include after the initial command. 47845386Swpaul */ 47945386Swpaulstatic void ti_cmd_ext(sc, cmd, arg, len) 48045386Swpaul struct ti_softc *sc; 48145386Swpaul struct ti_cmd_desc *cmd; 48245386Swpaul caddr_t arg; 48345386Swpaul int len; 48445386Swpaul{ 48545386Swpaul u_int32_t index; 48645386Swpaul register int i; 48745386Swpaul 48845386Swpaul if (sc->ti_rdata->ti_cmd_ring == NULL) 48945386Swpaul return; 49045386Swpaul 49145386Swpaul index = sc->ti_cmd_saved_prodidx; 49245386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 49345386Swpaul TI_INC(index, TI_CMD_RING_CNT); 49445386Swpaul for (i = 0; i < len; i++) { 49545386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 49645386Swpaul *(u_int32_t *)(&arg[i * 4])); 49745386Swpaul TI_INC(index, TI_CMD_RING_CNT); 49845386Swpaul } 49945386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 50045386Swpaul sc->ti_cmd_saved_prodidx = index; 50145386Swpaul 50245386Swpaul return; 50345386Swpaul} 50445386Swpaul 50545386Swpaul/* 50645386Swpaul * Handle events that have triggered interrupts. 50745386Swpaul */ 50845386Swpaulstatic void ti_handle_events(sc) 50945386Swpaul struct ti_softc *sc; 51045386Swpaul{ 51145386Swpaul struct ti_event_desc *e; 51245386Swpaul 51345386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 51445386Swpaul return; 51545386Swpaul 51645386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 51745386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 51845386Swpaul switch(e->ti_event) { 51945386Swpaul case TI_EV_LINKSTAT_CHANGED: 52045386Swpaul sc->ti_linkstat = e->ti_code; 52145386Swpaul if (e->ti_code == TI_EV_CODE_LINK_UP) 52245386Swpaul printf("ti%d: 10/100 link up\n", sc->ti_unit); 52345386Swpaul else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 52445386Swpaul printf("ti%d: gigabit link up\n", sc->ti_unit); 52545386Swpaul else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 52645386Swpaul printf("ti%d: link down\n", sc->ti_unit); 52745386Swpaul break; 52845386Swpaul case TI_EV_ERROR: 52945386Swpaul if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 53045386Swpaul printf("ti%d: invalid command\n", sc->ti_unit); 53145386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 53245386Swpaul printf("ti%d: unknown command\n", sc->ti_unit); 53345386Swpaul else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 53445386Swpaul printf("ti%d: bad config data\n", sc->ti_unit); 53545386Swpaul break; 53645386Swpaul case TI_EV_FIRMWARE_UP: 53745386Swpaul ti_init2(sc); 53845386Swpaul break; 53945386Swpaul case TI_EV_STATS_UPDATED: 54045386Swpaul ti_stats_update(sc); 54145386Swpaul break; 54245386Swpaul case TI_EV_RESET_JUMBO_RING: 54345386Swpaul case TI_EV_MCAST_UPDATED: 54445386Swpaul /* Who cares. */ 54545386Swpaul break; 54645386Swpaul default: 54745386Swpaul printf("ti%d: unknown event: %d\n", 54845386Swpaul sc->ti_unit, e->ti_event); 54945386Swpaul break; 55045386Swpaul } 55145386Swpaul /* Advance the consumer index. */ 55245386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 55345386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 55445386Swpaul } 55545386Swpaul 55645386Swpaul return; 55745386Swpaul} 55845386Swpaul 55945386Swpaul/* 56045386Swpaul * Memory management for the jumbo receive ring is a pain in the 56145386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 56245386Swpaul * _and_ it has to be contiguous (unless you use the extended 56345386Swpaul * jumbo descriptor format). Using malloc() all the time won't 56445386Swpaul * work: malloc() allocates memory in powers of two, which means we 56545386Swpaul * would end up wasting a considerable amount of space by allocating 56645386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 56745386Swpaul * to do our own memory management. 56845386Swpaul * 56945386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 57045386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 57145386Swpaul * as external mbuf storage. 57245386Swpaul * 57345386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 57445386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 57545386Swpaul * RAM. This is a bit much, especially considering we also need 57645386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 57745386Swpaul * save space, we only actually allocate enough memory for 64 slots 57845386Swpaul * by default, which works out to between 500 and 600K. This can 57945386Swpaul * be tuned by changing a #define in if_tireg.h. 58045386Swpaul */ 58145386Swpaul 58245386Swpaulstatic int ti_alloc_jumbo_mem(sc) 58345386Swpaul struct ti_softc *sc; 58445386Swpaul{ 58545386Swpaul caddr_t ptr; 58645386Swpaul register int i; 58745386Swpaul struct ti_jpool_entry *entry; 58845386Swpaul 58945386Swpaul /* Grab a big chunk o' storage. */ 59045386Swpaul sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 59145386Swpaul M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 59245386Swpaul 59345386Swpaul if (sc->ti_cdata.ti_jumbo_buf == NULL) { 59445386Swpaul printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 59545386Swpaul return(ENOBUFS); 59645386Swpaul } 59745386Swpaul 59845386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 59945386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 60045386Swpaul 60145386Swpaul /* 60245386Swpaul * Now divide it up into 9K pieces and save the addresses 60345386Swpaul * in an array. Note that we play an evil trick here by using 60445386Swpaul * the first few bytes in the buffer to hold the the address 60545386Swpaul * of the softc structure for this interface. This is because 60645386Swpaul * ti_jfree() needs it, but it is called by the mbuf management 60745386Swpaul * code which will not pass it to us explicitly. 60845386Swpaul */ 60945386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 61045386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 61145386Swpaul u_int64_t **aptr; 61245386Swpaul aptr = (u_int64_t **)ptr; 61345386Swpaul aptr[0] = (u_int64_t *)sc; 61445386Swpaul ptr += sizeof(u_int64_t); 61545386Swpaul sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 61645386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 61745386Swpaul ptr += (TI_JLEN - sizeof(u_int64_t)); 61845386Swpaul entry = malloc(sizeof(struct ti_jpool_entry), 61945386Swpaul M_DEVBUF, M_NOWAIT); 62045386Swpaul if (entry == NULL) { 62145386Swpaul free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 62245386Swpaul sc->ti_cdata.ti_jumbo_buf = NULL; 62345386Swpaul printf("ti%d: no memory for jumbo " 62445386Swpaul "buffer queue!\n", sc->ti_unit); 62545386Swpaul return(ENOBUFS); 62645386Swpaul } 62745386Swpaul entry->slot = i; 62845386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 62945386Swpaul } 63045386Swpaul 63145386Swpaul return(0); 63245386Swpaul} 63345386Swpaul 63445386Swpaul/* 63545386Swpaul * Allocate a jumbo buffer. 63645386Swpaul */ 63745386Swpaulstatic void *ti_jalloc(sc) 63845386Swpaul struct ti_softc *sc; 63945386Swpaul{ 64045386Swpaul struct ti_jpool_entry *entry; 64145386Swpaul 64245386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 64345386Swpaul 64445386Swpaul if (entry == NULL) { 64545386Swpaul printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 64645386Swpaul return(NULL); 64745386Swpaul } 64845386Swpaul 64945386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 65045386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 65145386Swpaul sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 65245386Swpaul return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 65345386Swpaul} 65445386Swpaul 65545386Swpaul/* 65645386Swpaul * Adjust usage count on a jumbo buffer. In general this doesn't 65745386Swpaul * get used much because our jumbo buffers don't get passed around 65845386Swpaul * too much, but it's implemented for correctness. 65945386Swpaul */ 66045386Swpaulstatic void ti_jref(buf, size) 66145386Swpaul caddr_t buf; 66245386Swpaul u_int size; 66345386Swpaul{ 66445386Swpaul struct ti_softc *sc; 66545386Swpaul u_int64_t **aptr; 66645386Swpaul register int i; 66745386Swpaul 66845386Swpaul /* Extract the softc struct pointer. */ 66945386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 67045386Swpaul sc = (struct ti_softc *)(aptr[0]); 67145386Swpaul 67245386Swpaul if (sc == NULL) 67345386Swpaul panic("ti_jref: can't find softc pointer!"); 67445386Swpaul 67545386Swpaul if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 67645386Swpaul panic("ti_jref: adjusting refcount of buf of wrong size!"); 67745386Swpaul 67845386Swpaul /* calculate the slot this buffer belongs to */ 67945386Swpaul 68045386Swpaul i = ((vm_offset_t)aptr 68145386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 68245386Swpaul 68345386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 68445386Swpaul panic("ti_jref: asked to reference buffer " 68545386Swpaul "that we don't manage!"); 68645386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 68745386Swpaul panic("ti_jref: buffer already free!"); 68845386Swpaul else 68945386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse++; 69045386Swpaul 69145386Swpaul return; 69245386Swpaul} 69345386Swpaul 69445386Swpaul/* 69545386Swpaul * Release a jumbo buffer. 69645386Swpaul */ 69745386Swpaulstatic void ti_jfree(buf, size) 69845386Swpaul caddr_t buf; 69945386Swpaul u_int size; 70045386Swpaul{ 70145386Swpaul struct ti_softc *sc; 70245386Swpaul u_int64_t **aptr; 70345386Swpaul int i; 70445386Swpaul struct ti_jpool_entry *entry; 70545386Swpaul 70645386Swpaul /* Extract the softc struct pointer. */ 70745386Swpaul aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 70845386Swpaul sc = (struct ti_softc *)(aptr[0]); 70945386Swpaul 71045386Swpaul if (sc == NULL) 71145386Swpaul panic("ti_jfree: can't find softc pointer!"); 71245386Swpaul 71345386Swpaul if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 71445386Swpaul panic("ti_jfree: freeing buffer of wrong size!"); 71545386Swpaul 71645386Swpaul /* calculate the slot this buffer belongs to */ 71745386Swpaul 71845386Swpaul i = ((vm_offset_t)aptr 71945386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 72045386Swpaul 72145386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 72245386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 72345386Swpaul else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 72445386Swpaul panic("ti_jfree: buffer already free!"); 72545386Swpaul else { 72645386Swpaul sc->ti_cdata.ti_jslots[i].ti_inuse--; 72745386Swpaul if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 72845386Swpaul entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 72945386Swpaul if (entry == NULL) 73045386Swpaul panic("ti_jfree: buffer not in use!"); 73145386Swpaul entry->slot = i; 73245386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 73345386Swpaul jpool_entries); 73445386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 73545386Swpaul entry, jpool_entries); 73645386Swpaul } 73745386Swpaul } 73845386Swpaul 73945386Swpaul return; 74045386Swpaul} 74145386Swpaul 74245386Swpaul 74345386Swpaul/* 74445386Swpaul * Intialize a standard receive ring descriptor. 74545386Swpaul */ 74645386Swpaulstatic int ti_newbuf_std(sc, i, m) 74745386Swpaul struct ti_softc *sc; 74845386Swpaul int i; 74945386Swpaul struct mbuf *m; 75045386Swpaul{ 75145386Swpaul struct mbuf *m_new = NULL; 75245386Swpaul struct ti_rx_desc *r; 75345386Swpaul 75445386Swpaul if (m != NULL) { 75545386Swpaul m_new = m; 75645386Swpaul } else { 75745386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 75845386Swpaul if (m_new == NULL) { 75945386Swpaul printf("ti%d: mbuf allocation failed " 76045386Swpaul "-- packet dropped!\n", sc->ti_unit); 76145386Swpaul return(ENOBUFS); 76245386Swpaul } 76345386Swpaul 76445386Swpaul MCLGET(m_new, M_DONTWAIT); 76545386Swpaul if (!(m_new->m_flags & M_EXT)) { 76645386Swpaul printf("ti%d: cluster allocation failed " 76745386Swpaul "-- packet dropped!\n", sc->ti_unit); 76845386Swpaul m_freem(m_new); 76945386Swpaul return(ENOBUFS); 77045386Swpaul } 77145386Swpaul } 77245386Swpaul 77345386Swpaul m_new->m_len -= ETHER_ALIGN; 77445386Swpaul m_new->m_data += ETHER_ALIGN; 77545386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 77645386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 77745386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 77845386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 77945386Swpaul#ifdef TI_CSUM_OFFLOAD 78045386Swpaul r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 78145386Swpaul#else 78245386Swpaul r->ti_flags = 0; 78345386Swpaul#endif 78445386Swpaul r->ti_len = MCLBYTES - ETHER_ALIGN; 78545386Swpaul r->ti_idx = i; 78645386Swpaul 78745386Swpaul return(0); 78845386Swpaul} 78945386Swpaul 79045386Swpaul/* 79145386Swpaul * Intialize a mini receive ring descriptor. This only applies to 79245386Swpaul * the Tigon 2. 79345386Swpaul */ 79445386Swpaulstatic int ti_newbuf_mini(sc, i, m) 79545386Swpaul struct ti_softc *sc; 79645386Swpaul int i; 79745386Swpaul struct mbuf *m; 79845386Swpaul{ 79945386Swpaul struct mbuf *m_new = NULL; 80045386Swpaul struct ti_rx_desc *r; 80145386Swpaul 80245386Swpaul if (m != NULL) { 80345386Swpaul m_new = m; 80445386Swpaul } else { 80545386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 80645386Swpaul if (m_new == NULL) { 80745386Swpaul printf("ti%d: mbuf allocation failed " 80845386Swpaul "-- packet dropped!\n", sc->ti_unit); 80945386Swpaul return(ENOBUFS); 81045386Swpaul } 81145386Swpaul } 81245386Swpaul m_new->m_len -= ETHER_ALIGN; 81345386Swpaul m_new->m_data += ETHER_ALIGN; 81445386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 81545386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 81645386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 81745386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 81845386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 81945386Swpaul#ifdef TI_CSUM_OFFLOAD 82045386Swpaul r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 82145386Swpaul#endif 82245386Swpaul r->ti_len = MHLEN - ETHER_ALIGN; 82345386Swpaul r->ti_idx = i; 82445386Swpaul 82545386Swpaul return(0); 82645386Swpaul} 82745386Swpaul 82845386Swpaul/* 82945386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 83045386Swpaul * a jumbo buffer from the pool managed internally by the driver. 83145386Swpaul */ 83245386Swpaulstatic int ti_newbuf_jumbo(sc, i, m) 83345386Swpaul struct ti_softc *sc; 83445386Swpaul int i; 83545386Swpaul struct mbuf *m; 83645386Swpaul{ 83745386Swpaul struct mbuf *m_new = NULL; 83845386Swpaul struct ti_rx_desc *r; 83945386Swpaul 84045386Swpaul if (m != NULL) { 84145386Swpaul m_new = m; 84245386Swpaul } else { 84345386Swpaul caddr_t *buf = NULL; 84445386Swpaul 84545386Swpaul /* Allocate the mbuf. */ 84645386Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 84745386Swpaul if (m_new == NULL) { 84845386Swpaul printf("ti%d: mbuf allocation failed " 84945386Swpaul "-- packet dropped!\n", sc->ti_unit); 85045386Swpaul return(ENOBUFS); 85145386Swpaul } 85245386Swpaul 85345386Swpaul /* Allocate the jumbo buffer */ 85445386Swpaul buf = ti_jalloc(sc); 85545386Swpaul if (buf == NULL) { 85645386Swpaul m_freem(m_new); 85745386Swpaul printf("ti%d: jumbo allocation failed " 85845386Swpaul "-- packet dropped!\n", sc->ti_unit); 85945386Swpaul return(ENOBUFS); 86045386Swpaul } 86145386Swpaul 86245386Swpaul /* Attach the buffer to the mbuf. */ 86345386Swpaul m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 86445386Swpaul m_new->m_data += ETHER_ALIGN; 86545386Swpaul m_new->m_flags |= M_EXT; 86645386Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 86745386Swpaul m_new->m_ext.ext_free = ti_jfree; 86845386Swpaul m_new->m_ext.ext_ref = ti_jref; 86945386Swpaul } 87045386Swpaul 87145386Swpaul /* Set up the descriptor. */ 87245386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 87345386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 87445386Swpaul TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 87545386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 87645386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 87745386Swpaul#ifdef TI_CSUM_OFFLOAD 87845386Swpaul r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 87945386Swpaul#endif 88045386Swpaul r->ti_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 88145386Swpaul r->ti_idx = i; 88245386Swpaul 88345386Swpaul return(0); 88445386Swpaul} 88545386Swpaul 88645386Swpaul/* 88745386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 88845386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 88945386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 89045386Swpaul * the NIC. 89145386Swpaul */ 89245386Swpaulstatic int ti_init_rx_ring_std(sc) 89345386Swpaul struct ti_softc *sc; 89445386Swpaul{ 89545386Swpaul register int i; 89645386Swpaul struct ti_cmd_desc cmd; 89745386Swpaul 89845386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 89945386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 90045386Swpaul return(ENOBUFS); 90145386Swpaul }; 90245386Swpaul 90345386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 90445386Swpaul sc->ti_std_old = sc->ti_std = i - 1; 90545386Swpaul sc->ti_std_cnt = 0; 90645386Swpaul 90745386Swpaul return(0); 90845386Swpaul} 90945386Swpaul 91045386Swpaulstatic void ti_free_rx_ring_std(sc) 91145386Swpaul struct ti_softc *sc; 91245386Swpaul{ 91345386Swpaul register int i; 91445386Swpaul 91545386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 91645386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 91745386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 91845386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 91945386Swpaul } 92045386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 92145386Swpaul sizeof(struct ti_rx_desc)); 92245386Swpaul } 92345386Swpaul 92445386Swpaul return; 92545386Swpaul} 92645386Swpaul 92745386Swpaulstatic int ti_init_rx_ring_jumbo(sc) 92845386Swpaul struct ti_softc *sc; 92945386Swpaul{ 93045386Swpaul register int i; 93145386Swpaul struct ti_cmd_desc cmd; 93245386Swpaul 93345386Swpaul for (i = 0; i < (TI_JSLOTS - 20); i++) { 93445386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 93545386Swpaul return(ENOBUFS); 93645386Swpaul }; 93745386Swpaul 93845386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 93945386Swpaul sc->ti_jumbo_old = sc->ti_jumbo = i - 1; 94045386Swpaul sc->ti_jumbo_cnt = 0; 94145386Swpaul 94245386Swpaul return(0); 94345386Swpaul} 94445386Swpaul 94545386Swpaulstatic void ti_free_rx_ring_jumbo(sc) 94645386Swpaul struct ti_softc *sc; 94745386Swpaul{ 94845386Swpaul register int i; 94945386Swpaul 95045386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 95145386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 95245386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 95345386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 95445386Swpaul } 95545386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 95645386Swpaul sizeof(struct ti_rx_desc)); 95745386Swpaul } 95845386Swpaul 95945386Swpaul return; 96045386Swpaul} 96145386Swpaul 96245386Swpaulstatic int ti_init_rx_ring_mini(sc) 96345386Swpaul struct ti_softc *sc; 96445386Swpaul{ 96545386Swpaul register int i; 96645386Swpaul 96745386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 96845386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 96945386Swpaul return(ENOBUFS); 97045386Swpaul }; 97145386Swpaul 97245386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 97345386Swpaul sc->ti_mini_old = sc->ti_mini = i - 1; 97445386Swpaul sc->ti_mini_cnt = 0; 97545386Swpaul 97645386Swpaul return(0); 97745386Swpaul} 97845386Swpaul 97945386Swpaulstatic void ti_free_rx_ring_mini(sc) 98045386Swpaul struct ti_softc *sc; 98145386Swpaul{ 98245386Swpaul register int i; 98345386Swpaul 98445386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 98545386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 98645386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 98745386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 98845386Swpaul } 98945386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 99045386Swpaul sizeof(struct ti_rx_desc)); 99145386Swpaul } 99245386Swpaul 99345386Swpaul return; 99445386Swpaul} 99545386Swpaul 99645386Swpaul/* 99745386Swpaul * In order to reduce the amount of work we have to do in the interrupt 99845386Swpaul * handler, we delay putting new buffers in the receive rings until a 99945386Swpaul * certain amount have been used. This lets us hand over descriptors to 100045386Swpaul * the NIC in fairly large chunks instead of one (or a few) at a time, 100145386Swpaul * and it lets tx_rxeof() run a bit faster some of the time. 100245386Swpaul */ 100345386Swpaulstatic void ti_refill_rx_rings(sc) 100445386Swpaul struct ti_softc *sc; 100545386Swpaul{ 100645386Swpaul register int i; 100745386Swpaul struct ti_cmd_desc cmd; 100845386Swpaul 100945386Swpaul if (sc->ti_std_cnt > 15) { 101045386Swpaul for (i = sc->ti_std_old; i != sc->ti_std; 101145386Swpaul TI_INC(i, TI_STD_RX_RING_CNT)) { 101245386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 101345386Swpaul break; 101445386Swpaul }; 101545386Swpaul TI_UPDATE_STDPROD(sc, i); 101645386Swpaul sc->ti_std_old = i; 101745386Swpaul sc->ti_std_cnt = 0; 101845386Swpaul } 101945386Swpaul 102045386Swpaul if (sc->ti_jumbo_cnt > 15) { 102145386Swpaul for (i = sc->ti_jumbo_old; i != sc->ti_jumbo; 102245386Swpaul TI_INC(i, TI_JUMBO_RX_RING_CNT)) { 102345386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 102445386Swpaul break; 102545386Swpaul }; 102645386Swpaul TI_UPDATE_JUMBOPROD(sc, i); 102745386Swpaul sc->ti_jumbo_old = i; 102845386Swpaul sc->ti_jumbo_cnt = 0; 102945386Swpaul } 103045386Swpaul 103145386Swpaul if (sc->ti_mini_cnt > 15) { 103245386Swpaul for (i = sc->ti_mini_old; i != sc->ti_mini; 103345386Swpaul TI_INC(i, TI_MINI_RX_RING_CNT)) { 103445386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 103545386Swpaul break; 103645386Swpaul }; 103745386Swpaul TI_UPDATE_MINIPROD(sc, i); 103845386Swpaul sc->ti_mini_old = i; 103945386Swpaul sc->ti_mini_cnt = 0; 104045386Swpaul } 104145386Swpaul 104245386Swpaul return; 104345386Swpaul} 104445386Swpaul 104545386Swpaulstatic void ti_free_tx_ring(sc) 104645386Swpaul struct ti_softc *sc; 104745386Swpaul{ 104845386Swpaul register int i; 104945386Swpaul 105045386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 105145386Swpaul return; 105245386Swpaul 105345386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 105445386Swpaul if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 105545386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[i]); 105645386Swpaul sc->ti_cdata.ti_tx_chain[i] = NULL; 105745386Swpaul } 105845386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 105945386Swpaul sizeof(struct ti_tx_desc)); 106045386Swpaul } 106145386Swpaul 106245386Swpaul return; 106345386Swpaul} 106445386Swpaul 106545386Swpaulstatic int ti_init_tx_ring(sc) 106645386Swpaul struct ti_softc *sc; 106745386Swpaul{ 106845386Swpaul sc->ti_tx_saved_considx = 0; 106945386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 107045386Swpaul return(0); 107145386Swpaul} 107245386Swpaul 107345386Swpaul/* 107445386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 107545386Swpaul * but we have to support the old way too so that Tigon 1 cards will 107645386Swpaul * work. 107745386Swpaul */ 107845386Swpaulvoid ti_add_mcast(sc, addr) 107945386Swpaul struct ti_softc *sc; 108045386Swpaul struct ether_addr *addr; 108145386Swpaul{ 108245386Swpaul struct ti_cmd_desc cmd; 108345386Swpaul u_int16_t *m; 108445386Swpaul u_int32_t ext[2] = {0, 0}; 108545386Swpaul 108645386Swpaul m = (u_int16_t *)&addr->octet[0]; 108745386Swpaul 108845386Swpaul switch(sc->ti_hwrev) { 108945386Swpaul case TI_HWREV_TIGON: 109045386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 109145386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 109245386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 109345386Swpaul break; 109445386Swpaul case TI_HWREV_TIGON_II: 109545386Swpaul ext[0] = htons(m[0]); 109645386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 109745386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 109845386Swpaul break; 109945386Swpaul default: 110045386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 110145386Swpaul break; 110245386Swpaul } 110345386Swpaul 110445386Swpaul return; 110545386Swpaul} 110645386Swpaul 110745386Swpaulvoid ti_del_mcast(sc, addr) 110845386Swpaul struct ti_softc *sc; 110945386Swpaul struct ether_addr *addr; 111045386Swpaul{ 111145386Swpaul struct ti_cmd_desc cmd; 111245386Swpaul u_int16_t *m; 111345386Swpaul u_int32_t ext[2] = {0, 0}; 111445386Swpaul 111545386Swpaul m = (u_int16_t *)&addr->octet[0]; 111645386Swpaul 111745386Swpaul switch(sc->ti_hwrev) { 111845386Swpaul case TI_HWREV_TIGON: 111945386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 112045386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 112145386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 112245386Swpaul break; 112345386Swpaul case TI_HWREV_TIGON_II: 112445386Swpaul ext[0] = htons(m[0]); 112545386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 112645386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 112745386Swpaul break; 112845386Swpaul default: 112945386Swpaul printf("ti%d: unknown hwrev\n", sc->ti_unit); 113045386Swpaul break; 113145386Swpaul } 113245386Swpaul 113345386Swpaul return; 113445386Swpaul} 113545386Swpaul 113645386Swpaul/* 113745386Swpaul * Configure the Tigon's multicast address filter. 113845386Swpaul * 113945386Swpaul * The actual multicast table management is a bit of a pain, thanks to 114045386Swpaul * slight brain damage on the part of both Alteon and us. With our 114145386Swpaul * multicast code, we are only alerted when the multicast address table 114245386Swpaul * changes and at that point we only have the current list of addresses: 114345386Swpaul * we only know the current state, not the previous state, so we don't 114445386Swpaul * actually know what addresses were removed or added. The firmware has 114545386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 114645386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 114745386Swpaul * state so we know what addresses have been programmed into the NIC at 114845386Swpaul * any given time. 114945386Swpaul */ 115045386Swpaulstatic void ti_setmulti(sc) 115145386Swpaul struct ti_softc *sc; 115245386Swpaul{ 115345386Swpaul struct ifnet *ifp; 115445386Swpaul struct ifmultiaddr *ifma; 115545386Swpaul struct ti_cmd_desc cmd; 115645386Swpaul struct ti_mc_entry *mc; 115745386Swpaul u_int32_t intrs; 115845386Swpaul 115945386Swpaul ifp = &sc->arpcom.ac_if; 116045386Swpaul 116145386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 116245386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 116345386Swpaul return; 116445386Swpaul } else { 116545386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 116645386Swpaul } 116745386Swpaul 116845386Swpaul /* Disable interrupts. */ 116945386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 117045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 117145386Swpaul 117245386Swpaul /* First, zot all the existing filters. */ 117345386Swpaul while (sc->ti_mc_listhead.slh_first != NULL) { 117445386Swpaul mc = sc->ti_mc_listhead.slh_first; 117545386Swpaul ti_del_mcast(sc, &mc->mc_addr); 117645386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 117745386Swpaul free(mc, M_DEVBUF); 117845386Swpaul } 117945386Swpaul 118045386Swpaul /* Now program new ones. */ 118145386Swpaul for (ifma = ifp->if_multiaddrs.lh_first; 118245386Swpaul ifma != NULL; ifma = ifma->ifma_link.le_next) { 118345386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 118445386Swpaul continue; 118545386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 118645386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 118745386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 118845386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 118945386Swpaul ti_add_mcast(sc, &mc->mc_addr); 119045386Swpaul } 119145386Swpaul 119245386Swpaul /* Re-enable interrupts. */ 119345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 119445386Swpaul 119545386Swpaul return; 119645386Swpaul} 119745386Swpaul 119845386Swpaul/* 119945386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 120045386Swpaul * we aren't actually in one. If we detect this condition, we can work 120145386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 120245386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 120345386Swpaul */ 120445386Swpaulstatic int ti_64bitslot_war(sc) 120545386Swpaul struct ti_softc *sc; 120645386Swpaul{ 120745386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 120845386Swpaul CSR_WRITE_4(sc, 0x600, 0); 120945386Swpaul CSR_WRITE_4(sc, 0x604, 0); 121045386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 121145386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 121245386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 121345386Swpaul return(EINVAL); 121445386Swpaul else { 121545386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 121645386Swpaul TI_PCISTATE_32BIT_BUS); 121745386Swpaul return(0); 121845386Swpaul } 121945386Swpaul } 122045386Swpaul } 122145386Swpaul 122245386Swpaul return(0); 122345386Swpaul} 122445386Swpaul 122545386Swpaul/* 122645386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 122745386Swpaul * self-test results. 122845386Swpaul */ 122945386Swpaulstatic int ti_chipinit(sc) 123045386Swpaul struct ti_softc *sc; 123145386Swpaul{ 123245386Swpaul u_int32_t cacheline; 123345386Swpaul u_int32_t pci_writemax = 0; 123445386Swpaul 123545386Swpaul /* Initialize link to down state. */ 123645386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 123745386Swpaul 123845386Swpaul /* Set endianness before we access any non-PCI registers. */ 123945386Swpaul#if BYTE_ORDER == BIG_ENDIAN 124045386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 124145386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 124245386Swpaul#else 124345386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 124445386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 124545386Swpaul#endif 124645386Swpaul 124745386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 124845386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 124945386Swpaul printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 125045386Swpaul return(ENODEV); 125145386Swpaul } 125245386Swpaul 125345386Swpaul /* Halt the CPU. */ 125445386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 125545386Swpaul 125645386Swpaul /* Figure out the hardware revision. */ 125745386Swpaul switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 125845386Swpaul case TI_REV_TIGON_I: 125945386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 126045386Swpaul break; 126145386Swpaul case TI_REV_TIGON_II: 126245386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 126345386Swpaul break; 126445386Swpaul default: 126545386Swpaul printf("ti%d: unsupported chip revision\n", sc->ti_unit); 126645386Swpaul return(ENODEV); 126745386Swpaul } 126845386Swpaul 126945386Swpaul /* Do special setup for Tigon 2. */ 127045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 127145386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 127245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 127345386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 127445386Swpaul } 127545386Swpaul 127645386Swpaul /* Set up the PCI state register. */ 127745386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 127845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 127945386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 128045386Swpaul } 128145386Swpaul 128245386Swpaul /* Clear the read/write max DMA parameters. */ 128345386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 128445386Swpaul TI_PCISTATE_READ_MAXDMA)); 128545386Swpaul 128645386Swpaul /* Get cache line size. */ 128745386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 128845386Swpaul 128945386Swpaul /* 129045386Swpaul * If the system has set enabled the PCI memory write 129145386Swpaul * and invalidate command in the command register, set 129245386Swpaul * the write max parameter accordingly. This is necessary 129345386Swpaul * to use MWI with the Tigon 2. 129445386Swpaul */ 129545386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 129645386Swpaul switch(cacheline) { 129745386Swpaul case 1: 129845386Swpaul case 4: 129945386Swpaul case 8: 130045386Swpaul case 16: 130145386Swpaul case 32: 130245386Swpaul case 64: 130345386Swpaul break; 130445386Swpaul default: 130545386Swpaul /* Disable PCI memory write and invalidate. */ 130645386Swpaul if (bootverbose) 130745386Swpaul printf("ti%d: cache line size %d not " 130845386Swpaul "supported; disabling PCI MWI\n", 130945386Swpaul sc->ti_unit, cacheline); 131045386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 131145386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 131245386Swpaul break; 131345386Swpaul } 131445386Swpaul } 131545386Swpaul 131645386Swpaul#ifdef __brokenalpha__ 131745386Swpaul /* 131845386Swpaul * From the Alteon sample driver: 131945386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 132045386Swpaul * for DMA reads. Our highest limit is 1K bytes. This is a 132145386Swpaul * restriction on some ALPHA platforms with early revision 132245386Swpaul * 21174 PCI chipsets, such as the AlphaPC 164lx 132345386Swpaul */ 132445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 132545386Swpaul#else 132645386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 132745386Swpaul#endif 132845386Swpaul 132945386Swpaul /* This sets the min dma param all the way up (0xff). */ 133045386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 133145386Swpaul 133245386Swpaul /* Configure DMA variables. */ 133345386Swpaul#if BYTE_ORDER == BIG_ENDIAN 133445386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 133545386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 133645386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 133745386Swpaul TI_OPMODE_DONT_FRAG_JUMBO); 133845386Swpaul#else 133945386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 134045386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 134145386Swpaul TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 134245386Swpaul#endif 134345386Swpaul 134445386Swpaul /* 134545386Swpaul * Only allow 1 DMA channel to be active at a time. 134645386Swpaul * I don't think this is a good idea, but without it 134745386Swpaul * the firmware racks up lots of nicDmaReadRingFull 134845386Swpaul * errors. 134945386Swpaul */ 135045386Swpaul#ifndef TI_CSUM_OFFLOAD 135145386Swpaul TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 135245386Swpaul#endif 135345386Swpaul 135445386Swpaul /* Recommended settings from Tigon manual. */ 135545386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 135645386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 135745386Swpaul 135845386Swpaul if (ti_64bitslot_war(sc)) { 135945386Swpaul printf("ti%d: bios thinks we're in a 64 bit slot, " 136045386Swpaul "but we aren't", sc->ti_unit); 136145386Swpaul return(EINVAL); 136245386Swpaul } 136345386Swpaul 136445386Swpaul return(0); 136545386Swpaul} 136645386Swpaul 136745386Swpaul/* 136845386Swpaul * Initialize the general information block and firmware, and 136945386Swpaul * start the CPU(s) running. 137045386Swpaul */ 137145386Swpaulstatic int ti_gibinit(sc) 137245386Swpaul struct ti_softc *sc; 137345386Swpaul{ 137445386Swpaul struct ti_rcb *rcb; 137545386Swpaul int i; 137645386Swpaul struct ifnet *ifp; 137745386Swpaul 137845386Swpaul ifp = &sc->arpcom.ac_if; 137945386Swpaul 138045386Swpaul /* Disable interrupts for now. */ 138145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 138245386Swpaul 138345386Swpaul /* Tell the chip where to find the general information block. */ 138445386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 138545386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 138645386Swpaul 138745386Swpaul /* Load the firmware into SRAM. */ 138845386Swpaul ti_loadfw(sc); 138945386Swpaul 139045386Swpaul /* Set up the contents of the general info and ring control blocks. */ 139145386Swpaul 139245386Swpaul /* Set up the event ring and producer pointer. */ 139345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 139445386Swpaul 139545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 139645386Swpaul rcb->ti_flags = 0; 139745386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 139845386Swpaul vtophys(&sc->ti_ev_prodidx); 139945386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 140045386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 140145386Swpaul sc->ti_ev_saved_considx = 0; 140245386Swpaul 140345386Swpaul /* Set up the command ring and producer mailbox. */ 140445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 140545386Swpaul 140645386Swpaul#ifdef __i386__ 140745386Swpaul sc->ti_rdata->ti_cmd_ring = 140845386Swpaul (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING); 140945386Swpaul#endif 141045386Swpaul#ifdef __alpha__ 141145386Swpaul sc->ti_rdata->ti_cmd_ring = 141245386Swpaul (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 141345386Swpaul#endif 141445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 141545386Swpaul rcb->ti_flags = 0; 141645386Swpaul rcb->ti_max_len = 0; 141745386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 141845386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 141945386Swpaul } 142045386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 142145386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 142245386Swpaul sc->ti_cmd_saved_prodidx = 0; 142345386Swpaul 142445386Swpaul /* 142545386Swpaul * Assign the address of the stats refresh buffer. 142645386Swpaul * We re-use the current stats buffer for this to 142745386Swpaul * conserve memory. 142845386Swpaul */ 142945386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 143045386Swpaul vtophys(&sc->ti_rdata->ti_info.ti_stats); 143145386Swpaul 143245386Swpaul /* Set up the standard receive ring. */ 143345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 143445386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 143545386Swpaul rcb->ti_max_len = TI_FRAMELEN; 143645386Swpaul rcb->ti_flags = 0; 143745386Swpaul#ifdef TI_CSUM_OFFLOAD 143845386Swpaul rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 143945386Swpaul#endif 144045386Swpaul#if NVLAN > 0 144145386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 144245386Swpaul#endif 144345386Swpaul 144445386Swpaul /* Set up the jumbo receive ring. */ 144545386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 144645386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 144745386Swpaul vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 144845386Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 144945386Swpaul rcb->ti_flags = 0; 145045386Swpaul#ifdef TI_CSUM_OFFLOAD 145145386Swpaul rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 145245386Swpaul#endif 145345386Swpaul#if NVLAN > 0 145445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 145545386Swpaul#endif 145645386Swpaul 145745386Swpaul /* 145845386Swpaul * Set up the mini ring. Only activated on the 145945386Swpaul * Tigon 2 but the slot in the config block is 146045386Swpaul * still there on the Tigon 1. 146145386Swpaul */ 146245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 146345386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 146445386Swpaul vtophys(&sc->ti_rdata->ti_rx_mini_ring); 146545386Swpaul rcb->ti_max_len = MHLEN; 146645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 146745386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 146845386Swpaul else 146945386Swpaul rcb->ti_flags = 0; 147045386Swpaul#ifdef TI_CSUM_OFFLOAD 147145386Swpaul rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 147245386Swpaul#endif 147345386Swpaul#if NVLAN > 0 147445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 147545386Swpaul#endif 147645386Swpaul 147745386Swpaul /* 147845386Swpaul * Set up the receive return ring. 147945386Swpaul */ 148045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 148145386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 148245386Swpaul vtophys(&sc->ti_rdata->ti_rx_return_ring); 148345386Swpaul rcb->ti_flags = 0; 148445386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 148545386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 148645386Swpaul vtophys(&sc->ti_return_prodidx); 148745386Swpaul 148845386Swpaul /* 148945386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 149045386Swpaul * of putting the transmit ring in the host's address space and 149145386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 149245386Swpaul * memory and accessing it through the shared memory region. We 149345386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 149445386Swpaul * so we have to revert to the shared memory scheme if we detect 149545386Swpaul * a Tigon 1 chip. 149645386Swpaul */ 149745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 149845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 149945386Swpaul#ifdef __i386__ 150045386Swpaul sc->ti_rdata->ti_tx_ring_nic = 150145386Swpaul (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW); 150245386Swpaul#endif 150345386Swpaul#ifdef __alpha__ 150445386Swpaul sc->ti_rdata->ti_tx_ring_nic = 150545386Swpaul (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 150645386Swpaul#endif 150745386Swpaul } 150845386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 150945386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 151045386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 151145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 151245386Swpaul rcb->ti_flags = 0; 151345386Swpaul else 151445386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 151545386Swpaul#if NVLAN > 0 151645386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 151745386Swpaul#endif 151845386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 151945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 152045386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 152145386Swpaul else 152245386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = 152345386Swpaul vtophys(&sc->ti_rdata->ti_tx_ring); 152445386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 152545386Swpaul vtophys(&sc->ti_tx_considx); 152645386Swpaul 152745386Swpaul /* Set up tuneables */ 152845386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 152945386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 153045386Swpaul (sc->ti_rx_coal_ticks / 10)); 153145386Swpaul else 153245386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 153345386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 153445386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 153545386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 153645386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 153745386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 153845386Swpaul 153945386Swpaul /* Turn interrupts on. */ 154045386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 154145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 154245386Swpaul 154345386Swpaul /* Start CPU. */ 154445386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 154545386Swpaul 154645386Swpaul return(0); 154745386Swpaul} 154845386Swpaul 154945386Swpaul/* 155045386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 155145386Swpaul * against our list and return its name if we find a match. 155245386Swpaul */ 155345386Swpaulstatic const char * 155445386Swpaulti_probe(config_id, device_id) 155545386Swpaul pcici_t config_id; 155645386Swpaul pcidi_t device_id; 155745386Swpaul{ 155845386Swpaul struct ti_type *t; 155945386Swpaul 156045386Swpaul t = ti_devs; 156145386Swpaul 156245386Swpaul while(t->ti_name != NULL) { 156345386Swpaul if ((device_id & 0xFFFF) == t->ti_vid && 156445386Swpaul ((device_id >> 16) & 0xFFFF) == t->ti_did) 156545386Swpaul return(t->ti_name); 156645386Swpaul t++; 156745386Swpaul } 156845386Swpaul 156945386Swpaul return(NULL); 157045386Swpaul} 157145386Swpaul 157245386Swpaul 157345386Swpaulstatic void 157445386Swpaulti_attach(config_id, unit) 157545386Swpaul pcici_t config_id; 157645386Swpaul int unit; 157745386Swpaul{ 157845386Swpaul vm_offset_t pbase, vbase; 157945386Swpaul int s; 158045386Swpaul u_int32_t command; 158145386Swpaul struct ifnet *ifp; 158245386Swpaul struct ti_softc *sc; 158345386Swpaul 158445386Swpaul s = splimp(); 158545386Swpaul 158645386Swpaul /* First, allocate memory for the softc struct. */ 158745386Swpaul sc = malloc(sizeof(struct ti_softc), M_DEVBUF, M_NOWAIT); 158845386Swpaul if (sc == NULL) { 158945386Swpaul printf("ti%d: no memory for softc struct!\n", unit); 159045386Swpaul goto fail; 159145386Swpaul } 159245386Swpaul 159345386Swpaul bzero(sc, sizeof(struct ti_softc)); 159445386Swpaul 159545386Swpaul /* 159645386Swpaul * Map control/status registers. 159745386Swpaul */ 159845386Swpaul command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 159945386Swpaul command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 160045386Swpaul pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 160145386Swpaul command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 160245386Swpaul 160345386Swpaul if (!(command & PCIM_CMD_MEMEN)) { 160445386Swpaul printf("ti%d: failed to enable memory mapping!\n", unit); 160545386Swpaul free(sc, M_DEVBUF); 160645386Swpaul goto fail; 160745386Swpaul } 160845386Swpaul 160945386Swpaul#ifdef __i386__ 161045386Swpaul if (!pci_map_mem(config_id, TI_PCI_LOMEM, &vbase, &pbase)) { 161145386Swpaul printf ("ti%d: couldn't map memory\n", unit); 161245386Swpaul free(sc, M_DEVBUF); 161345386Swpaul goto fail; 161445386Swpaul } 161545386Swpaul 161645386Swpaul sc->ti_bhandle = vbase; 161745386Swpaul sc->ti_btag = I386_BUS_SPACE_MEM; 161845386Swpaul#endif 161945386Swpaul 162045386Swpaul#ifdef __alpha__ 162145386Swpaul if (!(pci_map_bwx(config_id, TI_PCI_LOMEM, &vbase, &pbase) || 162245386Swpaul pci_map_dense(config_id, TI_PCI_LOMEM, &vbase, &pbase))){ 162345386Swpaul printf ("ti%d: couldn't map memory\n", unit); 162445386Swpaul free(sc, M_DEVBUF); 162545386Swpaul goto fail; 162645386Swpaul } 162745386Swpaul 162845386Swpaul sc->ti_bhandle = pbase; 162945386Swpaul sc->ti_vhandle = vbase; 163045386Swpaul sc->ti_btag = ALPHA_BUS_SPACE_MEM; 163145386Swpaul#endif 163245386Swpaul /* Allocate interrupt */ 163345386Swpaul if (!pci_map_int(config_id, ti_intr, sc, &net_imask)) { 163445386Swpaul printf("ti%d: couldn't map interrupt\n", unit); 163545386Swpaul free(sc, M_DEVBUF); 163645386Swpaul goto fail; 163745386Swpaul } 163845386Swpaul 163945386Swpaul sc->ti_unit = unit; 164045386Swpaul 164145386Swpaul if (ti_chipinit(sc)) { 164245386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 164345386Swpaul free(sc, M_DEVBUF); 164445386Swpaul goto fail; 164545386Swpaul } 164645386Swpaul 164745386Swpaul /* Zero out the NIC's on-board SRAM. */ 164845386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 164945386Swpaul 165045386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 165145386Swpaul if (ti_chipinit(sc)) { 165245386Swpaul printf("ti%d: chip initialization failed\n", sc->ti_unit); 165345386Swpaul free(sc, M_DEVBUF); 165445386Swpaul goto fail; 165545386Swpaul } 165645386Swpaul 165745386Swpaul /* 165845386Swpaul * Get station address from the EEPROM. Note: the manual states 165945386Swpaul * that the MAC address is at offset 0x8c, however the data is 166045386Swpaul * stored as two longwords (since that's how it's loaded into 166145386Swpaul * the NIC). This means the MAC address is actually preceeded 166245386Swpaul * by two zero bytes. We need to skip over those. 166345386Swpaul */ 166445386Swpaul if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 166545386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 166645386Swpaul printf("ti%d: failed to read station address\n", unit); 166745386Swpaul free(sc, M_DEVBUF); 166845386Swpaul goto fail; 166945386Swpaul } 167045386Swpaul 167145386Swpaul /* 167245386Swpaul * A Tigon chip was detected. Inform the world. 167345386Swpaul */ 167445386Swpaul printf("ti%d: Ethernet address: %6D\n", unit, 167545386Swpaul sc->arpcom.ac_enaddr, ":"); 167645386Swpaul 167745386Swpaul /* Allocate the general information block and ring buffers. */ 167845386Swpaul sc->ti_rdata_ptr = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 167945386Swpaul M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 168045386Swpaul 168145386Swpaul if (sc->ti_rdata_ptr == NULL) { 168245386Swpaul free(sc, M_DEVBUF); 168345386Swpaul printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 168445386Swpaul goto fail; 168545386Swpaul } 168645386Swpaul 168745386Swpaul sc->ti_rdata = (struct ti_ring_data *)sc->ti_rdata_ptr; 168845386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 168945386Swpaul 169045386Swpaul /* Try to allocate memory for jumbo buffers. */ 169145386Swpaul if (ti_alloc_jumbo_mem(sc)) { 169245386Swpaul printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 169345386Swpaul free(sc->ti_rdata_ptr, M_DEVBUF); 169445386Swpaul free(sc, M_DEVBUF); 169545386Swpaul goto fail; 169645386Swpaul } 169745386Swpaul 169845386Swpaul /* Set default tuneable values. */ 169945386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 170045386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 170145386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 170245386Swpaul sc->ti_rx_max_coal_bds = 64; 170345386Swpaul sc->ti_tx_max_coal_bds = 128; 170445386Swpaul sc->ti_tx_buf_ratio = 21; 170545386Swpaul 170645386Swpaul /* Set up ifnet structure */ 170745386Swpaul ifp = &sc->arpcom.ac_if; 170845386Swpaul ifp->if_softc = sc; 170945386Swpaul ifp->if_unit = sc->ti_unit; 171045386Swpaul ifp->if_name = "ti"; 171145386Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 171245386Swpaul ifp->if_ioctl = ti_ioctl; 171345386Swpaul ifp->if_output = ether_output; 171445386Swpaul ifp->if_start = ti_start; 171545386Swpaul ifp->if_watchdog = ti_watchdog; 171645386Swpaul ifp->if_init = ti_init; 171745386Swpaul ifp->if_mtu = ETHERMTU; 171845386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 171945386Swpaul 172045386Swpaul /* Set up ifmedia support. */ 172145386Swpaul ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 172245386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 172345386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 172445386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 172545386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 172645386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 172745386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 172845386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 172945386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 173045386Swpaul 173145386Swpaul /* 173245386Swpaul * Call MI attach routines. 173345386Swpaul */ 173445386Swpaul if_attach(ifp); 173545386Swpaul ether_ifattach(ifp); 173645386Swpaul 173745386Swpaul#if NBPFILTER > 0 173845386Swpaul bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 173945386Swpaul#endif 174045386Swpaul 174145386Swpaul at_shutdown(ti_shutdown, sc, SHUTDOWN_POST_SYNC); 174245386Swpaul 174345386Swpaulfail: 174445386Swpaul splx(s); 174545386Swpaul 174645386Swpaul return; 174745386Swpaul} 174845386Swpaul 174945386Swpaul/* 175045386Swpaul * Frame reception handling. This is called if there's a frame 175145386Swpaul * on the receive return list. 175245386Swpaul * 175345386Swpaul * Note: we have to be able to handle three possibilities here: 175445386Swpaul * 1) the frame is from the mini receive ring (can only happen) 175545386Swpaul * on Tigon 2 boards) 175645386Swpaul * 2) the frame is from the jumbo recieve ring 175745386Swpaul * 3) the frame is from the standard receive ring 175845386Swpaul */ 175945386Swpaul 176045386Swpaulstatic void ti_rxeof(sc) 176145386Swpaul struct ti_softc *sc; 176245386Swpaul{ 176345386Swpaul struct ifnet *ifp; 176445386Swpaul 176545386Swpaul ifp = &sc->arpcom.ac_if; 176645386Swpaul 176745386Swpaul while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 176845386Swpaul struct ti_rx_desc *cur_rx; 176945386Swpaul u_int32_t rxidx; 177045386Swpaul struct ether_header *eh; 177145386Swpaul struct mbuf *m = NULL; 177245386Swpaul#if NVLAN > 0 177345386Swpaul u_int16_t vlan_tag = 0; 177445386Swpaul int have_tag = 0; 177545386Swpaul#endif 177645386Swpaul#ifdef TI_CSUM_OFFLOAD 177745386Swpaul struct ip *ip; 177845386Swpaul#endif 177945386Swpaul 178045386Swpaul cur_rx = 178145386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 178245386Swpaul rxidx = cur_rx->ti_idx; 178345386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 178445386Swpaul 178545386Swpaul#if NVLAN > 0 178645386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 178745386Swpaul have_tag = 1; 178845386Swpaul vlan_tag = cur_rx->ti_vlan_tag; 178945386Swpaul } 179045386Swpaul#endif 179145386Swpaul 179245386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 179345386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 179445386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 179545386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 179645386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 179745386Swpaul ifp->if_ierrors++; 179845386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 179945386Swpaul TI_INC(sc->ti_jumbo_old, TI_JUMBO_RX_RING_CNT); 180045386Swpaul continue; 180145386Swpaul } 180245386Swpaul sc->ti_jumbo_cnt++; 180345386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 180445386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 180545386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 180645386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 180745386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 180845386Swpaul ifp->if_ierrors++; 180945386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 181045386Swpaul TI_INC(sc->ti_mini_old, TI_MINI_RX_RING_CNT); 181145386Swpaul continue; 181245386Swpaul } 181345386Swpaul sc->ti_mini_cnt++; 181445386Swpaul } else { 181545386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 181645386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 181745386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 181845386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 181945386Swpaul ifp->if_ierrors++; 182045386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 182145386Swpaul TI_INC(sc->ti_std_old, TI_STD_RX_RING_CNT); 182245386Swpaul continue; 182345386Swpaul } 182445386Swpaul sc->ti_std_cnt++; 182545386Swpaul } 182645386Swpaul 182745386Swpaul m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 182845386Swpaul ifp->if_ipackets++; 182945386Swpaul eh = mtod(m, struct ether_header *); 183045386Swpaul m->m_pkthdr.rcvif = ifp; 183145386Swpaul 183245386Swpaul#if NBPFILTER > 0 183345386Swpaul /* 183445386Swpaul * Handle BPF listeners. Let the BPF user see the packet, but 183545386Swpaul * don't pass it up to the ether_input() layer unless it's 183645386Swpaul * a broadcast packet, multicast packet, matches our ethernet 183745386Swpaul * address or the interface is in promiscuous mode. 183845386Swpaul */ 183945386Swpaul if (ifp->if_bpf) { 184045386Swpaul bpf_mtap(ifp, m); 184145386Swpaul if (ifp->if_flags & IFF_PROMISC && 184245386Swpaul (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 184345386Swpaul ETHER_ADDR_LEN) && 184445386Swpaul (eh->ether_dhost[0] & 1) == 0)) { 184545386Swpaul m_freem(m); 184645386Swpaul continue; 184745386Swpaul } 184845386Swpaul } 184945386Swpaul#endif 185045386Swpaul 185145386Swpaul /* Remove header from mbuf and pass it on. */ 185245386Swpaul m_adj(m, sizeof(struct ether_header)); 185345386Swpaul 185445386Swpaul#ifdef TI_CSUM_OFFLOAD 185545386Swpaul ip = mtod(m, struct ip *); 185645386Swpaul if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 185745391Swpaul !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 185845386Swpaul m->m_flags |= M_HWCKSUM; 185945386Swpaul#endif 186045386Swpaul 186145386Swpaul#if NVLAN > 0 186245386Swpaul /* 186345386Swpaul * If we received a packet with a vlan tag, pass it 186445386Swpaul * to vlan_input() instead of ether_input(). 186545386Swpaul */ 186645386Swpaul if (have_tag) { 186745386Swpaul vlan_input_tag(eh, m, vlan_tag); 186845386Swpaul have_tag = vlan_tag = 0; 186945386Swpaul continue; 187045386Swpaul } 187145386Swpaul#endif 187245386Swpaul ether_input(ifp, eh, m); 187345386Swpaul } 187445386Swpaul 187545386Swpaul /* Only necessary on the Tigon 1. */ 187645386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 187745386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 187845386Swpaul sc->ti_rx_saved_considx); 187945386Swpaul 188045386Swpaul ti_refill_rx_rings(sc); 188145386Swpaul 188245386Swpaul return; 188345386Swpaul} 188445386Swpaul 188545386Swpaulstatic void ti_txeof(sc) 188645386Swpaul struct ti_softc *sc; 188745386Swpaul{ 188845386Swpaul struct ti_tx_desc *cur_tx = NULL; 188945386Swpaul struct ifnet *ifp; 189045386Swpaul 189145386Swpaul ifp = &sc->arpcom.ac_if; 189245386Swpaul 189345386Swpaul /* 189445386Swpaul * Go through our tx ring and free mbufs for those 189545386Swpaul * frames that have been sent. 189645386Swpaul */ 189745386Swpaul while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 189845386Swpaul u_int32_t idx = 0; 189945386Swpaul 190045386Swpaul idx = sc->ti_tx_saved_considx; 190145386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 190245386Swpaul if (idx > 383) 190345386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 190445386Swpaul TI_TX_RING_BASE + 6144); 190545386Swpaul else if (idx > 255) 190645386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 190745386Swpaul TI_TX_RING_BASE + 4096); 190845386Swpaul else if (idx > 127) 190945386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191045386Swpaul TI_TX_RING_BASE + 2048); 191145386Swpaul else 191245386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 191345386Swpaul TI_TX_RING_BASE); 191445386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 191545386Swpaul } else 191645386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 191745386Swpaul if (cur_tx->ti_flags & TI_BDFLAG_END) 191845386Swpaul ifp->if_opackets++; 191945386Swpaul if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 192045386Swpaul m_freem(sc->ti_cdata.ti_tx_chain[idx]); 192145386Swpaul sc->ti_cdata.ti_tx_chain[idx] = NULL; 192245386Swpaul } 192345386Swpaul TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 192445386Swpaul ifp->if_timer = 0; 192545386Swpaul } 192645386Swpaul 192745386Swpaul if (cur_tx != NULL) 192845386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 192945386Swpaul 193045386Swpaul return; 193145386Swpaul} 193245386Swpaul 193345386Swpaulstatic void ti_intr(xsc) 193445386Swpaul void *xsc; 193545386Swpaul{ 193645386Swpaul struct ti_softc *sc; 193745386Swpaul struct ifnet *ifp; 193845386Swpaul 193945386Swpaul sc = xsc; 194045386Swpaul ifp = &sc->arpcom.ac_if; 194145386Swpaul 194245386Swpaul#ifdef notdef 194345386Swpaul /* Avoid this for now -- checking this register is expensive. */ 194445386Swpaul /* Make sure this is really our interrupt. */ 194545386Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 194645386Swpaul return; 194745386Swpaul#endif 194845386Swpaul 194945386Swpaul /* Ack interrupt and stop others from occuring. */ 195045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 195145386Swpaul 195245386Swpaul if (ifp->if_flags & IFF_RUNNING) { 195345386Swpaul /* Check RX return ring producer/consumer */ 195445386Swpaul ti_rxeof(sc); 195545386Swpaul 195645386Swpaul /* Check TX ring producer/consumer */ 195745386Swpaul ti_txeof(sc); 195845386Swpaul } 195945386Swpaul 196045386Swpaul ti_handle_events(sc); 196145386Swpaul 196245386Swpaul /* Re-enable interrupts. */ 196345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 196445386Swpaul 196545386Swpaul if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 196645386Swpaul ti_start(ifp); 196745386Swpaul 196845386Swpaul return; 196945386Swpaul} 197045386Swpaul 197145386Swpaulstatic void ti_stats_update(sc) 197245386Swpaul struct ti_softc *sc; 197345386Swpaul{ 197445386Swpaul struct ifnet *ifp; 197545386Swpaul 197645386Swpaul ifp = &sc->arpcom.ac_if; 197745386Swpaul 197845386Swpaul ifp->if_collisions += 197945386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 198045386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 198145386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 198245386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 198345386Swpaul ifp->if_collisions; 198445386Swpaul 198545386Swpaul return; 198645386Swpaul} 198745386Swpaul 198845386Swpaul/* 198945386Swpaul * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 199045386Swpaul * pointers to descriptors. 199145386Swpaul */ 199245386Swpaulstatic int ti_encap(sc, m_head, txidx) 199345386Swpaul struct ti_softc *sc; 199445386Swpaul struct mbuf *m_head; 199545386Swpaul u_int32_t *txidx; 199645386Swpaul{ 199745386Swpaul struct ti_tx_desc *f = NULL; 199845386Swpaul struct mbuf *m; 199945386Swpaul u_int32_t frag, cur; 200045386Swpaul#if NVLAN > 0 200145386Swpaul struct ifvlan *ifv = NULL; 200245386Swpaul 200345386Swpaul if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 200445386Swpaul m_head->m_pkthdr.rcvif != NULL && 200545386Swpaul m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 200645386Swpaul ifv = m_head->m_pkthdr.rcvif->if_softc; 200745386Swpaul#endif 200845386Swpaul 200945386Swpaul m = m_head; 201045386Swpaul cur = frag = *txidx; 201145386Swpaul 201245386Swpaul /* 201345386Swpaul * Start packing the mbufs in this chain into 201445386Swpaul * the fragment pointers. Stop when we run out 201545386Swpaul * of fragments or hit the end of the mbuf chain. 201645386Swpaul */ 201745386Swpaul for (m = m_head; m != NULL; m = m->m_next) { 201845386Swpaul if (m->m_len != 0) { 201945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 202045386Swpaul if (frag > 383) 202145386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 202245386Swpaul TI_TX_RING_BASE + 6144); 202345386Swpaul else if (frag > 255) 202445386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 202545386Swpaul TI_TX_RING_BASE + 4096); 202645386Swpaul else if (frag > 127) 202745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 202845386Swpaul TI_TX_RING_BASE + 2048); 202945386Swpaul else 203045386Swpaul CSR_WRITE_4(sc, TI_WINBASE, 203145386Swpaul TI_TX_RING_BASE); 203245386Swpaul f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 203345386Swpaul } else 203445386Swpaul f = &sc->ti_rdata->ti_tx_ring[frag]; 203545386Swpaul if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 203645386Swpaul break; 203745386Swpaul TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 203845386Swpaul f->ti_len = m->m_len; 203945386Swpaul f->ti_flags = 0; 204045386Swpaul#if NVLAN > 0 204145386Swpaul if (ifv != NULL) { 204245386Swpaul f->ti_flags |= TI_BDFLAG_VLAN_TAG; 204345386Swpaul f->ti_vlan_tag = ifv->ifv_tag; 204445386Swpaul } else { 204545386Swpaul f->ti_vlan_tag = 0; 204645386Swpaul } 204745386Swpaul#endif 204845386Swpaul cur = frag; 204945386Swpaul TI_INC(frag, TI_TX_RING_CNT); 205045386Swpaul } 205145386Swpaul } 205245386Swpaul 205345386Swpaul if (m != NULL) 205445386Swpaul return(ENOBUFS); 205545386Swpaul 205646177Swpaul if (frag == sc->ti_tx_saved_considx) 205746177Swpaul return(ENOBUFS); 205846177Swpaul 205945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 206045386Swpaul sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 206145386Swpaul TI_BDFLAG_END; 206245386Swpaul else 206345386Swpaul sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 206445386Swpaul sc->ti_cdata.ti_tx_chain[*txidx] = m_head; 206545386Swpaul 206645386Swpaul *txidx = frag; 206745386Swpaul 206845386Swpaul return(0); 206945386Swpaul} 207045386Swpaul 207145386Swpaul/* 207245386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 207345386Swpaul * to the mbuf data regions directly in the transmit descriptors. 207445386Swpaul */ 207545386Swpaulstatic void ti_start(ifp) 207645386Swpaul struct ifnet *ifp; 207745386Swpaul{ 207845386Swpaul struct ti_softc *sc; 207945386Swpaul struct mbuf *m_head = NULL; 208045386Swpaul u_int32_t prodidx = 0; 208145386Swpaul 208245386Swpaul sc = ifp->if_softc; 208345386Swpaul 208445386Swpaul prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 208545386Swpaul 208645386Swpaul while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 208745386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 208845386Swpaul if (m_head == NULL) 208945386Swpaul break; 209045386Swpaul 209145386Swpaul /* 209245386Swpaul * Pack the data into the transmit ring. If we 209345386Swpaul * don't have room, set the OACTIVE flag and wait 209445386Swpaul * for the NIC to drain the ring. 209545386Swpaul */ 209645386Swpaul if (ti_encap(sc, m_head, &prodidx)) { 209745386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 209845386Swpaul ifp->if_flags |= IFF_OACTIVE; 209945386Swpaul break; 210045386Swpaul } 210145386Swpaul 210245386Swpaul /* 210345386Swpaul * If there's a BPF listener, bounce a copy of this frame 210445386Swpaul * to him. 210545386Swpaul */ 210645386Swpaul#if NBPFILTER > 0 210745386Swpaul if (ifp->if_bpf) 210845386Swpaul bpf_mtap(ifp, m_head); 210945386Swpaul#endif 211045386Swpaul } 211145386Swpaul 211245386Swpaul /* Transmit */ 211345386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 211445386Swpaul 211545386Swpaul /* 211645386Swpaul * Set a timeout in case the chip goes out to lunch. 211745386Swpaul */ 211845386Swpaul ifp->if_timer = 5; 211945386Swpaul 212045386Swpaul return; 212145386Swpaul} 212245386Swpaul 212345386Swpaulstatic void ti_init(xsc) 212445386Swpaul void *xsc; 212545386Swpaul{ 212645386Swpaul struct ti_softc *sc = xsc; 212745386Swpaul int s; 212845386Swpaul 212945386Swpaul s = splimp(); 213045386Swpaul 213145386Swpaul /* Cancel pending I/O and flush buffers. */ 213245386Swpaul ti_stop(sc); 213345386Swpaul 213445386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 213545386Swpaul if (ti_gibinit(sc)) { 213645386Swpaul printf("ti%d: initialization failure\n", sc->ti_unit); 213745386Swpaul splx(s); 213845386Swpaul return; 213945386Swpaul } 214045386Swpaul 214145386Swpaul splx(s); 214245386Swpaul 214345386Swpaul return; 214445386Swpaul} 214545386Swpaul 214645386Swpaulstatic void ti_init2(sc) 214745386Swpaul struct ti_softc *sc; 214845386Swpaul{ 214945386Swpaul struct ti_cmd_desc cmd; 215045386Swpaul struct ifnet *ifp; 215145386Swpaul u_int16_t *m; 215245386Swpaul struct ifmedia *ifm; 215345386Swpaul int tmp; 215445386Swpaul 215545386Swpaul ifp = &sc->arpcom.ac_if; 215645386Swpaul 215745386Swpaul /* Specify MTU and interface index. */ 215845386Swpaul CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 215945386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 216045386Swpaul ETHER_HDR_LEN + ETHER_CRC_LEN); 216145386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 216245386Swpaul 216345386Swpaul /* Load our MAC address. */ 216445386Swpaul m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 216545386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 216645386Swpaul CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 216745386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 216845386Swpaul 216945386Swpaul /* Enable or disable promiscuous mode as needed. */ 217045386Swpaul if (ifp->if_flags & IFF_PROMISC) { 217145386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 217245386Swpaul } else { 217345386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 217445386Swpaul } 217545386Swpaul 217645386Swpaul /* Program multicast filter. */ 217745386Swpaul ti_setmulti(sc); 217845386Swpaul 217945386Swpaul /* 218045386Swpaul * If this is a Tigon 1, we should tell the 218145386Swpaul * firmware to use software packet filtering. 218245386Swpaul */ 218345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 218445386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 218545386Swpaul } 218645386Swpaul 218745386Swpaul /* Init RX ring. */ 218845386Swpaul ti_init_rx_ring_std(sc); 218945386Swpaul 219045386Swpaul /* Init jumbo RX ring. */ 219145386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 219245386Swpaul ti_init_rx_ring_jumbo(sc); 219345386Swpaul 219445386Swpaul /* 219545386Swpaul * If this is a Tigon 2, we can also configure the 219645386Swpaul * mini ring. 219745386Swpaul */ 219845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 219945386Swpaul ti_init_rx_ring_mini(sc); 220045386Swpaul 220145386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 220245386Swpaul sc->ti_rx_saved_considx = 0; 220345386Swpaul 220445386Swpaul /* Init TX ring. */ 220545386Swpaul ti_init_tx_ring(sc); 220645386Swpaul 220745386Swpaul /* Tell firmware we're alive. */ 220845386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 220945386Swpaul 221045386Swpaul /* Enable host interrupts. */ 221145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 221245386Swpaul 221345386Swpaul ifp->if_flags |= IFF_RUNNING; 221445386Swpaul ifp->if_flags &= ~IFF_OACTIVE; 221545386Swpaul 221645386Swpaul /* 221745386Swpaul * Make sure to set media properly. We have to do this 221845386Swpaul * here since we have to issue commands in order to set 221945386Swpaul * the link negotiation and we can't issue commands until 222045386Swpaul * the firmware is running. 222145386Swpaul */ 222245386Swpaul ifm = &sc->ifmedia; 222345386Swpaul tmp = ifm->ifm_media; 222445386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 222545386Swpaul ti_ifmedia_upd(ifp); 222645386Swpaul ifm->ifm_media = tmp; 222745386Swpaul 222845386Swpaul return; 222945386Swpaul} 223045386Swpaul 223145386Swpaul/* 223245386Swpaul * Set media options. 223345386Swpaul */ 223445386Swpaulstatic int ti_ifmedia_upd(ifp) 223545386Swpaul struct ifnet *ifp; 223645386Swpaul{ 223745386Swpaul struct ti_softc *sc; 223845386Swpaul struct ifmedia *ifm; 223945386Swpaul struct ti_cmd_desc cmd; 224045386Swpaul 224145386Swpaul sc = ifp->if_softc; 224245386Swpaul ifm = &sc->ifmedia; 224345386Swpaul 224445386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 224545386Swpaul return(EINVAL); 224645386Swpaul 224745386Swpaul switch(IFM_SUBTYPE(ifm->ifm_media)) { 224845386Swpaul case IFM_AUTO: 224945386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 225045386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 225145386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 225245386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 225345386Swpaul TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 225445386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 225545386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 225645386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 225745386Swpaul break; 225845386Swpaul case IFM_1000_SX: 225945386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 226045386Swpaul TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 226145386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 226245386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 226345386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 226445386Swpaul break; 226545386Swpaul case IFM_100_FX: 226645386Swpaul case IFM_10_FL: 226745386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 226845386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 226945386Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 227045386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 227145386Swpaul } else { 227245386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 227345386Swpaul } 227445386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 227545386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 227645386Swpaul } else { 227745386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 227845386Swpaul } 227945386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 228045386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 228145386Swpaul break; 228245386Swpaul } 228345386Swpaul 228445386Swpaul return(0); 228545386Swpaul} 228645386Swpaul 228745386Swpaul/* 228845386Swpaul * Report current media status. 228945386Swpaul */ 229045386Swpaulstatic void ti_ifmedia_sts(ifp, ifmr) 229145386Swpaul struct ifnet *ifp; 229245386Swpaul struct ifmediareq *ifmr; 229345386Swpaul{ 229445386Swpaul struct ti_softc *sc; 229545386Swpaul 229645386Swpaul sc = ifp->if_softc; 229745386Swpaul 229845386Swpaul ifmr->ifm_status = IFM_AVALID; 229945386Swpaul ifmr->ifm_active = IFM_ETHER; 230045386Swpaul 230145386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 230245386Swpaul return; 230345386Swpaul 230445386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 230545386Swpaul 230645386Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 230745386Swpaul ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 230845386Swpaul else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 230945386Swpaul u_int32_t media; 231045386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 231145386Swpaul if (media & TI_LNK_100MB) 231245386Swpaul ifmr->ifm_active |= IFM_100_FX; 231345386Swpaul if (media & TI_LNK_10MB) 231445386Swpaul ifmr->ifm_active |= IFM_10_FL; 231545386Swpaul if (media & TI_LNK_FULL_DUPLEX) 231645386Swpaul ifmr->ifm_active |= IFM_FDX; 231745386Swpaul if (media & TI_LNK_HALF_DUPLEX) 231845386Swpaul ifmr->ifm_active |= IFM_HDX; 231945386Swpaul } 232045386Swpaul 232145386Swpaul return; 232245386Swpaul} 232345386Swpaul 232445386Swpaulstatic int ti_ioctl(ifp, command, data) 232545386Swpaul struct ifnet *ifp; 232645386Swpaul u_long command; 232745386Swpaul caddr_t data; 232845386Swpaul{ 232945386Swpaul struct ti_softc *sc = ifp->if_softc; 233045386Swpaul struct ifreq *ifr = (struct ifreq *) data; 233145386Swpaul int s, error = 0; 233245386Swpaul struct ti_cmd_desc cmd; 233345386Swpaul 233445386Swpaul s = splimp(); 233545386Swpaul 233645386Swpaul switch(command) { 233745386Swpaul case SIOCSIFADDR: 233845386Swpaul case SIOCGIFADDR: 233945386Swpaul error = ether_ioctl(ifp, command, data); 234045386Swpaul break; 234145386Swpaul case SIOCSIFMTU: 234245386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 234345386Swpaul error = EINVAL; 234445386Swpaul else { 234545386Swpaul ifp->if_mtu = ifr->ifr_mtu; 234645386Swpaul ti_init(sc); 234745386Swpaul } 234845386Swpaul break; 234945386Swpaul case SIOCSIFFLAGS: 235045386Swpaul if (ifp->if_flags & IFF_UP) { 235145386Swpaul /* 235245386Swpaul * If only the state of the PROMISC flag changed, 235345386Swpaul * then just use the 'set promisc mode' command 235445386Swpaul * instead of reinitializing the entire NIC. Doing 235545386Swpaul * a full re-init means reloading the firmware and 235645386Swpaul * waiting for it to start up, which may take a 235745386Swpaul * second or two. 235845386Swpaul */ 235945386Swpaul if (ifp->if_flags & IFF_RUNNING && 236045386Swpaul ifp->if_flags & IFF_PROMISC && 236145386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 236245386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 236345386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 236445386Swpaul } else if (ifp->if_flags & IFF_RUNNING && 236545386Swpaul !(ifp->if_flags & IFF_PROMISC) && 236645386Swpaul sc->ti_if_flags & IFF_PROMISC) { 236745386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 236845386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 236945386Swpaul } else 237045386Swpaul ti_init(sc); 237145386Swpaul } else { 237245386Swpaul if (ifp->if_flags & IFF_RUNNING) { 237345386Swpaul ti_stop(sc); 237445386Swpaul } 237545386Swpaul } 237645386Swpaul sc->ti_if_flags = ifp->if_flags; 237745386Swpaul error = 0; 237845386Swpaul break; 237945386Swpaul case SIOCADDMULTI: 238045386Swpaul case SIOCDELMULTI: 238145386Swpaul if (ifp->if_flags & IFF_RUNNING) { 238245386Swpaul ti_setmulti(sc); 238345386Swpaul error = 0; 238445386Swpaul } 238545386Swpaul break; 238645386Swpaul case SIOCSIFMEDIA: 238745386Swpaul case SIOCGIFMEDIA: 238845386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 238945386Swpaul break; 239045386Swpaul default: 239145386Swpaul error = EINVAL; 239245386Swpaul break; 239345386Swpaul } 239445386Swpaul 239545386Swpaul (void)splx(s); 239645386Swpaul 239745386Swpaul return(error); 239845386Swpaul} 239945386Swpaul 240045386Swpaulstatic void ti_watchdog(ifp) 240145386Swpaul struct ifnet *ifp; 240245386Swpaul{ 240345386Swpaul struct ti_softc *sc; 240445386Swpaul 240545386Swpaul sc = ifp->if_softc; 240645386Swpaul 240745386Swpaul printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 240845386Swpaul ti_stop(sc); 240945386Swpaul ti_init(sc); 241045386Swpaul 241145386Swpaul ifp->if_oerrors++; 241245386Swpaul 241345386Swpaul return; 241445386Swpaul} 241545386Swpaul 241645386Swpaul/* 241745386Swpaul * Stop the adapter and free any mbufs allocated to the 241845386Swpaul * RX and TX lists. 241945386Swpaul */ 242045386Swpaulstatic void ti_stop(sc) 242145386Swpaul struct ti_softc *sc; 242245386Swpaul{ 242345386Swpaul struct ifnet *ifp; 242445386Swpaul struct ti_cmd_desc cmd; 242545386Swpaul 242645386Swpaul ifp = &sc->arpcom.ac_if; 242745386Swpaul 242845386Swpaul /* Disable host interrupts. */ 242945386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 243045386Swpaul /* 243145386Swpaul * Tell firmware we're shutting down. 243245386Swpaul */ 243345386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 243445386Swpaul 243545386Swpaul /* Halt and reinitialize. */ 243645386Swpaul ti_chipinit(sc); 243745386Swpaul ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 243845386Swpaul ti_chipinit(sc); 243945386Swpaul 244045386Swpaul /* Free the RX lists. */ 244145386Swpaul ti_free_rx_ring_std(sc); 244245386Swpaul 244345386Swpaul /* Free jumbo RX list. */ 244445386Swpaul ti_free_rx_ring_jumbo(sc); 244545386Swpaul 244645386Swpaul /* Free mini RX list. */ 244745386Swpaul ti_free_rx_ring_mini(sc); 244845386Swpaul 244945386Swpaul /* Free TX buffers. */ 245045386Swpaul ti_free_tx_ring(sc); 245145386Swpaul 245245386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 245345386Swpaul sc->ti_return_prodidx.ti_idx = 0; 245445386Swpaul sc->ti_tx_considx.ti_idx = 0; 245545386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 245645386Swpaul 245745386Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 245845386Swpaul 245945386Swpaul return; 246045386Swpaul} 246145386Swpaul 246245386Swpaul/* 246345386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 246445386Swpaul * get confused by errant DMAs when rebooting. 246545386Swpaul */ 246645386Swpaulstatic void ti_shutdown(howto, xsc) 246745386Swpaul int howto; 246845386Swpaul void *xsc; 246945386Swpaul{ 247045386Swpaul struct ti_softc *sc; 247145386Swpaul 247245386Swpaul sc = xsc; 247345386Swpaul 247445386Swpaul ti_chipinit(sc); 247545386Swpaul 247645386Swpaul return; 247745386Swpaul} 247845386Swpaul 247945386Swpaulstatic struct pci_device ti_device = { 248045386Swpaul "ti", 248145386Swpaul ti_probe, 248245386Swpaul ti_attach, 248345386Swpaul &ti_count, 248445386Swpaul NULL 248545386Swpaul}; 248646024Speter#ifdef COMPAT_PCI_DRIVER 248746024SpeterCOMPAT_PCI_DRIVER(ti, ti_device); 248846024Speter#else 248945386SwpaulDATA_SET(pcidevice_set, ti_device); 249046024Speter#endif /* COMPAT_PCI_DRIVER */ 2491