if_ti.c revision 45386
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_ti.c,v 1.106 1999/04/06 15:55:01 wpaul Exp $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "bpfilter.h" 82#include "vlan.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/socket.h> 91#include <sys/queue.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#if NBPFILTER > 0 100#include <net/bpf.h> 101#endif 102 103#if NVLAN > 0 104#include <net/if_types.h> 105#include <net/if_vlan_var.h> 106#endif 107 108#include <netinet/in_systm.h> 109#include <netinet/in.h> 110#include <netinet/ip.h> 111 112#include <vm/vm.h> /* for vtophys */ 113#include <vm/pmap.h> /* for vtophys */ 114#include <machine/clock.h> /* for DELAY */ 115#include <machine/bus_memio.h> 116#include <machine/bus.h> 117 118#include <pci/pcireg.h> 119#include <pci/pcivar.h> 120 121#include <pci/if_tireg.h> 122#include <pci/ti_fw.h> 123#include <pci/ti_fw2.h> 124 125#ifdef M_HWCKSUM 126/*#define TI_CSUM_OFFLOAD*/ 127#endif 128 129#if !defined(lint) 130static const char rcsid[] = 131 "$Id: if_ti.c,v 1.106 1999/04/06 15:55:01 wpaul Exp $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137 138static struct ti_type ti_devs[] = { 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 140 "Alteon AceNIC Gigabit Ethernet" }, 141 { TC_VENDORID, TC_DEVICEID_3C985, 142 "3Com 3c985-SX Gigabit Ethernet" }, 143 { NG_VENDORID, NG_DEVICEID_GA620, 144 "Netgear GA620 Gigabit Ethernet" }, 145 { SGI_VENDORID, SGI_DEVICEID_TIGON, 146 "Silicon Graphics Gigabit Ethernet" }, 147 { 0, 0, NULL } 148}; 149 150static unsigned long ti_count; 151 152static const char *ti_probe __P((pcici_t, pcidi_t)); 153static void ti_attach __P((pcici_t, int)); 154static void ti_txeof __P((struct ti_softc *)); 155static void ti_rxeof __P((struct ti_softc *)); 156 157static void ti_stats_update __P((struct ti_softc *)); 158static int ti_encap __P((struct ti_softc *, struct mbuf *, 159 u_int32_t *)); 160 161static void ti_intr __P((void *)); 162static void ti_start __P((struct ifnet *)); 163static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 164static void ti_init __P((void *)); 165static void ti_init2 __P((struct ti_softc *)); 166static void ti_stop __P((struct ti_softc *)); 167static void ti_watchdog __P((struct ifnet *)); 168static void ti_shutdown __P((int, void *)); 169static int ti_ifmedia_upd __P((struct ifnet *)); 170static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 171 172static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 173static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 174 int, u_int8_t *)); 175static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 176 177static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 178static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 179static void ti_setmulti __P((struct ti_softc *)); 180 181static void ti_mem __P((struct ti_softc *, u_int32_t, 182 u_int32_t, caddr_t)); 183static void ti_loadfw __P((struct ti_softc *)); 184static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 185static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 186 caddr_t, int)); 187static void ti_handle_events __P((struct ti_softc *)); 188static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 189static void *ti_jalloc __P((struct ti_softc *)); 190static void ti_jfree __P((caddr_t, u_int)); 191static void ti_jref __P((caddr_t, u_int)); 192static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 193static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 194static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 195static int ti_init_rx_ring_std __P((struct ti_softc *)); 196static void ti_free_rx_ring_std __P((struct ti_softc *)); 197static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 198static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 199static int ti_init_rx_ring_mini __P((struct ti_softc *)); 200static void ti_free_rx_ring_mini __P((struct ti_softc *)); 201static void ti_refill_rx_rings __P((struct ti_softc *)); 202static void ti_free_tx_ring __P((struct ti_softc *)); 203static int ti_init_tx_ring __P((struct ti_softc *)); 204 205static int ti_64bitslot_war __P((struct ti_softc *)); 206static int ti_chipinit __P((struct ti_softc *)); 207static int ti_gibinit __P((struct ti_softc *)); 208 209/* 210 * Send an instruction or address to the EEPROM, check for ACK. 211 */ 212static u_int32_t ti_eeprom_putbyte(sc, byte) 213 struct ti_softc *sc; 214 int byte; 215{ 216 register int i, ack = 0; 217 218 /* 219 * Make sure we're in TX mode. 220 */ 221 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 222 223 /* 224 * Feed in each bit and stobe the clock. 225 */ 226 for (i = 0x80; i; i >>= 1) { 227 if (byte & i) { 228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 229 } else { 230 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 231 } 232 DELAY(1); 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 234 DELAY(1); 235 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 236 } 237 238 /* 239 * Turn off TX mode. 240 */ 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 242 243 /* 244 * Check for ack. 245 */ 246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 249 250 return(ack); 251} 252 253/* 254 * Read a byte of data stored in the EEPROM at address 'addr.' 255 * We have to send two address bytes since the EEPROM can hold 256 * more than 256 bytes of data. 257 */ 258static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 259 struct ti_softc *sc; 260 int addr; 261 u_int8_t *dest; 262{ 263 register int i; 264 u_int8_t byte = 0; 265 266 EEPROM_START; 267 268 /* 269 * Send write control code to EEPROM. 270 */ 271 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 272 printf("ti%d: failed to send write command, status: %x\n", 273 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 274 return(1); 275 } 276 277 /* 278 * Send first byte of address of byte we want to read. 279 */ 280 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 281 printf("ti%d: failed to send address, status: %x\n", 282 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 283 return(1); 284 } 285 /* 286 * Send second byte address of byte we want to read. 287 */ 288 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 289 printf("ti%d: failed to send address, status: %x\n", 290 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 291 return(1); 292 } 293 294 EEPROM_STOP; 295 EEPROM_START; 296 /* 297 * Send read control code to EEPROM. 298 */ 299 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 300 printf("ti%d: failed to send read command, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 305 /* 306 * Start reading bits from EEPROM. 307 */ 308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 309 for (i = 0x80; i; i >>= 1) { 310 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 311 DELAY(1); 312 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 313 byte |= i; 314 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 315 DELAY(1); 316 } 317 318 EEPROM_STOP; 319 320 /* 321 * No ACK generated for read, so just return byte. 322 */ 323 324 *dest = byte; 325 326 return(0); 327} 328 329/* 330 * Read a sequence of bytes from the EEPROM. 331 */ 332static int ti_read_eeprom(sc, dest, off, cnt) 333 struct ti_softc *sc; 334 caddr_t dest; 335 int off; 336 int cnt; 337{ 338 int err = 0, i; 339 u_int8_t byte = 0; 340 341 for (i = 0; i < cnt; i++) { 342 err = ti_eeprom_getbyte(sc, off + i, &byte); 343 if (err) 344 break; 345 *(dest + i) = byte; 346 } 347 348 return(err ? 1 : 0); 349} 350 351/* 352 * NIC memory access function. Can be used to either clear a section 353 * of NIC local memory or (if buf is non-NULL) copy data into it. 354 */ 355static void ti_mem(sc, addr, len, buf) 356 struct ti_softc *sc; 357 u_int32_t addr, len; 358 caddr_t buf; 359{ 360 int segptr, segsize, cnt; 361 caddr_t ti_winbase, ptr; 362 363 segptr = addr; 364 cnt = len; 365#ifdef __i386__ 366 ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW); 367#endif 368#ifdef __alpha__ 369 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 370#endif 371 ptr = buf; 372 373 while(cnt) { 374 if (cnt < TI_WINLEN) 375 segsize = cnt; 376 else 377 segsize = TI_WINLEN - (segptr % TI_WINLEN); 378 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 379 if (buf == NULL) 380 bzero((char *)ti_winbase + (segptr & 381 (TI_WINLEN - 1)), segsize); 382 else { 383 bcopy((char *)ptr, (char *)ti_winbase + 384 (segptr & (TI_WINLEN - 1)), segsize); 385 ptr += segsize; 386 } 387 segptr += segsize; 388 cnt -= segsize; 389 } 390 391 return; 392} 393 394/* 395 * Load firmware image into the NIC. Check that the firmware revision 396 * is acceptable and see if we want the firmware for the Tigon 1 or 397 * Tigon 2. 398 */ 399static void ti_loadfw(sc) 400 struct ti_softc *sc; 401{ 402 switch(sc->ti_hwrev) { 403 case TI_HWREV_TIGON: 404 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 405 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 406 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 407 printf("ti%d: firmware revision mismatch; want " 408 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 409 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 410 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 411 tigonFwReleaseMinor, tigonFwReleaseFix); 412 return; 413 } 414 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 415 (caddr_t)tigonFwText); 416 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 417 (caddr_t)tigonFwData); 418 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 419 (caddr_t)tigonFwRodata); 420 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 421 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 422 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 423 break; 424 case TI_HWREV_TIGON_II: 425 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 426 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 427 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 428 printf("ti%d: firmware revision mismatch; want " 429 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 430 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 431 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 432 tigon2FwReleaseMinor, tigon2FwReleaseFix); 433 return; 434 } 435 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 436 (caddr_t)tigon2FwText); 437 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 438 (caddr_t)tigon2FwData); 439 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 440 (caddr_t)tigon2FwRodata); 441 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 442 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 443 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 444 break; 445 default: 446 printf("ti%d: can't load firmware: unknown hardware rev\n", 447 sc->ti_unit); 448 break; 449 } 450 451 return; 452} 453 454/* 455 * Send the NIC a command via the command ring. 456 */ 457static void ti_cmd(sc, cmd) 458 struct ti_softc *sc; 459 struct ti_cmd_desc *cmd; 460{ 461 u_int32_t index; 462 463 if (sc->ti_rdata->ti_cmd_ring == NULL) 464 return; 465 466 index = sc->ti_cmd_saved_prodidx; 467 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 468 TI_INC(index, TI_CMD_RING_CNT); 469 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 470 sc->ti_cmd_saved_prodidx = index; 471 472 return; 473} 474 475/* 476 * Send the NIC an extended command. The 'len' parameter specifies the 477 * number of command slots to include after the initial command. 478 */ 479static void ti_cmd_ext(sc, cmd, arg, len) 480 struct ti_softc *sc; 481 struct ti_cmd_desc *cmd; 482 caddr_t arg; 483 int len; 484{ 485 u_int32_t index; 486 register int i; 487 488 if (sc->ti_rdata->ti_cmd_ring == NULL) 489 return; 490 491 index = sc->ti_cmd_saved_prodidx; 492 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 493 TI_INC(index, TI_CMD_RING_CNT); 494 for (i = 0; i < len; i++) { 495 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 496 *(u_int32_t *)(&arg[i * 4])); 497 TI_INC(index, TI_CMD_RING_CNT); 498 } 499 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 500 sc->ti_cmd_saved_prodidx = index; 501 502 return; 503} 504 505/* 506 * Handle events that have triggered interrupts. 507 */ 508static void ti_handle_events(sc) 509 struct ti_softc *sc; 510{ 511 struct ti_event_desc *e; 512 513 if (sc->ti_rdata->ti_event_ring == NULL) 514 return; 515 516 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 517 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 518 switch(e->ti_event) { 519 case TI_EV_LINKSTAT_CHANGED: 520 sc->ti_linkstat = e->ti_code; 521 if (e->ti_code == TI_EV_CODE_LINK_UP) 522 printf("ti%d: 10/100 link up\n", sc->ti_unit); 523 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 524 printf("ti%d: gigabit link up\n", sc->ti_unit); 525 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 526 printf("ti%d: link down\n", sc->ti_unit); 527 break; 528 case TI_EV_ERROR: 529 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 530 printf("ti%d: invalid command\n", sc->ti_unit); 531 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 532 printf("ti%d: unknown command\n", sc->ti_unit); 533 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 534 printf("ti%d: bad config data\n", sc->ti_unit); 535 break; 536 case TI_EV_FIRMWARE_UP: 537 ti_init2(sc); 538 break; 539 case TI_EV_STATS_UPDATED: 540 ti_stats_update(sc); 541 break; 542 case TI_EV_RESET_JUMBO_RING: 543 case TI_EV_MCAST_UPDATED: 544 /* Who cares. */ 545 break; 546 default: 547 printf("ti%d: unknown event: %d\n", 548 sc->ti_unit, e->ti_event); 549 break; 550 } 551 /* Advance the consumer index. */ 552 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 553 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 554 } 555 556 return; 557} 558 559/* 560 * Memory management for the jumbo receive ring is a pain in the 561 * butt. We need to allocate at least 9018 bytes of space per frame, 562 * _and_ it has to be contiguous (unless you use the extended 563 * jumbo descriptor format). Using malloc() all the time won't 564 * work: malloc() allocates memory in powers of two, which means we 565 * would end up wasting a considerable amount of space by allocating 566 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 567 * to do our own memory management. 568 * 569 * The driver needs to allocate a contiguous chunk of memory at boot 570 * time. We then chop this up ourselves into 9K pieces and use them 571 * as external mbuf storage. 572 * 573 * One issue here is how much memory to allocate. The jumbo ring has 574 * 256 slots in it, but at 9K per slot than can consume over 2MB of 575 * RAM. This is a bit much, especially considering we also need 576 * RAM for the standard ring and mini ring (on the Tigon 2). To 577 * save space, we only actually allocate enough memory for 64 slots 578 * by default, which works out to between 500 and 600K. This can 579 * be tuned by changing a #define in if_tireg.h. 580 */ 581 582static int ti_alloc_jumbo_mem(sc) 583 struct ti_softc *sc; 584{ 585 caddr_t ptr; 586 register int i; 587 struct ti_jpool_entry *entry; 588 589 /* Grab a big chunk o' storage. */ 590 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 591 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 592 593 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 594 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 595 return(ENOBUFS); 596 } 597 598 SLIST_INIT(&sc->ti_jfree_listhead); 599 SLIST_INIT(&sc->ti_jinuse_listhead); 600 601 /* 602 * Now divide it up into 9K pieces and save the addresses 603 * in an array. Note that we play an evil trick here by using 604 * the first few bytes in the buffer to hold the the address 605 * of the softc structure for this interface. This is because 606 * ti_jfree() needs it, but it is called by the mbuf management 607 * code which will not pass it to us explicitly. 608 */ 609 ptr = sc->ti_cdata.ti_jumbo_buf; 610 for (i = 0; i < TI_JSLOTS; i++) { 611 u_int64_t **aptr; 612 aptr = (u_int64_t **)ptr; 613 aptr[0] = (u_int64_t *)sc; 614 ptr += sizeof(u_int64_t); 615 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 616 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 617 ptr += (TI_JLEN - sizeof(u_int64_t)); 618 entry = malloc(sizeof(struct ti_jpool_entry), 619 M_DEVBUF, M_NOWAIT); 620 if (entry == NULL) { 621 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 622 sc->ti_cdata.ti_jumbo_buf = NULL; 623 printf("ti%d: no memory for jumbo " 624 "buffer queue!\n", sc->ti_unit); 625 return(ENOBUFS); 626 } 627 entry->slot = i; 628 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 629 } 630 631 return(0); 632} 633 634/* 635 * Allocate a jumbo buffer. 636 */ 637static void *ti_jalloc(sc) 638 struct ti_softc *sc; 639{ 640 struct ti_jpool_entry *entry; 641 642 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 643 644 if (entry == NULL) { 645 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 646 return(NULL); 647 } 648 649 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 650 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 651 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 652 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 653} 654 655/* 656 * Adjust usage count on a jumbo buffer. In general this doesn't 657 * get used much because our jumbo buffers don't get passed around 658 * too much, but it's implemented for correctness. 659 */ 660static void ti_jref(buf, size) 661 caddr_t buf; 662 u_int size; 663{ 664 struct ti_softc *sc; 665 u_int64_t **aptr; 666 register int i; 667 668 /* Extract the softc struct pointer. */ 669 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 670 sc = (struct ti_softc *)(aptr[0]); 671 672 if (sc == NULL) 673 panic("ti_jref: can't find softc pointer!"); 674 675 if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 676 panic("ti_jref: adjusting refcount of buf of wrong size!"); 677 678 /* calculate the slot this buffer belongs to */ 679 680 i = ((vm_offset_t)aptr 681 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 682 683 if ((i < 0) || (i >= TI_JSLOTS)) 684 panic("ti_jref: asked to reference buffer " 685 "that we don't manage!"); 686 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 687 panic("ti_jref: buffer already free!"); 688 else 689 sc->ti_cdata.ti_jslots[i].ti_inuse++; 690 691 return; 692} 693 694/* 695 * Release a jumbo buffer. 696 */ 697static void ti_jfree(buf, size) 698 caddr_t buf; 699 u_int size; 700{ 701 struct ti_softc *sc; 702 u_int64_t **aptr; 703 int i; 704 struct ti_jpool_entry *entry; 705 706 /* Extract the softc struct pointer. */ 707 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 708 sc = (struct ti_softc *)(aptr[0]); 709 710 if (sc == NULL) 711 panic("ti_jfree: can't find softc pointer!"); 712 713 if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 714 panic("ti_jfree: freeing buffer of wrong size!"); 715 716 /* calculate the slot this buffer belongs to */ 717 718 i = ((vm_offset_t)aptr 719 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 720 721 if ((i < 0) || (i >= TI_JSLOTS)) 722 panic("ti_jfree: asked to free buffer that we don't manage!"); 723 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 724 panic("ti_jfree: buffer already free!"); 725 else { 726 sc->ti_cdata.ti_jslots[i].ti_inuse--; 727 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 728 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 729 if (entry == NULL) 730 panic("ti_jfree: buffer not in use!"); 731 entry->slot = i; 732 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 733 jpool_entries); 734 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 735 entry, jpool_entries); 736 } 737 } 738 739 return; 740} 741 742 743/* 744 * Intialize a standard receive ring descriptor. 745 */ 746static int ti_newbuf_std(sc, i, m) 747 struct ti_softc *sc; 748 int i; 749 struct mbuf *m; 750{ 751 struct mbuf *m_new = NULL; 752 struct ti_rx_desc *r; 753 754 if (m != NULL) { 755 m_new = m; 756 } else { 757 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 758 if (m_new == NULL) { 759 printf("ti%d: mbuf allocation failed " 760 "-- packet dropped!\n", sc->ti_unit); 761 return(ENOBUFS); 762 } 763 764 MCLGET(m_new, M_DONTWAIT); 765 if (!(m_new->m_flags & M_EXT)) { 766 printf("ti%d: cluster allocation failed " 767 "-- packet dropped!\n", sc->ti_unit); 768 m_freem(m_new); 769 return(ENOBUFS); 770 } 771 } 772 773 m_new->m_len -= ETHER_ALIGN; 774 m_new->m_data += ETHER_ALIGN; 775 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 776 r = &sc->ti_rdata->ti_rx_std_ring[i]; 777 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 778 r->ti_type = TI_BDTYPE_RECV_BD; 779#ifdef TI_CSUM_OFFLOAD 780 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 781#else 782 r->ti_flags = 0; 783#endif 784 r->ti_len = MCLBYTES - ETHER_ALIGN; 785 r->ti_idx = i; 786 787 return(0); 788} 789 790/* 791 * Intialize a mini receive ring descriptor. This only applies to 792 * the Tigon 2. 793 */ 794static int ti_newbuf_mini(sc, i, m) 795 struct ti_softc *sc; 796 int i; 797 struct mbuf *m; 798{ 799 struct mbuf *m_new = NULL; 800 struct ti_rx_desc *r; 801 802 if (m != NULL) { 803 m_new = m; 804 } else { 805 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 806 if (m_new == NULL) { 807 printf("ti%d: mbuf allocation failed " 808 "-- packet dropped!\n", sc->ti_unit); 809 return(ENOBUFS); 810 } 811 } 812 m_new->m_len -= ETHER_ALIGN; 813 m_new->m_data += ETHER_ALIGN; 814 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 815 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 816 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 817 r->ti_type = TI_BDTYPE_RECV_BD; 818 r->ti_flags = TI_BDFLAG_MINI_RING; 819#ifdef TI_CSUM_OFFLOAD 820 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 821#endif 822 r->ti_len = MHLEN - ETHER_ALIGN; 823 r->ti_idx = i; 824 825 return(0); 826} 827 828/* 829 * Initialize a jumbo receive ring descriptor. This allocates 830 * a jumbo buffer from the pool managed internally by the driver. 831 */ 832static int ti_newbuf_jumbo(sc, i, m) 833 struct ti_softc *sc; 834 int i; 835 struct mbuf *m; 836{ 837 struct mbuf *m_new = NULL; 838 struct ti_rx_desc *r; 839 840 if (m != NULL) { 841 m_new = m; 842 } else { 843 caddr_t *buf = NULL; 844 845 /* Allocate the mbuf. */ 846 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 847 if (m_new == NULL) { 848 printf("ti%d: mbuf allocation failed " 849 "-- packet dropped!\n", sc->ti_unit); 850 return(ENOBUFS); 851 } 852 853 /* Allocate the jumbo buffer */ 854 buf = ti_jalloc(sc); 855 if (buf == NULL) { 856 m_freem(m_new); 857 printf("ti%d: jumbo allocation failed " 858 "-- packet dropped!\n", sc->ti_unit); 859 return(ENOBUFS); 860 } 861 862 /* Attach the buffer to the mbuf. */ 863 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 864 m_new->m_data += ETHER_ALIGN; 865 m_new->m_flags |= M_EXT; 866 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 867 m_new->m_ext.ext_free = ti_jfree; 868 m_new->m_ext.ext_ref = ti_jref; 869 } 870 871 /* Set up the descriptor. */ 872 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 873 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 874 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 875 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 876 r->ti_flags = TI_BDFLAG_JUMBO_RING; 877#ifdef TI_CSUM_OFFLOAD 878 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 879#endif 880 r->ti_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 881 r->ti_idx = i; 882 883 return(0); 884} 885 886/* 887 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 888 * that's 1MB or memory, which is a lot. For now, we fill only the first 889 * 256 ring entries and hope that our CPU is fast enough to keep up with 890 * the NIC. 891 */ 892static int ti_init_rx_ring_std(sc) 893 struct ti_softc *sc; 894{ 895 register int i; 896 struct ti_cmd_desc cmd; 897 898 for (i = 0; i < TI_SSLOTS; i++) { 899 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 900 return(ENOBUFS); 901 }; 902 903 TI_UPDATE_STDPROD(sc, i - 1); 904 sc->ti_std_old = sc->ti_std = i - 1; 905 sc->ti_std_cnt = 0; 906 907 return(0); 908} 909 910static void ti_free_rx_ring_std(sc) 911 struct ti_softc *sc; 912{ 913 register int i; 914 915 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 916 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 917 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 918 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 919 } 920 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 921 sizeof(struct ti_rx_desc)); 922 } 923 924 return; 925} 926 927static int ti_init_rx_ring_jumbo(sc) 928 struct ti_softc *sc; 929{ 930 register int i; 931 struct ti_cmd_desc cmd; 932 933 for (i = 0; i < (TI_JSLOTS - 20); i++) { 934 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 935 return(ENOBUFS); 936 }; 937 938 TI_UPDATE_JUMBOPROD(sc, i - 1); 939 sc->ti_jumbo_old = sc->ti_jumbo = i - 1; 940 sc->ti_jumbo_cnt = 0; 941 942 return(0); 943} 944 945static void ti_free_rx_ring_jumbo(sc) 946 struct ti_softc *sc; 947{ 948 register int i; 949 950 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 951 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 952 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 953 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 954 } 955 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 956 sizeof(struct ti_rx_desc)); 957 } 958 959 return; 960} 961 962static int ti_init_rx_ring_mini(sc) 963 struct ti_softc *sc; 964{ 965 register int i; 966 967 for (i = 0; i < TI_MSLOTS; i++) { 968 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 969 return(ENOBUFS); 970 }; 971 972 TI_UPDATE_MINIPROD(sc, i - 1); 973 sc->ti_mini_old = sc->ti_mini = i - 1; 974 sc->ti_mini_cnt = 0; 975 976 return(0); 977} 978 979static void ti_free_rx_ring_mini(sc) 980 struct ti_softc *sc; 981{ 982 register int i; 983 984 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 985 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 986 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 987 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 988 } 989 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 990 sizeof(struct ti_rx_desc)); 991 } 992 993 return; 994} 995 996/* 997 * In order to reduce the amount of work we have to do in the interrupt 998 * handler, we delay putting new buffers in the receive rings until a 999 * certain amount have been used. This lets us hand over descriptors to 1000 * the NIC in fairly large chunks instead of one (or a few) at a time, 1001 * and it lets tx_rxeof() run a bit faster some of the time. 1002 */ 1003static void ti_refill_rx_rings(sc) 1004 struct ti_softc *sc; 1005{ 1006 register int i; 1007 struct ti_cmd_desc cmd; 1008 1009 if (sc->ti_std_cnt > 15) { 1010 for (i = sc->ti_std_old; i != sc->ti_std; 1011 TI_INC(i, TI_STD_RX_RING_CNT)) { 1012 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1013 break; 1014 }; 1015 TI_UPDATE_STDPROD(sc, i); 1016 sc->ti_std_old = i; 1017 sc->ti_std_cnt = 0; 1018 } 1019 1020 if (sc->ti_jumbo_cnt > 15) { 1021 for (i = sc->ti_jumbo_old; i != sc->ti_jumbo; 1022 TI_INC(i, TI_JUMBO_RX_RING_CNT)) { 1023 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1024 break; 1025 }; 1026 TI_UPDATE_JUMBOPROD(sc, i); 1027 sc->ti_jumbo_old = i; 1028 sc->ti_jumbo_cnt = 0; 1029 } 1030 1031 if (sc->ti_mini_cnt > 15) { 1032 for (i = sc->ti_mini_old; i != sc->ti_mini; 1033 TI_INC(i, TI_MINI_RX_RING_CNT)) { 1034 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1035 break; 1036 }; 1037 TI_UPDATE_MINIPROD(sc, i); 1038 sc->ti_mini_old = i; 1039 sc->ti_mini_cnt = 0; 1040 } 1041 1042 return; 1043} 1044 1045static void ti_free_tx_ring(sc) 1046 struct ti_softc *sc; 1047{ 1048 register int i; 1049 1050 if (sc->ti_rdata->ti_tx_ring == NULL) 1051 return; 1052 1053 for (i = 0; i < TI_TX_RING_CNT; i++) { 1054 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1055 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1056 sc->ti_cdata.ti_tx_chain[i] = NULL; 1057 } 1058 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1059 sizeof(struct ti_tx_desc)); 1060 } 1061 1062 return; 1063} 1064 1065static int ti_init_tx_ring(sc) 1066 struct ti_softc *sc; 1067{ 1068 sc->ti_tx_saved_considx = 0; 1069 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1070 return(0); 1071} 1072 1073/* 1074 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1075 * but we have to support the old way too so that Tigon 1 cards will 1076 * work. 1077 */ 1078void ti_add_mcast(sc, addr) 1079 struct ti_softc *sc; 1080 struct ether_addr *addr; 1081{ 1082 struct ti_cmd_desc cmd; 1083 u_int16_t *m; 1084 u_int32_t ext[2] = {0, 0}; 1085 1086 m = (u_int16_t *)&addr->octet[0]; 1087 1088 switch(sc->ti_hwrev) { 1089 case TI_HWREV_TIGON: 1090 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1091 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1092 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1093 break; 1094 case TI_HWREV_TIGON_II: 1095 ext[0] = htons(m[0]); 1096 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1097 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1098 break; 1099 default: 1100 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1101 break; 1102 } 1103 1104 return; 1105} 1106 1107void ti_del_mcast(sc, addr) 1108 struct ti_softc *sc; 1109 struct ether_addr *addr; 1110{ 1111 struct ti_cmd_desc cmd; 1112 u_int16_t *m; 1113 u_int32_t ext[2] = {0, 0}; 1114 1115 m = (u_int16_t *)&addr->octet[0]; 1116 1117 switch(sc->ti_hwrev) { 1118 case TI_HWREV_TIGON: 1119 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1120 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1121 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1122 break; 1123 case TI_HWREV_TIGON_II: 1124 ext[0] = htons(m[0]); 1125 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1126 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1127 break; 1128 default: 1129 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1130 break; 1131 } 1132 1133 return; 1134} 1135 1136/* 1137 * Configure the Tigon's multicast address filter. 1138 * 1139 * The actual multicast table management is a bit of a pain, thanks to 1140 * slight brain damage on the part of both Alteon and us. With our 1141 * multicast code, we are only alerted when the multicast address table 1142 * changes and at that point we only have the current list of addresses: 1143 * we only know the current state, not the previous state, so we don't 1144 * actually know what addresses were removed or added. The firmware has 1145 * state, but we can't get our grubby mits on it, and there is no 'delete 1146 * all multicast addresses' command. Hence, we have to maintain our own 1147 * state so we know what addresses have been programmed into the NIC at 1148 * any given time. 1149 */ 1150static void ti_setmulti(sc) 1151 struct ti_softc *sc; 1152{ 1153 struct ifnet *ifp; 1154 struct ifmultiaddr *ifma; 1155 struct ti_cmd_desc cmd; 1156 struct ti_mc_entry *mc; 1157 u_int32_t intrs; 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 if (ifp->if_flags & IFF_ALLMULTI) { 1162 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1163 return; 1164 } else { 1165 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1166 } 1167 1168 /* Disable interrupts. */ 1169 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1170 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1171 1172 /* First, zot all the existing filters. */ 1173 while (sc->ti_mc_listhead.slh_first != NULL) { 1174 mc = sc->ti_mc_listhead.slh_first; 1175 ti_del_mcast(sc, &mc->mc_addr); 1176 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1177 free(mc, M_DEVBUF); 1178 } 1179 1180 /* Now program new ones. */ 1181 for (ifma = ifp->if_multiaddrs.lh_first; 1182 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1183 if (ifma->ifma_addr->sa_family != AF_LINK) 1184 continue; 1185 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1186 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1187 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1188 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1189 ti_add_mcast(sc, &mc->mc_addr); 1190 } 1191 1192 /* Re-enable interrupts. */ 1193 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1194 1195 return; 1196} 1197 1198/* 1199 * Check to see if the BIOS has configured us for a 64 bit slot when 1200 * we aren't actually in one. If we detect this condition, we can work 1201 * around it on the Tigon 2 by setting a bit in the PCI state register, 1202 * but for the Tigon 1 we must give up and abort the interface attach. 1203 */ 1204static int ti_64bitslot_war(sc) 1205 struct ti_softc *sc; 1206{ 1207 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1208 CSR_WRITE_4(sc, 0x600, 0); 1209 CSR_WRITE_4(sc, 0x604, 0); 1210 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1211 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1212 if (sc->ti_hwrev == TI_HWREV_TIGON) 1213 return(EINVAL); 1214 else { 1215 TI_SETBIT(sc, TI_PCI_STATE, 1216 TI_PCISTATE_32BIT_BUS); 1217 return(0); 1218 } 1219 } 1220 } 1221 1222 return(0); 1223} 1224 1225/* 1226 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1227 * self-test results. 1228 */ 1229static int ti_chipinit(sc) 1230 struct ti_softc *sc; 1231{ 1232 u_int32_t cacheline; 1233 u_int32_t pci_writemax = 0; 1234 1235 /* Initialize link to down state. */ 1236 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1237 1238 /* Set endianness before we access any non-PCI registers. */ 1239#if BYTE_ORDER == BIG_ENDIAN 1240 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1241 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1242#else 1243 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1244 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1245#endif 1246 1247 /* Check the ROM failed bit to see if self-tests passed. */ 1248 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1249 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1250 return(ENODEV); 1251 } 1252 1253 /* Halt the CPU. */ 1254 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1255 1256 /* Figure out the hardware revision. */ 1257 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1258 case TI_REV_TIGON_I: 1259 sc->ti_hwrev = TI_HWREV_TIGON; 1260 break; 1261 case TI_REV_TIGON_II: 1262 sc->ti_hwrev = TI_HWREV_TIGON_II; 1263 break; 1264 default: 1265 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1266 return(ENODEV); 1267 } 1268 1269 /* Do special setup for Tigon 2. */ 1270 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1271 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1272 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1273 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1274 } 1275 1276 /* Set up the PCI state register. */ 1277 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1278 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1279 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1280 } 1281 1282 /* Clear the read/write max DMA parameters. */ 1283 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1284 TI_PCISTATE_READ_MAXDMA)); 1285 1286 /* Get cache line size. */ 1287 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1288 1289 /* 1290 * If the system has set enabled the PCI memory write 1291 * and invalidate command in the command register, set 1292 * the write max parameter accordingly. This is necessary 1293 * to use MWI with the Tigon 2. 1294 */ 1295 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1296 switch(cacheline) { 1297 case 1: 1298 case 4: 1299 case 8: 1300 case 16: 1301 case 32: 1302 case 64: 1303 break; 1304 default: 1305 /* Disable PCI memory write and invalidate. */ 1306 if (bootverbose) 1307 printf("ti%d: cache line size %d not " 1308 "supported; disabling PCI MWI\n", 1309 sc->ti_unit, cacheline); 1310 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1311 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1312 break; 1313 } 1314 } 1315 1316#ifdef __brokenalpha__ 1317 /* 1318 * From the Alteon sample driver: 1319 * Must insure that we do not cross an 8K (bytes) boundary 1320 * for DMA reads. Our highest limit is 1K bytes. This is a 1321 * restriction on some ALPHA platforms with early revision 1322 * 21174 PCI chipsets, such as the AlphaPC 164lx 1323 */ 1324 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1325#else 1326 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1327#endif 1328 1329 /* This sets the min dma param all the way up (0xff). */ 1330 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1331 1332 /* Configure DMA variables. */ 1333#if BYTE_ORDER == BIG_ENDIAN 1334 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1335 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1336 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1337 TI_OPMODE_DONT_FRAG_JUMBO); 1338#else 1339 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1340 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1341 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1342#endif 1343 1344 /* 1345 * Only allow 1 DMA channel to be active at a time. 1346 * I don't think this is a good idea, but without it 1347 * the firmware racks up lots of nicDmaReadRingFull 1348 * errors. 1349 */ 1350#ifndef TI_CSUM_OFFLOAD 1351 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1352#endif 1353 1354 /* Recommended settings from Tigon manual. */ 1355 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1356 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1357 1358 if (ti_64bitslot_war(sc)) { 1359 printf("ti%d: bios thinks we're in a 64 bit slot, " 1360 "but we aren't", sc->ti_unit); 1361 return(EINVAL); 1362 } 1363 1364 return(0); 1365} 1366 1367/* 1368 * Initialize the general information block and firmware, and 1369 * start the CPU(s) running. 1370 */ 1371static int ti_gibinit(sc) 1372 struct ti_softc *sc; 1373{ 1374 struct ti_rcb *rcb; 1375 int i; 1376 struct ifnet *ifp; 1377 1378 ifp = &sc->arpcom.ac_if; 1379 1380 /* Disable interrupts for now. */ 1381 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1382 1383 /* Tell the chip where to find the general information block. */ 1384 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1385 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1386 1387 /* Load the firmware into SRAM. */ 1388 ti_loadfw(sc); 1389 1390 /* Set up the contents of the general info and ring control blocks. */ 1391 1392 /* Set up the event ring and producer pointer. */ 1393 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1394 1395 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1396 rcb->ti_flags = 0; 1397 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1398 vtophys(&sc->ti_ev_prodidx); 1399 sc->ti_ev_prodidx.ti_idx = 0; 1400 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1401 sc->ti_ev_saved_considx = 0; 1402 1403 /* Set up the command ring and producer mailbox. */ 1404 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1405 1406#ifdef __i386__ 1407 sc->ti_rdata->ti_cmd_ring = 1408 (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING); 1409#endif 1410#ifdef __alpha__ 1411 sc->ti_rdata->ti_cmd_ring = 1412 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1413#endif 1414 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1415 rcb->ti_flags = 0; 1416 rcb->ti_max_len = 0; 1417 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1418 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1419 } 1420 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1421 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1422 sc->ti_cmd_saved_prodidx = 0; 1423 1424 /* 1425 * Assign the address of the stats refresh buffer. 1426 * We re-use the current stats buffer for this to 1427 * conserve memory. 1428 */ 1429 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1430 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1431 1432 /* Set up the standard receive ring. */ 1433 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1434 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1435 rcb->ti_max_len = TI_FRAMELEN; 1436 rcb->ti_flags = 0; 1437#ifdef TI_CSUM_OFFLOAD 1438 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1439#endif 1440#if NVLAN > 0 1441 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1442#endif 1443 1444 /* Set up the jumbo receive ring. */ 1445 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1446 TI_HOSTADDR(rcb->ti_hostaddr) = 1447 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1448 rcb->ti_max_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 1449 rcb->ti_flags = 0; 1450#ifdef TI_CSUM_OFFLOAD 1451 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1452#endif 1453#if NVLAN > 0 1454 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1455#endif 1456 1457 /* 1458 * Set up the mini ring. Only activated on the 1459 * Tigon 2 but the slot in the config block is 1460 * still there on the Tigon 1. 1461 */ 1462 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1463 TI_HOSTADDR(rcb->ti_hostaddr) = 1464 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1465 rcb->ti_max_len = MHLEN; 1466 if (sc->ti_hwrev == TI_HWREV_TIGON) 1467 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1468 else 1469 rcb->ti_flags = 0; 1470#ifdef TI_CSUM_OFFLOAD 1471 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1472#endif 1473#if NVLAN > 0 1474 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1475#endif 1476 1477 /* 1478 * Set up the receive return ring. 1479 */ 1480 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1481 TI_HOSTADDR(rcb->ti_hostaddr) = 1482 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1483 rcb->ti_flags = 0; 1484 rcb->ti_max_len = TI_RETURN_RING_CNT; 1485 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1486 vtophys(&sc->ti_return_prodidx); 1487 1488 /* 1489 * Set up the tx ring. Note: for the Tigon 2, we have the option 1490 * of putting the transmit ring in the host's address space and 1491 * letting the chip DMA it instead of leaving the ring in the NIC's 1492 * memory and accessing it through the shared memory region. We 1493 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1494 * so we have to revert to the shared memory scheme if we detect 1495 * a Tigon 1 chip. 1496 */ 1497 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1498 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1499#ifdef __i386__ 1500 sc->ti_rdata->ti_tx_ring_nic = 1501 (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW); 1502#endif 1503#ifdef __alpha__ 1504 sc->ti_rdata->ti_tx_ring_nic = 1505 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1506#endif 1507 } 1508 bzero((char *)sc->ti_rdata->ti_tx_ring, 1509 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1510 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1511 if (sc->ti_hwrev == TI_HWREV_TIGON) 1512 rcb->ti_flags = 0; 1513 else 1514 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1515#if NVLAN > 0 1516 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1517#endif 1518 rcb->ti_max_len = TI_TX_RING_CNT; 1519 if (sc->ti_hwrev == TI_HWREV_TIGON) 1520 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1521 else 1522 TI_HOSTADDR(rcb->ti_hostaddr) = 1523 vtophys(&sc->ti_rdata->ti_tx_ring); 1524 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1525 vtophys(&sc->ti_tx_considx); 1526 1527 /* Set up tuneables */ 1528 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1529 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1530 (sc->ti_rx_coal_ticks / 10)); 1531 else 1532 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1533 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1534 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1535 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1536 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1537 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1538 1539 /* Turn interrupts on. */ 1540 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1541 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1542 1543 /* Start CPU. */ 1544 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1545 1546 return(0); 1547} 1548 1549/* 1550 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1551 * against our list and return its name if we find a match. 1552 */ 1553static const char * 1554ti_probe(config_id, device_id) 1555 pcici_t config_id; 1556 pcidi_t device_id; 1557{ 1558 struct ti_type *t; 1559 1560 t = ti_devs; 1561 1562 while(t->ti_name != NULL) { 1563 if ((device_id & 0xFFFF) == t->ti_vid && 1564 ((device_id >> 16) & 0xFFFF) == t->ti_did) 1565 return(t->ti_name); 1566 t++; 1567 } 1568 1569 return(NULL); 1570} 1571 1572 1573static void 1574ti_attach(config_id, unit) 1575 pcici_t config_id; 1576 int unit; 1577{ 1578 vm_offset_t pbase, vbase; 1579 int s; 1580 u_int32_t command; 1581 struct ifnet *ifp; 1582 struct ti_softc *sc; 1583 1584 s = splimp(); 1585 1586 /* First, allocate memory for the softc struct. */ 1587 sc = malloc(sizeof(struct ti_softc), M_DEVBUF, M_NOWAIT); 1588 if (sc == NULL) { 1589 printf("ti%d: no memory for softc struct!\n", unit); 1590 goto fail; 1591 } 1592 1593 bzero(sc, sizeof(struct ti_softc)); 1594 1595 /* 1596 * Map control/status registers. 1597 */ 1598 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1599 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1600 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1601 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1602 1603 if (!(command & PCIM_CMD_MEMEN)) { 1604 printf("ti%d: failed to enable memory mapping!\n", unit); 1605 free(sc, M_DEVBUF); 1606 goto fail; 1607 } 1608 1609#ifdef __i386__ 1610 if (!pci_map_mem(config_id, TI_PCI_LOMEM, &vbase, &pbase)) { 1611 printf ("ti%d: couldn't map memory\n", unit); 1612 free(sc, M_DEVBUF); 1613 goto fail; 1614 } 1615 1616 sc->ti_bhandle = vbase; 1617 sc->ti_btag = I386_BUS_SPACE_MEM; 1618#endif 1619 1620#ifdef __alpha__ 1621 if (!(pci_map_bwx(config_id, TI_PCI_LOMEM, &vbase, &pbase) || 1622 pci_map_dense(config_id, TI_PCI_LOMEM, &vbase, &pbase))){ 1623 printf ("ti%d: couldn't map memory\n", unit); 1624 free(sc, M_DEVBUF); 1625 goto fail; 1626 } 1627 1628 sc->ti_bhandle = pbase; 1629 sc->ti_vhandle = vbase; 1630 sc->ti_btag = ALPHA_BUS_SPACE_MEM; 1631#endif 1632 /* Allocate interrupt */ 1633 if (!pci_map_int(config_id, ti_intr, sc, &net_imask)) { 1634 printf("ti%d: couldn't map interrupt\n", unit); 1635 free(sc, M_DEVBUF); 1636 goto fail; 1637 } 1638 1639 sc->ti_unit = unit; 1640 1641 if (ti_chipinit(sc)) { 1642 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1643 free(sc, M_DEVBUF); 1644 goto fail; 1645 } 1646 1647 /* Zero out the NIC's on-board SRAM. */ 1648 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1649 1650 /* Init again -- zeroing memory may have clobbered some registers. */ 1651 if (ti_chipinit(sc)) { 1652 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1653 free(sc, M_DEVBUF); 1654 goto fail; 1655 } 1656 1657 /* 1658 * Get station address from the EEPROM. Note: the manual states 1659 * that the MAC address is at offset 0x8c, however the data is 1660 * stored as two longwords (since that's how it's loaded into 1661 * the NIC). This means the MAC address is actually preceeded 1662 * by two zero bytes. We need to skip over those. 1663 */ 1664 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1665 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1666 printf("ti%d: failed to read station address\n", unit); 1667 free(sc, M_DEVBUF); 1668 goto fail; 1669 } 1670 1671 /* 1672 * A Tigon chip was detected. Inform the world. 1673 */ 1674 printf("ti%d: Ethernet address: %6D\n", unit, 1675 sc->arpcom.ac_enaddr, ":"); 1676 1677 /* Allocate the general information block and ring buffers. */ 1678 sc->ti_rdata_ptr = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1679 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1680 1681 if (sc->ti_rdata_ptr == NULL) { 1682 free(sc, M_DEVBUF); 1683 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1684 goto fail; 1685 } 1686 1687 sc->ti_rdata = (struct ti_ring_data *)sc->ti_rdata_ptr; 1688 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1689 1690 /* Try to allocate memory for jumbo buffers. */ 1691 if (ti_alloc_jumbo_mem(sc)) { 1692 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1693 free(sc->ti_rdata_ptr, M_DEVBUF); 1694 free(sc, M_DEVBUF); 1695 goto fail; 1696 } 1697 1698 /* Set default tuneable values. */ 1699 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1700 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1701 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1702 sc->ti_rx_max_coal_bds = 64; 1703 sc->ti_tx_max_coal_bds = 128; 1704 sc->ti_tx_buf_ratio = 21; 1705 1706 /* Set up ifnet structure */ 1707 ifp = &sc->arpcom.ac_if; 1708 ifp->if_softc = sc; 1709 ifp->if_unit = sc->ti_unit; 1710 ifp->if_name = "ti"; 1711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1712 ifp->if_ioctl = ti_ioctl; 1713 ifp->if_output = ether_output; 1714 ifp->if_start = ti_start; 1715 ifp->if_watchdog = ti_watchdog; 1716 ifp->if_init = ti_init; 1717 ifp->if_mtu = ETHERMTU; 1718 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1719 1720 /* Set up ifmedia support. */ 1721 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1722 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1723 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1724 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1725 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1726 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1727 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1728 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1729 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1730 1731 /* 1732 * Call MI attach routines. 1733 */ 1734 if_attach(ifp); 1735 ether_ifattach(ifp); 1736 1737#if NBPFILTER > 0 1738 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1739#endif 1740 1741 at_shutdown(ti_shutdown, sc, SHUTDOWN_POST_SYNC); 1742 1743fail: 1744 splx(s); 1745 1746 return; 1747} 1748 1749/* 1750 * Frame reception handling. This is called if there's a frame 1751 * on the receive return list. 1752 * 1753 * Note: we have to be able to handle three possibilities here: 1754 * 1) the frame is from the mini receive ring (can only happen) 1755 * on Tigon 2 boards) 1756 * 2) the frame is from the jumbo recieve ring 1757 * 3) the frame is from the standard receive ring 1758 */ 1759int ti_cksumok = 0; 1760 1761static void ti_rxeof(sc) 1762 struct ti_softc *sc; 1763{ 1764 struct ifnet *ifp; 1765 1766 ifp = &sc->arpcom.ac_if; 1767 1768 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1769 struct ti_rx_desc *cur_rx; 1770 u_int32_t rxidx; 1771 struct ether_header *eh; 1772 struct mbuf *m = NULL; 1773#if NVLAN > 0 1774 u_int16_t vlan_tag = 0; 1775 int have_tag = 0; 1776#endif 1777#ifdef TI_CSUM_OFFLOAD 1778 struct ip *ip; 1779#endif 1780 1781 cur_rx = 1782 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1783 rxidx = cur_rx->ti_idx; 1784 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1785 1786#if NVLAN > 0 1787 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1788 have_tag = 1; 1789 vlan_tag = cur_rx->ti_vlan_tag; 1790 } 1791#endif 1792 1793 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1794 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1795 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1796 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1797 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1798 ifp->if_ierrors++; 1799 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1800 TI_INC(sc->ti_jumbo_old, TI_JUMBO_RX_RING_CNT); 1801 continue; 1802 } 1803 sc->ti_jumbo_cnt++; 1804 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1805 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1806 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1807 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1808 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1809 ifp->if_ierrors++; 1810 ti_newbuf_mini(sc, sc->ti_mini, m); 1811 TI_INC(sc->ti_mini_old, TI_MINI_RX_RING_CNT); 1812 continue; 1813 } 1814 sc->ti_mini_cnt++; 1815 } else { 1816 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1817 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1818 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1819 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1820 ifp->if_ierrors++; 1821 ti_newbuf_std(sc, sc->ti_std, m); 1822 TI_INC(sc->ti_std_old, TI_STD_RX_RING_CNT); 1823 continue; 1824 } 1825 sc->ti_std_cnt++; 1826 } 1827 1828 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1829 ifp->if_ipackets++; 1830 eh = mtod(m, struct ether_header *); 1831 m->m_pkthdr.rcvif = ifp; 1832 1833#if NBPFILTER > 0 1834 /* 1835 * Handle BPF listeners. Let the BPF user see the packet, but 1836 * don't pass it up to the ether_input() layer unless it's 1837 * a broadcast packet, multicast packet, matches our ethernet 1838 * address or the interface is in promiscuous mode. 1839 */ 1840 if (ifp->if_bpf) { 1841 bpf_mtap(ifp, m); 1842 if (ifp->if_flags & IFF_PROMISC && 1843 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1844 ETHER_ADDR_LEN) && 1845 (eh->ether_dhost[0] & 1) == 0)) { 1846 m_freem(m); 1847 continue; 1848 } 1849 } 1850#endif 1851 1852 /* Remove header from mbuf and pass it on. */ 1853 m_adj(m, sizeof(struct ether_header)); 1854 1855#ifdef TI_CSUM_OFFLOAD 1856 ip = mtod(m, struct ip *); 1857 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1858 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) { 1859 m->m_flags |= M_HWCKSUM; 1860 ti_cksumok++; 1861 } 1862#endif 1863 1864#if NVLAN > 0 1865 /* 1866 * If we received a packet with a vlan tag, pass it 1867 * to vlan_input() instead of ether_input(). 1868 */ 1869 if (have_tag) { 1870 vlan_input_tag(eh, m, vlan_tag); 1871 have_tag = vlan_tag = 0; 1872 continue; 1873 } 1874#endif 1875 ether_input(ifp, eh, m); 1876 } 1877 1878 /* Only necessary on the Tigon 1. */ 1879 if (sc->ti_hwrev == TI_HWREV_TIGON) 1880 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1881 sc->ti_rx_saved_considx); 1882 1883 ti_refill_rx_rings(sc); 1884 1885 return; 1886} 1887 1888static void ti_txeof(sc) 1889 struct ti_softc *sc; 1890{ 1891 struct ti_tx_desc *cur_tx = NULL; 1892 struct ifnet *ifp; 1893 1894 ifp = &sc->arpcom.ac_if; 1895 1896 /* 1897 * Go through our tx ring and free mbufs for those 1898 * frames that have been sent. 1899 */ 1900 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1901 u_int32_t idx = 0; 1902 1903 idx = sc->ti_tx_saved_considx; 1904 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1905 if (idx > 383) 1906 CSR_WRITE_4(sc, TI_WINBASE, 1907 TI_TX_RING_BASE + 6144); 1908 else if (idx > 255) 1909 CSR_WRITE_4(sc, TI_WINBASE, 1910 TI_TX_RING_BASE + 4096); 1911 else if (idx > 127) 1912 CSR_WRITE_4(sc, TI_WINBASE, 1913 TI_TX_RING_BASE + 2048); 1914 else 1915 CSR_WRITE_4(sc, TI_WINBASE, 1916 TI_TX_RING_BASE); 1917 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1918 } else 1919 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1920 if (cur_tx->ti_flags & TI_BDFLAG_END) 1921 ifp->if_opackets++; 1922 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1923 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1924 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1925 } 1926 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1927 ifp->if_timer = 0; 1928 } 1929 1930 if (cur_tx != NULL) 1931 ifp->if_flags &= ~IFF_OACTIVE; 1932 1933 return; 1934} 1935 1936static void ti_intr(xsc) 1937 void *xsc; 1938{ 1939 struct ti_softc *sc; 1940 struct ifnet *ifp; 1941 1942 sc = xsc; 1943 ifp = &sc->arpcom.ac_if; 1944 1945#ifdef notdef 1946 /* Avoid this for now -- checking this register is expensive. */ 1947 /* Make sure this is really our interrupt. */ 1948 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1949 return; 1950#endif 1951 1952 /* Ack interrupt and stop others from occuring. */ 1953 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1954 1955 if (ifp->if_flags & IFF_RUNNING) { 1956 /* Check RX return ring producer/consumer */ 1957 ti_rxeof(sc); 1958 1959 /* Check TX ring producer/consumer */ 1960 ti_txeof(sc); 1961 } 1962 1963 ti_handle_events(sc); 1964 1965 /* Re-enable interrupts. */ 1966 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1967 1968 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1969 ti_start(ifp); 1970 1971 return; 1972} 1973 1974static void ti_stats_update(sc) 1975 struct ti_softc *sc; 1976{ 1977 struct ifnet *ifp; 1978 1979 ifp = &sc->arpcom.ac_if; 1980 1981 ifp->if_collisions += 1982 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1983 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1984 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1985 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1986 ifp->if_collisions; 1987 1988 return; 1989} 1990 1991/* 1992 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1993 * pointers to descriptors. 1994 */ 1995static int ti_encap(sc, m_head, txidx) 1996 struct ti_softc *sc; 1997 struct mbuf *m_head; 1998 u_int32_t *txidx; 1999{ 2000 struct ti_tx_desc *f = NULL; 2001 struct mbuf *m; 2002 u_int32_t frag, cur; 2003#if NVLAN > 0 2004 struct ifvlan *ifv = NULL; 2005 2006 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2007 m_head->m_pkthdr.rcvif != NULL && 2008 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2009 ifv = m_head->m_pkthdr.rcvif->if_softc; 2010#endif 2011 2012 m = m_head; 2013 cur = frag = *txidx; 2014 2015 /* 2016 * Start packing the mbufs in this chain into 2017 * the fragment pointers. Stop when we run out 2018 * of fragments or hit the end of the mbuf chain. 2019 */ 2020 for (m = m_head; m != NULL; m = m->m_next) { 2021 if (m->m_len != 0) { 2022 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2023 if (frag > 383) 2024 CSR_WRITE_4(sc, TI_WINBASE, 2025 TI_TX_RING_BASE + 6144); 2026 else if (frag > 255) 2027 CSR_WRITE_4(sc, TI_WINBASE, 2028 TI_TX_RING_BASE + 4096); 2029 else if (frag > 127) 2030 CSR_WRITE_4(sc, TI_WINBASE, 2031 TI_TX_RING_BASE + 2048); 2032 else 2033 CSR_WRITE_4(sc, TI_WINBASE, 2034 TI_TX_RING_BASE); 2035 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2036 } else 2037 f = &sc->ti_rdata->ti_tx_ring[frag]; 2038 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2039 break; 2040 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2041 f->ti_len = m->m_len; 2042 f->ti_flags = 0; 2043#if NVLAN > 0 2044 if (ifv != NULL) { 2045 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2046 f->ti_vlan_tag = ifv->ifv_tag; 2047 } else { 2048 f->ti_vlan_tag = 0; 2049 } 2050#endif 2051 cur = frag; 2052 TI_INC(frag, TI_TX_RING_CNT); 2053 } 2054 } 2055 2056 if (m != NULL) 2057 return(ENOBUFS); 2058 2059 if (sc->ti_hwrev == TI_HWREV_TIGON) 2060 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2061 TI_BDFLAG_END; 2062 else 2063 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2064 sc->ti_cdata.ti_tx_chain[*txidx] = m_head; 2065 2066 *txidx = frag; 2067 2068 return(0); 2069} 2070 2071/* 2072 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2073 * to the mbuf data regions directly in the transmit descriptors. 2074 */ 2075static void ti_start(ifp) 2076 struct ifnet *ifp; 2077{ 2078 struct ti_softc *sc; 2079 struct mbuf *m_head = NULL; 2080 u_int32_t prodidx = 0; 2081 2082 sc = ifp->if_softc; 2083 2084 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2085 2086 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2087 IF_DEQUEUE(&ifp->if_snd, m_head); 2088 if (m_head == NULL) 2089 break; 2090 2091 /* 2092 * Pack the data into the transmit ring. If we 2093 * don't have room, set the OACTIVE flag and wait 2094 * for the NIC to drain the ring. 2095 */ 2096 if (ti_encap(sc, m_head, &prodidx)) { 2097 IF_PREPEND(&ifp->if_snd, m_head); 2098 ifp->if_flags |= IFF_OACTIVE; 2099 break; 2100 } 2101 2102 /* 2103 * If there's a BPF listener, bounce a copy of this frame 2104 * to him. 2105 */ 2106#if NBPFILTER > 0 2107 if (ifp->if_bpf) 2108 bpf_mtap(ifp, m_head); 2109#endif 2110 } 2111 2112 /* Transmit */ 2113 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2114 2115 /* 2116 * Set a timeout in case the chip goes out to lunch. 2117 */ 2118 ifp->if_timer = 5; 2119 2120 return; 2121} 2122 2123static void ti_init(xsc) 2124 void *xsc; 2125{ 2126 struct ti_softc *sc = xsc; 2127 int s; 2128 2129 s = splimp(); 2130 2131 /* Cancel pending I/O and flush buffers. */ 2132 ti_stop(sc); 2133 2134 /* Init the gen info block, ring control blocks and firmware. */ 2135 if (ti_gibinit(sc)) { 2136 printf("ti%d: initialization failure\n", sc->ti_unit); 2137 splx(s); 2138 return; 2139 } 2140 2141 splx(s); 2142 2143 return; 2144} 2145 2146static void ti_init2(sc) 2147 struct ti_softc *sc; 2148{ 2149 struct ti_cmd_desc cmd; 2150 struct ifnet *ifp; 2151 u_int16_t *m; 2152 struct ifmedia *ifm; 2153 int tmp; 2154 2155 ifp = &sc->arpcom.ac_if; 2156 2157 /* Specify MTU and interface index. */ 2158 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2159 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2160 ETHER_HDR_LEN + ETHER_CRC_LEN); 2161 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2162 2163 /* Load our MAC address. */ 2164 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2165 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2166 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2167 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2168 2169 /* Enable or disable promiscuous mode as needed. */ 2170 if (ifp->if_flags & IFF_PROMISC) { 2171 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2172 } else { 2173 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2174 } 2175 2176 /* Program multicast filter. */ 2177 ti_setmulti(sc); 2178 2179 /* 2180 * If this is a Tigon 1, we should tell the 2181 * firmware to use software packet filtering. 2182 */ 2183 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2184 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2185 } 2186 2187 /* Init RX ring. */ 2188 ti_init_rx_ring_std(sc); 2189 2190 /* Init jumbo RX ring. */ 2191 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2192 ti_init_rx_ring_jumbo(sc); 2193 2194 /* 2195 * If this is a Tigon 2, we can also configure the 2196 * mini ring. 2197 */ 2198 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2199 ti_init_rx_ring_mini(sc); 2200 2201 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2202 sc->ti_rx_saved_considx = 0; 2203 2204 /* Init TX ring. */ 2205 ti_init_tx_ring(sc); 2206 2207 /* Tell firmware we're alive. */ 2208 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2209 2210 /* Enable host interrupts. */ 2211 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2212 2213 ifp->if_flags |= IFF_RUNNING; 2214 ifp->if_flags &= ~IFF_OACTIVE; 2215 2216 /* 2217 * Make sure to set media properly. We have to do this 2218 * here since we have to issue commands in order to set 2219 * the link negotiation and we can't issue commands until 2220 * the firmware is running. 2221 */ 2222 ifm = &sc->ifmedia; 2223 tmp = ifm->ifm_media; 2224 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2225 ti_ifmedia_upd(ifp); 2226 ifm->ifm_media = tmp; 2227 2228 return; 2229} 2230 2231/* 2232 * Set media options. 2233 */ 2234static int ti_ifmedia_upd(ifp) 2235 struct ifnet *ifp; 2236{ 2237 struct ti_softc *sc; 2238 struct ifmedia *ifm; 2239 struct ti_cmd_desc cmd; 2240 2241 sc = ifp->if_softc; 2242 ifm = &sc->ifmedia; 2243 2244 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2245 return(EINVAL); 2246 2247 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2248 case IFM_AUTO: 2249 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2250 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2251 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2252 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2253 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2254 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2255 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2256 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2257 break; 2258 case IFM_1000_SX: 2259 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2260 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2261 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2262 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2263 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2264 break; 2265 case IFM_100_FX: 2266 case IFM_10_FL: 2267 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2268 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2269 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2270 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2271 } else { 2272 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2273 } 2274 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2275 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2276 } else { 2277 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2278 } 2279 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2280 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2281 break; 2282 } 2283 2284 return(0); 2285} 2286 2287/* 2288 * Report current media status. 2289 */ 2290static void ti_ifmedia_sts(ifp, ifmr) 2291 struct ifnet *ifp; 2292 struct ifmediareq *ifmr; 2293{ 2294 struct ti_softc *sc; 2295 2296 sc = ifp->if_softc; 2297 2298 ifmr->ifm_status = IFM_AVALID; 2299 ifmr->ifm_active = IFM_ETHER; 2300 2301 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2302 return; 2303 2304 ifmr->ifm_status |= IFM_ACTIVE; 2305 2306 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2307 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2308 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2309 u_int32_t media; 2310 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2311 if (media & TI_LNK_100MB) 2312 ifmr->ifm_active |= IFM_100_FX; 2313 if (media & TI_LNK_10MB) 2314 ifmr->ifm_active |= IFM_10_FL; 2315 if (media & TI_LNK_FULL_DUPLEX) 2316 ifmr->ifm_active |= IFM_FDX; 2317 if (media & TI_LNK_HALF_DUPLEX) 2318 ifmr->ifm_active |= IFM_HDX; 2319 } 2320 2321 return; 2322} 2323 2324static int ti_ioctl(ifp, command, data) 2325 struct ifnet *ifp; 2326 u_long command; 2327 caddr_t data; 2328{ 2329 struct ti_softc *sc = ifp->if_softc; 2330 struct ifreq *ifr = (struct ifreq *) data; 2331 int s, error = 0; 2332 struct ti_cmd_desc cmd; 2333 2334 s = splimp(); 2335 2336 switch(command) { 2337 case SIOCSIFADDR: 2338 case SIOCGIFADDR: 2339 error = ether_ioctl(ifp, command, data); 2340 break; 2341 case SIOCSIFMTU: 2342 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2343 error = EINVAL; 2344 else { 2345 ifp->if_mtu = ifr->ifr_mtu; 2346 ti_init(sc); 2347 } 2348 break; 2349 case SIOCSIFFLAGS: 2350 if (ifp->if_flags & IFF_UP) { 2351 /* 2352 * If only the state of the PROMISC flag changed, 2353 * then just use the 'set promisc mode' command 2354 * instead of reinitializing the entire NIC. Doing 2355 * a full re-init means reloading the firmware and 2356 * waiting for it to start up, which may take a 2357 * second or two. 2358 */ 2359 if (ifp->if_flags & IFF_RUNNING && 2360 ifp->if_flags & IFF_PROMISC && 2361 !(sc->ti_if_flags & IFF_PROMISC)) { 2362 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2363 TI_CMD_CODE_PROMISC_ENB, 0); 2364 } else if (ifp->if_flags & IFF_RUNNING && 2365 !(ifp->if_flags & IFF_PROMISC) && 2366 sc->ti_if_flags & IFF_PROMISC) { 2367 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2368 TI_CMD_CODE_PROMISC_DIS, 0); 2369 } else 2370 ti_init(sc); 2371 } else { 2372 if (ifp->if_flags & IFF_RUNNING) { 2373 ti_stop(sc); 2374 } 2375 } 2376 sc->ti_if_flags = ifp->if_flags; 2377 error = 0; 2378 break; 2379 case SIOCADDMULTI: 2380 case SIOCDELMULTI: 2381 if (ifp->if_flags & IFF_RUNNING) { 2382 ti_setmulti(sc); 2383 error = 0; 2384 } 2385 break; 2386 case SIOCSIFMEDIA: 2387 case SIOCGIFMEDIA: 2388 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2389 break; 2390 default: 2391 error = EINVAL; 2392 break; 2393 } 2394 2395 (void)splx(s); 2396 2397 return(error); 2398} 2399 2400static void ti_watchdog(ifp) 2401 struct ifnet *ifp; 2402{ 2403 struct ti_softc *sc; 2404 2405 sc = ifp->if_softc; 2406 2407 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2408 ti_stop(sc); 2409 ti_init(sc); 2410 2411 ifp->if_oerrors++; 2412 2413 return; 2414} 2415 2416/* 2417 * Stop the adapter and free any mbufs allocated to the 2418 * RX and TX lists. 2419 */ 2420static void ti_stop(sc) 2421 struct ti_softc *sc; 2422{ 2423 struct ifnet *ifp; 2424 struct ti_cmd_desc cmd; 2425 2426 ifp = &sc->arpcom.ac_if; 2427 2428 /* Disable host interrupts. */ 2429 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2430 /* 2431 * Tell firmware we're shutting down. 2432 */ 2433 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2434 2435 /* Halt and reinitialize. */ 2436 ti_chipinit(sc); 2437 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2438 ti_chipinit(sc); 2439 2440 /* Free the RX lists. */ 2441 ti_free_rx_ring_std(sc); 2442 2443 /* Free jumbo RX list. */ 2444 ti_free_rx_ring_jumbo(sc); 2445 2446 /* Free mini RX list. */ 2447 ti_free_rx_ring_mini(sc); 2448 2449 /* Free TX buffers. */ 2450 ti_free_tx_ring(sc); 2451 2452 sc->ti_ev_prodidx.ti_idx = 0; 2453 sc->ti_return_prodidx.ti_idx = 0; 2454 sc->ti_tx_considx.ti_idx = 0; 2455 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2456 2457 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2458 2459 return; 2460} 2461 2462/* 2463 * Stop all chip I/O so that the kernel's probe routines don't 2464 * get confused by errant DMAs when rebooting. 2465 */ 2466static void ti_shutdown(howto, xsc) 2467 int howto; 2468 void *xsc; 2469{ 2470 struct ti_softc *sc; 2471 2472 sc = xsc; 2473 2474 ti_chipinit(sc); 2475 2476 return; 2477} 2478 2479static struct pci_device ti_device = { 2480 "ti", 2481 ti_probe, 2482 ti_attach, 2483 &ti_count, 2484 NULL 2485}; 2486DATA_SET(pcidevice_set, ti_device); 2487