if_ti.c revision 227512
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 227512 2011-11-14 20:38:14Z yongari $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#ifdef TI_SF_BUF_JUMBO 116#include <vm/vm.h> 117#include <vm/vm_page.h> 118#endif 119 120#include <dev/pci/pcireg.h> 121#include <dev/pci/pcivar.h> 122 123#include <sys/tiio.h> 124#include <dev/ti/if_tireg.h> 125#include <dev/ti/ti_fw.h> 126#include <dev/ti/ti_fw2.h> 127 128#include <sys/sysctl.h> 129 130#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 131/* 132 * We can only turn on header splitting if we're using extended receive 133 * BDs. 134 */ 135#if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 136#error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 137#endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 138 139typedef enum { 140 TI_SWAP_HTON, 141 TI_SWAP_NTOH 142} ti_swap_type; 143 144/* 145 * Various supported device vendors/types and their names. 146 */ 147 148static const struct ti_type const ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static void ti_stats_update(struct ti_softc *); 187static int ti_encap(struct ti_softc *, struct mbuf **); 188 189static void ti_intr(void *); 190static void ti_start(struct ifnet *); 191static void ti_start_locked(struct ifnet *); 192static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193static void ti_init(void *); 194static void ti_init_locked(void *); 195static void ti_init2(struct ti_softc *); 196static void ti_stop(struct ti_softc *); 197static void ti_watchdog(void *); 198static int ti_shutdown(device_t); 199static int ti_ifmedia_upd(struct ifnet *); 200static int ti_ifmedia_upd_locked(struct ti_softc *); 201static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 202 203static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 204static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 205static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 206 207static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 208static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 209static void ti_setmulti(struct ti_softc *); 210 211static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 212static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 213static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 214static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 215 int); 216static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 217 int, int, int); 218static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219static void ti_loadfw(struct ti_softc *); 220static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222static void ti_handle_events(struct ti_softc *); 223static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 224static int ti_dma_alloc(struct ti_softc *); 225static void ti_dma_free(struct ti_softc *); 226static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 227 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 228static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 229 bus_dmamap_t *); 230static int ti_newbuf_std(struct ti_softc *, int); 231static int ti_newbuf_mini(struct ti_softc *, int); 232static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 233static int ti_init_rx_ring_std(struct ti_softc *); 234static void ti_free_rx_ring_std(struct ti_softc *); 235static int ti_init_rx_ring_jumbo(struct ti_softc *); 236static void ti_free_rx_ring_jumbo(struct ti_softc *); 237static int ti_init_rx_ring_mini(struct ti_softc *); 238static void ti_free_rx_ring_mini(struct ti_softc *); 239static void ti_free_tx_ring(struct ti_softc *); 240static int ti_init_tx_ring(struct ti_softc *); 241static void ti_discard_std(struct ti_softc *, int); 242#ifndef TI_SF_BUF_JUMBO 243static void ti_discard_jumbo(struct ti_softc *, int); 244#endif 245static void ti_discard_mini(struct ti_softc *, int); 246 247static int ti_64bitslot_war(struct ti_softc *); 248static int ti_chipinit(struct ti_softc *); 249static int ti_gibinit(struct ti_softc *); 250 251#ifdef TI_JUMBO_HDRSPLIT 252static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 253 int idx); 254#endif /* TI_JUMBO_HDRSPLIT */ 255 256static void ti_sysctl_node(struct ti_softc *); 257 258static device_method_t ti_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, ti_probe), 261 DEVMETHOD(device_attach, ti_attach), 262 DEVMETHOD(device_detach, ti_detach), 263 DEVMETHOD(device_shutdown, ti_shutdown), 264 { 0, 0 } 265}; 266 267static driver_t ti_driver = { 268 "ti", 269 ti_methods, 270 sizeof(struct ti_softc) 271}; 272 273static devclass_t ti_devclass; 274 275DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 276MODULE_DEPEND(ti, pci, 1, 1, 1); 277MODULE_DEPEND(ti, ether, 1, 1, 1); 278 279/* 280 * Send an instruction or address to the EEPROM, check for ACK. 281 */ 282static uint32_t 283ti_eeprom_putbyte(struct ti_softc *sc, int byte) 284{ 285 int i, ack = 0; 286 287 /* 288 * Make sure we're in TX mode. 289 */ 290 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 291 292 /* 293 * Feed in each bit and stobe the clock. 294 */ 295 for (i = 0x80; i; i >>= 1) { 296 if (byte & i) { 297 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 298 } else { 299 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 300 } 301 DELAY(1); 302 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 303 DELAY(1); 304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 305 } 306 307 /* 308 * Turn off TX mode. 309 */ 310 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 311 312 /* 313 * Check for ack. 314 */ 315 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 316 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 318 319 return (ack); 320} 321 322/* 323 * Read a byte of data stored in the EEPROM at address 'addr.' 324 * We have to send two address bytes since the EEPROM can hold 325 * more than 256 bytes of data. 326 */ 327static uint8_t 328ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 329{ 330 int i; 331 uint8_t byte = 0; 332 333 EEPROM_START; 334 335 /* 336 * Send write control code to EEPROM. 337 */ 338 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 339 device_printf(sc->ti_dev, 340 "failed to send write command, status: %x\n", 341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 342 return (1); 343 } 344 345 /* 346 * Send first byte of address of byte we want to read. 347 */ 348 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 349 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 /* 354 * Send second byte address of byte we want to read. 355 */ 356 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 357 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 358 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 359 return (1); 360 } 361 362 EEPROM_STOP; 363 EEPROM_START; 364 /* 365 * Send read control code to EEPROM. 366 */ 367 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 368 device_printf(sc->ti_dev, 369 "failed to send read command, status: %x\n", 370 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 371 return (1); 372 } 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 378 for (i = 0x80; i; i >>= 1) { 379 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 380 DELAY(1); 381 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 382 byte |= i; 383 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 384 DELAY(1); 385 } 386 387 EEPROM_STOP; 388 389 /* 390 * No ACK generated for read, so just return byte. 391 */ 392 393 *dest = byte; 394 395 return (0); 396} 397 398/* 399 * Read a sequence of bytes from the EEPROM. 400 */ 401static int 402ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 403{ 404 int err = 0, i; 405 uint8_t byte = 0; 406 407 for (i = 0; i < cnt; i++) { 408 err = ti_eeprom_getbyte(sc, off + i, &byte); 409 if (err) 410 break; 411 *(dest + i) = byte; 412 } 413 414 return (err ? 1 : 0); 415} 416 417/* 418 * NIC memory read function. 419 * Can be used to copy data from NIC local memory. 420 */ 421static void 422ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 423{ 424 int segptr, segsize, cnt; 425 char *ptr; 426 427 segptr = addr; 428 cnt = len; 429 ptr = buf; 430 431 while (cnt) { 432 if (cnt < TI_WINLEN) 433 segsize = cnt; 434 else 435 segsize = TI_WINLEN - (segptr % TI_WINLEN); 436 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 437 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 438 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 439 segsize / 4); 440 ptr += segsize; 441 segptr += segsize; 442 cnt -= segsize; 443 } 444} 445 446 447/* 448 * NIC memory write function. 449 * Can be used to copy data into NIC local memory. 450 */ 451static void 452ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 453{ 454 int segptr, segsize, cnt; 455 char *ptr; 456 457 segptr = addr; 458 cnt = len; 459 ptr = buf; 460 461 while (cnt) { 462 if (cnt < TI_WINLEN) 463 segsize = cnt; 464 else 465 segsize = TI_WINLEN - (segptr % TI_WINLEN); 466 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 467 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 468 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 469 segsize / 4); 470 ptr += segsize; 471 segptr += segsize; 472 cnt -= segsize; 473 } 474} 475 476/* 477 * NIC memory read function. 478 * Can be used to clear a section of NIC local memory. 479 */ 480static void 481ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 482{ 483 int segptr, segsize, cnt; 484 485 segptr = addr; 486 cnt = len; 487 488 while (cnt) { 489 if (cnt < TI_WINLEN) 490 segsize = cnt; 491 else 492 segsize = TI_WINLEN - (segptr % TI_WINLEN); 493 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 494 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 495 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 496 segptr += segsize; 497 cnt -= segsize; 498 } 499} 500 501static int 502ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 503 caddr_t buf, int useraddr, int readdata) 504{ 505 int segptr, segsize, cnt; 506 caddr_t ptr; 507 uint32_t origwin; 508 int resid, segresid; 509 int first_pass; 510 511 TI_LOCK_ASSERT(sc); 512 513 /* 514 * At the moment, we don't handle non-aligned cases, we just bail. 515 * If this proves to be a problem, it will be fixed. 516 */ 517 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 518 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 519 "word-aligned\n", __func__, tigon_addr); 520 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 521 "yet supported\n", __func__); 522 return (EINVAL); 523 } 524 525 segptr = tigon_addr & ~0x3; 526 segresid = tigon_addr - segptr; 527 528 /* 529 * This is the non-aligned amount left over that we'll need to 530 * copy. 531 */ 532 resid = len & 0x3; 533 534 /* Add in the left over amount at the front of the buffer */ 535 resid += segresid; 536 537 cnt = len & ~0x3; 538 /* 539 * If resid + segresid is >= 4, add multiples of 4 to the count and 540 * decrease the residual by that much. 541 */ 542 cnt += resid & ~0x3; 543 resid -= resid & ~0x3; 544 545 ptr = buf; 546 547 first_pass = 1; 548 549 /* 550 * Save the old window base value. 551 */ 552 origwin = CSR_READ_4(sc, TI_WINBASE); 553 554 while (cnt) { 555 bus_size_t ti_offset; 556 557 if (cnt < TI_WINLEN) 558 segsize = cnt; 559 else 560 segsize = TI_WINLEN - (segptr % TI_WINLEN); 561 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 562 563 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 564 565 if (readdata) { 566 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 567 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 568 if (useraddr) { 569 /* 570 * Yeah, this is a little on the kludgy 571 * side, but at least this code is only 572 * used for debugging. 573 */ 574 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 575 segsize, TI_SWAP_NTOH); 576 577 TI_UNLOCK(sc); 578 if (first_pass) { 579 copyout(&sc->ti_membuf2[segresid], ptr, 580 segsize - segresid); 581 first_pass = 0; 582 } else 583 copyout(sc->ti_membuf2, ptr, segsize); 584 TI_LOCK(sc); 585 } else { 586 if (first_pass) { 587 588 ti_bcopy_swap(sc->ti_membuf, 589 sc->ti_membuf2, segsize, 590 TI_SWAP_NTOH); 591 TI_UNLOCK(sc); 592 bcopy(&sc->ti_membuf2[segresid], ptr, 593 segsize - segresid); 594 TI_LOCK(sc); 595 first_pass = 0; 596 } else 597 ti_bcopy_swap(sc->ti_membuf, ptr, 598 segsize, TI_SWAP_NTOH); 599 } 600 601 } else { 602 if (useraddr) { 603 TI_UNLOCK(sc); 604 copyin(ptr, sc->ti_membuf2, segsize); 605 TI_LOCK(sc); 606 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 607 segsize, TI_SWAP_HTON); 608 } else 609 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 610 TI_SWAP_HTON); 611 612 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 613 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 614 } 615 segptr += segsize; 616 ptr += segsize; 617 cnt -= segsize; 618 } 619 620 /* 621 * Handle leftover, non-word-aligned bytes. 622 */ 623 if (resid != 0) { 624 uint32_t tmpval, tmpval2; 625 bus_size_t ti_offset; 626 627 /* 628 * Set the segment pointer. 629 */ 630 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 631 632 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 633 634 /* 635 * First, grab whatever is in our source/destination. 636 * We'll obviously need this for reads, but also for 637 * writes, since we'll be doing read/modify/write. 638 */ 639 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 640 ti_offset, &tmpval, 1); 641 642 /* 643 * Next, translate this from little-endian to big-endian 644 * (at least on i386 boxes). 645 */ 646 tmpval2 = ntohl(tmpval); 647 648 if (readdata) { 649 /* 650 * If we're reading, just copy the leftover number 651 * of bytes from the host byte order buffer to 652 * the user's buffer. 653 */ 654 if (useraddr) { 655 TI_UNLOCK(sc); 656 copyout(&tmpval2, ptr, resid); 657 TI_LOCK(sc); 658 } else 659 bcopy(&tmpval2, ptr, resid); 660 } else { 661 /* 662 * If we're writing, first copy the bytes to be 663 * written into the network byte order buffer, 664 * leaving the rest of the buffer with whatever was 665 * originally in there. Then, swap the bytes 666 * around into host order and write them out. 667 * 668 * XXX KDM the read side of this has been verified 669 * to work, but the write side of it has not been 670 * verified. So user beware. 671 */ 672 if (useraddr) { 673 TI_UNLOCK(sc); 674 copyin(ptr, &tmpval2, resid); 675 TI_LOCK(sc); 676 } else 677 bcopy(ptr, &tmpval2, resid); 678 679 tmpval = htonl(tmpval2); 680 681 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 682 ti_offset, &tmpval, 1); 683 } 684 } 685 686 CSR_WRITE_4(sc, TI_WINBASE, origwin); 687 688 return (0); 689} 690 691static int 692ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 693 caddr_t buf, int useraddr, int readdata, int cpu) 694{ 695 uint32_t segptr; 696 int cnt; 697 uint32_t tmpval, tmpval2; 698 caddr_t ptr; 699 700 TI_LOCK_ASSERT(sc); 701 702 /* 703 * At the moment, we don't handle non-aligned cases, we just bail. 704 * If this proves to be a problem, it will be fixed. 705 */ 706 if (tigon_addr & 0x3) { 707 device_printf(sc->ti_dev, "%s: tigon address %#x " 708 "isn't word-aligned\n", __func__, tigon_addr); 709 return (EINVAL); 710 } 711 712 if (len & 0x3) { 713 device_printf(sc->ti_dev, "%s: transfer length %d " 714 "isn't word-aligned\n", __func__, len); 715 return (EINVAL); 716 } 717 718 segptr = tigon_addr; 719 cnt = len; 720 ptr = buf; 721 722 while (cnt) { 723 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 724 725 if (readdata) { 726 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 727 728 tmpval = ntohl(tmpval2); 729 730 /* 731 * Note: I've used this debugging interface 732 * extensively with Alteon's 12.3.15 firmware, 733 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 734 * 735 * When you compile the firmware without 736 * optimization, which is necessary sometimes in 737 * order to properly step through it, you sometimes 738 * read out a bogus value of 0xc0017c instead of 739 * whatever was supposed to be in that scratchpad 740 * location. That value is on the stack somewhere, 741 * but I've never been able to figure out what was 742 * causing the problem. 743 * 744 * The address seems to pop up in random places, 745 * often not in the same place on two subsequent 746 * reads. 747 * 748 * In any case, the underlying data doesn't seem 749 * to be affected, just the value read out. 750 * 751 * KDM, 3/7/2000 752 */ 753 754 if (tmpval2 == 0xc0017c) 755 device_printf(sc->ti_dev, "found 0xc0017c at " 756 "%#x (tmpval2)\n", segptr); 757 758 if (tmpval == 0xc0017c) 759 device_printf(sc->ti_dev, "found 0xc0017c at " 760 "%#x (tmpval)\n", segptr); 761 762 if (useraddr) 763 copyout(&tmpval, ptr, 4); 764 else 765 bcopy(&tmpval, ptr, 4); 766 } else { 767 if (useraddr) 768 copyin(ptr, &tmpval2, 4); 769 else 770 bcopy(ptr, &tmpval2, 4); 771 772 tmpval = htonl(tmpval2); 773 774 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 775 } 776 777 cnt -= 4; 778 segptr += 4; 779 ptr += 4; 780 } 781 782 return (0); 783} 784 785static int 786ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 787{ 788 const uint8_t *tmpsrc; 789 uint8_t *tmpdst; 790 size_t tmplen; 791 792 if (len & 0x3) { 793 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 794 return (-1); 795 } 796 797 tmpsrc = src; 798 tmpdst = dst; 799 tmplen = len; 800 801 while (tmplen) { 802 if (swap_type == TI_SWAP_NTOH) 803 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 804 else 805 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 806 tmpsrc += 4; 807 tmpdst += 4; 808 tmplen -= 4; 809 } 810 811 return (0); 812} 813 814/* 815 * Load firmware image into the NIC. Check that the firmware revision 816 * is acceptable and see if we want the firmware for the Tigon 1 or 817 * Tigon 2. 818 */ 819static void 820ti_loadfw(struct ti_softc *sc) 821{ 822 823 TI_LOCK_ASSERT(sc); 824 825 switch (sc->ti_hwrev) { 826 case TI_HWREV_TIGON: 827 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 828 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 829 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 830 device_printf(sc->ti_dev, "firmware revision mismatch; " 831 "want %d.%d.%d, got %d.%d.%d\n", 832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 833 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 834 tigonFwReleaseMinor, tigonFwReleaseFix); 835 return; 836 } 837 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 838 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 839 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 840 tigonFwRodata); 841 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 842 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 844 break; 845 case TI_HWREV_TIGON_II: 846 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 847 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 848 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 849 device_printf(sc->ti_dev, "firmware revision mismatch; " 850 "want %d.%d.%d, got %d.%d.%d\n", 851 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 852 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 853 tigon2FwReleaseMinor, tigon2FwReleaseFix); 854 return; 855 } 856 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 857 tigon2FwText); 858 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 859 tigon2FwData); 860 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 861 tigon2FwRodata); 862 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 863 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 864 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 865 break; 866 default: 867 device_printf(sc->ti_dev, 868 "can't load firmware: unknown hardware rev\n"); 869 break; 870 } 871} 872 873/* 874 * Send the NIC a command via the command ring. 875 */ 876static void 877ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 878{ 879 int index; 880 881 index = sc->ti_cmd_saved_prodidx; 882 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 883 TI_INC(index, TI_CMD_RING_CNT); 884 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 885 sc->ti_cmd_saved_prodidx = index; 886} 887 888/* 889 * Send the NIC an extended command. The 'len' parameter specifies the 890 * number of command slots to include after the initial command. 891 */ 892static void 893ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 894{ 895 int index; 896 int i; 897 898 index = sc->ti_cmd_saved_prodidx; 899 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 900 TI_INC(index, TI_CMD_RING_CNT); 901 for (i = 0; i < len; i++) { 902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 903 *(uint32_t *)(&arg[i * 4])); 904 TI_INC(index, TI_CMD_RING_CNT); 905 } 906 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 907 sc->ti_cmd_saved_prodidx = index; 908} 909 910/* 911 * Handle events that have triggered interrupts. 912 */ 913static void 914ti_handle_events(struct ti_softc *sc) 915{ 916 struct ti_event_desc *e; 917 918 if (sc->ti_rdata.ti_event_ring == NULL) 919 return; 920 921 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 922 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 924 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 925 switch (TI_EVENT_EVENT(e)) { 926 case TI_EV_LINKSTAT_CHANGED: 927 sc->ti_linkstat = TI_EVENT_CODE(e); 928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 930 sc->ti_ifp->if_baudrate = IF_Mbps(100); 931 if (bootverbose) 932 device_printf(sc->ti_dev, 933 "10/100 link up\n"); 934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 937 if (bootverbose) 938 device_printf(sc->ti_dev, 939 "gigabit link up\n"); 940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 941 if_link_state_change(sc->ti_ifp, 942 LINK_STATE_DOWN); 943 sc->ti_ifp->if_baudrate = 0; 944 if (bootverbose) 945 device_printf(sc->ti_dev, 946 "link down\n"); 947 } 948 break; 949 case TI_EV_ERROR: 950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 951 device_printf(sc->ti_dev, "invalid command\n"); 952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 953 device_printf(sc->ti_dev, "unknown command\n"); 954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 955 device_printf(sc->ti_dev, "bad config data\n"); 956 break; 957 case TI_EV_FIRMWARE_UP: 958 ti_init2(sc); 959 break; 960 case TI_EV_STATS_UPDATED: 961 ti_stats_update(sc); 962 break; 963 case TI_EV_RESET_JUMBO_RING: 964 case TI_EV_MCAST_UPDATED: 965 /* Who cares. */ 966 break; 967 default: 968 device_printf(sc->ti_dev, "unknown event: %d\n", 969 TI_EVENT_EVENT(e)); 970 break; 971 } 972 /* Advance the consumer index. */ 973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 975 } 976 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 977 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 978} 979 980struct ti_dmamap_arg { 981 bus_addr_t ti_busaddr; 982}; 983 984static void 985ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 986{ 987 struct ti_dmamap_arg *ctx; 988 989 if (error) 990 return; 991 992 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 993 994 ctx = arg; 995 ctx->ti_busaddr = segs->ds_addr; 996} 997 998static int 999ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 1000 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1001 const char *msg) 1002{ 1003 struct ti_dmamap_arg ctx; 1004 int error; 1005 1006 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1007 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1008 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1009 if (error != 0) { 1010 device_printf(sc->ti_dev, 1011 "could not create %s dma tag\n", msg); 1012 return (error); 1013 } 1014 /* Allocate DMA'able memory for ring. */ 1015 error = bus_dmamem_alloc(*tag, (void **)ring, 1016 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1017 if (error != 0) { 1018 device_printf(sc->ti_dev, 1019 "could not allocate DMA'able memory for %s\n", msg); 1020 return (error); 1021 } 1022 /* Load the address of the ring. */ 1023 ctx.ti_busaddr = 0; 1024 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1025 &ctx, BUS_DMA_NOWAIT); 1026 if (error != 0) { 1027 device_printf(sc->ti_dev, 1028 "could not load DMA'able memory for %s\n", msg); 1029 return (error); 1030 } 1031 *paddr = ctx.ti_busaddr; 1032 return (0); 1033} 1034 1035static void 1036ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1037 bus_dmamap_t *map) 1038{ 1039 1040 if (*map != NULL) 1041 bus_dmamap_unload(*tag, *map); 1042 if (*map != NULL && *ring != NULL) { 1043 bus_dmamem_free(*tag, *ring, *map); 1044 *ring = NULL; 1045 *map = NULL; 1046 } 1047 if (*tag) { 1048 bus_dma_tag_destroy(*tag); 1049 *tag = NULL; 1050 } 1051} 1052 1053static int 1054ti_dma_alloc(struct ti_softc *sc) 1055{ 1056 bus_addr_t lowaddr; 1057 int i, error; 1058 1059 lowaddr = BUS_SPACE_MAXADDR; 1060 if (sc->ti_dac == 0) 1061 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1062 1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1064 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1065 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1066 &sc->ti_cdata.ti_parent_tag); 1067 if (error != 0) { 1068 device_printf(sc->ti_dev, 1069 "could not allocate parent dma tag\n"); 1070 return (ENOMEM); 1071 } 1072 1073 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1074 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1075 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1076 if (error) 1077 return (error); 1078 1079 /* Producer/consumer status */ 1080 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1081 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1082 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1083 "event ring"); 1084 if (error) 1085 return (error); 1086 1087 /* Event ring */ 1088 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1089 &sc->ti_cdata.ti_event_ring_tag, 1090 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1091 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1092 "event ring"); 1093 if (error) 1094 return (error); 1095 1096 /* Command ring lives in shared memory so no need to create DMA area. */ 1097 1098 /* Standard RX ring */ 1099 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1100 &sc->ti_cdata.ti_rx_std_ring_tag, 1101 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1102 &sc->ti_cdata.ti_rx_std_ring_map, 1103 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1104 if (error) 1105 return (error); 1106 1107 /* Jumbo RX ring */ 1108 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1109 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1110 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1111 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1112 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1113 if (error) 1114 return (error); 1115 1116 /* RX return ring */ 1117 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1118 &sc->ti_cdata.ti_rx_return_ring_tag, 1119 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1120 &sc->ti_cdata.ti_rx_return_ring_map, 1121 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1122 if (error) 1123 return (error); 1124 1125 /* Create DMA tag for standard RX mbufs. */ 1126 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1128 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1129 if (error) { 1130 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1131 return (error); 1132 } 1133 1134 /* Create DMA tag for jumbo RX mbufs. */ 1135#ifdef TI_SF_BUF_JUMBO 1136 /* 1137 * The VM system will take care of providing aligned pages. Alignment 1138 * is set to 1 here so that busdma resources won't be wasted. 1139 */ 1140 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1141 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1142 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1143#else 1144 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1146 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1147#endif 1148 if (error) { 1149 device_printf(sc->ti_dev, 1150 "could not allocate jumbo RX dma tag\n"); 1151 return (error); 1152 } 1153 1154 /* Create DMA tag for TX mbufs. */ 1155 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1156 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1157 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1158 &sc->ti_cdata.ti_tx_tag); 1159 if (error) { 1160 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1161 return (ENOMEM); 1162 } 1163 1164 /* Create DMA maps for RX buffers. */ 1165 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1166 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1167 &sc->ti_cdata.ti_rx_std_maps[i]); 1168 if (error) { 1169 device_printf(sc->ti_dev, 1170 "could not create DMA map for RX\n"); 1171 return (error); 1172 } 1173 } 1174 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1175 &sc->ti_cdata.ti_rx_std_sparemap); 1176 if (error) { 1177 device_printf(sc->ti_dev, 1178 "could not create spare DMA map for RX\n"); 1179 return (error); 1180 } 1181 1182 /* Create DMA maps for jumbo RX buffers. */ 1183 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1184 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1185 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1186 if (error) { 1187 device_printf(sc->ti_dev, 1188 "could not create DMA map for jumbo RX\n"); 1189 return (error); 1190 } 1191 } 1192 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1193 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1194 if (error) { 1195 device_printf(sc->ti_dev, 1196 "could not create spare DMA map for jumbo RX\n"); 1197 return (error); 1198 } 1199 1200 /* Create DMA maps for TX buffers. */ 1201 for (i = 0; i < TI_TX_RING_CNT; i++) { 1202 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1203 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1204 if (error) { 1205 device_printf(sc->ti_dev, 1206 "could not create DMA map for TX\n"); 1207 return (ENOMEM); 1208 } 1209 } 1210 1211 /* Mini ring and TX ring is not available on Tigon 1. */ 1212 if (sc->ti_hwrev == TI_HWREV_TIGON) 1213 return (0); 1214 1215 /* TX ring */ 1216 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1217 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1218 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1219 "TX ring"); 1220 if (error) 1221 return (error); 1222 1223 /* Mini RX ring */ 1224 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1225 &sc->ti_cdata.ti_rx_mini_ring_tag, 1226 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1227 &sc->ti_cdata.ti_rx_mini_ring_map, 1228 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1229 if (error) 1230 return (error); 1231 1232 /* Create DMA tag for mini RX mbufs. */ 1233 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1235 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1236 if (error) { 1237 device_printf(sc->ti_dev, 1238 "could not allocate mini RX dma tag\n"); 1239 return (error); 1240 } 1241 1242 /* Create DMA maps for mini RX buffers. */ 1243 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1244 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1245 &sc->ti_cdata.ti_rx_mini_maps[i]); 1246 if (error) { 1247 device_printf(sc->ti_dev, 1248 "could not create DMA map for mini RX\n"); 1249 return (error); 1250 } 1251 } 1252 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1253 &sc->ti_cdata.ti_rx_mini_sparemap); 1254 if (error) { 1255 device_printf(sc->ti_dev, 1256 "could not create spare DMA map for mini RX\n"); 1257 return (error); 1258 } 1259 1260 return (0); 1261} 1262 1263static void 1264ti_dma_free(struct ti_softc *sc) 1265{ 1266 int i; 1267 1268 /* Destroy DMA maps for RX buffers. */ 1269 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1270 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1271 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1272 sc->ti_cdata.ti_rx_std_maps[i]); 1273 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1274 } 1275 } 1276 if (sc->ti_cdata.ti_rx_std_sparemap) { 1277 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1278 sc->ti_cdata.ti_rx_std_sparemap); 1279 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1280 } 1281 if (sc->ti_cdata.ti_rx_std_tag) { 1282 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1283 sc->ti_cdata.ti_rx_std_tag = NULL; 1284 } 1285 1286 /* Destroy DMA maps for jumbo RX buffers. */ 1287 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1288 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1289 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1290 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1291 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1292 } 1293 } 1294 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1295 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1296 sc->ti_cdata.ti_rx_jumbo_sparemap); 1297 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1298 } 1299 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1300 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1301 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1302 } 1303 1304 /* Destroy DMA maps for mini RX buffers. */ 1305 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1306 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1307 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1308 sc->ti_cdata.ti_rx_mini_maps[i]); 1309 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1310 } 1311 } 1312 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1313 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1314 sc->ti_cdata.ti_rx_mini_sparemap); 1315 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1316 } 1317 if (sc->ti_cdata.ti_rx_mini_tag) { 1318 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1319 sc->ti_cdata.ti_rx_mini_tag = NULL; 1320 } 1321 1322 /* Destroy DMA maps for TX buffers. */ 1323 for (i = 0; i < TI_TX_RING_CNT; i++) { 1324 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1325 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1326 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1327 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1328 } 1329 } 1330 if (sc->ti_cdata.ti_tx_tag) { 1331 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1332 sc->ti_cdata.ti_tx_tag = NULL; 1333 } 1334 1335 /* Destroy standard RX ring. */ 1336 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1337 (void *)&sc->ti_rdata.ti_rx_std_ring, 1338 &sc->ti_cdata.ti_rx_std_ring_map); 1339 /* Destroy jumbo RX ring. */ 1340 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1341 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1342 &sc->ti_cdata.ti_rx_jumbo_ring_map); 1343 /* Destroy mini RX ring. */ 1344 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1345 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1346 &sc->ti_cdata.ti_rx_mini_ring_map); 1347 /* Destroy RX return ring. */ 1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1349 (void *)&sc->ti_rdata.ti_rx_return_ring, 1350 &sc->ti_cdata.ti_rx_return_ring_map); 1351 /* Destroy TX ring. */ 1352 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1353 (void *)&sc->ti_rdata.ti_tx_ring, &sc->ti_cdata.ti_tx_ring_map); 1354 /* Destroy status block. */ 1355 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1356 (void *)&sc->ti_rdata.ti_status, &sc->ti_cdata.ti_status_map); 1357 /* Destroy event ring. */ 1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1359 (void *)&sc->ti_rdata.ti_event_ring, 1360 &sc->ti_cdata.ti_event_ring_map); 1361 /* Destroy GIB */ 1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1363 (void *)&sc->ti_rdata.ti_info, &sc->ti_cdata.ti_gib_map); 1364 1365 /* Destroy the parent tag. */ 1366 if (sc->ti_cdata.ti_parent_tag) { 1367 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1368 sc->ti_cdata.ti_parent_tag = NULL; 1369 } 1370} 1371 1372/* 1373 * Intialize a standard receive ring descriptor. 1374 */ 1375static int 1376ti_newbuf_std(struct ti_softc *sc, int i) 1377{ 1378 bus_dmamap_t map; 1379 bus_dma_segment_t segs[1]; 1380 struct mbuf *m; 1381 struct ti_rx_desc *r; 1382 int error, nsegs; 1383 1384 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1385 if (m == NULL) 1386 return (ENOBUFS); 1387 m->m_len = m->m_pkthdr.len = MCLBYTES; 1388 m_adj(m, ETHER_ALIGN); 1389 1390 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1391 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1392 if (error != 0) { 1393 m_freem(m); 1394 return (error); 1395 } 1396 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1397 1398 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1399 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1400 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1402 sc->ti_cdata.ti_rx_std_maps[i]); 1403 } 1404 1405 map = sc->ti_cdata.ti_rx_std_maps[i]; 1406 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1407 sc->ti_cdata.ti_rx_std_sparemap = map; 1408 sc->ti_cdata.ti_rx_std_chain[i] = m; 1409 1410 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1411 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1412 r->ti_len = segs[0].ds_len; 1413 r->ti_type = TI_BDTYPE_RECV_BD; 1414 r->ti_flags = 0; 1415 r->ti_vlan_tag = 0; 1416 r->ti_tcp_udp_cksum = 0; 1417 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1418 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1419 r->ti_idx = i; 1420 1421 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1422 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1423 return (0); 1424} 1425 1426/* 1427 * Intialize a mini receive ring descriptor. This only applies to 1428 * the Tigon 2. 1429 */ 1430static int 1431ti_newbuf_mini(struct ti_softc *sc, int i) 1432{ 1433 bus_dmamap_t map; 1434 bus_dma_segment_t segs[1]; 1435 struct mbuf *m; 1436 struct ti_rx_desc *r; 1437 int error, nsegs; 1438 1439 MGETHDR(m, M_DONTWAIT, MT_DATA); 1440 if (m == NULL) 1441 return (ENOBUFS); 1442 m->m_len = m->m_pkthdr.len = MHLEN; 1443 m_adj(m, ETHER_ALIGN); 1444 1445 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1446 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1447 if (error != 0) { 1448 m_freem(m); 1449 return (error); 1450 } 1451 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1452 1453 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1454 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1455 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1456 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1457 sc->ti_cdata.ti_rx_mini_maps[i]); 1458 } 1459 1460 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1461 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1462 sc->ti_cdata.ti_rx_mini_sparemap = map; 1463 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1464 1465 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1466 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1467 r->ti_len = segs[0].ds_len; 1468 r->ti_type = TI_BDTYPE_RECV_BD; 1469 r->ti_flags = TI_BDFLAG_MINI_RING; 1470 r->ti_vlan_tag = 0; 1471 r->ti_tcp_udp_cksum = 0; 1472 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1473 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1474 r->ti_idx = i; 1475 1476 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1477 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1478 return (0); 1479} 1480 1481#ifndef TI_SF_BUF_JUMBO 1482 1483/* 1484 * Initialize a jumbo receive ring descriptor. This allocates 1485 * a jumbo buffer from the pool managed internally by the driver. 1486 */ 1487static int 1488ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1489{ 1490 bus_dmamap_t map; 1491 bus_dma_segment_t segs[1]; 1492 struct mbuf *m; 1493 struct ti_rx_desc *r; 1494 int error, nsegs; 1495 1496 (void)dummy; 1497 1498 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1499 if (m == NULL) 1500 return (ENOBUFS); 1501 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1502 m_adj(m, ETHER_ALIGN); 1503 1504 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1505 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1506 if (error != 0) { 1507 m_freem(m); 1508 return (error); 1509 } 1510 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1511 1512 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1513 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1514 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1515 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1516 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1517 } 1518 1519 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1520 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1521 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1522 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1523 1524 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1525 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1526 r->ti_len = segs[0].ds_len; 1527 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1528 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1529 r->ti_vlan_tag = 0; 1530 r->ti_tcp_udp_cksum = 0; 1531 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1532 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1533 r->ti_idx = i; 1534 1535 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1536 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1537 return (0); 1538} 1539 1540#else 1541 1542#if (PAGE_SIZE == 4096) 1543#define NPAYLOAD 2 1544#else 1545#define NPAYLOAD 1 1546#endif 1547 1548#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1549#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1550#define NFS_HDR_LEN (UDP_HDR_LEN) 1551static int HDR_LEN = TCP_HDR_LEN; 1552 1553/* 1554 * Initialize a jumbo receive ring descriptor. This allocates 1555 * a jumbo buffer from the pool managed internally by the driver. 1556 */ 1557static int 1558ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1559{ 1560 bus_dmamap_t map; 1561 struct mbuf *cur, *m_new = NULL; 1562 struct mbuf *m[3] = {NULL, NULL, NULL}; 1563 struct ti_rx_desc_ext *r; 1564 vm_page_t frame; 1565 static int color; 1566 /* 1 extra buf to make nobufs easy*/ 1567 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1568 int i; 1569 bus_dma_segment_t segs[4]; 1570 int nsegs; 1571 1572 if (m_old != NULL) { 1573 m_new = m_old; 1574 cur = m_old->m_next; 1575 for (i = 0; i <= NPAYLOAD; i++){ 1576 m[i] = cur; 1577 cur = cur->m_next; 1578 } 1579 } else { 1580 /* Allocate the mbufs. */ 1581 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1582 if (m_new == NULL) { 1583 device_printf(sc->ti_dev, "mbuf allocation failed " 1584 "-- packet dropped!\n"); 1585 goto nobufs; 1586 } 1587 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1588 if (m[NPAYLOAD] == NULL) { 1589 device_printf(sc->ti_dev, "cluster mbuf allocation " 1590 "failed -- packet dropped!\n"); 1591 goto nobufs; 1592 } 1593 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1594 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1595 device_printf(sc->ti_dev, "mbuf allocation failed " 1596 "-- packet dropped!\n"); 1597 goto nobufs; 1598 } 1599 m[NPAYLOAD]->m_len = MCLBYTES; 1600 1601 for (i = 0; i < NPAYLOAD; i++){ 1602 MGET(m[i], M_DONTWAIT, MT_DATA); 1603 if (m[i] == NULL) { 1604 device_printf(sc->ti_dev, "mbuf allocation " 1605 "failed -- packet dropped!\n"); 1606 goto nobufs; 1607 } 1608 frame = vm_page_alloc(NULL, color++, 1609 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1610 VM_ALLOC_WIRED); 1611 if (frame == NULL) { 1612 device_printf(sc->ti_dev, "buffer allocation " 1613 "failed -- packet dropped!\n"); 1614 printf(" index %d page %d\n", idx, i); 1615 goto nobufs; 1616 } 1617 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1618 if (sf[i] == NULL) { 1619 vm_page_unwire(frame, 0); 1620 vm_page_free(frame); 1621 device_printf(sc->ti_dev, "buffer allocation " 1622 "failed -- packet dropped!\n"); 1623 printf(" index %d page %d\n", idx, i); 1624 goto nobufs; 1625 } 1626 } 1627 for (i = 0; i < NPAYLOAD; i++){ 1628 /* Attach the buffer to the mbuf. */ 1629 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1630 m[i]->m_len = PAGE_SIZE; 1631 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1632 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1633 0, EXT_DISPOSABLE); 1634 m[i]->m_next = m[i+1]; 1635 } 1636 /* link the buffers to the header */ 1637 m_new->m_next = m[0]; 1638 m_new->m_data += ETHER_ALIGN; 1639 if (sc->ti_hdrsplit) 1640 m_new->m_len = MHLEN - ETHER_ALIGN; 1641 else 1642 m_new->m_len = HDR_LEN; 1643 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1644 } 1645 1646 /* Set up the descriptor. */ 1647 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1648 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1649 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1650 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1651 segs, &nsegs, 0)) 1652 return (ENOBUFS); 1653 if ((nsegs < 1) || (nsegs > 4)) 1654 return (ENOBUFS); 1655 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1656 r->ti_len0 = m_new->m_len; 1657 1658 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1659 r->ti_len1 = PAGE_SIZE; 1660 1661 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1662 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1663 1664 if (PAGE_SIZE == 4096) { 1665 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1666 r->ti_len3 = MCLBYTES; 1667 } else { 1668 r->ti_len3 = 0; 1669 } 1670 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1671 1672 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1673 1674 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1675 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1676 1677 r->ti_idx = idx; 1678 1679 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1680 return (0); 1681 1682nobufs: 1683 1684 /* 1685 * Warning! : 1686 * This can only be called before the mbufs are strung together. 1687 * If the mbufs are strung together, m_freem() will free the chain, 1688 * so that the later mbufs will be freed multiple times. 1689 */ 1690 if (m_new) 1691 m_freem(m_new); 1692 1693 for (i = 0; i < 3; i++) { 1694 if (m[i]) 1695 m_freem(m[i]); 1696 if (sf[i]) 1697 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1698 } 1699 return (ENOBUFS); 1700} 1701#endif 1702 1703/* 1704 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1705 * that's 1MB or memory, which is a lot. For now, we fill only the first 1706 * 256 ring entries and hope that our CPU is fast enough to keep up with 1707 * the NIC. 1708 */ 1709static int 1710ti_init_rx_ring_std(struct ti_softc *sc) 1711{ 1712 int i; 1713 struct ti_cmd_desc cmd; 1714 1715 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1716 if (ti_newbuf_std(sc, i) != 0) 1717 return (ENOBUFS); 1718 }; 1719 1720 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1721 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1722 1723 return (0); 1724} 1725 1726static void 1727ti_free_rx_ring_std(struct ti_softc *sc) 1728{ 1729 bus_dmamap_t map; 1730 int i; 1731 1732 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1733 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1734 map = sc->ti_cdata.ti_rx_std_maps[i]; 1735 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1736 BUS_DMASYNC_POSTREAD); 1737 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1738 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1739 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1740 } 1741 } 1742 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1743 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1744 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1745} 1746 1747static int 1748ti_init_rx_ring_jumbo(struct ti_softc *sc) 1749{ 1750 struct ti_cmd_desc cmd; 1751 int i; 1752 1753 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1754 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1755 return (ENOBUFS); 1756 }; 1757 1758 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1759 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1760 1761 return (0); 1762} 1763 1764static void 1765ti_free_rx_ring_jumbo(struct ti_softc *sc) 1766{ 1767 bus_dmamap_t map; 1768 int i; 1769 1770 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1771 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1772 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1773 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1774 BUS_DMASYNC_POSTREAD); 1775 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1776 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1777 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1778 } 1779 } 1780 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1781 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1782 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1783} 1784 1785static int 1786ti_init_rx_ring_mini(struct ti_softc *sc) 1787{ 1788 int i; 1789 1790 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1791 if (ti_newbuf_mini(sc, i) != 0) 1792 return (ENOBUFS); 1793 }; 1794 1795 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1796 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1797 1798 return (0); 1799} 1800 1801static void 1802ti_free_rx_ring_mini(struct ti_softc *sc) 1803{ 1804 bus_dmamap_t map; 1805 int i; 1806 1807 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1808 return; 1809 1810 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1811 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1812 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1813 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1814 BUS_DMASYNC_POSTREAD); 1815 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1816 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1817 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1818 } 1819 } 1820 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1821 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1822 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1823} 1824 1825static void 1826ti_free_tx_ring(struct ti_softc *sc) 1827{ 1828 struct ti_txdesc *txd; 1829 int i; 1830 1831 if (sc->ti_rdata.ti_tx_ring == NULL) 1832 return; 1833 1834 for (i = 0; i < TI_TX_RING_CNT; i++) { 1835 txd = &sc->ti_cdata.ti_txdesc[i]; 1836 if (txd->tx_m != NULL) { 1837 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1838 BUS_DMASYNC_POSTWRITE); 1839 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1840 txd->tx_dmamap); 1841 m_freem(txd->tx_m); 1842 txd->tx_m = NULL; 1843 } 1844 } 1845 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1846 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1847 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1848} 1849 1850static int 1851ti_init_tx_ring(struct ti_softc *sc) 1852{ 1853 struct ti_txdesc *txd; 1854 int i; 1855 1856 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1857 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1858 for (i = 0; i < TI_TX_RING_CNT; i++) { 1859 txd = &sc->ti_cdata.ti_txdesc[i]; 1860 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1861 } 1862 sc->ti_txcnt = 0; 1863 sc->ti_tx_saved_considx = 0; 1864 sc->ti_tx_saved_prodidx = 0; 1865 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1866 return (0); 1867} 1868 1869/* 1870 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1871 * but we have to support the old way too so that Tigon 1 cards will 1872 * work. 1873 */ 1874static void 1875ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1876{ 1877 struct ti_cmd_desc cmd; 1878 uint16_t *m; 1879 uint32_t ext[2] = {0, 0}; 1880 1881 m = (uint16_t *)&addr->octet[0]; 1882 1883 switch (sc->ti_hwrev) { 1884 case TI_HWREV_TIGON: 1885 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1886 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1887 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1888 break; 1889 case TI_HWREV_TIGON_II: 1890 ext[0] = htons(m[0]); 1891 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1892 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1893 break; 1894 default: 1895 device_printf(sc->ti_dev, "unknown hwrev\n"); 1896 break; 1897 } 1898} 1899 1900static void 1901ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1902{ 1903 struct ti_cmd_desc cmd; 1904 uint16_t *m; 1905 uint32_t ext[2] = {0, 0}; 1906 1907 m = (uint16_t *)&addr->octet[0]; 1908 1909 switch (sc->ti_hwrev) { 1910 case TI_HWREV_TIGON: 1911 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1912 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1913 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1914 break; 1915 case TI_HWREV_TIGON_II: 1916 ext[0] = htons(m[0]); 1917 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1918 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1919 break; 1920 default: 1921 device_printf(sc->ti_dev, "unknown hwrev\n"); 1922 break; 1923 } 1924} 1925 1926/* 1927 * Configure the Tigon's multicast address filter. 1928 * 1929 * The actual multicast table management is a bit of a pain, thanks to 1930 * slight brain damage on the part of both Alteon and us. With our 1931 * multicast code, we are only alerted when the multicast address table 1932 * changes and at that point we only have the current list of addresses: 1933 * we only know the current state, not the previous state, so we don't 1934 * actually know what addresses were removed or added. The firmware has 1935 * state, but we can't get our grubby mits on it, and there is no 'delete 1936 * all multicast addresses' command. Hence, we have to maintain our own 1937 * state so we know what addresses have been programmed into the NIC at 1938 * any given time. 1939 */ 1940static void 1941ti_setmulti(struct ti_softc *sc) 1942{ 1943 struct ifnet *ifp; 1944 struct ifmultiaddr *ifma; 1945 struct ti_cmd_desc cmd; 1946 struct ti_mc_entry *mc; 1947 uint32_t intrs; 1948 1949 TI_LOCK_ASSERT(sc); 1950 1951 ifp = sc->ti_ifp; 1952 1953 if (ifp->if_flags & IFF_ALLMULTI) { 1954 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1955 return; 1956 } else { 1957 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1958 } 1959 1960 /* Disable interrupts. */ 1961 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1962 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1963 1964 /* First, zot all the existing filters. */ 1965 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1966 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1967 ti_del_mcast(sc, &mc->mc_addr); 1968 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1969 free(mc, M_DEVBUF); 1970 } 1971 1972 /* Now program new ones. */ 1973 if_maddr_rlock(ifp); 1974 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1975 if (ifma->ifma_addr->sa_family != AF_LINK) 1976 continue; 1977 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1978 if (mc == NULL) { 1979 device_printf(sc->ti_dev, 1980 "no memory for mcast filter entry\n"); 1981 continue; 1982 } 1983 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1984 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1985 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1986 ti_add_mcast(sc, &mc->mc_addr); 1987 } 1988 if_maddr_runlock(ifp); 1989 1990 /* Re-enable interrupts. */ 1991 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1992} 1993 1994/* 1995 * Check to see if the BIOS has configured us for a 64 bit slot when 1996 * we aren't actually in one. If we detect this condition, we can work 1997 * around it on the Tigon 2 by setting a bit in the PCI state register, 1998 * but for the Tigon 1 we must give up and abort the interface attach. 1999 */ 2000static int 2001ti_64bitslot_war(struct ti_softc *sc) 2002{ 2003 2004 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 2005 CSR_WRITE_4(sc, 0x600, 0); 2006 CSR_WRITE_4(sc, 0x604, 0); 2007 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2008 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2009 if (sc->ti_hwrev == TI_HWREV_TIGON) 2010 return (EINVAL); 2011 else { 2012 TI_SETBIT(sc, TI_PCI_STATE, 2013 TI_PCISTATE_32BIT_BUS); 2014 return (0); 2015 } 2016 } 2017 } 2018 2019 return (0); 2020} 2021 2022/* 2023 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2024 * self-test results. 2025 */ 2026static int 2027ti_chipinit(struct ti_softc *sc) 2028{ 2029 uint32_t cacheline; 2030 uint32_t pci_writemax = 0; 2031 uint32_t hdrsplit; 2032 2033 /* Initialize link to down state. */ 2034 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2035 2036 /* Set endianness before we access any non-PCI registers. */ 2037#if 0 && BYTE_ORDER == BIG_ENDIAN 2038 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2039 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2040#else 2041 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2042 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2043#endif 2044 2045 /* Check the ROM failed bit to see if self-tests passed. */ 2046 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2047 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2048 return (ENODEV); 2049 } 2050 2051 /* Halt the CPU. */ 2052 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2053 2054 /* Figure out the hardware revision. */ 2055 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2056 case TI_REV_TIGON_I: 2057 sc->ti_hwrev = TI_HWREV_TIGON; 2058 break; 2059 case TI_REV_TIGON_II: 2060 sc->ti_hwrev = TI_HWREV_TIGON_II; 2061 break; 2062 default: 2063 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2064 return (ENODEV); 2065 } 2066 2067 /* Do special setup for Tigon 2. */ 2068 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2069 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2070 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2071 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2072 } 2073 2074 /* 2075 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2076 * can't do header splitting. 2077 */ 2078#ifdef TI_JUMBO_HDRSPLIT 2079 if (sc->ti_hwrev != TI_HWREV_TIGON) 2080 sc->ti_hdrsplit = 1; 2081 else 2082 device_printf(sc->ti_dev, 2083 "can't do header splitting on a Tigon I board\n"); 2084#endif /* TI_JUMBO_HDRSPLIT */ 2085 2086 /* Set up the PCI state register. */ 2087 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2088 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2089 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2090 } 2091 2092 /* Clear the read/write max DMA parameters. */ 2093 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2094 TI_PCISTATE_READ_MAXDMA)); 2095 2096 /* Get cache line size. */ 2097 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2098 2099 /* 2100 * If the system has set enabled the PCI memory write 2101 * and invalidate command in the command register, set 2102 * the write max parameter accordingly. This is necessary 2103 * to use MWI with the Tigon 2. 2104 */ 2105 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2106 switch (cacheline) { 2107 case 1: 2108 case 4: 2109 case 8: 2110 case 16: 2111 case 32: 2112 case 64: 2113 break; 2114 default: 2115 /* Disable PCI memory write and invalidate. */ 2116 if (bootverbose) 2117 device_printf(sc->ti_dev, "cache line size %d" 2118 " not supported; disabling PCI MWI\n", 2119 cacheline); 2120 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2121 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2122 break; 2123 } 2124 } 2125 2126 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2127 2128 /* This sets the min dma param all the way up (0xff). */ 2129 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2130 2131 if (sc->ti_hdrsplit) 2132 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2133 else 2134 hdrsplit = 0; 2135 2136 /* Configure DMA variables. */ 2137#if BYTE_ORDER == BIG_ENDIAN 2138 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2139 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2140 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2141 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2142#else /* BYTE_ORDER */ 2143 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2144 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2145 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2146#endif /* BYTE_ORDER */ 2147 2148 /* 2149 * Only allow 1 DMA channel to be active at a time. 2150 * I don't think this is a good idea, but without it 2151 * the firmware racks up lots of nicDmaReadRingFull 2152 * errors. This is not compatible with hardware checksums. 2153 */ 2154 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2155 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2156 2157 /* Recommended settings from Tigon manual. */ 2158 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2159 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2160 2161 if (ti_64bitslot_war(sc)) { 2162 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2163 "but we aren't"); 2164 return (EINVAL); 2165 } 2166 2167 return (0); 2168} 2169 2170/* 2171 * Initialize the general information block and firmware, and 2172 * start the CPU(s) running. 2173 */ 2174static int 2175ti_gibinit(struct ti_softc *sc) 2176{ 2177 struct ifnet *ifp; 2178 struct ti_rcb *rcb; 2179 int i; 2180 2181 TI_LOCK_ASSERT(sc); 2182 2183 ifp = sc->ti_ifp; 2184 2185 /* Disable interrupts for now. */ 2186 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2187 2188 /* Tell the chip where to find the general information block. */ 2189 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2190 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2191 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2192 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2193 2194 /* Load the firmware into SRAM. */ 2195 ti_loadfw(sc); 2196 2197 /* Set up the contents of the general info and ring control blocks. */ 2198 2199 /* Set up the event ring and producer pointer. */ 2200 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2201 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2202 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2203 rcb->ti_flags = 0; 2204 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2205 sc->ti_rdata.ti_status_paddr + 2206 offsetof(struct ti_status, ti_ev_prodidx_r)); 2207 sc->ti_ev_prodidx.ti_idx = 0; 2208 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2209 sc->ti_ev_saved_considx = 0; 2210 2211 /* Set up the command ring and producer mailbox. */ 2212 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2213 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2214 rcb->ti_flags = 0; 2215 rcb->ti_max_len = 0; 2216 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2217 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2218 } 2219 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2220 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2221 sc->ti_cmd_saved_prodidx = 0; 2222 2223 /* 2224 * Assign the address of the stats refresh buffer. 2225 * We re-use the current stats buffer for this to 2226 * conserve memory. 2227 */ 2228 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2229 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2230 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2231 2232 /* Set up the standard receive ring. */ 2233 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2234 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2235 rcb->ti_max_len = TI_FRAMELEN; 2236 rcb->ti_flags = 0; 2237 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2238 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2239 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2240 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2241 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2242 2243 /* Set up the jumbo receive ring. */ 2244 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2245 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2246 2247#ifndef TI_SF_BUF_JUMBO 2248 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2249 rcb->ti_flags = 0; 2250#else 2251 rcb->ti_max_len = PAGE_SIZE; 2252 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2253#endif 2254 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2255 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2256 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2257 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2258 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2259 2260 /* 2261 * Set up the mini ring. Only activated on the 2262 * Tigon 2 but the slot in the config block is 2263 * still there on the Tigon 1. 2264 */ 2265 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2266 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2267 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2268 if (sc->ti_hwrev == TI_HWREV_TIGON) 2269 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2270 else 2271 rcb->ti_flags = 0; 2272 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2273 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2274 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2275 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2276 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2277 2278 /* 2279 * Set up the receive return ring. 2280 */ 2281 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2282 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2283 rcb->ti_flags = 0; 2284 rcb->ti_max_len = TI_RETURN_RING_CNT; 2285 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2286 sc->ti_rdata.ti_status_paddr + 2287 offsetof(struct ti_status, ti_return_prodidx_r)); 2288 2289 /* 2290 * Set up the tx ring. Note: for the Tigon 2, we have the option 2291 * of putting the transmit ring in the host's address space and 2292 * letting the chip DMA it instead of leaving the ring in the NIC's 2293 * memory and accessing it through the shared memory region. We 2294 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2295 * so we have to revert to the shared memory scheme if we detect 2296 * a Tigon 1 chip. 2297 */ 2298 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2299 if (sc->ti_rdata.ti_tx_ring != NULL) 2300 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2301 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2302 if (sc->ti_hwrev == TI_HWREV_TIGON) 2303 rcb->ti_flags = 0; 2304 else 2305 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2306 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2307 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2308 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2309 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2310 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2311 rcb->ti_max_len = TI_TX_RING_CNT; 2312 if (sc->ti_hwrev == TI_HWREV_TIGON) 2313 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2314 else 2315 ti_hostaddr64(&rcb->ti_hostaddr, 2316 sc->ti_rdata.ti_tx_ring_paddr); 2317 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2318 sc->ti_rdata.ti_status_paddr + 2319 offsetof(struct ti_status, ti_tx_considx_r)); 2320 2321 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2323 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2325 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2326 sc->ti_cdata.ti_event_ring_map, 2327 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2328 if (sc->ti_rdata.ti_tx_ring != NULL) 2329 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2330 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2331 2332 /* Set up tunables */ 2333#if 0 2334 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2335 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2336 (sc->ti_rx_coal_ticks / 10)); 2337 else 2338#endif 2339 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2340 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2341 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2342 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2343 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2344 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2345 2346 /* Turn interrupts on. */ 2347 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2348 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2349 2350 /* Start CPU. */ 2351 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2352 2353 return (0); 2354} 2355 2356/* 2357 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2358 * against our list and return its name if we find a match. 2359 */ 2360static int 2361ti_probe(device_t dev) 2362{ 2363 const struct ti_type *t; 2364 2365 t = ti_devs; 2366 2367 while (t->ti_name != NULL) { 2368 if ((pci_get_vendor(dev) == t->ti_vid) && 2369 (pci_get_device(dev) == t->ti_did)) { 2370 device_set_desc(dev, t->ti_name); 2371 return (BUS_PROBE_DEFAULT); 2372 } 2373 t++; 2374 } 2375 2376 return (ENXIO); 2377} 2378 2379static int 2380ti_attach(device_t dev) 2381{ 2382 struct ifnet *ifp; 2383 struct ti_softc *sc; 2384 int error = 0, rid; 2385 u_char eaddr[6]; 2386 2387 sc = device_get_softc(dev); 2388 sc->ti_dev = dev; 2389 2390 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2391 MTX_DEF); 2392 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2393 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2394 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2395 if (ifp == NULL) { 2396 device_printf(dev, "can not if_alloc()\n"); 2397 error = ENOSPC; 2398 goto fail; 2399 } 2400 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2401 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2402 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2403 2404 /* 2405 * Map control/status registers. 2406 */ 2407 pci_enable_busmaster(dev); 2408 2409 rid = PCIR_BAR(0); 2410 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2411 RF_ACTIVE); 2412 2413 if (sc->ti_res == NULL) { 2414 device_printf(dev, "couldn't map memory\n"); 2415 error = ENXIO; 2416 goto fail; 2417 } 2418 2419 sc->ti_btag = rman_get_bustag(sc->ti_res); 2420 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2421 2422 /* Allocate interrupt */ 2423 rid = 0; 2424 2425 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2426 RF_SHAREABLE | RF_ACTIVE); 2427 2428 if (sc->ti_irq == NULL) { 2429 device_printf(dev, "couldn't map interrupt\n"); 2430 error = ENXIO; 2431 goto fail; 2432 } 2433 2434 if (ti_chipinit(sc)) { 2435 device_printf(dev, "chip initialization failed\n"); 2436 error = ENXIO; 2437 goto fail; 2438 } 2439 2440 /* Zero out the NIC's on-board SRAM. */ 2441 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2442 2443 /* Init again -- zeroing memory may have clobbered some registers. */ 2444 if (ti_chipinit(sc)) { 2445 device_printf(dev, "chip initialization failed\n"); 2446 error = ENXIO; 2447 goto fail; 2448 } 2449 2450 /* 2451 * Get station address from the EEPROM. Note: the manual states 2452 * that the MAC address is at offset 0x8c, however the data is 2453 * stored as two longwords (since that's how it's loaded into 2454 * the NIC). This means the MAC address is actually preceded 2455 * by two zero bytes. We need to skip over those. 2456 */ 2457 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2458 device_printf(dev, "failed to read station address\n"); 2459 error = ENXIO; 2460 goto fail; 2461 } 2462 2463 /* Allocate working area for memory dump. */ 2464 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2465 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2466 M_NOWAIT); 2467 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2468 device_printf(dev, "cannot allocate memory buffer\n"); 2469 error = ENOMEM; 2470 goto fail; 2471 } 2472 if ((error = ti_dma_alloc(sc)) != 0) 2473 goto fail; 2474 2475 /* 2476 * We really need a better way to tell a 1000baseTX card 2477 * from a 1000baseSX one, since in theory there could be 2478 * OEMed 1000baseTX cards from lame vendors who aren't 2479 * clever enough to change the PCI ID. For the moment 2480 * though, the AceNIC is the only copper card available. 2481 */ 2482 if (pci_get_vendor(dev) == ALT_VENDORID && 2483 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2484 sc->ti_copper = 1; 2485 /* Ok, it's not the only copper card available. */ 2486 if (pci_get_vendor(dev) == NG_VENDORID && 2487 pci_get_device(dev) == NG_DEVICEID_GA620T) 2488 sc->ti_copper = 1; 2489 2490 /* Set default tunable values. */ 2491 ti_sysctl_node(sc); 2492 2493 /* Set up ifnet structure */ 2494 ifp->if_softc = sc; 2495 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2497 ifp->if_ioctl = ti_ioctl; 2498 ifp->if_start = ti_start; 2499 ifp->if_init = ti_init; 2500 ifp->if_baudrate = IF_Gbps(1UL); 2501 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2502 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2503 IFQ_SET_READY(&ifp->if_snd); 2504 2505 /* Set up ifmedia support. */ 2506 if (sc->ti_copper) { 2507 /* 2508 * Copper cards allow manual 10/100 mode selection, 2509 * but not manual 1000baseTX mode selection. Why? 2510 * Becuase currently there's no way to specify the 2511 * master/slave setting through the firmware interface, 2512 * so Alteon decided to just bag it and handle it 2513 * via autonegotiation. 2514 */ 2515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2516 ifmedia_add(&sc->ifmedia, 2517 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2519 ifmedia_add(&sc->ifmedia, 2520 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2522 ifmedia_add(&sc->ifmedia, 2523 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2524 } else { 2525 /* Fiber cards don't support 10/100 modes. */ 2526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2527 ifmedia_add(&sc->ifmedia, 2528 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2529 } 2530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2531 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2532 2533 /* 2534 * We're assuming here that card initialization is a sequential 2535 * thing. If it isn't, multiple cards probing at the same time 2536 * could stomp on the list of softcs here. 2537 */ 2538 2539 /* Register the device */ 2540 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2541 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2542 sc->dev->si_drv1 = sc; 2543 2544 /* 2545 * Call MI attach routine. 2546 */ 2547 ether_ifattach(ifp, eaddr); 2548 2549 /* VLAN capability setup. */ 2550 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2551 IFCAP_VLAN_HWTAGGING; 2552 ifp->if_capenable = ifp->if_capabilities; 2553 /* Tell the upper layer we support VLAN over-sized frames. */ 2554 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2555 2556 /* Driver supports link state tracking. */ 2557 ifp->if_capabilities |= IFCAP_LINKSTATE; 2558 ifp->if_capenable |= IFCAP_LINKSTATE; 2559 2560 /* Hook interrupt last to avoid having to lock softc */ 2561 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2562 NULL, ti_intr, sc, &sc->ti_intrhand); 2563 2564 if (error) { 2565 device_printf(dev, "couldn't set up irq\n"); 2566 goto fail; 2567 } 2568 2569fail: 2570 if (error) 2571 ti_detach(dev); 2572 2573 return (error); 2574} 2575 2576/* 2577 * Shutdown hardware and free up resources. This can be called any 2578 * time after the mutex has been initialized. It is called in both 2579 * the error case in attach and the normal detach case so it needs 2580 * to be careful about only freeing resources that have actually been 2581 * allocated. 2582 */ 2583static int 2584ti_detach(device_t dev) 2585{ 2586 struct ti_softc *sc; 2587 struct ifnet *ifp; 2588 2589 sc = device_get_softc(dev); 2590 if (sc->dev) 2591 destroy_dev(sc->dev); 2592 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2593 ifp = sc->ti_ifp; 2594 if (device_is_attached(dev)) { 2595 ether_ifdetach(ifp); 2596 TI_LOCK(sc); 2597 ti_stop(sc); 2598 TI_UNLOCK(sc); 2599 } 2600 2601 /* These should only be active if attach succeeded */ 2602 callout_drain(&sc->ti_watchdog); 2603 bus_generic_detach(dev); 2604 ti_dma_free(sc); 2605 ifmedia_removeall(&sc->ifmedia); 2606 2607 if (sc->ti_intrhand) 2608 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2609 if (sc->ti_irq) 2610 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2611 if (sc->ti_res) { 2612 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2613 sc->ti_res); 2614 } 2615 if (ifp) 2616 if_free(ifp); 2617 if (sc->ti_membuf) 2618 free(sc->ti_membuf, M_DEVBUF); 2619 if (sc->ti_membuf2) 2620 free(sc->ti_membuf2, M_DEVBUF); 2621 2622 mtx_destroy(&sc->ti_mtx); 2623 2624 return (0); 2625} 2626 2627#ifdef TI_JUMBO_HDRSPLIT 2628/* 2629 * If hdr_len is 0, that means that header splitting wasn't done on 2630 * this packet for some reason. The two most likely reasons are that 2631 * the protocol isn't a supported protocol for splitting, or this 2632 * packet had a fragment offset that wasn't 0. 2633 * 2634 * The header length, if it is non-zero, will always be the length of 2635 * the headers on the packet, but that length could be longer than the 2636 * first mbuf. So we take the minimum of the two as the actual 2637 * length. 2638 */ 2639static __inline void 2640ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2641{ 2642 int i = 0; 2643 int lengths[4] = {0, 0, 0, 0}; 2644 struct mbuf *m, *mp; 2645 2646 if (hdr_len != 0) 2647 top->m_len = min(hdr_len, top->m_len); 2648 pkt_len -= top->m_len; 2649 lengths[i++] = top->m_len; 2650 2651 mp = top; 2652 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2653 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2654 pkt_len -= m->m_len; 2655 lengths[i++] = m->m_len; 2656 mp = m; 2657 } 2658 2659#if 0 2660 if (hdr_len != 0) 2661 printf("got split packet: "); 2662 else 2663 printf("got non-split packet: "); 2664 2665 printf("%d,%d,%d,%d = %d\n", lengths[0], 2666 lengths[1], lengths[2], lengths[3], 2667 lengths[0] + lengths[1] + lengths[2] + 2668 lengths[3]); 2669#endif 2670 2671 if (pkt_len) 2672 panic("header splitting didn't"); 2673 2674 if (m) { 2675 m_freem(m); 2676 mp->m_next = NULL; 2677 2678 } 2679 if (mp->m_next != NULL) 2680 panic("ti_hdr_split: last mbuf in chain should be null"); 2681} 2682#endif /* TI_JUMBO_HDRSPLIT */ 2683 2684static void 2685ti_discard_std(struct ti_softc *sc, int i) 2686{ 2687 2688 struct ti_rx_desc *r; 2689 2690 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2691 r->ti_len = MCLBYTES - ETHER_ALIGN; 2692 r->ti_type = TI_BDTYPE_RECV_BD; 2693 r->ti_flags = 0; 2694 r->ti_vlan_tag = 0; 2695 r->ti_tcp_udp_cksum = 0; 2696 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2697 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2698 r->ti_idx = i; 2699} 2700 2701static void 2702ti_discard_mini(struct ti_softc *sc, int i) 2703{ 2704 2705 struct ti_rx_desc *r; 2706 2707 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2708 r->ti_len = MHLEN - ETHER_ALIGN; 2709 r->ti_type = TI_BDTYPE_RECV_BD; 2710 r->ti_flags = TI_BDFLAG_MINI_RING; 2711 r->ti_vlan_tag = 0; 2712 r->ti_tcp_udp_cksum = 0; 2713 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2714 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2715 r->ti_idx = i; 2716} 2717 2718#ifndef TI_SF_BUF_JUMBO 2719static void 2720ti_discard_jumbo(struct ti_softc *sc, int i) 2721{ 2722 2723 struct ti_rx_desc *r; 2724 2725 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2726 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2727 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2728 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2729 r->ti_vlan_tag = 0; 2730 r->ti_tcp_udp_cksum = 0; 2731 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2732 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2733 r->ti_idx = i; 2734} 2735#endif 2736 2737/* 2738 * Frame reception handling. This is called if there's a frame 2739 * on the receive return list. 2740 * 2741 * Note: we have to be able to handle three possibilities here: 2742 * 1) the frame is from the mini receive ring (can only happen) 2743 * on Tigon 2 boards) 2744 * 2) the frame is from the jumbo recieve ring 2745 * 3) the frame is from the standard receive ring 2746 */ 2747 2748static void 2749ti_rxeof(struct ti_softc *sc) 2750{ 2751 struct ifnet *ifp; 2752#ifdef TI_SF_BUF_JUMBO 2753 bus_dmamap_t map; 2754#endif 2755 struct ti_cmd_desc cmd; 2756 int jumbocnt, minicnt, stdcnt, ti_len; 2757 2758 TI_LOCK_ASSERT(sc); 2759 2760 ifp = sc->ti_ifp; 2761 2762 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2763 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2764 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2765 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2766 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2767 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2768 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2769 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2770 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2771 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2772 2773 jumbocnt = minicnt = stdcnt = 0; 2774 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2775 struct ti_rx_desc *cur_rx; 2776 uint32_t rxidx; 2777 struct mbuf *m = NULL; 2778 uint16_t vlan_tag = 0; 2779 int have_tag = 0; 2780 2781 cur_rx = 2782 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2783 rxidx = cur_rx->ti_idx; 2784 ti_len = cur_rx->ti_len; 2785 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2786 2787 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2788 have_tag = 1; 2789 vlan_tag = cur_rx->ti_vlan_tag; 2790 } 2791 2792 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2793 jumbocnt++; 2794 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2795 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2796#ifndef TI_SF_BUF_JUMBO 2797 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2798 ifp->if_ierrors++; 2799 ti_discard_jumbo(sc, rxidx); 2800 continue; 2801 } 2802 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2803 ifp->if_iqdrops++; 2804 ti_discard_jumbo(sc, rxidx); 2805 continue; 2806 } 2807 m->m_len = ti_len; 2808#else /* !TI_SF_BUF_JUMBO */ 2809 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2810 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2811 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2812 BUS_DMASYNC_POSTREAD); 2813 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2814 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2815 ifp->if_ierrors++; 2816 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2817 continue; 2818 } 2819 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2820 ifp->if_iqdrops++; 2821 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2822 continue; 2823 } 2824#ifdef TI_JUMBO_HDRSPLIT 2825 if (sc->ti_hdrsplit) 2826 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2827 ti_len, rxidx); 2828 else 2829#endif /* TI_JUMBO_HDRSPLIT */ 2830 m_adj(m, ti_len - m->m_pkthdr.len); 2831#endif /* TI_SF_BUF_JUMBO */ 2832 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2833 minicnt++; 2834 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2835 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2836 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2837 ifp->if_ierrors++; 2838 ti_discard_mini(sc, rxidx); 2839 continue; 2840 } 2841 if (ti_newbuf_mini(sc, rxidx) != 0) { 2842 ifp->if_iqdrops++; 2843 ti_discard_mini(sc, rxidx); 2844 continue; 2845 } 2846 m->m_len = ti_len; 2847 } else { 2848 stdcnt++; 2849 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2850 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2851 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2852 ifp->if_ierrors++; 2853 ti_discard_std(sc, rxidx); 2854 continue; 2855 } 2856 if (ti_newbuf_std(sc, rxidx) != 0) { 2857 ifp->if_iqdrops++; 2858 ti_discard_std(sc, rxidx); 2859 continue; 2860 } 2861 m->m_len = ti_len; 2862 } 2863 2864 m->m_pkthdr.len = ti_len; 2865 ifp->if_ipackets++; 2866 m->m_pkthdr.rcvif = ifp; 2867 2868 if (ifp->if_capenable & IFCAP_RXCSUM) { 2869 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2870 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2871 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2872 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2873 } 2874 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2875 m->m_pkthdr.csum_data = 2876 cur_rx->ti_tcp_udp_cksum; 2877 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2878 } 2879 } 2880 2881 /* 2882 * If we received a packet with a vlan tag, 2883 * tag it before passing the packet upward. 2884 */ 2885 if (have_tag) { 2886 m->m_pkthdr.ether_vtag = vlan_tag; 2887 m->m_flags |= M_VLANTAG; 2888 } 2889 TI_UNLOCK(sc); 2890 (*ifp->if_input)(ifp, m); 2891 TI_LOCK(sc); 2892 } 2893 2894 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2895 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2896 /* Only necessary on the Tigon 1. */ 2897 if (sc->ti_hwrev == TI_HWREV_TIGON) 2898 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2899 sc->ti_rx_saved_considx); 2900 2901 if (stdcnt > 0) { 2902 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2903 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2904 TI_UPDATE_STDPROD(sc, sc->ti_std); 2905 } 2906 if (minicnt > 0) { 2907 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2908 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2909 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2910 } 2911 if (jumbocnt > 0) { 2912 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2913 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2914 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2915 } 2916} 2917 2918static void 2919ti_txeof(struct ti_softc *sc) 2920{ 2921 struct ti_txdesc *txd; 2922 struct ti_tx_desc txdesc; 2923 struct ti_tx_desc *cur_tx = NULL; 2924 struct ifnet *ifp; 2925 int idx; 2926 2927 ifp = sc->ti_ifp; 2928 2929 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2930 if (txd == NULL) 2931 return; 2932 2933 if (sc->ti_rdata.ti_tx_ring != NULL) 2934 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2935 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2936 /* 2937 * Go through our tx ring and free mbufs for those 2938 * frames that have been sent. 2939 */ 2940 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2941 TI_INC(idx, TI_TX_RING_CNT)) { 2942 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2943 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2944 sizeof(txdesc), &txdesc); 2945 cur_tx = &txdesc; 2946 } else 2947 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2948 sc->ti_txcnt--; 2949 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2950 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2951 continue; 2952 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2953 BUS_DMASYNC_POSTWRITE); 2954 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2955 2956 ifp->if_opackets++; 2957 m_freem(txd->tx_m); 2958 txd->tx_m = NULL; 2959 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2960 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2961 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2962 } 2963 sc->ti_tx_saved_considx = idx; 2964 if (sc->ti_txcnt == 0) 2965 sc->ti_timer = 0; 2966} 2967 2968static void 2969ti_intr(void *xsc) 2970{ 2971 struct ti_softc *sc; 2972 struct ifnet *ifp; 2973 2974 sc = xsc; 2975 TI_LOCK(sc); 2976 ifp = sc->ti_ifp; 2977 2978 /* Make sure this is really our interrupt. */ 2979 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2980 TI_UNLOCK(sc); 2981 return; 2982 } 2983 2984 /* Ack interrupt and stop others from occuring. */ 2985 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2986 2987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2988 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2989 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2990 /* Check RX return ring producer/consumer */ 2991 ti_rxeof(sc); 2992 2993 /* Check TX ring producer/consumer */ 2994 ti_txeof(sc); 2995 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2996 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 2997 } 2998 2999 ti_handle_events(sc); 3000 3001 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3002 /* Re-enable interrupts. */ 3003 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3004 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3005 ti_start_locked(ifp); 3006 } 3007 3008 TI_UNLOCK(sc); 3009} 3010 3011static void 3012ti_stats_update(struct ti_softc *sc) 3013{ 3014 struct ifnet *ifp; 3015 struct ti_stats *s; 3016 3017 ifp = sc->ti_ifp; 3018 3019 if (sc->ti_stat_ticks == 0) 3020 return; 3021 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3022 BUS_DMASYNC_POSTREAD); 3023 3024 s = &sc->ti_rdata.ti_info->ti_stats; 3025 ifp->if_collisions += (s->dot3StatsSingleCollisionFrames + 3026 s->dot3StatsMultipleCollisionFrames + 3027 s->dot3StatsExcessiveCollisions + s->dot3StatsLateCollisions) - 3028 ifp->if_collisions; 3029 3030 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3031 BUS_DMASYNC_PREREAD); 3032} 3033 3034/* 3035 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3036 * pointers to descriptors. 3037 */ 3038static int 3039ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3040{ 3041 struct ti_txdesc *txd; 3042 struct ti_tx_desc *f; 3043 struct ti_tx_desc txdesc; 3044 struct mbuf *m; 3045 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3046 uint16_t csum_flags; 3047 int error, frag, i, nseg; 3048 3049 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3050 return (ENOBUFS); 3051 3052 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3053 *m_head, txsegs, &nseg, 0); 3054 if (error == EFBIG) { 3055 m = m_defrag(*m_head, M_DONTWAIT); 3056 if (m == NULL) { 3057 m_freem(*m_head); 3058 *m_head = NULL; 3059 return (ENOMEM); 3060 } 3061 *m_head = m; 3062 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3063 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3064 if (error) { 3065 m_freem(*m_head); 3066 *m_head = NULL; 3067 return (error); 3068 } 3069 } else if (error != 0) 3070 return (error); 3071 if (nseg == 0) { 3072 m_freem(*m_head); 3073 *m_head = NULL; 3074 return (EIO); 3075 } 3076 3077 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3078 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3079 return (ENOBUFS); 3080 } 3081 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3082 BUS_DMASYNC_PREWRITE); 3083 3084 m = *m_head; 3085 csum_flags = 0; 3086 if (m->m_pkthdr.csum_flags) { 3087 if (m->m_pkthdr.csum_flags & CSUM_IP) 3088 csum_flags |= TI_BDFLAG_IP_CKSUM; 3089 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3090 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3091 if (m->m_flags & M_LASTFRAG) 3092 csum_flags |= TI_BDFLAG_IP_FRAG_END; 3093 else if (m->m_flags & M_FRAG) 3094 csum_flags |= TI_BDFLAG_IP_FRAG; 3095 } 3096 3097 frag = sc->ti_tx_saved_prodidx; 3098 for (i = 0; i < nseg; i++) { 3099 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3100 bzero(&txdesc, sizeof(txdesc)); 3101 f = &txdesc; 3102 } else 3103 f = &sc->ti_rdata.ti_tx_ring[frag]; 3104 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3105 f->ti_len = txsegs[i].ds_len; 3106 f->ti_flags = csum_flags; 3107 if (m->m_flags & M_VLANTAG) { 3108 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3109 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3110 } else { 3111 f->ti_vlan_tag = 0; 3112 } 3113 3114 if (sc->ti_hwrev == TI_HWREV_TIGON) 3115 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3116 sizeof(txdesc), sizeof(txdesc), &txdesc); 3117 TI_INC(frag, TI_TX_RING_CNT); 3118 } 3119 3120 sc->ti_tx_saved_prodidx = frag; 3121 /* set TI_BDFLAG_END on the last descriptor */ 3122 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3123 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3124 txdesc.ti_flags |= TI_BDFLAG_END; 3125 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3126 sizeof(txdesc), &txdesc); 3127 } else 3128 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3129 3130 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3131 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3132 txd->tx_m = m; 3133 sc->ti_txcnt += nseg; 3134 3135 return (0); 3136} 3137 3138static void 3139ti_start(struct ifnet *ifp) 3140{ 3141 struct ti_softc *sc; 3142 3143 sc = ifp->if_softc; 3144 TI_LOCK(sc); 3145 ti_start_locked(ifp); 3146 TI_UNLOCK(sc); 3147} 3148 3149/* 3150 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3151 * to the mbuf data regions directly in the transmit descriptors. 3152 */ 3153static void 3154ti_start_locked(struct ifnet *ifp) 3155{ 3156 struct ti_softc *sc; 3157 struct mbuf *m_head = NULL; 3158 int enq = 0; 3159 3160 sc = ifp->if_softc; 3161 3162 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3163 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3164 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3165 if (m_head == NULL) 3166 break; 3167 3168 /* 3169 * XXX 3170 * safety overkill. If this is a fragmented packet chain 3171 * with delayed TCP/UDP checksums, then only encapsulate 3172 * it if we have enough descriptors to handle the entire 3173 * chain at once. 3174 * (paranoia -- may not actually be needed) 3175 */ 3176 if (m_head->m_flags & M_FIRSTFRAG && 3177 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3178 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3179 m_head->m_pkthdr.csum_data + 16) { 3180 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3181 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3182 break; 3183 } 3184 } 3185 3186 /* 3187 * Pack the data into the transmit ring. If we 3188 * don't have room, set the OACTIVE flag and wait 3189 * for the NIC to drain the ring. 3190 */ 3191 if (ti_encap(sc, &m_head)) { 3192 if (m_head == NULL) 3193 break; 3194 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3195 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3196 break; 3197 } 3198 3199 enq++; 3200 /* 3201 * If there's a BPF listener, bounce a copy of this frame 3202 * to him. 3203 */ 3204 ETHER_BPF_MTAP(ifp, m_head); 3205 } 3206 3207 if (enq > 0) { 3208 if (sc->ti_rdata.ti_tx_ring != NULL) 3209 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3210 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3211 /* Transmit */ 3212 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3213 3214 /* 3215 * Set a timeout in case the chip goes out to lunch. 3216 */ 3217 sc->ti_timer = 5; 3218 } 3219} 3220 3221static void 3222ti_init(void *xsc) 3223{ 3224 struct ti_softc *sc; 3225 3226 sc = xsc; 3227 TI_LOCK(sc); 3228 ti_init_locked(sc); 3229 TI_UNLOCK(sc); 3230} 3231 3232static void 3233ti_init_locked(void *xsc) 3234{ 3235 struct ti_softc *sc = xsc; 3236 3237 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3238 return; 3239 3240 /* Cancel pending I/O and flush buffers. */ 3241 ti_stop(sc); 3242 3243 /* Init the gen info block, ring control blocks and firmware. */ 3244 if (ti_gibinit(sc)) { 3245 device_printf(sc->ti_dev, "initialization failure\n"); 3246 return; 3247 } 3248} 3249 3250static void ti_init2(struct ti_softc *sc) 3251{ 3252 struct ti_cmd_desc cmd; 3253 struct ifnet *ifp; 3254 uint8_t *ea; 3255 struct ifmedia *ifm; 3256 int tmp; 3257 3258 TI_LOCK_ASSERT(sc); 3259 3260 ifp = sc->ti_ifp; 3261 3262 /* Specify MTU and interface index. */ 3263 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3264 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3265 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3266 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3267 3268 /* Load our MAC address. */ 3269 ea = IF_LLADDR(sc->ti_ifp); 3270 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3271 CSR_WRITE_4(sc, TI_GCR_PAR1, 3272 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3273 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3274 3275 /* Enable or disable promiscuous mode as needed. */ 3276 if (ifp->if_flags & IFF_PROMISC) { 3277 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3278 } else { 3279 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3280 } 3281 3282 /* Program multicast filter. */ 3283 ti_setmulti(sc); 3284 3285 /* 3286 * If this is a Tigon 1, we should tell the 3287 * firmware to use software packet filtering. 3288 */ 3289 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3290 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3291 } 3292 3293 /* Init RX ring. */ 3294 if (ti_init_rx_ring_std(sc) != 0) { 3295 /* XXX */ 3296 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3297 return; 3298 } 3299 3300 /* Init jumbo RX ring. */ 3301 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3302 if (ti_init_rx_ring_jumbo(sc) != 0) { 3303 /* XXX */ 3304 device_printf(sc->ti_dev, 3305 "no memory for jumbo Rx buffers.\n"); 3306 return; 3307 } 3308 } 3309 3310 /* 3311 * If this is a Tigon 2, we can also configure the 3312 * mini ring. 3313 */ 3314 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3315 if (ti_init_rx_ring_mini(sc) != 0) { 3316 /* XXX */ 3317 device_printf(sc->ti_dev, 3318 "no memory for mini Rx buffers.\n"); 3319 return; 3320 } 3321 } 3322 3323 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3324 sc->ti_rx_saved_considx = 0; 3325 3326 /* Init TX ring. */ 3327 ti_init_tx_ring(sc); 3328 3329 /* Tell firmware we're alive. */ 3330 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3331 3332 /* Enable host interrupts. */ 3333 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3334 3335 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3336 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3337 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3338 3339 /* 3340 * Make sure to set media properly. We have to do this 3341 * here since we have to issue commands in order to set 3342 * the link negotiation and we can't issue commands until 3343 * the firmware is running. 3344 */ 3345 ifm = &sc->ifmedia; 3346 tmp = ifm->ifm_media; 3347 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3348 ti_ifmedia_upd_locked(sc); 3349 ifm->ifm_media = tmp; 3350} 3351 3352/* 3353 * Set media options. 3354 */ 3355static int 3356ti_ifmedia_upd(struct ifnet *ifp) 3357{ 3358 struct ti_softc *sc; 3359 int error; 3360 3361 sc = ifp->if_softc; 3362 TI_LOCK(sc); 3363 error = ti_ifmedia_upd(ifp); 3364 TI_UNLOCK(sc); 3365 3366 return (error); 3367} 3368 3369static int 3370ti_ifmedia_upd_locked(struct ti_softc *sc) 3371{ 3372 struct ifmedia *ifm; 3373 struct ti_cmd_desc cmd; 3374 uint32_t flowctl; 3375 3376 ifm = &sc->ifmedia; 3377 3378 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3379 return (EINVAL); 3380 3381 flowctl = 0; 3382 3383 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3384 case IFM_AUTO: 3385 /* 3386 * Transmit flow control doesn't work on the Tigon 1. 3387 */ 3388 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3389 3390 /* 3391 * Transmit flow control can also cause problems on the 3392 * Tigon 2, apparantly with both the copper and fiber 3393 * boards. The symptom is that the interface will just 3394 * hang. This was reproduced with Alteon 180 switches. 3395 */ 3396#if 0 3397 if (sc->ti_hwrev != TI_HWREV_TIGON) 3398 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3399#endif 3400 3401 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3402 TI_GLNK_FULL_DUPLEX| flowctl | 3403 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3404 3405 flowctl = TI_LNK_RX_FLOWCTL_Y; 3406#if 0 3407 if (sc->ti_hwrev != TI_HWREV_TIGON) 3408 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3409#endif 3410 3411 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3412 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3413 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3414 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3415 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3416 break; 3417 case IFM_1000_SX: 3418 case IFM_1000_T: 3419 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3420#if 0 3421 if (sc->ti_hwrev != TI_HWREV_TIGON) 3422 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3423#endif 3424 3425 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3426 flowctl |TI_GLNK_ENB); 3427 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3428 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3429 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3430 } 3431 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3432 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3433 break; 3434 case IFM_100_FX: 3435 case IFM_10_FL: 3436 case IFM_100_TX: 3437 case IFM_10_T: 3438 flowctl = TI_LNK_RX_FLOWCTL_Y; 3439#if 0 3440 if (sc->ti_hwrev != TI_HWREV_TIGON) 3441 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3442#endif 3443 3444 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3445 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3446 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3447 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3448 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3449 } else { 3450 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3451 } 3452 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3453 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3454 } else { 3455 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3456 } 3457 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3458 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3459 break; 3460 } 3461 3462 return (0); 3463} 3464 3465/* 3466 * Report current media status. 3467 */ 3468static void 3469ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3470{ 3471 struct ti_softc *sc; 3472 uint32_t media = 0; 3473 3474 sc = ifp->if_softc; 3475 3476 TI_LOCK(sc); 3477 3478 ifmr->ifm_status = IFM_AVALID; 3479 ifmr->ifm_active = IFM_ETHER; 3480 3481 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3482 TI_UNLOCK(sc); 3483 return; 3484 } 3485 3486 ifmr->ifm_status |= IFM_ACTIVE; 3487 3488 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3489 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3490 if (sc->ti_copper) 3491 ifmr->ifm_active |= IFM_1000_T; 3492 else 3493 ifmr->ifm_active |= IFM_1000_SX; 3494 if (media & TI_GLNK_FULL_DUPLEX) 3495 ifmr->ifm_active |= IFM_FDX; 3496 else 3497 ifmr->ifm_active |= IFM_HDX; 3498 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3499 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3500 if (sc->ti_copper) { 3501 if (media & TI_LNK_100MB) 3502 ifmr->ifm_active |= IFM_100_TX; 3503 if (media & TI_LNK_10MB) 3504 ifmr->ifm_active |= IFM_10_T; 3505 } else { 3506 if (media & TI_LNK_100MB) 3507 ifmr->ifm_active |= IFM_100_FX; 3508 if (media & TI_LNK_10MB) 3509 ifmr->ifm_active |= IFM_10_FL; 3510 } 3511 if (media & TI_LNK_FULL_DUPLEX) 3512 ifmr->ifm_active |= IFM_FDX; 3513 if (media & TI_LNK_HALF_DUPLEX) 3514 ifmr->ifm_active |= IFM_HDX; 3515 } 3516 TI_UNLOCK(sc); 3517} 3518 3519static int 3520ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3521{ 3522 struct ti_softc *sc = ifp->if_softc; 3523 struct ifreq *ifr = (struct ifreq *) data; 3524 struct ti_cmd_desc cmd; 3525 int mask, error = 0; 3526 3527 switch (command) { 3528 case SIOCSIFMTU: 3529 TI_LOCK(sc); 3530 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3531 error = EINVAL; 3532 else { 3533 ifp->if_mtu = ifr->ifr_mtu; 3534 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3535 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3536 ti_init_locked(sc); 3537 } 3538 } 3539 TI_UNLOCK(sc); 3540 break; 3541 case SIOCSIFFLAGS: 3542 TI_LOCK(sc); 3543 if (ifp->if_flags & IFF_UP) { 3544 /* 3545 * If only the state of the PROMISC flag changed, 3546 * then just use the 'set promisc mode' command 3547 * instead of reinitializing the entire NIC. Doing 3548 * a full re-init means reloading the firmware and 3549 * waiting for it to start up, which may take a 3550 * second or two. 3551 */ 3552 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3553 ifp->if_flags & IFF_PROMISC && 3554 !(sc->ti_if_flags & IFF_PROMISC)) { 3555 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3556 TI_CMD_CODE_PROMISC_ENB, 0); 3557 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3558 !(ifp->if_flags & IFF_PROMISC) && 3559 sc->ti_if_flags & IFF_PROMISC) { 3560 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3561 TI_CMD_CODE_PROMISC_DIS, 0); 3562 } else 3563 ti_init_locked(sc); 3564 } else { 3565 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3566 ti_stop(sc); 3567 } 3568 } 3569 sc->ti_if_flags = ifp->if_flags; 3570 TI_UNLOCK(sc); 3571 break; 3572 case SIOCADDMULTI: 3573 case SIOCDELMULTI: 3574 TI_LOCK(sc); 3575 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3576 ti_setmulti(sc); 3577 TI_UNLOCK(sc); 3578 break; 3579 case SIOCSIFMEDIA: 3580 case SIOCGIFMEDIA: 3581 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3582 break; 3583 case SIOCSIFCAP: 3584 TI_LOCK(sc); 3585 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3586 if ((mask & IFCAP_TXCSUM) != 0 && 3587 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3588 ifp->if_capenable ^= IFCAP_TXCSUM; 3589 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3590 ifp->if_hwassist |= TI_CSUM_FEATURES; 3591 else 3592 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3593 } 3594 if ((mask & IFCAP_RXCSUM) != 0 && 3595 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3596 ifp->if_capenable ^= IFCAP_RXCSUM; 3597 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3598 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3599 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3600 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3601 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3602 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3603 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3604 IFCAP_VLAN_HWTAGGING)) != 0) { 3605 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3606 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3607 ti_init_locked(sc); 3608 } 3609 } 3610 TI_UNLOCK(sc); 3611 VLAN_CAPABILITIES(ifp); 3612 break; 3613 default: 3614 error = ether_ioctl(ifp, command, data); 3615 break; 3616 } 3617 3618 return (error); 3619} 3620 3621static int 3622ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3623{ 3624 struct ti_softc *sc; 3625 3626 sc = dev->si_drv1; 3627 if (sc == NULL) 3628 return (ENODEV); 3629 3630 TI_LOCK(sc); 3631 sc->ti_flags |= TI_FLAG_DEBUGING; 3632 TI_UNLOCK(sc); 3633 3634 return (0); 3635} 3636 3637static int 3638ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3639{ 3640 struct ti_softc *sc; 3641 3642 sc = dev->si_drv1; 3643 if (sc == NULL) 3644 return (ENODEV); 3645 3646 TI_LOCK(sc); 3647 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3648 TI_UNLOCK(sc); 3649 3650 return (0); 3651} 3652 3653/* 3654 * This ioctl routine goes along with the Tigon character device. 3655 */ 3656static int 3657ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3658 struct thread *td) 3659{ 3660 struct ti_softc *sc; 3661 int error; 3662 3663 sc = dev->si_drv1; 3664 if (sc == NULL) 3665 return (ENODEV); 3666 3667 error = 0; 3668 3669 switch (cmd) { 3670 case TIIOCGETSTATS: 3671 { 3672 struct ti_stats *outstats; 3673 3674 outstats = (struct ti_stats *)addr; 3675 3676 TI_LOCK(sc); 3677 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3678 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3679 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3680 sizeof(struct ti_stats)); 3681 TI_UNLOCK(sc); 3682 break; 3683 } 3684 case TIIOCGETPARAMS: 3685 { 3686 struct ti_params *params; 3687 3688 params = (struct ti_params *)addr; 3689 3690 TI_LOCK(sc); 3691 params->ti_stat_ticks = sc->ti_stat_ticks; 3692 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3693 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3694 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3695 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3696 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3697 params->param_mask = TI_PARAM_ALL; 3698 TI_UNLOCK(sc); 3699 break; 3700 } 3701 case TIIOCSETPARAMS: 3702 { 3703 struct ti_params *params; 3704 3705 params = (struct ti_params *)addr; 3706 3707 TI_LOCK(sc); 3708 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3709 sc->ti_stat_ticks = params->ti_stat_ticks; 3710 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3711 } 3712 3713 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3714 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3715 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3716 sc->ti_rx_coal_ticks); 3717 } 3718 3719 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3720 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3721 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3722 sc->ti_tx_coal_ticks); 3723 } 3724 3725 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3726 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3727 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3728 sc->ti_rx_max_coal_bds); 3729 } 3730 3731 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3732 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3733 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3734 sc->ti_tx_max_coal_bds); 3735 } 3736 3737 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3738 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3739 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3740 sc->ti_tx_buf_ratio); 3741 } 3742 TI_UNLOCK(sc); 3743 break; 3744 } 3745 case TIIOCSETTRACE: { 3746 ti_trace_type trace_type; 3747 3748 trace_type = *(ti_trace_type *)addr; 3749 3750 /* 3751 * Set tracing to whatever the user asked for. Setting 3752 * this register to 0 should have the effect of disabling 3753 * tracing. 3754 */ 3755 TI_LOCK(sc); 3756 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3757 TI_UNLOCK(sc); 3758 break; 3759 } 3760 case TIIOCGETTRACE: { 3761 struct ti_trace_buf *trace_buf; 3762 uint32_t trace_start, cur_trace_ptr, trace_len; 3763 3764 trace_buf = (struct ti_trace_buf *)addr; 3765 3766 TI_LOCK(sc); 3767 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3768 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3769 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3770#if 0 3771 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3772 "trace_len = %d\n", trace_start, 3773 cur_trace_ptr, trace_len); 3774 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3775 trace_buf->buf_len); 3776#endif 3777 error = ti_copy_mem(sc, trace_start, min(trace_len, 3778 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3779 if (error == 0) { 3780 trace_buf->fill_len = min(trace_len, 3781 trace_buf->buf_len); 3782 if (cur_trace_ptr < trace_start) 3783 trace_buf->cur_trace_ptr = 3784 trace_start - cur_trace_ptr; 3785 else 3786 trace_buf->cur_trace_ptr = 3787 cur_trace_ptr - trace_start; 3788 } else 3789 trace_buf->fill_len = 0; 3790 TI_UNLOCK(sc); 3791 break; 3792 } 3793 3794 /* 3795 * For debugging, five ioctls are needed: 3796 * ALT_ATTACH 3797 * ALT_READ_TG_REG 3798 * ALT_WRITE_TG_REG 3799 * ALT_READ_TG_MEM 3800 * ALT_WRITE_TG_MEM 3801 */ 3802 case ALT_ATTACH: 3803 /* 3804 * From what I can tell, Alteon's Solaris Tigon driver 3805 * only has one character device, so you have to attach 3806 * to the Tigon board you're interested in. This seems 3807 * like a not-so-good way to do things, since unless you 3808 * subsequently specify the unit number of the device 3809 * you're interested in every ioctl, you'll only be 3810 * able to debug one board at a time. 3811 */ 3812 break; 3813 case ALT_READ_TG_MEM: 3814 case ALT_WRITE_TG_MEM: 3815 { 3816 struct tg_mem *mem_param; 3817 uint32_t sram_end, scratch_end; 3818 3819 mem_param = (struct tg_mem *)addr; 3820 3821 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3822 sram_end = TI_END_SRAM_I; 3823 scratch_end = TI_END_SCRATCH_I; 3824 } else { 3825 sram_end = TI_END_SRAM_II; 3826 scratch_end = TI_END_SCRATCH_II; 3827 } 3828 3829 /* 3830 * For now, we'll only handle accessing regular SRAM, 3831 * nothing else. 3832 */ 3833 TI_LOCK(sc); 3834 if (mem_param->tgAddr >= TI_BEG_SRAM && 3835 mem_param->tgAddr + mem_param->len <= sram_end) { 3836 /* 3837 * In this instance, we always copy to/from user 3838 * space, so the user space argument is set to 1. 3839 */ 3840 error = ti_copy_mem(sc, mem_param->tgAddr, 3841 mem_param->len, mem_param->userAddr, 1, 3842 cmd == ALT_READ_TG_MEM ? 1 : 0); 3843 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3844 mem_param->tgAddr <= scratch_end) { 3845 error = ti_copy_scratch(sc, mem_param->tgAddr, 3846 mem_param->len, mem_param->userAddr, 1, 3847 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3848 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3849 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3850 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3851 if_printf(sc->ti_ifp, 3852 "invalid memory range for Tigon I\n"); 3853 error = EINVAL; 3854 break; 3855 } 3856 error = ti_copy_scratch(sc, mem_param->tgAddr - 3857 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3858 mem_param->userAddr, 1, 3859 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3860 } else { 3861 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3862 "out of supported range\n", 3863 mem_param->tgAddr, mem_param->len); 3864 error = EINVAL; 3865 } 3866 TI_UNLOCK(sc); 3867 break; 3868 } 3869 case ALT_READ_TG_REG: 3870 case ALT_WRITE_TG_REG: 3871 { 3872 struct tg_reg *regs; 3873 uint32_t tmpval; 3874 3875 regs = (struct tg_reg *)addr; 3876 3877 /* 3878 * Make sure the address in question isn't out of range. 3879 */ 3880 if (regs->addr > TI_REG_MAX) { 3881 error = EINVAL; 3882 break; 3883 } 3884 TI_LOCK(sc); 3885 if (cmd == ALT_READ_TG_REG) { 3886 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3887 regs->addr, &tmpval, 1); 3888 regs->data = ntohl(tmpval); 3889#if 0 3890 if ((regs->addr == TI_CPU_STATE) 3891 || (regs->addr == TI_CPU_CTL_B)) { 3892 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3893 regs->addr, tmpval); 3894 } 3895#endif 3896 } else { 3897 tmpval = htonl(regs->data); 3898 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3899 regs->addr, &tmpval, 1); 3900 } 3901 TI_UNLOCK(sc); 3902 break; 3903 } 3904 default: 3905 error = ENOTTY; 3906 break; 3907 } 3908 return (error); 3909} 3910 3911static void 3912ti_watchdog(void *arg) 3913{ 3914 struct ti_softc *sc; 3915 struct ifnet *ifp; 3916 3917 sc = arg; 3918 TI_LOCK_ASSERT(sc); 3919 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3920 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3921 return; 3922 3923 /* 3924 * When we're debugging, the chip is often stopped for long periods 3925 * of time, and that would normally cause the watchdog timer to fire. 3926 * Since that impedes debugging, we don't want to do that. 3927 */ 3928 if (sc->ti_flags & TI_FLAG_DEBUGING) 3929 return; 3930 3931 ifp = sc->ti_ifp; 3932 if_printf(ifp, "watchdog timeout -- resetting\n"); 3933 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3934 ti_init_locked(sc); 3935 3936 ifp->if_oerrors++; 3937} 3938 3939/* 3940 * Stop the adapter and free any mbufs allocated to the 3941 * RX and TX lists. 3942 */ 3943static void 3944ti_stop(struct ti_softc *sc) 3945{ 3946 struct ifnet *ifp; 3947 struct ti_cmd_desc cmd; 3948 3949 TI_LOCK_ASSERT(sc); 3950 3951 ifp = sc->ti_ifp; 3952 3953 /* Disable host interrupts. */ 3954 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3955 /* 3956 * Tell firmware we're shutting down. 3957 */ 3958 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3959 3960 /* Halt and reinitialize. */ 3961 if (ti_chipinit(sc) == 0) { 3962 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3963 /* XXX ignore init errors. */ 3964 ti_chipinit(sc); 3965 } 3966 3967 /* Free the RX lists. */ 3968 ti_free_rx_ring_std(sc); 3969 3970 /* Free jumbo RX list. */ 3971 ti_free_rx_ring_jumbo(sc); 3972 3973 /* Free mini RX list. */ 3974 ti_free_rx_ring_mini(sc); 3975 3976 /* Free TX buffers. */ 3977 ti_free_tx_ring(sc); 3978 3979 sc->ti_ev_prodidx.ti_idx = 0; 3980 sc->ti_return_prodidx.ti_idx = 0; 3981 sc->ti_tx_considx.ti_idx = 0; 3982 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3983 3984 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3985 callout_stop(&sc->ti_watchdog); 3986} 3987 3988/* 3989 * Stop all chip I/O so that the kernel's probe routines don't 3990 * get confused by errant DMAs when rebooting. 3991 */ 3992static int 3993ti_shutdown(device_t dev) 3994{ 3995 struct ti_softc *sc; 3996 3997 sc = device_get_softc(dev); 3998 TI_LOCK(sc); 3999 ti_chipinit(sc); 4000 TI_UNLOCK(sc); 4001 4002 return (0); 4003} 4004 4005static void 4006ti_sysctl_node(struct ti_softc *sc) 4007{ 4008 struct sysctl_ctx_list *ctx; 4009 struct sysctl_oid_list *child; 4010 char tname[32]; 4011 4012 ctx = device_get_sysctl_ctx(sc->ti_dev); 4013 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 4014 4015 /* Use DAC */ 4016 sc->ti_dac = 1; 4017 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 4018 device_get_unit(sc->ti_dev)); 4019 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 4020 4021 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 4022 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 4023 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4024 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4025 4026 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4027 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4028 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4029 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4030 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4031 &sc->ti_tx_buf_ratio, 0, 4032 "Ratio of NIC memory devoted to TX buffer"); 4033 4034 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4035 &sc->ti_stat_ticks, 0, 4036 "Number of clock ticks for statistics update interval"); 4037 4038 /* Pull in device tunables. */ 4039 sc->ti_rx_coal_ticks = 170; 4040 resource_int_value(device_get_name(sc->ti_dev), 4041 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4042 &sc->ti_rx_coal_ticks); 4043 sc->ti_rx_max_coal_bds = 64; 4044 resource_int_value(device_get_name(sc->ti_dev), 4045 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4046 &sc->ti_rx_max_coal_bds); 4047 4048 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4049 resource_int_value(device_get_name(sc->ti_dev), 4050 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4051 &sc->ti_tx_coal_ticks); 4052 sc->ti_tx_max_coal_bds = 32; 4053 resource_int_value(device_get_name(sc->ti_dev), 4054 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4055 &sc->ti_tx_max_coal_bds); 4056 sc->ti_tx_buf_ratio = 21; 4057 resource_int_value(device_get_name(sc->ti_dev), 4058 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4059 &sc->ti_tx_buf_ratio); 4060 4061 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4062 resource_int_value(device_get_name(sc->ti_dev), 4063 device_get_unit(sc->ti_dev), "stat_ticks", 4064 &sc->ti_stat_ticks); 4065} 4066