if_ti.c revision 173839
1139825Simp/*- 245386Swpaul * Copyright (c) 1997, 1998, 1999 345386Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 445386Swpaul * 545386Swpaul * Redistribution and use in source and binary forms, with or without 645386Swpaul * modification, are permitted provided that the following conditions 745386Swpaul * are met: 845386Swpaul * 1. Redistributions of source code must retain the above copyright 945386Swpaul * notice, this list of conditions and the following disclaimer. 1045386Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1145386Swpaul * notice, this list of conditions and the following disclaimer in the 1245386Swpaul * documentation and/or other materials provided with the distribution. 1345386Swpaul * 3. All advertising materials mentioning features or use of this software 1445386Swpaul * must display the following acknowledgement: 1545386Swpaul * This product includes software developed by Bill Paul. 1645386Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1745386Swpaul * may be used to endorse or promote products derived from this software 1845386Swpaul * without specific prior written permission. 1945386Swpaul * 2045386Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2145386Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2245386Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2345386Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2445386Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2545386Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2645386Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2745386Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2845386Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2945386Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3045386Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3145386Swpaul */ 3245386Swpaul 3345386Swpaul/* 3445386Swpaul * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3545386Swpaul * Manuals, sample driver and firmware source kits are available 3645386Swpaul * from http://www.alteon.com/support/openkits. 37131652Sbms * 3845386Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 3945386Swpaul * Electrical Engineering Department 4045386Swpaul * Columbia University, New York City 4145386Swpaul */ 4245386Swpaul 4345386Swpaul/* 4445386Swpaul * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4545386Swpaul * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4645386Swpaul * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4745386Swpaul * Tigon supports hardware IP, TCP and UCP checksumming, multicast 4845386Swpaul * filtering and jumbo (9014 byte) frames. The hardware is largely 4945386Swpaul * controlled by firmware, which must be loaded into the NIC during 5045386Swpaul * initialization. 5145386Swpaul * 5245386Swpaul * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5345386Swpaul * revision, which supports new features such as extended commands, 5445386Swpaul * extended jumbo receive ring desciptors and a mini receive ring. 5545386Swpaul * 5645386Swpaul * Alteon Networks is to be commended for releasing such a vast amount 5745386Swpaul * of development material for the Tigon NIC without requiring an NDA 5845386Swpaul * (although they really should have done it a long time ago). With 5945386Swpaul * any luck, the other vendors will finally wise up and follow Alteon's 6045386Swpaul * stellar example. 6145386Swpaul * 6245386Swpaul * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6345386Swpaul * this driver by #including it as a C header file. This bloats the 6445386Swpaul * driver somewhat, but it's the easiest method considering that the 6545386Swpaul * driver code and firmware code need to be kept in sync. The source 6645386Swpaul * for the firmware is not provided with the FreeBSD distribution since 6745386Swpaul * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 6845386Swpaul * 6945386Swpaul * The following people deserve special thanks: 7045386Swpaul * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7145386Swpaul * for testing 7245386Swpaul * - Raymond Lee of Netgear, for providing a pair of Netgear 7345386Swpaul * GA620 Tigon 2 boards for testing 7445386Swpaul * - Ulf Zimmermann, for bringing the GA260 to my attention and 7545386Swpaul * convincing me to write this driver. 7645386Swpaul * - Andrew Gallatin for providing FreeBSD/Alpha support. 7745386Swpaul */ 7845386Swpaul 79113038Sobrien#include <sys/cdefs.h> 80113038Sobrien__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 173839 2007-11-22 02:45:00Z yongari $"); 81113038Sobrien 8298849Sken#include "opt_ti.h" 8398849Sken 8445386Swpaul#include <sys/param.h> 8545386Swpaul#include <sys/systm.h> 8645386Swpaul#include <sys/sockio.h> 8745386Swpaul#include <sys/mbuf.h> 8845386Swpaul#include <sys/malloc.h> 8945386Swpaul#include <sys/kernel.h> 90129878Sphk#include <sys/module.h> 9145386Swpaul#include <sys/socket.h> 9245386Swpaul#include <sys/queue.h> 9398849Sken#include <sys/conf.h> 94153770Syongari#include <sys/sf_buf.h> 9545386Swpaul 9645386Swpaul#include <net/if.h> 9745386Swpaul#include <net/if_arp.h> 9845386Swpaul#include <net/ethernet.h> 9945386Swpaul#include <net/if_dl.h> 10045386Swpaul#include <net/if_media.h> 10183115Sbrooks#include <net/if_types.h> 10283115Sbrooks#include <net/if_vlan_var.h> 10345386Swpaul 10445386Swpaul#include <net/bpf.h> 10545386Swpaul 10645386Swpaul#include <netinet/in_systm.h> 10745386Swpaul#include <netinet/in.h> 10845386Swpaul#include <netinet/ip.h> 10945386Swpaul 11045386Swpaul#include <machine/bus.h> 11149011Swpaul#include <machine/resource.h> 11249011Swpaul#include <sys/bus.h> 11349011Swpaul#include <sys/rman.h> 11445386Swpaul 11598849Sken/* #define TI_PRIVATE_JUMBOS */ 116153770Syongari#ifndef TI_PRIVATE_JUMBOS 117153770Syongari#include <vm/vm.h> 11898849Sken#include <vm/vm_page.h> 119153770Syongari#endif 12098849Sken 121119288Simp#include <dev/pci/pcireg.h> 122119288Simp#include <dev/pci/pcivar.h> 12345386Swpaul 12498849Sken#include <sys/tiio.h> 125153280Sscottl#include <dev/ti/if_tireg.h> 126153280Sscottl#include <dev/ti/ti_fw.h> 127153280Sscottl#include <dev/ti/ti_fw2.h> 12845386Swpaul 12958698Sjlemon#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 13098849Sken/* 13198849Sken * We can only turn on header splitting if we're using extended receive 13298849Sken * BDs. 13398849Sken */ 13498849Sken#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 13598849Sken#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 13698849Sken#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 13745386Swpaul 13898849Skentypedef enum { 13998849Sken TI_SWAP_HTON, 14098849Sken TI_SWAP_NTOH 14198849Sken} ti_swap_type; 14298849Sken 14398849Sken 14445386Swpaul/* 14545386Swpaul * Various supported device vendors/types and their names. 14645386Swpaul */ 14745386Swpaul 14845386Swpaulstatic struct ti_type ti_devs[] = { 14945386Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC, 15063702Swpaul "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 15163699Swpaul { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 15263702Swpaul "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 15345386Swpaul { TC_VENDORID, TC_DEVICEID_3C985, 15445386Swpaul "3Com 3c985-SX Gigabit Ethernet" }, 15545386Swpaul { NG_VENDORID, NG_DEVICEID_GA620, 15664139Swpaul "Netgear GA620 1000baseSX Gigabit Ethernet" }, 15764139Swpaul { NG_VENDORID, NG_DEVICEID_GA620T, 15864139Swpaul "Netgear GA620 1000baseT Gigabit Ethernet" }, 15945386Swpaul { SGI_VENDORID, SGI_DEVICEID_TIGON, 16045386Swpaul "Silicon Graphics Gigabit Ethernet" }, 16156206Swpaul { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 16256206Swpaul "Farallon PN9000SX Gigabit Ethernet" }, 16345386Swpaul { 0, 0, NULL } 16445386Swpaul}; 16545386Swpaul 16698849Sken 16798849Skenstatic d_open_t ti_open; 16898849Skenstatic d_close_t ti_close; 16998849Skenstatic d_ioctl_t ti_ioctl2; 17098849Sken 17198849Skenstatic struct cdevsw ti_cdevsw = { 172126080Sphk .d_version = D_VERSION, 173153281Sscottl .d_flags = 0, 174111815Sphk .d_open = ti_open, 175111815Sphk .d_close = ti_close, 176111815Sphk .d_ioctl = ti_ioctl2, 177111815Sphk .d_name = "ti", 17898849Sken}; 17998849Sken 180142407Simpstatic int ti_probe(device_t); 181142407Simpstatic int ti_attach(device_t); 182142407Simpstatic int ti_detach(device_t); 183142407Simpstatic void ti_txeof(struct ti_softc *); 184142407Simpstatic void ti_rxeof(struct ti_softc *); 18545386Swpaul 186142407Simpstatic void ti_stats_update(struct ti_softc *); 187153982Syongaristatic int ti_encap(struct ti_softc *, struct mbuf **); 18845386Swpaul 189142407Simpstatic void ti_intr(void *); 190142407Simpstatic void ti_start(struct ifnet *); 191153770Syongaristatic void ti_start_locked(struct ifnet *); 192142407Simpstatic int ti_ioctl(struct ifnet *, u_long, caddr_t); 193142407Simpstatic void ti_init(void *); 194153770Syongaristatic void ti_init_locked(void *); 195142407Simpstatic void ti_init2(struct ti_softc *); 196142407Simpstatic void ti_stop(struct ti_softc *); 197142407Simpstatic void ti_watchdog(struct ifnet *); 198173839Syongaristatic int ti_shutdown(device_t); 199142407Simpstatic int ti_ifmedia_upd(struct ifnet *); 200142407Simpstatic void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 20145386Swpaul 202142407Simpstatic u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 203142407Simpstatic u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 204142407Simpstatic int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 20545386Swpaul 206142407Simpstatic void ti_add_mcast(struct ti_softc *, struct ether_addr *); 207142407Simpstatic void ti_del_mcast(struct ti_softc *, struct ether_addr *); 208142407Simpstatic void ti_setmulti(struct ti_softc *); 20945386Swpaul 210153770Syongaristatic void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 211153770Syongaristatic void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 212153770Syongaristatic void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 213142407Simpstatic int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 214142407Simpstatic int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 215142407Simp int, int, int); 216142407Simpstatic int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 217142407Simpstatic void ti_loadfw(struct ti_softc *); 218142407Simpstatic void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 219142407Simpstatic void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 220142407Simpstatic void ti_handle_events(struct ti_softc *); 221153396Sscottlstatic int ti_alloc_dmamaps(struct ti_softc *); 222153396Sscottlstatic void ti_free_dmamaps(struct ti_softc *); 223153396Sscottlstatic int ti_alloc_jumbo_mem(struct ti_softc *); 22498849Sken#ifdef TI_PRIVATE_JUMBOS 225142407Simpstatic void *ti_jalloc(struct ti_softc *); 226142407Simpstatic void ti_jfree(void *, void *); 22798849Sken#endif /* TI_PRIVATE_JUMBOS */ 228142407Simpstatic int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 229142407Simpstatic int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 230142407Simpstatic int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 231142407Simpstatic int ti_init_rx_ring_std(struct ti_softc *); 232142407Simpstatic void ti_free_rx_ring_std(struct ti_softc *); 233142407Simpstatic int ti_init_rx_ring_jumbo(struct ti_softc *); 234142407Simpstatic void ti_free_rx_ring_jumbo(struct ti_softc *); 235142407Simpstatic int ti_init_rx_ring_mini(struct ti_softc *); 236142407Simpstatic void ti_free_rx_ring_mini(struct ti_softc *); 237142407Simpstatic void ti_free_tx_ring(struct ti_softc *); 238142407Simpstatic int ti_init_tx_ring(struct ti_softc *); 23945386Swpaul 240142407Simpstatic int ti_64bitslot_war(struct ti_softc *); 241142407Simpstatic int ti_chipinit(struct ti_softc *); 242142407Simpstatic int ti_gibinit(struct ti_softc *); 24345386Swpaul 24498849Sken#ifdef TI_JUMBO_HDRSPLIT 24599013Speterstatic __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 24699013Speter int pkt_len, int idx); 24798849Sken#endif /* TI_JUMBO_HDRSPLIT */ 24898849Sken 24949011Swpaulstatic device_method_t ti_methods[] = { 25049011Swpaul /* Device interface */ 25149011Swpaul DEVMETHOD(device_probe, ti_probe), 25249011Swpaul DEVMETHOD(device_attach, ti_attach), 25349011Swpaul DEVMETHOD(device_detach, ti_detach), 25449011Swpaul DEVMETHOD(device_shutdown, ti_shutdown), 25549011Swpaul { 0, 0 } 25649011Swpaul}; 25749011Swpaul 25849011Swpaulstatic driver_t ti_driver = { 25951455Swpaul "ti", 26049011Swpaul ti_methods, 26149011Swpaul sizeof(struct ti_softc) 26249011Swpaul}; 26349011Swpaul 26449011Swpaulstatic devclass_t ti_devclass; 26549011Swpaul 266113506SmdoddDRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 267113506SmdoddMODULE_DEPEND(ti, pci, 1, 1, 1); 268113506SmdoddMODULE_DEPEND(ti, ether, 1, 1, 1); 26949011Swpaul 27045386Swpaul/* 27145386Swpaul * Send an instruction or address to the EEPROM, check for ACK. 27245386Swpaul */ 27345386Swpaulstatic u_int32_t ti_eeprom_putbyte(sc, byte) 27445386Swpaul struct ti_softc *sc; 27545386Swpaul int byte; 27645386Swpaul{ 277153770Syongari int i, ack = 0; 27845386Swpaul 27945386Swpaul /* 28045386Swpaul * Make sure we're in TX mode. 28145386Swpaul */ 28245386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 28345386Swpaul 28445386Swpaul /* 28545386Swpaul * Feed in each bit and stobe the clock. 28645386Swpaul */ 28745386Swpaul for (i = 0x80; i; i >>= 1) { 28845386Swpaul if (byte & i) { 28945386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 29045386Swpaul } else { 29145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 29245386Swpaul } 29345386Swpaul DELAY(1); 29445386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 29545386Swpaul DELAY(1); 29645386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 29745386Swpaul } 29845386Swpaul 29945386Swpaul /* 30045386Swpaul * Turn off TX mode. 30145386Swpaul */ 30245386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 30345386Swpaul 30445386Swpaul /* 30545386Swpaul * Check for ack. 30645386Swpaul */ 30745386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 30845386Swpaul ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 30945386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 31045386Swpaul 311131654Sbms return (ack); 31245386Swpaul} 31345386Swpaul 31445386Swpaul/* 31545386Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 31645386Swpaul * We have to send two address bytes since the EEPROM can hold 31745386Swpaul * more than 256 bytes of data. 31845386Swpaul */ 31945386Swpaulstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 32045386Swpaul struct ti_softc *sc; 32145386Swpaul int addr; 32245386Swpaul u_int8_t *dest; 32345386Swpaul{ 324153770Syongari int i; 32545386Swpaul u_int8_t byte = 0; 32645386Swpaul 32745386Swpaul EEPROM_START; 32845386Swpaul 32945386Swpaul /* 33045386Swpaul * Send write control code to EEPROM. 33145386Swpaul */ 33245386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 333162321Sglebius device_printf(sc->ti_dev, 334150719Sjhb "failed to send write command, status: %x\n", 335150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 336131654Sbms return (1); 33745386Swpaul } 33845386Swpaul 33945386Swpaul /* 34045386Swpaul * Send first byte of address of byte we want to read. 34145386Swpaul */ 34245386Swpaul if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 343162321Sglebius device_printf(sc->ti_dev, "failed to send address, status: %x\n", 344150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 345131654Sbms return (1); 34645386Swpaul } 34745386Swpaul /* 34845386Swpaul * Send second byte address of byte we want to read. 34945386Swpaul */ 35045386Swpaul if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 351162321Sglebius device_printf(sc->ti_dev, "failed to send address, status: %x\n", 352150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 353131654Sbms return (1); 35445386Swpaul } 35545386Swpaul 35645386Swpaul EEPROM_STOP; 35745386Swpaul EEPROM_START; 35845386Swpaul /* 35945386Swpaul * Send read control code to EEPROM. 36045386Swpaul */ 36145386Swpaul if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 362162321Sglebius device_printf(sc->ti_dev, 363150719Sjhb "failed to send read command, status: %x\n", 364150719Sjhb CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 365131654Sbms return (1); 36645386Swpaul } 36745386Swpaul 36845386Swpaul /* 36945386Swpaul * Start reading bits from EEPROM. 37045386Swpaul */ 37145386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 37245386Swpaul for (i = 0x80; i; i >>= 1) { 37345386Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 37445386Swpaul DELAY(1); 37545386Swpaul if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 37645386Swpaul byte |= i; 37745386Swpaul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 37845386Swpaul DELAY(1); 37945386Swpaul } 38045386Swpaul 38145386Swpaul EEPROM_STOP; 38245386Swpaul 38345386Swpaul /* 38445386Swpaul * No ACK generated for read, so just return byte. 38545386Swpaul */ 38645386Swpaul 38745386Swpaul *dest = byte; 38845386Swpaul 389131654Sbms return (0); 39045386Swpaul} 39145386Swpaul 39245386Swpaul/* 39345386Swpaul * Read a sequence of bytes from the EEPROM. 39445386Swpaul */ 395102336Salfredstatic int 396102336Salfredti_read_eeprom(sc, dest, off, cnt) 39745386Swpaul struct ti_softc *sc; 39845386Swpaul caddr_t dest; 39945386Swpaul int off; 40045386Swpaul int cnt; 40145386Swpaul{ 40245386Swpaul int err = 0, i; 40345386Swpaul u_int8_t byte = 0; 40445386Swpaul 40545386Swpaul for (i = 0; i < cnt; i++) { 40645386Swpaul err = ti_eeprom_getbyte(sc, off + i, &byte); 40745386Swpaul if (err) 40845386Swpaul break; 40945386Swpaul *(dest + i) = byte; 41045386Swpaul } 41145386Swpaul 412131654Sbms return (err ? 1 : 0); 41345386Swpaul} 41445386Swpaul 41545386Swpaul/* 416153770Syongari * NIC memory read function. 417153770Syongari * Can be used to copy data from NIC local memory. 41845386Swpaul */ 419102336Salfredstatic void 420153770Syongariti_mem_read(sc, addr, len, buf) 42145386Swpaul struct ti_softc *sc; 42245386Swpaul u_int32_t addr, len; 423153770Syongari void *buf; 42445386Swpaul{ 42545386Swpaul int segptr, segsize, cnt; 426153770Syongari char *ptr; 42745386Swpaul 42845386Swpaul segptr = addr; 42945386Swpaul cnt = len; 43045386Swpaul ptr = buf; 43145386Swpaul 432131654Sbms while (cnt) { 43345386Swpaul if (cnt < TI_WINLEN) 43445386Swpaul segsize = cnt; 43545386Swpaul else 43645386Swpaul segsize = TI_WINLEN - (segptr % TI_WINLEN); 43745386Swpaul CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438153770Syongari bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439153770Syongari TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 440153770Syongari segsize / 4); 441153770Syongari ptr += segsize; 44245386Swpaul segptr += segsize; 44345386Swpaul cnt -= segsize; 44445386Swpaul } 44545386Swpaul} 44645386Swpaul 447153770Syongari 448153770Syongari/* 449153770Syongari * NIC memory write function. 450153770Syongari * Can be used to copy data into NIC local memory. 451153770Syongari */ 452153770Syongaristatic void 453153770Syongariti_mem_write(sc, addr, len, buf) 454153770Syongari struct ti_softc *sc; 455153770Syongari u_int32_t addr, len; 456153770Syongari void *buf; 457153770Syongari{ 458153770Syongari int segptr, segsize, cnt; 459153770Syongari char *ptr; 460153770Syongari 461153770Syongari segptr = addr; 462153770Syongari cnt = len; 463153770Syongari ptr = buf; 464153770Syongari 465153770Syongari while (cnt) { 466153770Syongari if (cnt < TI_WINLEN) 467153770Syongari segsize = cnt; 468153770Syongari else 469153770Syongari segsize = TI_WINLEN - (segptr % TI_WINLEN); 470153770Syongari CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 471153770Syongari bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 472153770Syongari TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 473153770Syongari segsize / 4); 474153770Syongari ptr += segsize; 475153770Syongari segptr += segsize; 476153770Syongari cnt -= segsize; 477153770Syongari } 478153770Syongari} 479153770Syongari 480153770Syongari/* 481153770Syongari * NIC memory read function. 482153770Syongari * Can be used to clear a section of NIC local memory. 483153770Syongari */ 484153770Syongaristatic void 485153770Syongariti_mem_zero(sc, addr, len) 486153770Syongari struct ti_softc *sc; 487153770Syongari u_int32_t addr, len; 488153770Syongari{ 489153770Syongari int segptr, segsize, cnt; 490153770Syongari 491153770Syongari segptr = addr; 492153770Syongari cnt = len; 493153770Syongari 494153770Syongari while (cnt) { 495153770Syongari if (cnt < TI_WINLEN) 496153770Syongari segsize = cnt; 497153770Syongari else 498153770Syongari segsize = TI_WINLEN - (segptr % TI_WINLEN); 499153770Syongari CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 500153770Syongari bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 501153770Syongari TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 502153770Syongari segptr += segsize; 503153770Syongari cnt -= segsize; 504153770Syongari } 505153770Syongari} 506153770Syongari 50798849Skenstatic int 50898849Skenti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 50998849Sken struct ti_softc *sc; 51098849Sken u_int32_t tigon_addr, len; 51198849Sken caddr_t buf; 51298849Sken int useraddr, readdata; 51398849Sken{ 51498849Sken int segptr, segsize, cnt; 51598849Sken caddr_t ptr; 51698849Sken u_int32_t origwin; 51798849Sken u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 51898849Sken int resid, segresid; 51998849Sken int first_pass; 52098849Sken 521153770Syongari TI_LOCK_ASSERT(sc); 522153770Syongari 52398849Sken /* 52498849Sken * At the moment, we don't handle non-aligned cases, we just bail. 52598849Sken * If this proves to be a problem, it will be fixed. 52698849Sken */ 52798849Sken if ((readdata == 0) 52898849Sken && (tigon_addr & 0x3)) { 529162321Sglebius device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 530162321Sglebius "word-aligned\n", __func__, tigon_addr); 531162321Sglebius device_printf(sc->ti_dev, "%s: unaligned writes aren't " 532162321Sglebius "yet supported\n", __func__); 533131654Sbms return (EINVAL); 53498849Sken } 53598849Sken 53698849Sken segptr = tigon_addr & ~0x3; 53798849Sken segresid = tigon_addr - segptr; 53898849Sken 53998849Sken /* 54098849Sken * This is the non-aligned amount left over that we'll need to 54198849Sken * copy. 54298849Sken */ 54398849Sken resid = len & 0x3; 54498849Sken 54598849Sken /* Add in the left over amount at the front of the buffer */ 54698849Sken resid += segresid; 54798849Sken 54898849Sken cnt = len & ~0x3; 54998849Sken /* 55098849Sken * If resid + segresid is >= 4, add multiples of 4 to the count and 55198849Sken * decrease the residual by that much. 55298849Sken */ 55398849Sken cnt += resid & ~0x3; 55498849Sken resid -= resid & ~0x3; 55598849Sken 55698849Sken ptr = buf; 55798849Sken 55898849Sken first_pass = 1; 55998849Sken 56098849Sken /* 56198849Sken * Save the old window base value. 56298849Sken */ 56398849Sken origwin = CSR_READ_4(sc, TI_WINBASE); 56498849Sken 565131654Sbms while (cnt) { 56698849Sken bus_size_t ti_offset; 56798849Sken 56898849Sken if (cnt < TI_WINLEN) 56998849Sken segsize = cnt; 57098849Sken else 57198849Sken segsize = TI_WINLEN - (segptr % TI_WINLEN); 57298849Sken CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 57398849Sken 57498849Sken ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 57598849Sken 57698849Sken if (readdata) { 57798849Sken 57898849Sken bus_space_read_region_4(sc->ti_btag, 57998849Sken sc->ti_bhandle, ti_offset, 58098849Sken (u_int32_t *)tmparray, 58198849Sken segsize >> 2); 58298849Sken if (useraddr) { 58398849Sken /* 58498849Sken * Yeah, this is a little on the kludgy 58598849Sken * side, but at least this code is only 58698849Sken * used for debugging. 58798849Sken */ 58898849Sken ti_bcopy_swap(tmparray, tmparray2, segsize, 58998849Sken TI_SWAP_NTOH); 59098849Sken 591153281Sscottl TI_UNLOCK(sc); 59298849Sken if (first_pass) { 59398849Sken copyout(&tmparray2[segresid], ptr, 59498849Sken segsize - segresid); 59598849Sken first_pass = 0; 59698849Sken } else 59798849Sken copyout(tmparray2, ptr, segsize); 598153281Sscottl TI_LOCK(sc); 59998849Sken } else { 60098849Sken if (first_pass) { 60198849Sken 60298849Sken ti_bcopy_swap(tmparray, tmparray2, 60398849Sken segsize, TI_SWAP_NTOH); 604153281Sscottl TI_UNLOCK(sc); 60598849Sken bcopy(&tmparray2[segresid], ptr, 60698849Sken segsize - segresid); 607153281Sscottl TI_LOCK(sc); 60898849Sken first_pass = 0; 60998849Sken } else 61098849Sken ti_bcopy_swap(tmparray, ptr, segsize, 61198849Sken TI_SWAP_NTOH); 61298849Sken } 61398849Sken 61498849Sken } else { 61598849Sken if (useraddr) { 616153281Sscottl TI_UNLOCK(sc); 61798849Sken copyin(ptr, tmparray2, segsize); 618153281Sscottl TI_LOCK(sc); 61998849Sken ti_bcopy_swap(tmparray2, tmparray, segsize, 62098849Sken TI_SWAP_HTON); 62198849Sken } else 62298849Sken ti_bcopy_swap(ptr, tmparray, segsize, 62398849Sken TI_SWAP_HTON); 62498849Sken 62598849Sken bus_space_write_region_4(sc->ti_btag, 62698849Sken sc->ti_bhandle, ti_offset, 62798849Sken (u_int32_t *)tmparray, 62898849Sken segsize >> 2); 62998849Sken } 63098849Sken segptr += segsize; 63198849Sken ptr += segsize; 63298849Sken cnt -= segsize; 63398849Sken } 63498849Sken 63598849Sken /* 63698849Sken * Handle leftover, non-word-aligned bytes. 63798849Sken */ 63898849Sken if (resid != 0) { 63998849Sken u_int32_t tmpval, tmpval2; 64098849Sken bus_size_t ti_offset; 64198849Sken 64298849Sken /* 64398849Sken * Set the segment pointer. 64498849Sken */ 64598849Sken CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 64698849Sken 64798849Sken ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 64898849Sken 64998849Sken /* 65098849Sken * First, grab whatever is in our source/destination. 65198849Sken * We'll obviously need this for reads, but also for 65298849Sken * writes, since we'll be doing read/modify/write. 65398849Sken */ 65498849Sken bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 65598849Sken ti_offset, &tmpval, 1); 65698849Sken 65798849Sken /* 65898849Sken * Next, translate this from little-endian to big-endian 65998849Sken * (at least on i386 boxes). 66098849Sken */ 66198849Sken tmpval2 = ntohl(tmpval); 66298849Sken 66398849Sken if (readdata) { 66498849Sken /* 66598849Sken * If we're reading, just copy the leftover number 66698849Sken * of bytes from the host byte order buffer to 66798849Sken * the user's buffer. 66898849Sken */ 669153281Sscottl if (useraddr) { 670153281Sscottl TI_UNLOCK(sc); 67198849Sken copyout(&tmpval2, ptr, resid); 672153281Sscottl TI_LOCK(sc); 673153281Sscottl } else 67498849Sken bcopy(&tmpval2, ptr, resid); 67598849Sken } else { 67698849Sken /* 67798849Sken * If we're writing, first copy the bytes to be 67898849Sken * written into the network byte order buffer, 67998849Sken * leaving the rest of the buffer with whatever was 68098849Sken * originally in there. Then, swap the bytes 68198849Sken * around into host order and write them out. 68298849Sken * 68398849Sken * XXX KDM the read side of this has been verified 68498849Sken * to work, but the write side of it has not been 68598849Sken * verified. So user beware. 68698849Sken */ 687153281Sscottl if (useraddr) { 688153281Sscottl TI_UNLOCK(sc); 68998849Sken copyin(ptr, &tmpval2, resid); 690153281Sscottl TI_LOCK(sc); 691153281Sscottl } else 69298849Sken bcopy(ptr, &tmpval2, resid); 69398849Sken 69498849Sken tmpval = htonl(tmpval2); 69598849Sken 69698849Sken bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 69798849Sken ti_offset, &tmpval, 1); 69898849Sken } 69998849Sken } 70098849Sken 70198849Sken CSR_WRITE_4(sc, TI_WINBASE, origwin); 70298849Sken 703131654Sbms return (0); 70498849Sken} 70598849Sken 70698849Skenstatic int 70798849Skenti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 70898849Sken struct ti_softc *sc; 70998849Sken u_int32_t tigon_addr, len; 71098849Sken caddr_t buf; 71198849Sken int useraddr, readdata; 71298849Sken int cpu; 71398849Sken{ 71498849Sken u_int32_t segptr; 71598849Sken int cnt; 71698849Sken u_int32_t tmpval, tmpval2; 71798849Sken caddr_t ptr; 71898849Sken 719153770Syongari TI_LOCK_ASSERT(sc); 720153770Syongari 72198849Sken /* 72298849Sken * At the moment, we don't handle non-aligned cases, we just bail. 72398849Sken * If this proves to be a problem, it will be fixed. 72498849Sken */ 72598849Sken if (tigon_addr & 0x3) { 726162321Sglebius device_printf(sc->ti_dev, "%s: tigon address %#x " 727162321Sglebius "isn't word-aligned\n", __func__, tigon_addr); 728131654Sbms return (EINVAL); 72998849Sken } 73098849Sken 73198849Sken if (len & 0x3) { 732162321Sglebius device_printf(sc->ti_dev, "%s: transfer length %d " 733162321Sglebius "isn't word-aligned\n", __func__, len); 734131654Sbms return (EINVAL); 73598849Sken } 73698849Sken 73798849Sken segptr = tigon_addr; 73898849Sken cnt = len; 73998849Sken ptr = buf; 74098849Sken 74198849Sken while (cnt) { 74298849Sken CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 74398849Sken 74498849Sken if (readdata) { 74598849Sken tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 74698849Sken 74798849Sken tmpval = ntohl(tmpval2); 74898849Sken 74998849Sken /* 75098849Sken * Note: I've used this debugging interface 75198849Sken * extensively with Alteon's 12.3.15 firmware, 75298849Sken * compiled with GCC 2.7.2.1 and binutils 2.9.1. 75398849Sken * 75498849Sken * When you compile the firmware without 75598849Sken * optimization, which is necessary sometimes in 75698849Sken * order to properly step through it, you sometimes 757131652Sbms * read out a bogus value of 0xc0017c instead of 75898849Sken * whatever was supposed to be in that scratchpad 75998849Sken * location. That value is on the stack somewhere, 76098849Sken * but I've never been able to figure out what was 76198849Sken * causing the problem. 76298849Sken * 76398849Sken * The address seems to pop up in random places, 76498849Sken * often not in the same place on two subsequent 76598849Sken * reads. 76698849Sken * 76798849Sken * In any case, the underlying data doesn't seem 76898849Sken * to be affected, just the value read out. 76998849Sken * 77098849Sken * KDM, 3/7/2000 77198849Sken */ 77298849Sken 77398849Sken if (tmpval2 == 0xc0017c) 774162321Sglebius device_printf(sc->ti_dev, "found 0xc0017c at " 775162321Sglebius "%#x (tmpval2)\n", segptr); 77698849Sken 77798849Sken if (tmpval == 0xc0017c) 778162321Sglebius device_printf(sc->ti_dev, "found 0xc0017c at " 779162321Sglebius "%#x (tmpval)\n", segptr); 78098849Sken 78198849Sken if (useraddr) 78298849Sken copyout(&tmpval, ptr, 4); 78398849Sken else 78498849Sken bcopy(&tmpval, ptr, 4); 78598849Sken } else { 78698849Sken if (useraddr) 78798849Sken copyin(ptr, &tmpval2, 4); 78898849Sken else 78998849Sken bcopy(ptr, &tmpval2, 4); 79098849Sken 79198849Sken tmpval = htonl(tmpval2); 79298849Sken 79398849Sken CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 79498849Sken } 79598849Sken 79698849Sken cnt -= 4; 79798849Sken segptr += 4; 79898849Sken ptr += 4; 79998849Sken } 80098849Sken 801131654Sbms return (0); 80298849Sken} 80398849Sken 80498849Skenstatic int 80598849Skenti_bcopy_swap(src, dst, len, swap_type) 80698849Sken const void *src; 80798849Sken void *dst; 80898849Sken size_t len; 80998849Sken ti_swap_type swap_type; 81098849Sken{ 81198849Sken const u_int8_t *tmpsrc; 81298849Sken u_int8_t *tmpdst; 81398849Sken size_t tmplen; 81498849Sken 81598849Sken if (len & 0x3) { 816106627Sjhb printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 81798849Sken len); 818131654Sbms return (-1); 81998849Sken } 82098849Sken 82198849Sken tmpsrc = src; 82298849Sken tmpdst = dst; 82398849Sken tmplen = len; 82498849Sken 82598849Sken while (tmplen) { 82698849Sken if (swap_type == TI_SWAP_NTOH) 82798849Sken *(u_int32_t *)tmpdst = 82898849Sken ntohl(*(const u_int32_t *)tmpsrc); 82998849Sken else 83098849Sken *(u_int32_t *)tmpdst = 83198849Sken htonl(*(const u_int32_t *)tmpsrc); 83298849Sken 83398849Sken tmpsrc += 4; 83498849Sken tmpdst += 4; 83598849Sken tmplen -= 4; 83698849Sken } 83798849Sken 838131654Sbms return (0); 83998849Sken} 84098849Sken 84145386Swpaul/* 84245386Swpaul * Load firmware image into the NIC. Check that the firmware revision 84345386Swpaul * is acceptable and see if we want the firmware for the Tigon 1 or 84445386Swpaul * Tigon 2. 84545386Swpaul */ 846102336Salfredstatic void 847102336Salfredti_loadfw(sc) 84845386Swpaul struct ti_softc *sc; 84945386Swpaul{ 850153770Syongari 851153770Syongari TI_LOCK_ASSERT(sc); 852153770Syongari 853131654Sbms switch (sc->ti_hwrev) { 85445386Swpaul case TI_HWREV_TIGON: 85545386Swpaul if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 85645386Swpaul tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 85745386Swpaul tigonFwReleaseFix != TI_FIRMWARE_FIX) { 858162321Sglebius device_printf(sc->ti_dev, "firmware revision mismatch; " 859150719Sjhb "want %d.%d.%d, got %d.%d.%d\n", 86045386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 86145386Swpaul TI_FIRMWARE_FIX, tigonFwReleaseMajor, 86245386Swpaul tigonFwReleaseMinor, tigonFwReleaseFix); 86345386Swpaul return; 86445386Swpaul } 865153770Syongari ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 866153770Syongari ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 867153770Syongari ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 868153770Syongari tigonFwRodata); 869153770Syongari ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 870153770Syongari ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 87145386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 87245386Swpaul break; 87345386Swpaul case TI_HWREV_TIGON_II: 87445386Swpaul if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 87545386Swpaul tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 87645386Swpaul tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 877162321Sglebius device_printf(sc->ti_dev, "firmware revision mismatch; " 878150719Sjhb "want %d.%d.%d, got %d.%d.%d\n", 87945386Swpaul TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 88045386Swpaul TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 88145386Swpaul tigon2FwReleaseMinor, tigon2FwReleaseFix); 88245386Swpaul return; 88345386Swpaul } 884153770Syongari ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 885153770Syongari tigon2FwText); 886153770Syongari ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 887153770Syongari tigon2FwData); 888153770Syongari ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 889153770Syongari tigon2FwRodata); 890153770Syongari ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 891153770Syongari ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 89245386Swpaul CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 89345386Swpaul break; 89445386Swpaul default: 895162321Sglebius device_printf(sc->ti_dev, 896150719Sjhb "can't load firmware: unknown hardware rev\n"); 89745386Swpaul break; 89845386Swpaul } 89945386Swpaul} 90045386Swpaul 90145386Swpaul/* 90245386Swpaul * Send the NIC a command via the command ring. 90345386Swpaul */ 904102336Salfredstatic void 905102336Salfredti_cmd(sc, cmd) 90645386Swpaul struct ti_softc *sc; 90745386Swpaul struct ti_cmd_desc *cmd; 90845386Swpaul{ 909153982Syongari int index; 91045386Swpaul 91145386Swpaul index = sc->ti_cmd_saved_prodidx; 91245386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 91345386Swpaul TI_INC(index, TI_CMD_RING_CNT); 91445386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 91545386Swpaul sc->ti_cmd_saved_prodidx = index; 91645386Swpaul} 91745386Swpaul 91845386Swpaul/* 91945386Swpaul * Send the NIC an extended command. The 'len' parameter specifies the 92045386Swpaul * number of command slots to include after the initial command. 92145386Swpaul */ 922102336Salfredstatic void 923102336Salfredti_cmd_ext(sc, cmd, arg, len) 92445386Swpaul struct ti_softc *sc; 92545386Swpaul struct ti_cmd_desc *cmd; 92645386Swpaul caddr_t arg; 92745386Swpaul int len; 92845386Swpaul{ 929153982Syongari int index; 930153770Syongari int i; 93145386Swpaul 93245386Swpaul index = sc->ti_cmd_saved_prodidx; 93345386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 93445386Swpaul TI_INC(index, TI_CMD_RING_CNT); 93545386Swpaul for (i = 0; i < len; i++) { 93645386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 93745386Swpaul *(u_int32_t *)(&arg[i * 4])); 93845386Swpaul TI_INC(index, TI_CMD_RING_CNT); 93945386Swpaul } 94045386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 94145386Swpaul sc->ti_cmd_saved_prodidx = index; 94245386Swpaul} 94345386Swpaul 94445386Swpaul/* 94545386Swpaul * Handle events that have triggered interrupts. 94645386Swpaul */ 947102336Salfredstatic void 948102336Salfredti_handle_events(sc) 94945386Swpaul struct ti_softc *sc; 95045386Swpaul{ 95145386Swpaul struct ti_event_desc *e; 95245386Swpaul 95345386Swpaul if (sc->ti_rdata->ti_event_ring == NULL) 95445386Swpaul return; 95545386Swpaul 95645386Swpaul while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 95745386Swpaul e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 958153770Syongari switch (TI_EVENT_EVENT(e)) { 95945386Swpaul case TI_EV_LINKSTAT_CHANGED: 960153770Syongari sc->ti_linkstat = TI_EVENT_CODE(e); 961153770Syongari if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 962162321Sglebius device_printf(sc->ti_dev, "10/100 link up\n"); 963153770Syongari else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 964162321Sglebius device_printf(sc->ti_dev, "gigabit link up\n"); 965153770Syongari else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 966162321Sglebius device_printf(sc->ti_dev, "link down\n"); 96745386Swpaul break; 96845386Swpaul case TI_EV_ERROR: 969153770Syongari if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 970162321Sglebius device_printf(sc->ti_dev, "invalid command\n"); 971153770Syongari else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 972162321Sglebius device_printf(sc->ti_dev, "unknown command\n"); 973153770Syongari else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 974162321Sglebius device_printf(sc->ti_dev, "bad config data\n"); 97545386Swpaul break; 97645386Swpaul case TI_EV_FIRMWARE_UP: 97745386Swpaul ti_init2(sc); 97845386Swpaul break; 97945386Swpaul case TI_EV_STATS_UPDATED: 98045386Swpaul ti_stats_update(sc); 98145386Swpaul break; 98245386Swpaul case TI_EV_RESET_JUMBO_RING: 98345386Swpaul case TI_EV_MCAST_UPDATED: 98445386Swpaul /* Who cares. */ 98545386Swpaul break; 98645386Swpaul default: 987162321Sglebius device_printf(sc->ti_dev, "unknown event: %d\n", 988153770Syongari TI_EVENT_EVENT(e)); 98945386Swpaul break; 99045386Swpaul } 99145386Swpaul /* Advance the consumer index. */ 99245386Swpaul TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 99345386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 99445386Swpaul } 99545386Swpaul} 99645386Swpaul 997153396Sscottlstatic int 998153396Sscottlti_alloc_dmamaps(struct ti_softc *sc) 999153396Sscottl{ 1000153396Sscottl int i; 1001153396Sscottl 1002153396Sscottl for (i = 0; i < TI_TX_RING_CNT; i++) { 1003153982Syongari sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 1004153982Syongari sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1005153396Sscottl if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006153982Syongari &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) 1007153396Sscottl return (ENOBUFS); 1008153396Sscottl } 1009153396Sscottl for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010153396Sscottl if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011153396Sscottl &sc->ti_cdata.ti_rx_std_maps[i])) 1012153396Sscottl return (ENOBUFS); 1013153396Sscottl } 1014153396Sscottl 1015153396Sscottl for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016153396Sscottl if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017153396Sscottl &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018153396Sscottl return (ENOBUFS); 1019153396Sscottl } 1020153396Sscottl for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021153396Sscottl if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022153396Sscottl &sc->ti_cdata.ti_rx_mini_maps[i])) 1023153396Sscottl return (ENOBUFS); 1024153396Sscottl } 1025153396Sscottl 1026153396Sscottl return (0); 1027153396Sscottl} 1028153396Sscottl 1029153396Sscottlstatic void 1030153396Sscottlti_free_dmamaps(struct ti_softc *sc) 1031153396Sscottl{ 1032153396Sscottl int i; 1033153396Sscottl 1034153770Syongari if (sc->ti_mbuftx_dmat) 1035153770Syongari for (i = 0; i < TI_TX_RING_CNT; i++) 1036153982Syongari if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1037153770Syongari bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038153982Syongari sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1039153982Syongari sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1040153770Syongari } 1041153396Sscottl 1042153770Syongari if (sc->ti_mbufrx_dmat) 1043153770Syongari for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044153770Syongari if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045153770Syongari bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046153770Syongari sc->ti_cdata.ti_rx_std_maps[i]); 1047153770Syongari sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048153770Syongari } 1049153396Sscottl 1050153770Syongari if (sc->ti_jumbo_dmat) 1051153770Syongari for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052153770Syongari if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053153770Syongari bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054153770Syongari sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055153770Syongari sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056153770Syongari } 1057153770Syongari if (sc->ti_mbufrx_dmat) 1058153770Syongari for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059153770Syongari if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060153770Syongari bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061153770Syongari sc->ti_cdata.ti_rx_mini_maps[i]); 1062153770Syongari sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063153770Syongari } 1064153396Sscottl} 1065153396Sscottl 106698849Sken#ifdef TI_PRIVATE_JUMBOS 106798849Sken 106845386Swpaul/* 106945386Swpaul * Memory management for the jumbo receive ring is a pain in the 107045386Swpaul * butt. We need to allocate at least 9018 bytes of space per frame, 107145386Swpaul * _and_ it has to be contiguous (unless you use the extended 107245386Swpaul * jumbo descriptor format). Using malloc() all the time won't 107345386Swpaul * work: malloc() allocates memory in powers of two, which means we 107445386Swpaul * would end up wasting a considerable amount of space by allocating 107545386Swpaul * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 107645386Swpaul * to do our own memory management. 107745386Swpaul * 107845386Swpaul * The driver needs to allocate a contiguous chunk of memory at boot 107945386Swpaul * time. We then chop this up ourselves into 9K pieces and use them 108045386Swpaul * as external mbuf storage. 108145386Swpaul * 108245386Swpaul * One issue here is how much memory to allocate. The jumbo ring has 108345386Swpaul * 256 slots in it, but at 9K per slot than can consume over 2MB of 108445386Swpaul * RAM. This is a bit much, especially considering we also need 108545386Swpaul * RAM for the standard ring and mini ring (on the Tigon 2). To 108645386Swpaul * save space, we only actually allocate enough memory for 64 slots 108745386Swpaul * by default, which works out to between 500 and 600K. This can 108845386Swpaul * be tuned by changing a #define in if_tireg.h. 108945386Swpaul */ 109045386Swpaul 1091102336Salfredstatic int 1092102336Salfredti_alloc_jumbo_mem(sc) 109345386Swpaul struct ti_softc *sc; 109445386Swpaul{ 109545386Swpaul caddr_t ptr; 1096153770Syongari int i; 109745386Swpaul struct ti_jpool_entry *entry; 109845386Swpaul 1099153396Sscottl /* 1100153396Sscottl * Grab a big chunk o' storage. Since we are chopping this pool up 1101153396Sscottl * into ~9k chunks, there doesn't appear to be a need to use page 1102153396Sscottl * alignment. 1103153396Sscottl */ 1104153288Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105153396Sscottl 1, 0, /* algnmnt, boundary */ 1106153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 1107153288Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 1108153288Sscottl NULL, NULL, /* filter, filterarg */ 1109153288Sscottl TI_JMEM, /* maxsize */ 1110153288Sscottl 1, /* nsegments */ 1111153288Sscottl TI_JMEM, /* maxsegsize */ 1112153288Sscottl 0, /* flags */ 1113153288Sscottl NULL, NULL, /* lockfunc, lockarg */ 1114153288Sscottl &sc->ti_jumbo_dmat) != 0) { 1115153396Sscottl device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116153288Sscottl return (ENOBUFS); 1117153288Sscottl } 111845386Swpaul 1119153288Sscottl if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120153288Sscottl (void**)&sc->ti_cdata.ti_jumbo_buf, 1121153288Sscottl BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) { 1122153396Sscottl device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1123131654Sbms return (ENOBUFS); 112445386Swpaul } 112545386Swpaul 112645386Swpaul SLIST_INIT(&sc->ti_jfree_listhead); 112745386Swpaul SLIST_INIT(&sc->ti_jinuse_listhead); 112845386Swpaul 112945386Swpaul /* 113045386Swpaul * Now divide it up into 9K pieces and save the addresses 113167405Sbmilekic * in an array. 113245386Swpaul */ 113345386Swpaul ptr = sc->ti_cdata.ti_jumbo_buf; 113445386Swpaul for (i = 0; i < TI_JSLOTS; i++) { 113567405Sbmilekic sc->ti_cdata.ti_jslots[i] = ptr; 113667405Sbmilekic ptr += TI_JLEN; 1137131652Sbms entry = malloc(sizeof(struct ti_jpool_entry), 113845386Swpaul M_DEVBUF, M_NOWAIT); 113945386Swpaul if (entry == NULL) { 1140153396Sscottl device_printf(sc->ti_dev, "no memory for jumbo " 1141150719Sjhb "buffer queue!\n"); 1142131654Sbms return (ENOBUFS); 114345386Swpaul } 114445386Swpaul entry->slot = i; 114545386Swpaul SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 114645386Swpaul } 114745386Swpaul 1148131654Sbms return (0); 114945386Swpaul} 115045386Swpaul 115145386Swpaul/* 115245386Swpaul * Allocate a jumbo buffer. 115345386Swpaul */ 115445386Swpaulstatic void *ti_jalloc(sc) 115545386Swpaul struct ti_softc *sc; 115645386Swpaul{ 1157131655Sbms struct ti_jpool_entry *entry; 1158131652Sbms 115945386Swpaul entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1160131652Sbms 116145386Swpaul if (entry == NULL) { 1162162321Sglebius device_printf(sc->ti_dev, "no free jumbo buffers\n"); 1163131654Sbms return (NULL); 116445386Swpaul } 116545386Swpaul 116645386Swpaul SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 116745386Swpaul SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1168131654Sbms return (sc->ti_cdata.ti_jslots[entry->slot]); 116945386Swpaul} 117045386Swpaul 117145386Swpaul/* 117245386Swpaul * Release a jumbo buffer. 117345386Swpaul */ 1174102336Salfredstatic void 1175102336Salfredti_jfree(buf, args) 117699058Salfred void *buf; 117764837Sdwmalone void *args; 117845386Swpaul{ 117945386Swpaul struct ti_softc *sc; 1180131655Sbms int i; 1181131655Sbms struct ti_jpool_entry *entry; 118245386Swpaul 118345386Swpaul /* Extract the softc struct pointer. */ 118467405Sbmilekic sc = (struct ti_softc *)args; 118545386Swpaul 118645386Swpaul if (sc == NULL) 118767405Sbmilekic panic("ti_jfree: didn't get softc pointer!"); 118845386Swpaul 118945386Swpaul /* calculate the slot this buffer belongs to */ 119067405Sbmilekic i = ((vm_offset_t)buf 119145386Swpaul - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 119245386Swpaul 119345386Swpaul if ((i < 0) || (i >= TI_JSLOTS)) 119445386Swpaul panic("ti_jfree: asked to free buffer that we don't manage!"); 119545386Swpaul 119664837Sdwmalone entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 119764837Sdwmalone if (entry == NULL) 119864837Sdwmalone panic("ti_jfree: buffer not in use!"); 119964837Sdwmalone entry->slot = i; 120064837Sdwmalone SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 120164837Sdwmalone SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 120245386Swpaul} 120345386Swpaul 1204153396Sscottl#else 1205153396Sscottl 1206153396Sscottlstatic int 1207153396Sscottlti_alloc_jumbo_mem(sc) 1208153396Sscottl struct ti_softc *sc; 1209153396Sscottl{ 1210153396Sscottl 1211153396Sscottl /* 1212153396Sscottl * The VM system will take care of providing aligned pages. Alignment 1213153396Sscottl * is set to 1 here so that busdma resources won't be wasted. 1214153396Sscottl */ 1215153396Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1216153396Sscottl 1, 0, /* algnmnt, boundary */ 1217153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 1218153396Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 1219153396Sscottl NULL, NULL, /* filter, filterarg */ 1220153396Sscottl PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1221153396Sscottl 4, /* nsegments */ 1222153396Sscottl PAGE_SIZE, /* maxsegsize */ 1223153396Sscottl 0, /* flags */ 1224153396Sscottl NULL, NULL, /* lockfunc, lockarg */ 1225153396Sscottl &sc->ti_jumbo_dmat) != 0) { 1226153396Sscottl device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1227153396Sscottl return (ENOBUFS); 1228153396Sscottl } 1229153396Sscottl 1230153396Sscottl return (0); 1231153396Sscottl} 1232153396Sscottl 123398849Sken#endif /* TI_PRIVATE_JUMBOS */ 123445386Swpaul 123545386Swpaul/* 123645386Swpaul * Intialize a standard receive ring descriptor. 123745386Swpaul */ 1238102336Salfredstatic int 1239102336Salfredti_newbuf_std(sc, i, m) 124045386Swpaul struct ti_softc *sc; 124145386Swpaul int i; 124245386Swpaul struct mbuf *m; 124345386Swpaul{ 1244153396Sscottl bus_dmamap_t map; 1245153396Sscottl bus_dma_segment_t segs; 124645386Swpaul struct mbuf *m_new = NULL; 124745386Swpaul struct ti_rx_desc *r; 1248153396Sscottl int nsegs; 124945386Swpaul 1250153396Sscottl nsegs = 0; 125149036Swpaul if (m == NULL) { 1252111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 125387846Sluigi if (m_new == NULL) 1254131654Sbms return (ENOBUFS); 125545386Swpaul 1256111119Simp MCLGET(m_new, M_DONTWAIT); 125745386Swpaul if (!(m_new->m_flags & M_EXT)) { 125845386Swpaul m_freem(m_new); 1259131654Sbms return (ENOBUFS); 126045386Swpaul } 126149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 126249036Swpaul } else { 126349036Swpaul m_new = m; 126449036Swpaul m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 126549036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 126645386Swpaul } 126745386Swpaul 126848597Swpaul m_adj(m_new, ETHER_ALIGN); 126945386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = m_new; 127045386Swpaul r = &sc->ti_rdata->ti_rx_std_ring[i]; 1271153396Sscottl map = sc->ti_cdata.ti_rx_std_maps[i]; 1272153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1273153396Sscottl &nsegs, 0)) 1274153396Sscottl return (ENOBUFS); 1275153396Sscottl if (nsegs != 1) 1276153396Sscottl return (ENOBUFS); 1277153396Sscottl ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1278153396Sscottl r->ti_len = segs.ds_len; 127945386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 128045386Swpaul r->ti_flags = 0; 1281147256Sbrooks if (sc->ti_ifp->if_hwassist) 128258698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 128345386Swpaul r->ti_idx = i; 128445386Swpaul 1285153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1286131654Sbms return (0); 128745386Swpaul} 128845386Swpaul 128945386Swpaul/* 129045386Swpaul * Intialize a mini receive ring descriptor. This only applies to 129145386Swpaul * the Tigon 2. 129245386Swpaul */ 1293102336Salfredstatic int 1294102336Salfredti_newbuf_mini(sc, i, m) 129545386Swpaul struct ti_softc *sc; 129645386Swpaul int i; 129745386Swpaul struct mbuf *m; 129845386Swpaul{ 1299153396Sscottl bus_dma_segment_t segs; 1300153396Sscottl bus_dmamap_t map; 130145386Swpaul struct mbuf *m_new = NULL; 130245386Swpaul struct ti_rx_desc *r; 1303153396Sscottl int nsegs; 130445386Swpaul 1305153396Sscottl nsegs = 0; 130649036Swpaul if (m == NULL) { 1307111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 130845386Swpaul if (m_new == NULL) { 1309131654Sbms return (ENOBUFS); 131045386Swpaul } 131149036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 131249036Swpaul } else { 131349036Swpaul m_new = m; 131449036Swpaul m_new->m_data = m_new->m_pktdat; 131549036Swpaul m_new->m_len = m_new->m_pkthdr.len = MHLEN; 131645386Swpaul } 131749036Swpaul 131848597Swpaul m_adj(m_new, ETHER_ALIGN); 131945386Swpaul r = &sc->ti_rdata->ti_rx_mini_ring[i]; 132045386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1321153396Sscottl map = sc->ti_cdata.ti_rx_mini_maps[i]; 1322153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1323153396Sscottl &nsegs, 0)) 1324153396Sscottl return (ENOBUFS); 1325153396Sscottl if (nsegs != 1) 1326153396Sscottl return (ENOBUFS); 1327153396Sscottl ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1328153396Sscottl r->ti_len = segs.ds_len; 132945386Swpaul r->ti_type = TI_BDTYPE_RECV_BD; 133045386Swpaul r->ti_flags = TI_BDFLAG_MINI_RING; 1331147256Sbrooks if (sc->ti_ifp->if_hwassist) 133258698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 133345386Swpaul r->ti_idx = i; 133445386Swpaul 1335153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1336131654Sbms return (0); 133745386Swpaul} 133845386Swpaul 133998849Sken#ifdef TI_PRIVATE_JUMBOS 134098849Sken 134145386Swpaul/* 134245386Swpaul * Initialize a jumbo receive ring descriptor. This allocates 134345386Swpaul * a jumbo buffer from the pool managed internally by the driver. 134445386Swpaul */ 1345102336Salfredstatic int 1346102336Salfredti_newbuf_jumbo(sc, i, m) 134745386Swpaul struct ti_softc *sc; 134845386Swpaul int i; 134945386Swpaul struct mbuf *m; 135045386Swpaul{ 1351153396Sscottl bus_dmamap_t map; 135245386Swpaul struct mbuf *m_new = NULL; 135345386Swpaul struct ti_rx_desc *r; 1354153396Sscottl int nsegs; 1355153396Sscottl bus_dma_segment_t segs; 135645386Swpaul 135749036Swpaul if (m == NULL) { 135845386Swpaul caddr_t *buf = NULL; 135945386Swpaul 136045386Swpaul /* Allocate the mbuf. */ 1361111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 136245386Swpaul if (m_new == NULL) { 1363131654Sbms return (ENOBUFS); 136445386Swpaul } 136545386Swpaul 136645386Swpaul /* Allocate the jumbo buffer */ 136745386Swpaul buf = ti_jalloc(sc); 136845386Swpaul if (buf == NULL) { 136945386Swpaul m_freem(m_new); 1370162321Sglebius device_printf(sc->ti_dev, "jumbo allocation failed " 1371150719Sjhb "-- packet dropped!\n"); 1372131654Sbms return (ENOBUFS); 137345386Swpaul } 137445386Swpaul 137545386Swpaul /* Attach the buffer to the mbuf. */ 137664837Sdwmalone m_new->m_data = (void *) buf; 137764837Sdwmalone m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 137867405Sbmilekic MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 137968621Sbmilekic (struct ti_softc *)sc, 0, EXT_NET_DRV); 138049036Swpaul } else { 138149036Swpaul m_new = m; 138249036Swpaul m_new->m_data = m_new->m_ext.ext_buf; 138349036Swpaul m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 138445386Swpaul } 138545386Swpaul 138649780Swpaul m_adj(m_new, ETHER_ALIGN); 138745386Swpaul /* Set up the descriptor. */ 138845386Swpaul r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 138945386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1390153396Sscottl map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1391153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1392153396Sscottl &nsegs, 0)) 1393153396Sscottl return (ENOBUFS); 1394153396Sscottl if (nsegs != 1) 1395153396Sscottl return (ENOBUFS); 1396153396Sscottl ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1397153396Sscottl r->ti_len = segs.ds_len; 139845386Swpaul r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 139945386Swpaul r->ti_flags = TI_BDFLAG_JUMBO_RING; 1400147256Sbrooks if (sc->ti_ifp->if_hwassist) 140158698Sjlemon r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 140245386Swpaul r->ti_idx = i; 140345386Swpaul 1404153396Sscottl bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1405131654Sbms return (0); 140645386Swpaul} 140745386Swpaul 140898849Sken#else 140998849Sken 141098849Sken#if (PAGE_SIZE == 4096) 141198849Sken#define NPAYLOAD 2 141298849Sken#else 141398849Sken#define NPAYLOAD 1 1414131652Sbms#endif 141598849Sken 141698849Sken#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 141798849Sken#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 141898849Sken#define NFS_HDR_LEN (UDP_HDR_LEN) 1419104401Salfredstatic int HDR_LEN = TCP_HDR_LEN; 142098849Sken 142198849Sken 1422131655Sbms/* 1423131655Sbms * Initialize a jumbo receive ring descriptor. This allocates 1424131655Sbms * a jumbo buffer from the pool managed internally by the driver. 1425131655Sbms */ 142698849Skenstatic int 142798849Skenti_newbuf_jumbo(sc, idx, m_old) 1428131655Sbms struct ti_softc *sc; 1429131655Sbms int idx; 1430131655Sbms struct mbuf *m_old; 143198849Sken{ 1432153396Sscottl bus_dmamap_t map; 143398849Sken struct mbuf *cur, *m_new = NULL; 143498849Sken struct mbuf *m[3] = {NULL, NULL, NULL}; 143598849Sken struct ti_rx_desc_ext *r; 143698849Sken vm_page_t frame; 1437138424Salc static int color; 143898849Sken /* 1 extra buf to make nobufs easy*/ 1439138424Salc struct sf_buf *sf[3] = {NULL, NULL, NULL}; 144098849Sken int i; 1441153396Sscottl bus_dma_segment_t segs[4]; 1442153396Sscottl int nsegs; 144398849Sken 144498849Sken if (m_old != NULL) { 144598849Sken m_new = m_old; 144698849Sken cur = m_old->m_next; 144798849Sken for (i = 0; i <= NPAYLOAD; i++){ 144898849Sken m[i] = cur; 144998849Sken cur = cur->m_next; 145098849Sken } 145198849Sken } else { 145298849Sken /* Allocate the mbufs. */ 1453111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145498849Sken if (m_new == NULL) { 1455162321Sglebius device_printf(sc->ti_dev, "mbuf allocation failed " 1456150719Sjhb "-- packet dropped!\n"); 145798849Sken goto nobufs; 145898849Sken } 1459111119Simp MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 146098849Sken if (m[NPAYLOAD] == NULL) { 1461162321Sglebius device_printf(sc->ti_dev, "cluster mbuf allocation " 1462162321Sglebius "failed -- packet dropped!\n"); 146398849Sken goto nobufs; 146498849Sken } 1465111119Simp MCLGET(m[NPAYLOAD], M_DONTWAIT); 146698849Sken if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1467162321Sglebius device_printf(sc->ti_dev, "mbuf allocation failed " 1468150719Sjhb "-- packet dropped!\n"); 146998849Sken goto nobufs; 147098849Sken } 147198849Sken m[NPAYLOAD]->m_len = MCLBYTES; 147298849Sken 147398849Sken for (i = 0; i < NPAYLOAD; i++){ 1474111119Simp MGET(m[i], M_DONTWAIT, MT_DATA); 147598849Sken if (m[i] == NULL) { 1476162321Sglebius device_printf(sc->ti_dev, "mbuf allocation " 1477162321Sglebius "failed -- packet dropped!\n"); 147898849Sken goto nobufs; 147998849Sken } 1480138424Salc frame = vm_page_alloc(NULL, color++, 1481138424Salc VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1482138424Salc VM_ALLOC_WIRED); 1483138424Salc if (frame == NULL) { 1484162321Sglebius device_printf(sc->ti_dev, "buffer allocation " 1485150719Sjhb "failed -- packet dropped!\n"); 148698849Sken printf(" index %d page %d\n", idx, i); 1487131655Sbms goto nobufs; 148898849Sken } 1489138424Salc sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1490138424Salc if (sf[i] == NULL) { 1491138424Salc vm_page_lock_queues(); 1492138424Salc vm_page_unwire(frame, 0); 1493138424Salc vm_page_free(frame); 1494138424Salc vm_page_unlock_queues(); 1495162321Sglebius device_printf(sc->ti_dev, "buffer allocation " 1496150719Sjhb "failed -- packet dropped!\n"); 1497138424Salc printf(" index %d page %d\n", idx, i); 1498138424Salc goto nobufs; 1499138424Salc } 150098849Sken } 150198849Sken for (i = 0; i < NPAYLOAD; i++){ 1502131655Sbms /* Attach the buffer to the mbuf. */ 1503138424Salc m[i]->m_data = (void *)sf_buf_kva(sf[i]); 150498849Sken m[i]->m_len = PAGE_SIZE; 1505138424Salc MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1506138424Salc sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 150798849Sken m[i]->m_next = m[i+1]; 150898849Sken } 150998849Sken /* link the buffers to the header */ 151098849Sken m_new->m_next = m[0]; 151198849Sken m_new->m_data += ETHER_ALIGN; 151298849Sken if (sc->ti_hdrsplit) 151398849Sken m_new->m_len = MHLEN - ETHER_ALIGN; 151498849Sken else 1515131655Sbms m_new->m_len = HDR_LEN; 151698849Sken m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 151798849Sken } 151898849Sken 151998849Sken /* Set up the descriptor. */ 152098849Sken r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 152198849Sken sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1522153396Sscottl map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1523153396Sscottl if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1524153396Sscottl &nsegs, 0)) 1525153396Sscottl return (ENOBUFS); 1526153396Sscottl if ((nsegs < 1) || (nsegs > 4)) 1527153396Sscottl return (ENOBUFS); 1528153396Sscottl ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 152998849Sken r->ti_len0 = m_new->m_len; 153098849Sken 1531153396Sscottl ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 153298849Sken r->ti_len1 = PAGE_SIZE; 153398849Sken 1534153396Sscottl ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 153598849Sken r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 153698849Sken 153798849Sken if (PAGE_SIZE == 4096) { 1538153396Sscottl ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 153998849Sken r->ti_len3 = MCLBYTES; 154098849Sken } else { 154198849Sken r->ti_len3 = 0; 154298849Sken } 1543131655Sbms r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 154498849Sken 1545131655Sbms r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 154698849Sken 1547147256Sbrooks if (sc->ti_ifp->if_hwassist) 154898849Sken r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 154998849Sken 1550131655Sbms r->ti_idx = idx; 155198849Sken 1552153396Sscottl bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1553131655Sbms return (0); 155498849Sken 1555131655Sbmsnobufs: 155698849Sken 155798849Sken /* 155898849Sken * Warning! : 155998849Sken * This can only be called before the mbufs are strung together. 1560131652Sbms * If the mbufs are strung together, m_freem() will free the chain, 156198849Sken * so that the later mbufs will be freed multiple times. 156298849Sken */ 1563131655Sbms if (m_new) 1564131655Sbms m_freem(m_new); 156598849Sken 1566131655Sbms for (i = 0; i < 3; i++) { 1567131655Sbms if (m[i]) 1568131655Sbms m_freem(m[i]); 1569138424Salc if (sf[i]) 1570138424Salc sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1571131655Sbms } 1572131655Sbms return (ENOBUFS); 157398849Sken} 157498849Sken#endif 157598849Sken 157698849Sken 157798849Sken 157845386Swpaul/* 157945386Swpaul * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 158045386Swpaul * that's 1MB or memory, which is a lot. For now, we fill only the first 158145386Swpaul * 256 ring entries and hope that our CPU is fast enough to keep up with 158245386Swpaul * the NIC. 158345386Swpaul */ 1584102336Salfredstatic int 1585102336Salfredti_init_rx_ring_std(sc) 158645386Swpaul struct ti_softc *sc; 158745386Swpaul{ 1588153770Syongari int i; 158945386Swpaul struct ti_cmd_desc cmd; 159045386Swpaul 159145386Swpaul for (i = 0; i < TI_SSLOTS; i++) { 159245386Swpaul if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1593131654Sbms return (ENOBUFS); 159445386Swpaul }; 159545386Swpaul 159645386Swpaul TI_UPDATE_STDPROD(sc, i - 1); 159748597Swpaul sc->ti_std = i - 1; 159845386Swpaul 1599131654Sbms return (0); 160045386Swpaul} 160145386Swpaul 1602102336Salfredstatic void 1603102336Salfredti_free_rx_ring_std(sc) 160445386Swpaul struct ti_softc *sc; 160545386Swpaul{ 1606153770Syongari bus_dmamap_t map; 1607153770Syongari int i; 160845386Swpaul 160945386Swpaul for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 161045386Swpaul if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1611153770Syongari map = sc->ti_cdata.ti_rx_std_maps[i]; 1612153770Syongari bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1613153770Syongari BUS_DMASYNC_POSTREAD); 1614153770Syongari bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 161545386Swpaul m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 161645386Swpaul sc->ti_cdata.ti_rx_std_chain[i] = NULL; 161745386Swpaul } 161845386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 161945386Swpaul sizeof(struct ti_rx_desc)); 162045386Swpaul } 162145386Swpaul} 162245386Swpaul 1623102336Salfredstatic int 1624102336Salfredti_init_rx_ring_jumbo(sc) 162545386Swpaul struct ti_softc *sc; 162645386Swpaul{ 1627153770Syongari int i; 162845386Swpaul struct ti_cmd_desc cmd; 162945386Swpaul 163063699Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 163145386Swpaul if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1632131654Sbms return (ENOBUFS); 163345386Swpaul }; 163445386Swpaul 163545386Swpaul TI_UPDATE_JUMBOPROD(sc, i - 1); 163648597Swpaul sc->ti_jumbo = i - 1; 163745386Swpaul 1638131654Sbms return (0); 163945386Swpaul} 164045386Swpaul 1641102336Salfredstatic void 1642102336Salfredti_free_rx_ring_jumbo(sc) 164345386Swpaul struct ti_softc *sc; 164445386Swpaul{ 1645153770Syongari bus_dmamap_t map; 1646153770Syongari int i; 164745386Swpaul 164845386Swpaul for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 164945386Swpaul if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1650153770Syongari map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1651153770Syongari bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1652153770Syongari BUS_DMASYNC_POSTREAD); 1653153770Syongari bus_dmamap_unload(sc->ti_jumbo_dmat, map); 165445386Swpaul m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 165545386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 165645386Swpaul } 165745386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 165845386Swpaul sizeof(struct ti_rx_desc)); 165945386Swpaul } 166045386Swpaul} 166145386Swpaul 1662102336Salfredstatic int 1663102336Salfredti_init_rx_ring_mini(sc) 166445386Swpaul struct ti_softc *sc; 166545386Swpaul{ 1666153770Syongari int i; 166745386Swpaul 166845386Swpaul for (i = 0; i < TI_MSLOTS; i++) { 166945386Swpaul if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1670131654Sbms return (ENOBUFS); 167145386Swpaul }; 167245386Swpaul 167345386Swpaul TI_UPDATE_MINIPROD(sc, i - 1); 167448597Swpaul sc->ti_mini = i - 1; 167545386Swpaul 1676131654Sbms return (0); 167745386Swpaul} 167845386Swpaul 1679102336Salfredstatic void 1680102336Salfredti_free_rx_ring_mini(sc) 168145386Swpaul struct ti_softc *sc; 168245386Swpaul{ 1683153770Syongari bus_dmamap_t map; 1684153770Syongari int i; 168545386Swpaul 168645386Swpaul for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 168745386Swpaul if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1688153770Syongari map = sc->ti_cdata.ti_rx_mini_maps[i]; 1689153770Syongari bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1690153770Syongari BUS_DMASYNC_POSTREAD); 1691153770Syongari bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 169245386Swpaul m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 169345386Swpaul sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 169445386Swpaul } 169545386Swpaul bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 169645386Swpaul sizeof(struct ti_rx_desc)); 169745386Swpaul } 169845386Swpaul} 169945386Swpaul 1700102336Salfredstatic void 1701102336Salfredti_free_tx_ring(sc) 170245386Swpaul struct ti_softc *sc; 170345386Swpaul{ 1704153982Syongari struct ti_txdesc *txd; 1705153770Syongari int i; 170645386Swpaul 170745386Swpaul if (sc->ti_rdata->ti_tx_ring == NULL) 170845386Swpaul return; 170945386Swpaul 171045386Swpaul for (i = 0; i < TI_TX_RING_CNT; i++) { 1711153982Syongari txd = &sc->ti_cdata.ti_txdesc[i]; 1712153982Syongari if (txd->tx_m != NULL) { 1713153982Syongari bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1714153770Syongari BUS_DMASYNC_POSTWRITE); 1715153982Syongari bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1716153982Syongari m_freem(txd->tx_m); 1717153982Syongari txd->tx_m = NULL; 171845386Swpaul } 171945386Swpaul bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 172045386Swpaul sizeof(struct ti_tx_desc)); 172145386Swpaul } 172245386Swpaul} 172345386Swpaul 1724102336Salfredstatic int 1725102336Salfredti_init_tx_ring(sc) 172645386Swpaul struct ti_softc *sc; 172745386Swpaul{ 1728153982Syongari struct ti_txdesc *txd; 1729153982Syongari int i; 1730153982Syongari 1731153982Syongari STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1732153982Syongari STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1733153982Syongari for (i = 0; i < TI_TX_RING_CNT; i++) { 1734153982Syongari txd = &sc->ti_cdata.ti_txdesc[i]; 1735153982Syongari STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1736153982Syongari } 173748011Swpaul sc->ti_txcnt = 0; 173845386Swpaul sc->ti_tx_saved_considx = 0; 1739153778Sscottl sc->ti_tx_saved_prodidx = 0; 174045386Swpaul CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1741131654Sbms return (0); 174245386Swpaul} 174345386Swpaul 174445386Swpaul/* 174545386Swpaul * The Tigon 2 firmware has a new way to add/delete multicast addresses, 174645386Swpaul * but we have to support the old way too so that Tigon 1 cards will 174745386Swpaul * work. 174845386Swpaul */ 1749105219Sphkstatic void 1750102336Salfredti_add_mcast(sc, addr) 175145386Swpaul struct ti_softc *sc; 175245386Swpaul struct ether_addr *addr; 175345386Swpaul{ 175445386Swpaul struct ti_cmd_desc cmd; 175545386Swpaul u_int16_t *m; 175645386Swpaul u_int32_t ext[2] = {0, 0}; 175745386Swpaul 175845386Swpaul m = (u_int16_t *)&addr->octet[0]; 175945386Swpaul 1760131654Sbms switch (sc->ti_hwrev) { 176145386Swpaul case TI_HWREV_TIGON: 176245386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 176345386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 176445386Swpaul TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 176545386Swpaul break; 176645386Swpaul case TI_HWREV_TIGON_II: 176745386Swpaul ext[0] = htons(m[0]); 176845386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 176945386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 177045386Swpaul break; 177145386Swpaul default: 1772162321Sglebius device_printf(sc->ti_dev, "unknown hwrev\n"); 177345386Swpaul break; 177445386Swpaul } 177545386Swpaul} 177645386Swpaul 1777105219Sphkstatic void 1778102336Salfredti_del_mcast(sc, addr) 177945386Swpaul struct ti_softc *sc; 178045386Swpaul struct ether_addr *addr; 178145386Swpaul{ 178245386Swpaul struct ti_cmd_desc cmd; 178345386Swpaul u_int16_t *m; 178445386Swpaul u_int32_t ext[2] = {0, 0}; 178545386Swpaul 178645386Swpaul m = (u_int16_t *)&addr->octet[0]; 178745386Swpaul 1788131654Sbms switch (sc->ti_hwrev) { 178945386Swpaul case TI_HWREV_TIGON: 179045386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 179145386Swpaul CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 179245386Swpaul TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 179345386Swpaul break; 179445386Swpaul case TI_HWREV_TIGON_II: 179545386Swpaul ext[0] = htons(m[0]); 179645386Swpaul ext[1] = (htons(m[1]) << 16) | htons(m[2]); 179745386Swpaul TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 179845386Swpaul break; 179945386Swpaul default: 1800162321Sglebius device_printf(sc->ti_dev, "unknown hwrev\n"); 180145386Swpaul break; 180245386Swpaul } 180345386Swpaul} 180445386Swpaul 180545386Swpaul/* 180645386Swpaul * Configure the Tigon's multicast address filter. 180745386Swpaul * 180845386Swpaul * The actual multicast table management is a bit of a pain, thanks to 180945386Swpaul * slight brain damage on the part of both Alteon and us. With our 181045386Swpaul * multicast code, we are only alerted when the multicast address table 181145386Swpaul * changes and at that point we only have the current list of addresses: 181245386Swpaul * we only know the current state, not the previous state, so we don't 181345386Swpaul * actually know what addresses were removed or added. The firmware has 181445386Swpaul * state, but we can't get our grubby mits on it, and there is no 'delete 181545386Swpaul * all multicast addresses' command. Hence, we have to maintain our own 181645386Swpaul * state so we know what addresses have been programmed into the NIC at 181745386Swpaul * any given time. 181845386Swpaul */ 1819102336Salfredstatic void 1820102336Salfredti_setmulti(sc) 182145386Swpaul struct ti_softc *sc; 182245386Swpaul{ 182345386Swpaul struct ifnet *ifp; 182445386Swpaul struct ifmultiaddr *ifma; 182545386Swpaul struct ti_cmd_desc cmd; 182645386Swpaul struct ti_mc_entry *mc; 182745386Swpaul u_int32_t intrs; 182845386Swpaul 1829153770Syongari TI_LOCK_ASSERT(sc); 1830153770Syongari 1831147256Sbrooks ifp = sc->ti_ifp; 183245386Swpaul 183345386Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 183445386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 183545386Swpaul return; 183645386Swpaul } else { 183745386Swpaul TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 183845386Swpaul } 183945386Swpaul 184045386Swpaul /* Disable interrupts. */ 184145386Swpaul intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 184245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 184345386Swpaul 184445386Swpaul /* First, zot all the existing filters. */ 184571999Sphk while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 184671999Sphk mc = SLIST_FIRST(&sc->ti_mc_listhead); 184745386Swpaul ti_del_mcast(sc, &mc->mc_addr); 184845386Swpaul SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 184945386Swpaul free(mc, M_DEVBUF); 185045386Swpaul } 185145386Swpaul 185245386Swpaul /* Now program new ones. */ 1853148654Srwatson IF_ADDR_LOCK(ifp); 185472084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 185545386Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 185645386Swpaul continue; 185745386Swpaul mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1858144165Ssam if (mc == NULL) { 1859162321Sglebius device_printf(sc->ti_dev, 1860162321Sglebius "no memory for mcast filter entry\n"); 1861144165Ssam continue; 1862144165Ssam } 186345386Swpaul bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 186445386Swpaul (char *)&mc->mc_addr, ETHER_ADDR_LEN); 186545386Swpaul SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 186645386Swpaul ti_add_mcast(sc, &mc->mc_addr); 186745386Swpaul } 1868148654Srwatson IF_ADDR_UNLOCK(ifp); 186945386Swpaul 187045386Swpaul /* Re-enable interrupts. */ 187145386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 187245386Swpaul} 187345386Swpaul 187445386Swpaul/* 187545386Swpaul * Check to see if the BIOS has configured us for a 64 bit slot when 187645386Swpaul * we aren't actually in one. If we detect this condition, we can work 187745386Swpaul * around it on the Tigon 2 by setting a bit in the PCI state register, 187845386Swpaul * but for the Tigon 1 we must give up and abort the interface attach. 187945386Swpaul */ 188045386Swpaulstatic int ti_64bitslot_war(sc) 188145386Swpaul struct ti_softc *sc; 188245386Swpaul{ 188345386Swpaul if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 188445386Swpaul CSR_WRITE_4(sc, 0x600, 0); 188545386Swpaul CSR_WRITE_4(sc, 0x604, 0); 188645386Swpaul CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 188745386Swpaul if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 188845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 1889131654Sbms return (EINVAL); 189045386Swpaul else { 189145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, 189245386Swpaul TI_PCISTATE_32BIT_BUS); 1893131654Sbms return (0); 189445386Swpaul } 189545386Swpaul } 189645386Swpaul } 189745386Swpaul 1898131654Sbms return (0); 189945386Swpaul} 190045386Swpaul 190145386Swpaul/* 190245386Swpaul * Do endian, PCI and DMA initialization. Also check the on-board ROM 190345386Swpaul * self-test results. 190445386Swpaul */ 1905102336Salfredstatic int 1906102336Salfredti_chipinit(sc) 190745386Swpaul struct ti_softc *sc; 190845386Swpaul{ 190945386Swpaul u_int32_t cacheline; 191045386Swpaul u_int32_t pci_writemax = 0; 191198849Sken u_int32_t hdrsplit; 191245386Swpaul 191345386Swpaul /* Initialize link to down state. */ 191445386Swpaul sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 191545386Swpaul 1916147256Sbrooks if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1917147256Sbrooks sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 191883630Sjlemon else 1919147256Sbrooks sc->ti_ifp->if_hwassist = 0; 192058698Sjlemon 192145386Swpaul /* Set endianness before we access any non-PCI registers. */ 1922153770Syongari#if 0 && BYTE_ORDER == BIG_ENDIAN 192345386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 192445386Swpaul TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 192545386Swpaul#else 192645386Swpaul CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 192745386Swpaul TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 192845386Swpaul#endif 192945386Swpaul 193045386Swpaul /* Check the ROM failed bit to see if self-tests passed. */ 193145386Swpaul if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1932162321Sglebius device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1933131654Sbms return (ENODEV); 193445386Swpaul } 193545386Swpaul 193645386Swpaul /* Halt the CPU. */ 193745386Swpaul TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 193845386Swpaul 193945386Swpaul /* Figure out the hardware revision. */ 1940131654Sbms switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 194145386Swpaul case TI_REV_TIGON_I: 194245386Swpaul sc->ti_hwrev = TI_HWREV_TIGON; 194345386Swpaul break; 194445386Swpaul case TI_REV_TIGON_II: 194545386Swpaul sc->ti_hwrev = TI_HWREV_TIGON_II; 194645386Swpaul break; 194745386Swpaul default: 1948162321Sglebius device_printf(sc->ti_dev, "unsupported chip revision\n"); 1949131654Sbms return (ENODEV); 195045386Swpaul } 195145386Swpaul 195245386Swpaul /* Do special setup for Tigon 2. */ 195345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 195445386Swpaul TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 195576033Swpaul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 195645386Swpaul TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 195745386Swpaul } 195845386Swpaul 195998849Sken /* 196098849Sken * We don't have firmware source for the Tigon 1, so Tigon 1 boards 196198849Sken * can't do header splitting. 196298849Sken */ 196398849Sken#ifdef TI_JUMBO_HDRSPLIT 196498849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 196598849Sken sc->ti_hdrsplit = 1; 196698849Sken else 1967162321Sglebius device_printf(sc->ti_dev, 1968150719Sjhb "can't do header splitting on a Tigon I board\n"); 196998849Sken#endif /* TI_JUMBO_HDRSPLIT */ 197098849Sken 197145386Swpaul /* Set up the PCI state register. */ 197245386Swpaul CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 197345386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 197445386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 197545386Swpaul } 197645386Swpaul 197745386Swpaul /* Clear the read/write max DMA parameters. */ 197845386Swpaul TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 197945386Swpaul TI_PCISTATE_READ_MAXDMA)); 198045386Swpaul 198145386Swpaul /* Get cache line size. */ 198245386Swpaul cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 198345386Swpaul 198445386Swpaul /* 198545386Swpaul * If the system has set enabled the PCI memory write 198645386Swpaul * and invalidate command in the command register, set 198745386Swpaul * the write max parameter accordingly. This is necessary 198845386Swpaul * to use MWI with the Tigon 2. 198945386Swpaul */ 199045386Swpaul if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1991131654Sbms switch (cacheline) { 199245386Swpaul case 1: 199345386Swpaul case 4: 199445386Swpaul case 8: 199545386Swpaul case 16: 199645386Swpaul case 32: 199745386Swpaul case 64: 199845386Swpaul break; 199945386Swpaul default: 200045386Swpaul /* Disable PCI memory write and invalidate. */ 200145386Swpaul if (bootverbose) 2002162321Sglebius device_printf(sc->ti_dev, "cache line size %d" 2003162321Sglebius " not supported; disabling PCI MWI\n", 2004150719Sjhb cacheline); 200545386Swpaul CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 200645386Swpaul TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 200745386Swpaul break; 200845386Swpaul } 200945386Swpaul } 201045386Swpaul 201145386Swpaul#ifdef __brokenalpha__ 201245386Swpaul /* 201345386Swpaul * From the Alteon sample driver: 201445386Swpaul * Must insure that we do not cross an 8K (bytes) boundary 2015131652Sbms * for DMA reads. Our highest limit is 1K bytes. This is a 2016131652Sbms * restriction on some ALPHA platforms with early revision 2017131652Sbms * 21174 PCI chipsets, such as the AlphaPC 164lx 201845386Swpaul */ 201945386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 202045386Swpaul#else 202145386Swpaul TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 202245386Swpaul#endif 202345386Swpaul 202445386Swpaul /* This sets the min dma param all the way up (0xff). */ 202545386Swpaul TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 202645386Swpaul 202798849Sken if (sc->ti_hdrsplit) 202898849Sken hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 202998849Sken else 203098849Sken hdrsplit = 0; 203198849Sken 203245386Swpaul /* Configure DMA variables. */ 203345386Swpaul#if BYTE_ORDER == BIG_ENDIAN 203445386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 203545386Swpaul TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 203645386Swpaul TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 203798849Sken TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 203898849Sken#else /* BYTE_ORDER */ 203945386Swpaul CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 204045386Swpaul TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 204198849Sken TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 204298849Sken#endif /* BYTE_ORDER */ 204345386Swpaul 204445386Swpaul /* 204545386Swpaul * Only allow 1 DMA channel to be active at a time. 204645386Swpaul * I don't think this is a good idea, but without it 204745386Swpaul * the firmware racks up lots of nicDmaReadRingFull 204858698Sjlemon * errors. This is not compatible with hardware checksums. 204945386Swpaul */ 2050147256Sbrooks if (sc->ti_ifp->if_hwassist == 0) 205158698Sjlemon TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 205245386Swpaul 205345386Swpaul /* Recommended settings from Tigon manual. */ 205445386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 205545386Swpaul CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 205645386Swpaul 205745386Swpaul if (ti_64bitslot_war(sc)) { 2058162321Sglebius device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2059150719Sjhb "but we aren't"); 2060131654Sbms return (EINVAL); 206145386Swpaul } 206245386Swpaul 2063131654Sbms return (0); 206445386Swpaul} 206545386Swpaul 206645386Swpaul/* 206745386Swpaul * Initialize the general information block and firmware, and 206845386Swpaul * start the CPU(s) running. 206945386Swpaul */ 2070102336Salfredstatic int 2071102336Salfredti_gibinit(sc) 207245386Swpaul struct ti_softc *sc; 207345386Swpaul{ 207445386Swpaul struct ti_rcb *rcb; 207545386Swpaul int i; 207645386Swpaul struct ifnet *ifp; 2077143903Sscottl uint32_t rdphys; 207845386Swpaul 2079153770Syongari TI_LOCK_ASSERT(sc); 2080153770Syongari 2081147256Sbrooks ifp = sc->ti_ifp; 2082143903Sscottl rdphys = sc->ti_rdata_phys; 208345386Swpaul 208445386Swpaul /* Disable interrupts for now. */ 208545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 208645386Swpaul 2087143903Sscottl /* 2088143903Sscottl * Tell the chip where to find the general information block. 2089143903Sscottl * While this struct could go into >4GB memory, we allocate it in a 2090143903Sscottl * single slab with the other descriptors, and those don't seem to 2091143903Sscottl * support being located in a 64-bit region. 2092143903Sscottl */ 209345386Swpaul CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2094143903Sscottl CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 209545386Swpaul 209645386Swpaul /* Load the firmware into SRAM. */ 209745386Swpaul ti_loadfw(sc); 209845386Swpaul 209945386Swpaul /* Set up the contents of the general info and ring control blocks. */ 210045386Swpaul 210145386Swpaul /* Set up the event ring and producer pointer. */ 210245386Swpaul rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 210345386Swpaul 2104143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 210545386Swpaul rcb->ti_flags = 0; 210645386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2107143903Sscottl rdphys + TI_RD_OFF(ti_ev_prodidx_r); 210845386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 210945386Swpaul CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 211045386Swpaul sc->ti_ev_saved_considx = 0; 211145386Swpaul 211245386Swpaul /* Set up the command ring and producer mailbox. */ 211345386Swpaul rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 211445386Swpaul 211545386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 211645386Swpaul rcb->ti_flags = 0; 211745386Swpaul rcb->ti_max_len = 0; 211845386Swpaul for (i = 0; i < TI_CMD_RING_CNT; i++) { 211945386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 212045386Swpaul } 212145386Swpaul CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 212245386Swpaul CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 212345386Swpaul sc->ti_cmd_saved_prodidx = 0; 212445386Swpaul 212545386Swpaul /* 212645386Swpaul * Assign the address of the stats refresh buffer. 212745386Swpaul * We re-use the current stats buffer for this to 212845386Swpaul * conserve memory. 212945386Swpaul */ 213045386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2131143903Sscottl rdphys + TI_RD_OFF(ti_info.ti_stats); 213245386Swpaul 213345386Swpaul /* Set up the standard receive ring. */ 213445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2135143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 213645386Swpaul rcb->ti_max_len = TI_FRAMELEN; 213745386Swpaul rcb->ti_flags = 0; 2138147256Sbrooks if (sc->ti_ifp->if_hwassist) 213958698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 214058698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 214145386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 214245386Swpaul 214345386Swpaul /* Set up the jumbo receive ring. */ 214445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2145143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 214698849Sken 214798849Sken#ifdef TI_PRIVATE_JUMBOS 214849036Swpaul rcb->ti_max_len = TI_JUMBO_FRAMELEN; 214945386Swpaul rcb->ti_flags = 0; 215098849Sken#else 215198849Sken rcb->ti_max_len = PAGE_SIZE; 215298849Sken rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 215398849Sken#endif 2154147256Sbrooks if (sc->ti_ifp->if_hwassist) 215558698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 215658698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 215745386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 215845386Swpaul 215945386Swpaul /* 216045386Swpaul * Set up the mini ring. Only activated on the 216145386Swpaul * Tigon 2 but the slot in the config block is 216245386Swpaul * still there on the Tigon 1. 216345386Swpaul */ 216445386Swpaul rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2165143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 216651352Swpaul rcb->ti_max_len = MHLEN - ETHER_ALIGN; 216745386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 216845386Swpaul rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 216945386Swpaul else 217045386Swpaul rcb->ti_flags = 0; 2171147256Sbrooks if (sc->ti_ifp->if_hwassist) 217258698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 217358698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 217445386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 217545386Swpaul 217645386Swpaul /* 217745386Swpaul * Set up the receive return ring. 217845386Swpaul */ 217945386Swpaul rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2180143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 218145386Swpaul rcb->ti_flags = 0; 218245386Swpaul rcb->ti_max_len = TI_RETURN_RING_CNT; 218345386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2184143903Sscottl rdphys + TI_RD_OFF(ti_return_prodidx_r); 218545386Swpaul 218645386Swpaul /* 218745386Swpaul * Set up the tx ring. Note: for the Tigon 2, we have the option 218845386Swpaul * of putting the transmit ring in the host's address space and 218945386Swpaul * letting the chip DMA it instead of leaving the ring in the NIC's 219045386Swpaul * memory and accessing it through the shared memory region. We 219145386Swpaul * do this for the Tigon 2, but it doesn't work on the Tigon 1, 219245386Swpaul * so we have to revert to the shared memory scheme if we detect 219345386Swpaul * a Tigon 1 chip. 219445386Swpaul */ 219545386Swpaul CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 219645386Swpaul bzero((char *)sc->ti_rdata->ti_tx_ring, 219745386Swpaul TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 219845386Swpaul rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 219945386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 220045386Swpaul rcb->ti_flags = 0; 220145386Swpaul else 220245386Swpaul rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 220345386Swpaul rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2204147256Sbrooks if (sc->ti_ifp->if_hwassist) 220558698Sjlemon rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 220658698Sjlemon TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 220745386Swpaul rcb->ti_max_len = TI_TX_RING_CNT; 220845386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 220945386Swpaul TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 221045386Swpaul else 2211143903Sscottl TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 221245386Swpaul TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2213143903Sscottl rdphys + TI_RD_OFF(ti_tx_considx_r); 221445386Swpaul 2215153770Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2216153770Syongari BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2217153770Syongari 221845386Swpaul /* Set up tuneables */ 221998849Sken#if 0 222045386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 222145386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 222245386Swpaul (sc->ti_rx_coal_ticks / 10)); 222345386Swpaul else 222498849Sken#endif 222545386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 222645386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 222745386Swpaul CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 222845386Swpaul CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 222945386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 223045386Swpaul CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 223145386Swpaul 223245386Swpaul /* Turn interrupts on. */ 223345386Swpaul CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 223445386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 223545386Swpaul 223645386Swpaul /* Start CPU. */ 223745386Swpaul TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 223845386Swpaul 2239131654Sbms return (0); 224045386Swpaul} 224145386Swpaul 2242143903Sscottlstatic void 2243143903Sscottlti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2244143903Sscottl{ 2245143903Sscottl struct ti_softc *sc; 2246143903Sscottl 2247143903Sscottl sc = arg; 2248143903Sscottl if (error || nseg != 1) 2249143903Sscottl return; 2250143903Sscottl 2251143903Sscottl /* 2252143903Sscottl * All of the Tigon data structures need to live at <4GB. This 2253143903Sscottl * cast is fine since busdma was told about this constraint. 2254143903Sscottl */ 2255153770Syongari sc->ti_rdata_phys = segs[0].ds_addr; 2256143903Sscottl return; 2257143903Sscottl} 2258143903Sscottl 225945386Swpaul/* 226045386Swpaul * Probe for a Tigon chip. Check the PCI vendor and device IDs 226145386Swpaul * against our list and return its name if we find a match. 226245386Swpaul */ 2263102336Salfredstatic int 2264102336Salfredti_probe(dev) 226549011Swpaul device_t dev; 226645386Swpaul{ 226745386Swpaul struct ti_type *t; 226845386Swpaul 226945386Swpaul t = ti_devs; 227045386Swpaul 2271131654Sbms while (t->ti_name != NULL) { 227249011Swpaul if ((pci_get_vendor(dev) == t->ti_vid) && 227349011Swpaul (pci_get_device(dev) == t->ti_did)) { 227449011Swpaul device_set_desc(dev, t->ti_name); 2275142398Simp return (BUS_PROBE_DEFAULT); 227649011Swpaul } 227745386Swpaul t++; 227845386Swpaul } 227945386Swpaul 2280131654Sbms return (ENXIO); 228145386Swpaul} 228245386Swpaul 228398849Skenstatic int 2284102336Salfredti_attach(dev) 228549011Swpaul device_t dev; 228645386Swpaul{ 228745386Swpaul struct ifnet *ifp; 228845386Swpaul struct ti_softc *sc; 2289150719Sjhb int error = 0, rid; 2290147256Sbrooks u_char eaddr[6]; 229145386Swpaul 229249011Swpaul sc = device_get_softc(dev); 2293150719Sjhb sc->ti_unit = device_get_unit(dev); 2294153396Sscottl sc->ti_dev = dev; 229545386Swpaul 229693818Sjhb mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2297153770Syongari MTX_DEF); 2298113609Snjl ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2299147805Sscottl ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2300147805Sscottl if (ifp == NULL) { 2301150719Sjhb device_printf(dev, "can not if_alloc()\n"); 2302147805Sscottl error = ENOSPC; 2303147805Sscottl goto fail; 2304147805Sscottl } 2305147256Sbrooks sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2306118454Ssimokawa IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2307147256Sbrooks sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 230869583Swpaul 230945386Swpaul /* 231045386Swpaul * Map control/status registers. 231145386Swpaul */ 231272813Swpaul pci_enable_busmaster(dev); 231345386Swpaul 231449011Swpaul rid = TI_PCI_LOMEM; 2315127135Snjl sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2316127135Snjl RF_ACTIVE|PCI_RF_DENSE); 231749011Swpaul 231849011Swpaul if (sc->ti_res == NULL) { 2319150719Sjhb device_printf(dev, "couldn't map memory\n"); 232049011Swpaul error = ENXIO; 232145386Swpaul goto fail; 232245386Swpaul } 232345386Swpaul 232449035Swpaul sc->ti_btag = rman_get_bustag(sc->ti_res); 232549035Swpaul sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 232649035Swpaul 232749011Swpaul /* Allocate interrupt */ 232849011Swpaul rid = 0; 2329131652Sbms 2330127135Snjl sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 233149011Swpaul RF_SHAREABLE | RF_ACTIVE); 233245386Swpaul 233349011Swpaul if (sc->ti_irq == NULL) { 2334150719Sjhb device_printf(dev, "couldn't map interrupt\n"); 233549011Swpaul error = ENXIO; 233645386Swpaul goto fail; 233745386Swpaul } 233845386Swpaul 233945386Swpaul if (ti_chipinit(sc)) { 2340150719Sjhb device_printf(dev, "chip initialization failed\n"); 234149011Swpaul error = ENXIO; 234245386Swpaul goto fail; 234345386Swpaul } 234445386Swpaul 234545386Swpaul /* Zero out the NIC's on-board SRAM. */ 2346153770Syongari ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 234745386Swpaul 234845386Swpaul /* Init again -- zeroing memory may have clobbered some registers. */ 234945386Swpaul if (ti_chipinit(sc)) { 2350150719Sjhb device_printf(dev, "chip initialization failed\n"); 235149011Swpaul error = ENXIO; 235245386Swpaul goto fail; 235345386Swpaul } 235445386Swpaul 235545386Swpaul /* 235645386Swpaul * Get station address from the EEPROM. Note: the manual states 235745386Swpaul * that the MAC address is at offset 0x8c, however the data is 235845386Swpaul * stored as two longwords (since that's how it's loaded into 235972645Sasmodai * the NIC). This means the MAC address is actually preceded 236045386Swpaul * by two zero bytes. We need to skip over those. 236145386Swpaul */ 2362147256Sbrooks if (ti_read_eeprom(sc, eaddr, 236345386Swpaul TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2364150719Sjhb device_printf(dev, "failed to read station address\n"); 236549011Swpaul error = ENXIO; 236645386Swpaul goto fail; 236745386Swpaul } 236845386Swpaul 236945386Swpaul /* Allocate the general information block and ring buffers. */ 2370166165Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2371143903Sscottl 1, 0, /* algnmnt, boundary */ 2372143903Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 2373143903Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2374143903Sscottl NULL, NULL, /* filter, filterarg */ 2375143903Sscottl BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2376143903Sscottl 0, /* nsegments */ 2377143903Sscottl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2378143903Sscottl 0, /* flags */ 2379143903Sscottl NULL, NULL, /* lockfunc, lockarg */ 2380143903Sscottl &sc->ti_parent_dmat) != 0) { 2381150719Sjhb device_printf(dev, "Failed to allocate parent dmat\n"); 2382143903Sscottl error = ENOMEM; 2383143903Sscottl goto fail; 2384143903Sscottl } 238545386Swpaul 2386143903Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2387143903Sscottl PAGE_SIZE, 0, /* algnmnt, boundary */ 2388143903Sscottl BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2389143903Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2390143903Sscottl NULL, NULL, /* filter, filterarg */ 2391143903Sscottl sizeof(struct ti_ring_data), /* maxsize */ 2392143903Sscottl 1, /* nsegments */ 2393143903Sscottl sizeof(struct ti_ring_data), /* maxsegsize */ 2394143903Sscottl 0, /* flags */ 2395143903Sscottl NULL, NULL, /* lockfunc, lockarg */ 2396143903Sscottl &sc->ti_rdata_dmat) != 0) { 2397150719Sjhb device_printf(dev, "Failed to allocate rdata dmat\n"); 2398143903Sscottl error = ENOMEM; 239945386Swpaul goto fail; 240045386Swpaul } 240145386Swpaul 2402143903Sscottl if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2403143903Sscottl BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2404150719Sjhb device_printf(dev, "Failed to allocate rdata memory\n"); 2405143903Sscottl error = ENOMEM; 2406143903Sscottl goto fail; 2407143903Sscottl } 2408143903Sscottl 2409143903Sscottl if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2410143903Sscottl sc->ti_rdata, sizeof(struct ti_ring_data), 2411143903Sscottl ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2412150719Sjhb device_printf(dev, "Failed to load rdata segments\n"); 2413143903Sscottl error = ENOMEM; 2414143903Sscottl goto fail; 2415143903Sscottl } 2416143903Sscottl 241745386Swpaul bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 241845386Swpaul 241945386Swpaul /* Try to allocate memory for jumbo buffers. */ 242045386Swpaul if (ti_alloc_jumbo_mem(sc)) { 2421150719Sjhb device_printf(dev, "jumbo buffer allocation failed\n"); 242249011Swpaul error = ENXIO; 242345386Swpaul goto fail; 242445386Swpaul } 242545386Swpaul 2426153396Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2427153396Sscottl 1, 0, /* algnmnt, boundary */ 2428153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 2429153396Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2430153396Sscottl NULL, NULL, /* filter, filterarg */ 2431153396Sscottl MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2432153396Sscottl TI_MAXTXSEGS, /* nsegments */ 2433153396Sscottl MCLBYTES, /* maxsegsize */ 2434153396Sscottl 0, /* flags */ 2435153396Sscottl NULL, NULL, /* lockfunc, lockarg */ 2436153396Sscottl &sc->ti_mbuftx_dmat) != 0) { 2437153396Sscottl device_printf(dev, "Failed to allocate rdata dmat\n"); 2438153396Sscottl error = ENOMEM; 2439153396Sscottl goto fail; 2440153396Sscottl } 2441153396Sscottl 2442153396Sscottl if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2443153396Sscottl 1, 0, /* algnmnt, boundary */ 2444153396Sscottl BUS_SPACE_MAXADDR, /* lowaddr */ 2445153396Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 2446153396Sscottl NULL, NULL, /* filter, filterarg */ 2447153396Sscottl MCLBYTES, /* maxsize */ 2448153396Sscottl 1, /* nsegments */ 2449153396Sscottl MCLBYTES, /* maxsegsize */ 2450153396Sscottl 0, /* flags */ 2451153396Sscottl NULL, NULL, /* lockfunc, lockarg */ 2452153396Sscottl &sc->ti_mbufrx_dmat) != 0) { 2453153396Sscottl device_printf(dev, "Failed to allocate rdata dmat\n"); 2454153396Sscottl error = ENOMEM; 2455153396Sscottl goto fail; 2456153396Sscottl } 2457153396Sscottl 2458153396Sscottl if (ti_alloc_dmamaps(sc)) { 2459153396Sscottl device_printf(dev, "dma map creation failed\n"); 2460153396Sscottl error = ENXIO; 2461153396Sscottl goto fail; 2462153396Sscottl } 2463153396Sscottl 246463699Swpaul /* 246563699Swpaul * We really need a better way to tell a 1000baseTX card 246663699Swpaul * from a 1000baseSX one, since in theory there could be 246763699Swpaul * OEMed 1000baseTX cards from lame vendors who aren't 246863699Swpaul * clever enough to change the PCI ID. For the moment 246963699Swpaul * though, the AceNIC is the only copper card available. 247063699Swpaul */ 247163699Swpaul if (pci_get_vendor(dev) == ALT_VENDORID && 247263699Swpaul pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 247363699Swpaul sc->ti_copper = 1; 247464139Swpaul /* Ok, it's not the only copper card available. */ 247564139Swpaul if (pci_get_vendor(dev) == NG_VENDORID && 247664139Swpaul pci_get_device(dev) == NG_DEVICEID_GA620T) 247764139Swpaul sc->ti_copper = 1; 247863699Swpaul 247945386Swpaul /* Set default tuneable values. */ 248045386Swpaul sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 248198849Sken#if 0 248245386Swpaul sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 248398849Sken#endif 248498849Sken sc->ti_rx_coal_ticks = 170; 248545386Swpaul sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 248645386Swpaul sc->ti_rx_max_coal_bds = 64; 248798849Sken#if 0 248845386Swpaul sc->ti_tx_max_coal_bds = 128; 248998849Sken#endif 249098849Sken sc->ti_tx_max_coal_bds = 32; 249145386Swpaul sc->ti_tx_buf_ratio = 21; 249245386Swpaul 249345386Swpaul /* Set up ifnet structure */ 249445386Swpaul ifp->if_softc = sc; 2495121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2496153281Sscottl ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 249745386Swpaul ifp->if_ioctl = ti_ioctl; 249845386Swpaul ifp->if_start = ti_start; 249945386Swpaul ifp->if_watchdog = ti_watchdog; 250045386Swpaul ifp->if_init = ti_init; 250145386Swpaul ifp->if_mtu = ETHERMTU; 250245386Swpaul ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 250345386Swpaul 250445386Swpaul /* Set up ifmedia support. */ 250563699Swpaul if (sc->ti_copper) { 250663699Swpaul /* 250763699Swpaul * Copper cards allow manual 10/100 mode selection, 250863699Swpaul * but not manual 1000baseTX mode selection. Why? 250963699Swpaul * Becuase currently there's no way to specify the 251063699Swpaul * master/slave setting through the firmware interface, 251163699Swpaul * so Alteon decided to just bag it and handle it 251263699Swpaul * via autonegotiation. 251363699Swpaul */ 251463699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 251563699Swpaul ifmedia_add(&sc->ifmedia, 251663699Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 251763699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 251863699Swpaul ifmedia_add(&sc->ifmedia, 251963699Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 252095673Sphk ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 252163699Swpaul ifmedia_add(&sc->ifmedia, 252295673Sphk IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 252363699Swpaul } else { 252463699Swpaul /* Fiber cards don't support 10/100 modes. */ 252563699Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 252663699Swpaul ifmedia_add(&sc->ifmedia, 252763699Swpaul IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 252863699Swpaul } 252945386Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 253045386Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 253145386Swpaul 253245386Swpaul /* 253398849Sken * We're assuming here that card initialization is a sequential 253498849Sken * thing. If it isn't, multiple cards probing at the same time 253598849Sken * could stomp on the list of softcs here. 253698849Sken */ 253798849Sken 253898849Sken /* Register the device */ 253998849Sken sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 254098849Sken 0600, "ti%d", sc->ti_unit); 2541120980Sphk sc->dev->si_drv1 = sc; 254298849Sken 254398849Sken /* 254463090Sarchie * Call MI attach routine. 254545386Swpaul */ 2546147256Sbrooks ether_ifattach(ifp, eaddr); 254745386Swpaul 2548113609Snjl /* Hook interrupt last to avoid having to lock softc */ 2549153281Sscottl error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2550166901Spiso NULL, ti_intr, sc, &sc->ti_intrhand); 2551112872Snjl 2552112872Snjl if (error) { 2553150719Sjhb device_printf(dev, "couldn't set up irq\n"); 2554112872Snjl goto fail; 2555112872Snjl } 2556112872Snjl 255745386Swpaulfail: 2558153770Syongari if (error) 2559112872Snjl ti_detach(dev); 2560112872Snjl 2561131654Sbms return (error); 256245386Swpaul} 256345386Swpaul 256498849Sken/* 2565113609Snjl * Shutdown hardware and free up resources. This can be called any 2566113609Snjl * time after the mutex has been initialized. It is called in both 2567113609Snjl * the error case in attach and the normal detach case so it needs 2568113609Snjl * to be careful about only freeing resources that have actually been 2569113609Snjl * allocated. 2570113609Snjl */ 2571102336Salfredstatic int 2572102336Salfredti_detach(dev) 257349011Swpaul device_t dev; 257449011Swpaul{ 257549011Swpaul struct ti_softc *sc; 257649011Swpaul struct ifnet *ifp; 2577153770Syongari int attached; 257849011Swpaul 257949011Swpaul sc = device_get_softc(dev); 2580144407Sscottl if (sc->dev) 2581144407Sscottl destroy_dev(sc->dev); 2582112930Sphk KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2583153770Syongari attached = device_is_attached(dev); 258467087Swpaul TI_LOCK(sc); 2585147256Sbrooks ifp = sc->ti_ifp; 2586153770Syongari if (attached) 2587153770Syongari ti_stop(sc); 2588153770Syongari TI_UNLOCK(sc); 2589153770Syongari if (attached) 2590153770Syongari ether_ifdetach(ifp); 259149011Swpaul 2592113609Snjl /* These should only be active if attach succeeded */ 2593153770Syongari if (attached) 2594112872Snjl bus_generic_detach(dev); 2595153770Syongari ti_free_dmamaps(sc); 2596113609Snjl ifmedia_removeall(&sc->ifmedia); 259749011Swpaul 2598153288Sscottl#ifdef TI_PRIVATE_JUMBOS 2599153288Sscottl if (sc->ti_cdata.ti_jumbo_buf) 2600153288Sscottl bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2601153288Sscottl sc->ti_jumbo_dmamap); 2602153396Sscottl#endif 2603153288Sscottl if (sc->ti_jumbo_dmat) 2604153288Sscottl bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2605153396Sscottl if (sc->ti_mbuftx_dmat) 2606153396Sscottl bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2607153396Sscottl if (sc->ti_mbufrx_dmat) 2608153396Sscottl bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2609143903Sscottl if (sc->ti_rdata) 2610143903Sscottl bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2611143903Sscottl sc->ti_rdata_dmamap); 2612143903Sscottl if (sc->ti_rdata_dmat) 2613143903Sscottl bus_dma_tag_destroy(sc->ti_rdata_dmat); 2614143903Sscottl if (sc->ti_parent_dmat) 2615143903Sscottl bus_dma_tag_destroy(sc->ti_parent_dmat); 2616112872Snjl if (sc->ti_intrhand) 2617112872Snjl bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2618112872Snjl if (sc->ti_irq) 2619112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2620112872Snjl if (sc->ti_res) { 2621112872Snjl bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2622112872Snjl sc->ti_res); 2623112872Snjl } 2624151297Sru if (ifp) 2625151297Sru if_free(ifp); 262649011Swpaul 262767087Swpaul mtx_destroy(&sc->ti_mtx); 262849011Swpaul 2629131654Sbms return (0); 263049011Swpaul} 263149011Swpaul 263298849Sken#ifdef TI_JUMBO_HDRSPLIT 263345386Swpaul/* 263498849Sken * If hdr_len is 0, that means that header splitting wasn't done on 263598849Sken * this packet for some reason. The two most likely reasons are that 263698849Sken * the protocol isn't a supported protocol for splitting, or this 263798849Sken * packet had a fragment offset that wasn't 0. 263898849Sken * 263998849Sken * The header length, if it is non-zero, will always be the length of 264098849Sken * the headers on the packet, but that length could be longer than the 264198849Sken * first mbuf. So we take the minimum of the two as the actual 2642131652Sbms * length. 264398849Sken */ 264498849Skenstatic __inline void 264598849Skenti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 264698849Sken{ 264798849Sken int i = 0; 264898849Sken int lengths[4] = {0, 0, 0, 0}; 264998849Sken struct mbuf *m, *mp; 265098849Sken 265198849Sken if (hdr_len != 0) 265298849Sken top->m_len = min(hdr_len, top->m_len); 265398849Sken pkt_len -= top->m_len; 265498849Sken lengths[i++] = top->m_len; 265598849Sken 265698849Sken mp = top; 265798849Sken for (m = top->m_next; m && pkt_len; m = m->m_next) { 265898849Sken m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 265998849Sken pkt_len -= m->m_len; 266098849Sken lengths[i++] = m->m_len; 266198849Sken mp = m; 266298849Sken } 266398849Sken 266498849Sken#if 0 266598849Sken if (hdr_len != 0) 266698849Sken printf("got split packet: "); 266798849Sken else 266898849Sken printf("got non-split packet: "); 2669131652Sbms 267098849Sken printf("%d,%d,%d,%d = %d\n", lengths[0], 267198849Sken lengths[1], lengths[2], lengths[3], 267298849Sken lengths[0] + lengths[1] + lengths[2] + 267398849Sken lengths[3]); 267498849Sken#endif 267598849Sken 267698849Sken if (pkt_len) 267798849Sken panic("header splitting didn't"); 2678131652Sbms 267998849Sken if (m) { 268098849Sken m_freem(m); 268198849Sken mp->m_next = NULL; 268298849Sken 268398849Sken } 268498849Sken if (mp->m_next != NULL) 268598849Sken panic("ti_hdr_split: last mbuf in chain should be null"); 268698849Sken} 268798849Sken#endif /* TI_JUMBO_HDRSPLIT */ 268898849Sken 268998849Sken/* 269045386Swpaul * Frame reception handling. This is called if there's a frame 269145386Swpaul * on the receive return list. 269245386Swpaul * 269345386Swpaul * Note: we have to be able to handle three possibilities here: 269445386Swpaul * 1) the frame is from the mini receive ring (can only happen) 269545386Swpaul * on Tigon 2 boards) 269645386Swpaul * 2) the frame is from the jumbo recieve ring 269745386Swpaul * 3) the frame is from the standard receive ring 269845386Swpaul */ 269945386Swpaul 2700102336Salfredstatic void 2701102336Salfredti_rxeof(sc) 270245386Swpaul struct ti_softc *sc; 270345386Swpaul{ 2704153396Sscottl bus_dmamap_t map; 270545386Swpaul struct ifnet *ifp; 270648597Swpaul struct ti_cmd_desc cmd; 270745386Swpaul 2708122689Ssam TI_LOCK_ASSERT(sc); 2709122689Ssam 2710147256Sbrooks ifp = sc->ti_ifp; 271145386Swpaul 2712131654Sbms while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 271345386Swpaul struct ti_rx_desc *cur_rx; 271445386Swpaul u_int32_t rxidx; 271545386Swpaul struct mbuf *m = NULL; 271645386Swpaul u_int16_t vlan_tag = 0; 271745386Swpaul int have_tag = 0; 271845386Swpaul 271945386Swpaul cur_rx = 272045386Swpaul &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 272145386Swpaul rxidx = cur_rx->ti_idx; 272245386Swpaul TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 272345386Swpaul 272445386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 272545386Swpaul have_tag = 1; 272677058Sphk vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 272745386Swpaul } 272845386Swpaul 272945386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 273098849Sken 273145386Swpaul TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 273245386Swpaul m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 273345386Swpaul sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2734153396Sscottl map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2735153396Sscottl bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2736153396Sscottl BUS_DMASYNC_POSTREAD); 2737153396Sscottl bus_dmamap_unload(sc->ti_jumbo_dmat, map); 273845386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 273945386Swpaul ifp->if_ierrors++; 274045386Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 274145386Swpaul continue; 274245386Swpaul } 274348597Swpaul if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 274448597Swpaul ifp->if_ierrors++; 274548597Swpaul ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 274648597Swpaul continue; 274748597Swpaul } 274898849Sken#ifdef TI_PRIVATE_JUMBOS 2749131655Sbms m->m_len = cur_rx->ti_len; 275098849Sken#else /* TI_PRIVATE_JUMBOS */ 275198849Sken#ifdef TI_JUMBO_HDRSPLIT 275298849Sken if (sc->ti_hdrsplit) 275398849Sken ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 275498849Sken cur_rx->ti_len, rxidx); 275598849Sken else 275698849Sken#endif /* TI_JUMBO_HDRSPLIT */ 2757131655Sbms m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 275898849Sken#endif /* TI_PRIVATE_JUMBOS */ 275945386Swpaul } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 276045386Swpaul TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 276145386Swpaul m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 276245386Swpaul sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2763153396Sscottl map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2764153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2765153396Sscottl BUS_DMASYNC_POSTREAD); 2766153396Sscottl bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 276745386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 276845386Swpaul ifp->if_ierrors++; 276945386Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 277045386Swpaul continue; 277145386Swpaul } 277248597Swpaul if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 277348597Swpaul ifp->if_ierrors++; 277448597Swpaul ti_newbuf_mini(sc, sc->ti_mini, m); 277548597Swpaul continue; 277648597Swpaul } 277798849Sken m->m_len = cur_rx->ti_len; 277845386Swpaul } else { 277945386Swpaul TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 278045386Swpaul m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 278145386Swpaul sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2782153396Sscottl map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2783153396Sscottl bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2784153396Sscottl BUS_DMASYNC_POSTREAD); 2785153396Sscottl bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 278645386Swpaul if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 278745386Swpaul ifp->if_ierrors++; 278845386Swpaul ti_newbuf_std(sc, sc->ti_std, m); 278945386Swpaul continue; 279045386Swpaul } 279148597Swpaul if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 279248597Swpaul ifp->if_ierrors++; 279348597Swpaul ti_newbuf_std(sc, sc->ti_std, m); 279448597Swpaul continue; 279548597Swpaul } 279698849Sken m->m_len = cur_rx->ti_len; 279745386Swpaul } 279845386Swpaul 279998849Sken m->m_pkthdr.len = cur_rx->ti_len; 280045386Swpaul ifp->if_ipackets++; 280145386Swpaul m->m_pkthdr.rcvif = ifp; 280245386Swpaul 280358698Sjlemon if (ifp->if_hwassist) { 280458698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 280558698Sjlemon CSUM_DATA_VALID; 280658698Sjlemon if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 280758698Sjlemon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 280858698Sjlemon m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 280958698Sjlemon } 281045386Swpaul 281145386Swpaul /* 2812106936Ssam * If we received a packet with a vlan tag, 2813106936Ssam * tag it before passing the packet upward. 281445386Swpaul */ 2815153512Sglebius if (have_tag) { 2816162375Sandre m->m_pkthdr.ether_vtag = vlan_tag; 2817162375Sandre m->m_flags |= M_VLANTAG; 2818153512Sglebius } 2819122689Ssam TI_UNLOCK(sc); 2820106936Ssam (*ifp->if_input)(ifp, m); 2821122689Ssam TI_LOCK(sc); 282245386Swpaul } 282345386Swpaul 282445386Swpaul /* Only necessary on the Tigon 1. */ 282545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) 282645386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 282745386Swpaul sc->ti_rx_saved_considx); 282845386Swpaul 282948597Swpaul TI_UPDATE_STDPROD(sc, sc->ti_std); 283048597Swpaul TI_UPDATE_MINIPROD(sc, sc->ti_mini); 283148597Swpaul TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 283245386Swpaul} 283345386Swpaul 2834102336Salfredstatic void 2835102336Salfredti_txeof(sc) 283645386Swpaul struct ti_softc *sc; 283745386Swpaul{ 2838153982Syongari struct ti_txdesc *txd; 2839153982Syongari struct ti_tx_desc txdesc; 284045386Swpaul struct ti_tx_desc *cur_tx = NULL; 284145386Swpaul struct ifnet *ifp; 2842153982Syongari int idx; 284345386Swpaul 2844147256Sbrooks ifp = sc->ti_ifp; 284545386Swpaul 2846153982Syongari txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2847153982Syongari if (txd == NULL) 2848153982Syongari return; 284945386Swpaul /* 285045386Swpaul * Go through our tx ring and free mbufs for those 285145386Swpaul * frames that have been sent. 285245386Swpaul */ 2853153982Syongari for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2854153982Syongari TI_INC(idx, TI_TX_RING_CNT)) { 285545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 2856153770Syongari ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2857153770Syongari sizeof(txdesc), &txdesc); 2858153770Syongari cur_tx = &txdesc; 285945386Swpaul } else 286045386Swpaul cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 286148011Swpaul sc->ti_txcnt--; 2862153982Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2863153982Syongari if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2864153982Syongari continue; 2865153982Syongari bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2866153982Syongari BUS_DMASYNC_POSTWRITE); 2867153982Syongari bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2868153982Syongari 2869153982Syongari ifp->if_opackets++; 2870153982Syongari m_freem(txd->tx_m); 2871153982Syongari txd->tx_m = NULL; 2872153982Syongari STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2873153982Syongari STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2874153982Syongari txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 287545386Swpaul } 2876153982Syongari sc->ti_tx_saved_considx = idx; 287745386Swpaul 2878153982Syongari ifp->if_timer = sc->ti_txcnt > 0 ? 5 : 0; 287945386Swpaul} 288045386Swpaul 2881102336Salfredstatic void 2882102336Salfredti_intr(xsc) 288345386Swpaul void *xsc; 288445386Swpaul{ 288545386Swpaul struct ti_softc *sc; 288645386Swpaul struct ifnet *ifp; 288745386Swpaul 288845386Swpaul sc = xsc; 288967087Swpaul TI_LOCK(sc); 2890147256Sbrooks ifp = sc->ti_ifp; 289145386Swpaul 289298849Sken/*#ifdef notdef*/ 289345386Swpaul /* Avoid this for now -- checking this register is expensive. */ 289445386Swpaul /* Make sure this is really our interrupt. */ 289567087Swpaul if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 289667087Swpaul TI_UNLOCK(sc); 289745386Swpaul return; 289867087Swpaul } 289998849Sken/*#endif*/ 290045386Swpaul 290145386Swpaul /* Ack interrupt and stop others from occuring. */ 290245386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 290345386Swpaul 2904148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 290545386Swpaul /* Check RX return ring producer/consumer */ 290645386Swpaul ti_rxeof(sc); 290745386Swpaul 290845386Swpaul /* Check TX ring producer/consumer */ 290945386Swpaul ti_txeof(sc); 291045386Swpaul } 291145386Swpaul 291245386Swpaul ti_handle_events(sc); 291345386Swpaul 291445386Swpaul /* Re-enable interrupts. */ 291545386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 291645386Swpaul 2917148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2918148887Srwatson ifp->if_snd.ifq_head != NULL) 2919153770Syongari ti_start_locked(ifp); 292045386Swpaul 292167087Swpaul TI_UNLOCK(sc); 292245386Swpaul} 292345386Swpaul 2924102336Salfredstatic void 2925102336Salfredti_stats_update(sc) 292645386Swpaul struct ti_softc *sc; 292745386Swpaul{ 292845386Swpaul struct ifnet *ifp; 292945386Swpaul 2930147256Sbrooks ifp = sc->ti_ifp; 293145386Swpaul 2932153770Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2933153770Syongari BUS_DMASYNC_POSTREAD); 2934153770Syongari 293545386Swpaul ifp->if_collisions += 293645386Swpaul (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 293745386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 293845386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 293945386Swpaul sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 294045386Swpaul ifp->if_collisions; 2941153770Syongari 2942153770Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2943153770Syongari BUS_DMASYNC_PREREAD); 294445386Swpaul} 294545386Swpaul 2946153982Syongari/* 2947153982Syongari * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2948153982Syongari * pointers to descriptors. 2949153982Syongari */ 2950153982Syongaristatic int 2951153982Syongariti_encap(sc, m_head) 2952153982Syongari struct ti_softc *sc; 2953153982Syongari struct mbuf **m_head; 2954153396Sscottl{ 2955153982Syongari struct ti_txdesc *txd; 2956153982Syongari struct ti_tx_desc *f; 2957153770Syongari struct ti_tx_desc txdesc; 2958161236Syongari struct mbuf *m; 2959153982Syongari bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2960153396Sscottl u_int16_t csum_flags; 2961153982Syongari int error, frag, i, nseg; 2962153396Sscottl 2963153982Syongari if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2964153982Syongari return (ENOBUFS); 2965153396Sscottl 2966153982Syongari error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2967161236Syongari *m_head, txsegs, &nseg, 0); 2968153982Syongari if (error == EFBIG) { 2969161236Syongari m = m_defrag(*m_head, M_DONTWAIT); 2970161236Syongari if (m == NULL) { 2971161236Syongari m_freem(*m_head); 2972161236Syongari *m_head = NULL; 2973153982Syongari return (ENOMEM); 2974153982Syongari } 2975161236Syongari *m_head = m; 2976153982Syongari error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2977161236Syongari txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2978153982Syongari if (error) { 2979161236Syongari m_freem(*m_head); 2980161236Syongari *m_head = NULL; 2981153982Syongari return (error); 2982153982Syongari } 2983153982Syongari } else if (error != 0) 2984153982Syongari return (error); 2985153982Syongari if (nseg == 0) { 2986161236Syongari m_freem(*m_head); 2987161236Syongari *m_head = NULL; 2988153982Syongari return (EIO); 2989153776Sscottl } 2990153776Sscottl 2991153982Syongari if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2992153982Syongari bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2993153982Syongari return (ENOBUFS); 2994153982Syongari } 2995153982Syongari 2996161236Syongari m = *m_head; 2997161236Syongari csum_flags = 0; 2998161236Syongari if (m->m_pkthdr.csum_flags) { 2999161236Syongari if (m->m_pkthdr.csum_flags & CSUM_IP) 3000161236Syongari csum_flags |= TI_BDFLAG_IP_CKSUM; 3001161236Syongari if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3002161236Syongari csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3003161236Syongari if (m->m_flags & M_LASTFRAG) 3004161236Syongari csum_flags |= TI_BDFLAG_IP_FRAG_END; 3005161236Syongari else if (m->m_flags & M_FRAG) 3006161236Syongari csum_flags |= TI_BDFLAG_IP_FRAG; 3007161236Syongari } 3008161236Syongari 3009153982Syongari bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 3010153982Syongari BUS_DMASYNC_PREWRITE); 3011153982Syongari bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 3012153982Syongari BUS_DMASYNC_PREWRITE); 3013153982Syongari 3014153982Syongari frag = sc->ti_tx_saved_prodidx; 3015153982Syongari for (i = 0; i < nseg; i++) { 3016153396Sscottl if (sc->ti_hwrev == TI_HWREV_TIGON) { 3017153770Syongari bzero(&txdesc, sizeof(txdesc)); 3018153770Syongari f = &txdesc; 3019153396Sscottl } else 3020153396Sscottl f = &sc->ti_rdata->ti_tx_ring[frag]; 3021153982Syongari ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3022153982Syongari f->ti_len = txsegs[i].ds_len; 3023153396Sscottl f->ti_flags = csum_flags; 3024162375Sandre if (m->m_flags & M_VLANTAG) { 3025153396Sscottl f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3026162375Sandre f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff; 3027153396Sscottl } else { 3028153396Sscottl f->ti_vlan_tag = 0; 3029153396Sscottl } 3030153396Sscottl 3031153770Syongari if (sc->ti_hwrev == TI_HWREV_TIGON) 3032153770Syongari ti_mem_write(sc, TI_TX_RING_BASE + frag * 3033153770Syongari sizeof(txdesc), sizeof(txdesc), &txdesc); 3034153396Sscottl TI_INC(frag, TI_TX_RING_CNT); 3035153396Sscottl } 3036153396Sscottl 3037153982Syongari sc->ti_tx_saved_prodidx = frag; 3038153982Syongari /* set TI_BDFLAG_END on the last descriptor */ 3039153982Syongari frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3040153770Syongari if (sc->ti_hwrev == TI_HWREV_TIGON) { 3041153770Syongari txdesc.ti_flags |= TI_BDFLAG_END; 3042153982Syongari ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3043153770Syongari sizeof(txdesc), &txdesc); 3044153770Syongari } else 3045153982Syongari sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3046153396Sscottl 3047153982Syongari STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3048153982Syongari STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3049153982Syongari txd->tx_m = m; 3050153982Syongari sc->ti_txcnt += nseg; 305145386Swpaul 3052131654Sbms return (0); 305345386Swpaul} 305445386Swpaul 3055153770Syongaristatic void 3056153770Syongariti_start(ifp) 3057153770Syongari struct ifnet *ifp; 3058153770Syongari{ 3059153770Syongari struct ti_softc *sc; 3060153770Syongari 3061153770Syongari sc = ifp->if_softc; 3062153770Syongari TI_LOCK(sc); 3063153770Syongari ti_start_locked(ifp); 3064153770Syongari TI_UNLOCK(sc); 3065153770Syongari} 3066153770Syongari 306745386Swpaul/* 306845386Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 306945386Swpaul * to the mbuf data regions directly in the transmit descriptors. 307045386Swpaul */ 3071102336Salfredstatic void 3072153770Syongariti_start_locked(ifp) 307345386Swpaul struct ifnet *ifp; 307445386Swpaul{ 307545386Swpaul struct ti_softc *sc; 307645386Swpaul struct mbuf *m_head = NULL; 3077153982Syongari int enq = 0; 307845386Swpaul 307945386Swpaul sc = ifp->if_softc; 308045386Swpaul 3081153982Syongari for (; ifp->if_snd.ifq_head != NULL && 3082153982Syongari sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 308345386Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 308445386Swpaul if (m_head == NULL) 308545386Swpaul break; 308645386Swpaul 308745386Swpaul /* 308858698Sjlemon * XXX 308958698Sjlemon * safety overkill. If this is a fragmented packet chain 309058698Sjlemon * with delayed TCP/UDP checksums, then only encapsulate 309158698Sjlemon * it if we have enough descriptors to handle the entire 309258698Sjlemon * chain at once. 309358698Sjlemon * (paranoia -- may not actually be needed) 309458698Sjlemon */ 309558698Sjlemon if (m_head->m_flags & M_FIRSTFRAG && 309658698Sjlemon m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 309758698Sjlemon if ((TI_TX_RING_CNT - sc->ti_txcnt) < 309858698Sjlemon m_head->m_pkthdr.csum_data + 16) { 309958698Sjlemon IF_PREPEND(&ifp->if_snd, m_head); 3100148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 310158698Sjlemon break; 310258698Sjlemon } 310358698Sjlemon } 310458698Sjlemon 310558698Sjlemon /* 310645386Swpaul * Pack the data into the transmit ring. If we 310745386Swpaul * don't have room, set the OACTIVE flag and wait 310845386Swpaul * for the NIC to drain the ring. 310945386Swpaul */ 3110153982Syongari if (ti_encap(sc, &m_head)) { 3111153982Syongari if (m_head == NULL) 3112153982Syongari break; 311345386Swpaul IF_PREPEND(&ifp->if_snd, m_head); 3114148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 311545386Swpaul break; 311645386Swpaul } 311745386Swpaul 3118153982Syongari enq++; 311945386Swpaul /* 312045386Swpaul * If there's a BPF listener, bounce a copy of this frame 312145386Swpaul * to him. 312245386Swpaul */ 3123167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 312445386Swpaul } 312545386Swpaul 3126153982Syongari if (enq > 0) { 3127153982Syongari /* Transmit */ 3128153982Syongari CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 312945386Swpaul 3130153982Syongari /* 3131153982Syongari * Set a timeout in case the chip goes out to lunch. 3132153982Syongari */ 3133153982Syongari ifp->if_timer = 5; 3134153982Syongari } 313545386Swpaul} 313645386Swpaul 3137102336Salfredstatic void 3138102336Salfredti_init(xsc) 313945386Swpaul void *xsc; 314045386Swpaul{ 3141153770Syongari struct ti_softc *sc; 3142153770Syongari 3143153770Syongari sc = xsc; 3144153770Syongari TI_LOCK(sc); 3145153770Syongari ti_init_locked(sc); 3146153770Syongari TI_UNLOCK(sc); 3147153770Syongari} 3148153770Syongari 3149153770Syongaristatic void 3150153770Syongariti_init_locked(xsc) 3151153770Syongari void *xsc; 3152153770Syongari{ 315345386Swpaul struct ti_softc *sc = xsc; 315445386Swpaul 315545386Swpaul /* Cancel pending I/O and flush buffers. */ 315645386Swpaul ti_stop(sc); 315745386Swpaul 315845386Swpaul /* Init the gen info block, ring control blocks and firmware. */ 315945386Swpaul if (ti_gibinit(sc)) { 3160162321Sglebius device_printf(sc->ti_dev, "initialization failure\n"); 316145386Swpaul return; 316245386Swpaul } 316345386Swpaul} 316445386Swpaul 316545386Swpaulstatic void ti_init2(sc) 316645386Swpaul struct ti_softc *sc; 316745386Swpaul{ 316845386Swpaul struct ti_cmd_desc cmd; 316945386Swpaul struct ifnet *ifp; 3170153770Syongari u_int8_t *ea; 317145386Swpaul struct ifmedia *ifm; 317245386Swpaul int tmp; 317345386Swpaul 3174153770Syongari TI_LOCK_ASSERT(sc); 3175153770Syongari 3176147256Sbrooks ifp = sc->ti_ifp; 317745386Swpaul 317845386Swpaul /* Specify MTU and interface index. */ 3179121816Sbrooks CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 318045386Swpaul CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3181118454Ssimokawa ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 318245386Swpaul TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 318345386Swpaul 318445386Swpaul /* Load our MAC address. */ 3185153770Syongari ea = IF_LLADDR(sc->ti_ifp); 3186153770Syongari CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3187153770Syongari CSR_WRITE_4(sc, TI_GCR_PAR1, 3188153770Syongari (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 318945386Swpaul TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 319045386Swpaul 319145386Swpaul /* Enable or disable promiscuous mode as needed. */ 319245386Swpaul if (ifp->if_flags & IFF_PROMISC) { 319345386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 319445386Swpaul } else { 319545386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 319645386Swpaul } 319745386Swpaul 319845386Swpaul /* Program multicast filter. */ 319945386Swpaul ti_setmulti(sc); 320045386Swpaul 320145386Swpaul /* 320245386Swpaul * If this is a Tigon 1, we should tell the 320345386Swpaul * firmware to use software packet filtering. 320445386Swpaul */ 320545386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON) { 320645386Swpaul TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 320745386Swpaul } 320845386Swpaul 320945386Swpaul /* Init RX ring. */ 321045386Swpaul ti_init_rx_ring_std(sc); 321145386Swpaul 321245386Swpaul /* Init jumbo RX ring. */ 321345386Swpaul if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 321445386Swpaul ti_init_rx_ring_jumbo(sc); 321545386Swpaul 321645386Swpaul /* 321745386Swpaul * If this is a Tigon 2, we can also configure the 321845386Swpaul * mini ring. 321945386Swpaul */ 322045386Swpaul if (sc->ti_hwrev == TI_HWREV_TIGON_II) 322145386Swpaul ti_init_rx_ring_mini(sc); 322245386Swpaul 322345386Swpaul CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 322445386Swpaul sc->ti_rx_saved_considx = 0; 322545386Swpaul 322645386Swpaul /* Init TX ring. */ 322745386Swpaul ti_init_tx_ring(sc); 322845386Swpaul 322945386Swpaul /* Tell firmware we're alive. */ 323045386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 323145386Swpaul 323245386Swpaul /* Enable host interrupts. */ 323345386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 323445386Swpaul 3235148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 3236148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 323745386Swpaul 323845386Swpaul /* 323945386Swpaul * Make sure to set media properly. We have to do this 324045386Swpaul * here since we have to issue commands in order to set 324145386Swpaul * the link negotiation and we can't issue commands until 324245386Swpaul * the firmware is running. 324345386Swpaul */ 324445386Swpaul ifm = &sc->ifmedia; 324545386Swpaul tmp = ifm->ifm_media; 324645386Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 324745386Swpaul ti_ifmedia_upd(ifp); 324845386Swpaul ifm->ifm_media = tmp; 324945386Swpaul} 325045386Swpaul 325145386Swpaul/* 325245386Swpaul * Set media options. 325345386Swpaul */ 3254102336Salfredstatic int 3255102336Salfredti_ifmedia_upd(ifp) 325645386Swpaul struct ifnet *ifp; 325745386Swpaul{ 325845386Swpaul struct ti_softc *sc; 325945386Swpaul struct ifmedia *ifm; 326045386Swpaul struct ti_cmd_desc cmd; 326198849Sken u_int32_t flowctl; 326245386Swpaul 326345386Swpaul sc = ifp->if_softc; 326445386Swpaul ifm = &sc->ifmedia; 326545386Swpaul 326645386Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3267131654Sbms return (EINVAL); 326845386Swpaul 326998849Sken flowctl = 0; 327098849Sken 3271131654Sbms switch (IFM_SUBTYPE(ifm->ifm_media)) { 327245386Swpaul case IFM_AUTO: 327398849Sken /* 327498849Sken * Transmit flow control doesn't work on the Tigon 1. 327598849Sken */ 327698849Sken flowctl = TI_GLNK_RX_FLOWCTL_Y; 327798849Sken 327898849Sken /* 327998849Sken * Transmit flow control can also cause problems on the 328098849Sken * Tigon 2, apparantly with both the copper and fiber 328198849Sken * boards. The symptom is that the interface will just 328298849Sken * hang. This was reproduced with Alteon 180 switches. 328398849Sken */ 328498849Sken#if 0 328598849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 3286131652Sbms flowctl |= TI_GLNK_TX_FLOWCTL_Y; 328798849Sken#endif 328898849Sken 328945386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 329098849Sken TI_GLNK_FULL_DUPLEX| flowctl | 329145386Swpaul TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 329298849Sken 329398849Sken flowctl = TI_LNK_RX_FLOWCTL_Y; 329498849Sken#if 0 329598849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 329698849Sken flowctl |= TI_LNK_TX_FLOWCTL_Y; 329798849Sken#endif 329898849Sken 329945386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 330098849Sken TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 330145386Swpaul TI_LNK_AUTONEGENB|TI_LNK_ENB); 330245386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 330345386Swpaul TI_CMD_CODE_NEGOTIATE_BOTH, 0); 330445386Swpaul break; 330545386Swpaul case IFM_1000_SX: 330695673Sphk case IFM_1000_T: 330798849Sken flowctl = TI_GLNK_RX_FLOWCTL_Y; 330898849Sken#if 0 330998849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 3310131652Sbms flowctl |= TI_GLNK_TX_FLOWCTL_Y; 331198849Sken#endif 331298849Sken 331345386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 331498849Sken flowctl |TI_GLNK_ENB); 331545386Swpaul CSR_WRITE_4(sc, TI_GCR_LINK, 0); 331663699Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 331763699Swpaul TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 331863699Swpaul } 331945386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 332045386Swpaul TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 332145386Swpaul break; 332245386Swpaul case IFM_100_FX: 332345386Swpaul case IFM_10_FL: 332463699Swpaul case IFM_100_TX: 332563699Swpaul case IFM_10_T: 332698849Sken flowctl = TI_LNK_RX_FLOWCTL_Y; 332798849Sken#if 0 332898849Sken if (sc->ti_hwrev != TI_HWREV_TIGON) 332998849Sken flowctl |= TI_LNK_TX_FLOWCTL_Y; 333098849Sken#endif 333198849Sken 333245386Swpaul CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 333398849Sken CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 333463699Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 333563699Swpaul IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 333645386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 333745386Swpaul } else { 333845386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 333945386Swpaul } 334045386Swpaul if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 334145386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 334245386Swpaul } else { 334345386Swpaul TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 334445386Swpaul } 334545386Swpaul TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 334645386Swpaul TI_CMD_CODE_NEGOTIATE_10_100, 0); 334745386Swpaul break; 334845386Swpaul } 334945386Swpaul 3350131654Sbms return (0); 335145386Swpaul} 335245386Swpaul 335345386Swpaul/* 335445386Swpaul * Report current media status. 335545386Swpaul */ 3356102336Salfredstatic void 3357102336Salfredti_ifmedia_sts(ifp, ifmr) 335845386Swpaul struct ifnet *ifp; 335945386Swpaul struct ifmediareq *ifmr; 336045386Swpaul{ 336145386Swpaul struct ti_softc *sc; 336263699Swpaul u_int32_t media = 0; 336345386Swpaul 336445386Swpaul sc = ifp->if_softc; 336545386Swpaul 336645386Swpaul ifmr->ifm_status = IFM_AVALID; 336745386Swpaul ifmr->ifm_active = IFM_ETHER; 336845386Swpaul 336945386Swpaul if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 337045386Swpaul return; 337145386Swpaul 337245386Swpaul ifmr->ifm_status |= IFM_ACTIVE; 337345386Swpaul 337463699Swpaul if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 337563699Swpaul media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 337663699Swpaul if (sc->ti_copper) 337795673Sphk ifmr->ifm_active |= IFM_1000_T; 337863699Swpaul else 337963699Swpaul ifmr->ifm_active |= IFM_1000_SX; 338063699Swpaul if (media & TI_GLNK_FULL_DUPLEX) 338163699Swpaul ifmr->ifm_active |= IFM_FDX; 338263699Swpaul else 338363699Swpaul ifmr->ifm_active |= IFM_HDX; 338463699Swpaul } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 338545386Swpaul media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 338663699Swpaul if (sc->ti_copper) { 338763699Swpaul if (media & TI_LNK_100MB) 338863699Swpaul ifmr->ifm_active |= IFM_100_TX; 338963699Swpaul if (media & TI_LNK_10MB) 339063699Swpaul ifmr->ifm_active |= IFM_10_T; 339163699Swpaul } else { 339263699Swpaul if (media & TI_LNK_100MB) 339363699Swpaul ifmr->ifm_active |= IFM_100_FX; 339463699Swpaul if (media & TI_LNK_10MB) 339563699Swpaul ifmr->ifm_active |= IFM_10_FL; 339663699Swpaul } 339745386Swpaul if (media & TI_LNK_FULL_DUPLEX) 339845386Swpaul ifmr->ifm_active |= IFM_FDX; 339945386Swpaul if (media & TI_LNK_HALF_DUPLEX) 340045386Swpaul ifmr->ifm_active |= IFM_HDX; 340145386Swpaul } 340245386Swpaul} 340345386Swpaul 3404102336Salfredstatic int 3405102336Salfredti_ioctl(ifp, command, data) 340645386Swpaul struct ifnet *ifp; 340745386Swpaul u_long command; 340845386Swpaul caddr_t data; 340945386Swpaul{ 341045386Swpaul struct ti_softc *sc = ifp->if_softc; 341145386Swpaul struct ifreq *ifr = (struct ifreq *) data; 341283630Sjlemon int mask, error = 0; 341345386Swpaul struct ti_cmd_desc cmd; 341445386Swpaul 3415131654Sbms switch (command) { 341645386Swpaul case SIOCSIFMTU: 3417153770Syongari TI_LOCK(sc); 341845386Swpaul if (ifr->ifr_mtu > TI_JUMBO_MTU) 341945386Swpaul error = EINVAL; 342045386Swpaul else { 342145386Swpaul ifp->if_mtu = ifr->ifr_mtu; 3422153770Syongari ti_init_locked(sc); 342345386Swpaul } 3424153770Syongari TI_UNLOCK(sc); 342545386Swpaul break; 342645386Swpaul case SIOCSIFFLAGS: 3427153770Syongari TI_LOCK(sc); 342845386Swpaul if (ifp->if_flags & IFF_UP) { 342945386Swpaul /* 343045386Swpaul * If only the state of the PROMISC flag changed, 343145386Swpaul * then just use the 'set promisc mode' command 343245386Swpaul * instead of reinitializing the entire NIC. Doing 343345386Swpaul * a full re-init means reloading the firmware and 343445386Swpaul * waiting for it to start up, which may take a 343545386Swpaul * second or two. 343645386Swpaul */ 3437148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 343845386Swpaul ifp->if_flags & IFF_PROMISC && 343945386Swpaul !(sc->ti_if_flags & IFF_PROMISC)) { 344045386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 344145386Swpaul TI_CMD_CODE_PROMISC_ENB, 0); 3442148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 344345386Swpaul !(ifp->if_flags & IFF_PROMISC) && 344445386Swpaul sc->ti_if_flags & IFF_PROMISC) { 344545386Swpaul TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 344645386Swpaul TI_CMD_CODE_PROMISC_DIS, 0); 344745386Swpaul } else 3448153770Syongari ti_init_locked(sc); 344945386Swpaul } else { 3450148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 345145386Swpaul ti_stop(sc); 345245386Swpaul } 345345386Swpaul } 345445386Swpaul sc->ti_if_flags = ifp->if_flags; 3455153770Syongari TI_UNLOCK(sc); 345645386Swpaul break; 345745386Swpaul case SIOCADDMULTI: 345845386Swpaul case SIOCDELMULTI: 3459153770Syongari TI_LOCK(sc); 3460153770Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 346145386Swpaul ti_setmulti(sc); 3462153770Syongari TI_UNLOCK(sc); 346345386Swpaul break; 346445386Swpaul case SIOCSIFMEDIA: 346545386Swpaul case SIOCGIFMEDIA: 346645386Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 346745386Swpaul break; 346883630Sjlemon case SIOCSIFCAP: 3469153770Syongari TI_LOCK(sc); 347083630Sjlemon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 347183630Sjlemon if (mask & IFCAP_HWCSUM) { 347283630Sjlemon if (IFCAP_HWCSUM & ifp->if_capenable) 347383630Sjlemon ifp->if_capenable &= ~IFCAP_HWCSUM; 3474131655Sbms else 3475131655Sbms ifp->if_capenable |= IFCAP_HWCSUM; 3476148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3477153770Syongari ti_init_locked(sc); 3478131655Sbms } 3479153770Syongari TI_UNLOCK(sc); 348083630Sjlemon break; 348145386Swpaul default: 3482106936Ssam error = ether_ioctl(ifp, command, data); 348345386Swpaul break; 348445386Swpaul } 348545386Swpaul 3486131654Sbms return (error); 348745386Swpaul} 348845386Swpaul 348998849Skenstatic int 3490130585Sphkti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 349198849Sken{ 349298849Sken struct ti_softc *sc; 349398849Sken 3494120980Sphk sc = dev->si_drv1; 349598849Sken if (sc == NULL) 3496131654Sbms return (ENODEV); 349798849Sken 349898849Sken TI_LOCK(sc); 349998849Sken sc->ti_flags |= TI_FLAG_DEBUGING; 350098849Sken TI_UNLOCK(sc); 350198849Sken 3502131654Sbms return (0); 350398849Sken} 350498849Sken 350598849Skenstatic int 3506130585Sphkti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 350798849Sken{ 350898849Sken struct ti_softc *sc; 350998849Sken 3510120980Sphk sc = dev->si_drv1; 351198849Sken if (sc == NULL) 3512131654Sbms return (ENODEV); 351398849Sken 351498849Sken TI_LOCK(sc); 351598849Sken sc->ti_flags &= ~TI_FLAG_DEBUGING; 351698849Sken TI_UNLOCK(sc); 351798849Sken 3518131654Sbms return (0); 351998849Sken} 352098849Sken 352198849Sken/* 352298849Sken * This ioctl routine goes along with the Tigon character device. 352398849Sken */ 3524131652Sbmsstatic int 3525150719Sjhbti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3526150719Sjhb struct thread *td) 352798849Sken{ 3528120980Sphk int error; 352998849Sken struct ti_softc *sc; 353098849Sken 3531120980Sphk sc = dev->si_drv1; 353298849Sken if (sc == NULL) 3533131654Sbms return (ENODEV); 353498849Sken 353598849Sken error = 0; 353698849Sken 3537131654Sbms switch (cmd) { 353898849Sken case TIIOCGETSTATS: 353998849Sken { 354098849Sken struct ti_stats *outstats; 354198849Sken 354298849Sken outstats = (struct ti_stats *)addr; 354398849Sken 3544153281Sscottl TI_LOCK(sc); 354598849Sken bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 354698849Sken sizeof(struct ti_stats)); 3547153281Sscottl TI_UNLOCK(sc); 354898849Sken break; 354998849Sken } 355098849Sken case TIIOCGETPARAMS: 355198849Sken { 355298849Sken struct ti_params *params; 355398849Sken 355498849Sken params = (struct ti_params *)addr; 355598849Sken 3556153281Sscottl TI_LOCK(sc); 355798849Sken params->ti_stat_ticks = sc->ti_stat_ticks; 355898849Sken params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 355998849Sken params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 356098849Sken params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 356198849Sken params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 356298849Sken params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 356398849Sken params->param_mask = TI_PARAM_ALL; 3564153281Sscottl TI_UNLOCK(sc); 356598849Sken 356698849Sken error = 0; 356798849Sken 356898849Sken break; 356998849Sken } 357098849Sken case TIIOCSETPARAMS: 357198849Sken { 357298849Sken struct ti_params *params; 357398849Sken 357498849Sken params = (struct ti_params *)addr; 357598849Sken 3576153281Sscottl TI_LOCK(sc); 357798849Sken if (params->param_mask & TI_PARAM_STAT_TICKS) { 357898849Sken sc->ti_stat_ticks = params->ti_stat_ticks; 357998849Sken CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 358098849Sken } 358198849Sken 358298849Sken if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 358398849Sken sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 358498849Sken CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 358598849Sken sc->ti_rx_coal_ticks); 358698849Sken } 358798849Sken 358898849Sken if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 358998849Sken sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 359098849Sken CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 359198849Sken sc->ti_tx_coal_ticks); 359298849Sken } 359398849Sken 359498849Sken if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 359598849Sken sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 359698849Sken CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 359798849Sken sc->ti_rx_max_coal_bds); 359898849Sken } 359998849Sken 360098849Sken if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 360198849Sken sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 360298849Sken CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 360398849Sken sc->ti_tx_max_coal_bds); 360498849Sken } 360598849Sken 360698849Sken if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 360798849Sken sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 360898849Sken CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 360998849Sken sc->ti_tx_buf_ratio); 361098849Sken } 3611153281Sscottl TI_UNLOCK(sc); 361298849Sken 361398849Sken error = 0; 361498849Sken 361598849Sken break; 361698849Sken } 361798849Sken case TIIOCSETTRACE: { 361898849Sken ti_trace_type trace_type; 361998849Sken 362098849Sken trace_type = *(ti_trace_type *)addr; 362198849Sken 362298849Sken /* 362398849Sken * Set tracing to whatever the user asked for. Setting 362498849Sken * this register to 0 should have the effect of disabling 362598849Sken * tracing. 362698849Sken */ 362798849Sken CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 362898849Sken 362998849Sken error = 0; 363098849Sken 363198849Sken break; 363298849Sken } 363398849Sken case TIIOCGETTRACE: { 363498849Sken struct ti_trace_buf *trace_buf; 363598849Sken u_int32_t trace_start, cur_trace_ptr, trace_len; 363698849Sken 363798849Sken trace_buf = (struct ti_trace_buf *)addr; 363898849Sken 3639153281Sscottl TI_LOCK(sc); 364098849Sken trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 364198849Sken cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 364298849Sken trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 364398849Sken 364498849Sken#if 0 3645150719Sjhb if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3646150719Sjhb "trace_len = %d\n", trace_start, 364798849Sken cur_trace_ptr, trace_len); 3648150719Sjhb if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 364998849Sken trace_buf->buf_len); 365098849Sken#endif 365198849Sken 365298849Sken error = ti_copy_mem(sc, trace_start, min(trace_len, 365398849Sken trace_buf->buf_len), 365498849Sken (caddr_t)trace_buf->buf, 1, 1); 365598849Sken 365698849Sken if (error == 0) { 365798849Sken trace_buf->fill_len = min(trace_len, 365898849Sken trace_buf->buf_len); 365998849Sken if (cur_trace_ptr < trace_start) 366098849Sken trace_buf->cur_trace_ptr = 366198849Sken trace_start - cur_trace_ptr; 366298849Sken else 366398849Sken trace_buf->cur_trace_ptr = 366498849Sken cur_trace_ptr - trace_start; 366598849Sken } else 366698849Sken trace_buf->fill_len = 0; 3667153281Sscottl TI_UNLOCK(sc); 366898849Sken 366998849Sken break; 367098849Sken } 367198849Sken 367298849Sken /* 367398849Sken * For debugging, five ioctls are needed: 367498849Sken * ALT_ATTACH 367598849Sken * ALT_READ_TG_REG 367698849Sken * ALT_WRITE_TG_REG 367798849Sken * ALT_READ_TG_MEM 367898849Sken * ALT_WRITE_TG_MEM 367998849Sken */ 368098849Sken case ALT_ATTACH: 368198849Sken /* 3682131652Sbms * From what I can tell, Alteon's Solaris Tigon driver 368398849Sken * only has one character device, so you have to attach 368498849Sken * to the Tigon board you're interested in. This seems 368598849Sken * like a not-so-good way to do things, since unless you 368698849Sken * subsequently specify the unit number of the device 368798849Sken * you're interested in in every ioctl, you'll only be 368898849Sken * able to debug one board at a time. 368998849Sken */ 369098849Sken error = 0; 369198849Sken break; 369298849Sken case ALT_READ_TG_MEM: 369398849Sken case ALT_WRITE_TG_MEM: 369498849Sken { 369598849Sken struct tg_mem *mem_param; 369698849Sken u_int32_t sram_end, scratch_end; 369798849Sken 369898849Sken mem_param = (struct tg_mem *)addr; 369998849Sken 370098849Sken if (sc->ti_hwrev == TI_HWREV_TIGON) { 370198849Sken sram_end = TI_END_SRAM_I; 370298849Sken scratch_end = TI_END_SCRATCH_I; 370398849Sken } else { 370498849Sken sram_end = TI_END_SRAM_II; 370598849Sken scratch_end = TI_END_SCRATCH_II; 370698849Sken } 370798849Sken 370898849Sken /* 370998849Sken * For now, we'll only handle accessing regular SRAM, 371098849Sken * nothing else. 371198849Sken */ 3712153281Sscottl TI_LOCK(sc); 371398849Sken if ((mem_param->tgAddr >= TI_BEG_SRAM) 371498849Sken && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 371598849Sken /* 371698849Sken * In this instance, we always copy to/from user 371798849Sken * space, so the user space argument is set to 1. 371898849Sken */ 371998849Sken error = ti_copy_mem(sc, mem_param->tgAddr, 372098849Sken mem_param->len, 372198849Sken mem_param->userAddr, 1, 372298849Sken (cmd == ALT_READ_TG_MEM) ? 1 : 0); 372398849Sken } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 372498849Sken && (mem_param->tgAddr <= scratch_end)) { 372598849Sken error = ti_copy_scratch(sc, mem_param->tgAddr, 372698849Sken mem_param->len, 372798849Sken mem_param->userAddr, 1, 372898849Sken (cmd == ALT_READ_TG_MEM) ? 372998849Sken 1 : 0, TI_PROCESSOR_A); 373098849Sken } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 373198849Sken && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 373298849Sken if (sc->ti_hwrev == TI_HWREV_TIGON) { 3733150719Sjhb if_printf(sc->ti_ifp, 3734150719Sjhb "invalid memory range for Tigon I\n"); 373598849Sken error = EINVAL; 373698849Sken break; 373798849Sken } 3738131652Sbms error = ti_copy_scratch(sc, mem_param->tgAddr - 373998849Sken TI_SCRATCH_DEBUG_OFF, 374098849Sken mem_param->len, 374198849Sken mem_param->userAddr, 1, 374298849Sken (cmd == ALT_READ_TG_MEM) ? 374398849Sken 1 : 0, TI_PROCESSOR_B); 374498849Sken } else { 3745150719Sjhb if_printf(sc->ti_ifp, "memory address %#x len %d is " 3746150719Sjhb "out of supported range\n", 374798849Sken mem_param->tgAddr, mem_param->len); 374898849Sken error = EINVAL; 374998849Sken } 3750153281Sscottl TI_UNLOCK(sc); 375198849Sken 375298849Sken break; 375398849Sken } 375498849Sken case ALT_READ_TG_REG: 375598849Sken case ALT_WRITE_TG_REG: 375698849Sken { 375798849Sken struct tg_reg *regs; 375898849Sken u_int32_t tmpval; 375998849Sken 376098849Sken regs = (struct tg_reg *)addr; 376198849Sken 376298849Sken /* 376398849Sken * Make sure the address in question isn't out of range. 376498849Sken */ 376598849Sken if (regs->addr > TI_REG_MAX) { 376698849Sken error = EINVAL; 376798849Sken break; 376898849Sken } 3769153281Sscottl TI_LOCK(sc); 377098849Sken if (cmd == ALT_READ_TG_REG) { 377198849Sken bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 377298849Sken regs->addr, &tmpval, 1); 377398849Sken regs->data = ntohl(tmpval); 377498849Sken#if 0 377598849Sken if ((regs->addr == TI_CPU_STATE) 377698849Sken || (regs->addr == TI_CPU_CTL_B)) { 3777150719Sjhb if_printf(sc->ti_ifp, "register %#x = %#x\n", 3778150719Sjhb regs->addr, tmpval); 377998849Sken } 378098849Sken#endif 378198849Sken } else { 378298849Sken tmpval = htonl(regs->data); 378398849Sken bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 378498849Sken regs->addr, &tmpval, 1); 378598849Sken } 3786153281Sscottl TI_UNLOCK(sc); 378798849Sken 378898849Sken break; 378998849Sken } 379098849Sken default: 379198849Sken error = ENOTTY; 379298849Sken break; 379398849Sken } 3794131654Sbms return (error); 379598849Sken} 379698849Sken 3797102336Salfredstatic void 3798102336Salfredti_watchdog(ifp) 379945386Swpaul struct ifnet *ifp; 380045386Swpaul{ 380145386Swpaul struct ti_softc *sc; 380245386Swpaul 380345386Swpaul sc = ifp->if_softc; 380467087Swpaul TI_LOCK(sc); 380545386Swpaul 380698849Sken /* 380798849Sken * When we're debugging, the chip is often stopped for long periods 380898849Sken * of time, and that would normally cause the watchdog timer to fire. 380998849Sken * Since that impedes debugging, we don't want to do that. 381098849Sken */ 381198849Sken if (sc->ti_flags & TI_FLAG_DEBUGING) { 381298849Sken TI_UNLOCK(sc); 381398849Sken return; 381498849Sken } 381598849Sken 3816150719Sjhb if_printf(ifp, "watchdog timeout -- resetting\n"); 381745386Swpaul ti_stop(sc); 3818153770Syongari ti_init_locked(sc); 381945386Swpaul 382045386Swpaul ifp->if_oerrors++; 382167087Swpaul TI_UNLOCK(sc); 382245386Swpaul} 382345386Swpaul 382445386Swpaul/* 382545386Swpaul * Stop the adapter and free any mbufs allocated to the 382645386Swpaul * RX and TX lists. 382745386Swpaul */ 3828102336Salfredstatic void 3829102336Salfredti_stop(sc) 383045386Swpaul struct ti_softc *sc; 383145386Swpaul{ 383245386Swpaul struct ifnet *ifp; 383345386Swpaul struct ti_cmd_desc cmd; 383445386Swpaul 3835153770Syongari TI_LOCK_ASSERT(sc); 383667087Swpaul 3837147256Sbrooks ifp = sc->ti_ifp; 383845386Swpaul 383945386Swpaul /* Disable host interrupts. */ 384045386Swpaul CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 384145386Swpaul /* 384245386Swpaul * Tell firmware we're shutting down. 384345386Swpaul */ 384445386Swpaul TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 384545386Swpaul 384645386Swpaul /* Halt and reinitialize. */ 3847153770Syongari if (ti_chipinit(sc) != 0) 3848153770Syongari return; 3849153770Syongari ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3850153770Syongari if (ti_chipinit(sc) != 0) 3851153770Syongari return; 385245386Swpaul 385345386Swpaul /* Free the RX lists. */ 385445386Swpaul ti_free_rx_ring_std(sc); 385545386Swpaul 385645386Swpaul /* Free jumbo RX list. */ 385745386Swpaul ti_free_rx_ring_jumbo(sc); 385845386Swpaul 385945386Swpaul /* Free mini RX list. */ 386045386Swpaul ti_free_rx_ring_mini(sc); 386145386Swpaul 386245386Swpaul /* Free TX buffers. */ 386345386Swpaul ti_free_tx_ring(sc); 386445386Swpaul 386545386Swpaul sc->ti_ev_prodidx.ti_idx = 0; 386645386Swpaul sc->ti_return_prodidx.ti_idx = 0; 386745386Swpaul sc->ti_tx_considx.ti_idx = 0; 386845386Swpaul sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 386945386Swpaul 3870148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 387145386Swpaul} 387245386Swpaul 387345386Swpaul/* 387445386Swpaul * Stop all chip I/O so that the kernel's probe routines don't 387545386Swpaul * get confused by errant DMAs when rebooting. 387645386Swpaul */ 3877173839Syongaristatic int 3878102336Salfredti_shutdown(dev) 387949011Swpaul device_t dev; 388045386Swpaul{ 388145386Swpaul struct ti_softc *sc; 388245386Swpaul 388349011Swpaul sc = device_get_softc(dev); 388467087Swpaul TI_LOCK(sc); 388545386Swpaul ti_chipinit(sc); 388667087Swpaul TI_UNLOCK(sc); 3887173839Syongari 3888173839Syongari return (0); 388945386Swpaul} 3890