if_ti.c revision 131652
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 131652 2004-07-05 22:35:18Z bms $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100#include <net/if_types.h> 101#include <net/if_vlan_var.h> 102 103#include <net/bpf.h> 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/bus_memio.h> 112#include <machine/bus.h> 113#include <machine/resource.h> 114#include <sys/bus.h> 115#include <sys/rman.h> 116 117/* #define TI_PRIVATE_JUMBOS */ 118 119#if !defined(TI_PRIVATE_JUMBOS) 120#include <sys/sockio.h> 121#include <sys/uio.h> 122#include <sys/lock.h> 123#include <vm/vm_extern.h> 124#include <vm/pmap.h> 125#include <vm/vm_map.h> 126#include <vm/vm_map.h> 127#include <vm/vm_param.h> 128#include <vm/vm_pageout.h> 129#include <sys/vmmeter.h> 130#include <vm/vm_page.h> 131#include <vm/vm_object.h> 132#include <vm/vm_kern.h> 133#include <sys/proc.h> 134#include <sys/jumbo.h> 135#endif /* !TI_PRIVATE_JUMBOS */ 136 137#include <dev/pci/pcireg.h> 138#include <dev/pci/pcivar.h> 139 140#include <sys/tiio.h> 141#include <pci/if_tireg.h> 142#include <pci/ti_fw.h> 143#include <pci/ti_fw2.h> 144 145#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 146/* 147 * We can only turn on header splitting if we're using extended receive 148 * BDs. 149 */ 150#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 151#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 152#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 153 154struct ti_softc *tis[8]; 155 156typedef enum { 157 TI_SWAP_HTON, 158 TI_SWAP_NTOH 159} ti_swap_type; 160 161 162/* 163 * Various supported device vendors/types and their names. 164 */ 165 166static struct ti_type ti_devs[] = { 167 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 170 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 171 { TC_VENDORID, TC_DEVICEID_3C985, 172 "3Com 3c985-SX Gigabit Ethernet" }, 173 { NG_VENDORID, NG_DEVICEID_GA620, 174 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 175 { NG_VENDORID, NG_DEVICEID_GA620T, 176 "Netgear GA620 1000baseT Gigabit Ethernet" }, 177 { SGI_VENDORID, SGI_DEVICEID_TIGON, 178 "Silicon Graphics Gigabit Ethernet" }, 179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 180 "Farallon PN9000SX Gigabit Ethernet" }, 181 { 0, 0, NULL } 182}; 183 184 185static d_open_t ti_open; 186static d_close_t ti_close; 187static d_ioctl_t ti_ioctl2; 188 189static struct cdevsw ti_cdevsw = { 190 .d_version = D_VERSION, 191 .d_flags = D_NEEDGIANT, 192 .d_open = ti_open, 193 .d_close = ti_close, 194 .d_ioctl = ti_ioctl2, 195 .d_name = "ti", 196}; 197 198static int ti_probe (device_t); 199static int ti_attach (device_t); 200static int ti_detach (device_t); 201static void ti_txeof (struct ti_softc *); 202static void ti_rxeof (struct ti_softc *); 203 204static void ti_stats_update (struct ti_softc *); 205static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 206 207static void ti_intr (void *); 208static void ti_start (struct ifnet *); 209static int ti_ioctl (struct ifnet *, u_long, caddr_t); 210static void ti_init (void *); 211static void ti_init2 (struct ti_softc *); 212static void ti_stop (struct ti_softc *); 213static void ti_watchdog (struct ifnet *); 214static void ti_shutdown (device_t); 215static int ti_ifmedia_upd (struct ifnet *); 216static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 219static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 220static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 221 222static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 223static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 224static void ti_setmulti (struct ti_softc *); 225 226static void ti_mem (struct ti_softc *, u_int32_t, 227 u_int32_t, caddr_t); 228static int ti_copy_mem (struct ti_softc *, u_int32_t, 229 u_int32_t, caddr_t, int, int); 230static int ti_copy_scratch (struct ti_softc *, u_int32_t, 231 u_int32_t, caddr_t, int, int, int); 232static int ti_bcopy_swap (const void *, void *, size_t, 233 ti_swap_type); 234static void ti_loadfw (struct ti_softc *); 235static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 236static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 237 caddr_t, int); 238static void ti_handle_events (struct ti_softc *); 239#ifdef TI_PRIVATE_JUMBOS 240static int ti_alloc_jumbo_mem (struct ti_softc *); 241static void *ti_jalloc (struct ti_softc *); 242static void ti_jfree (void *, void *); 243#endif /* TI_PRIVATE_JUMBOS */ 244static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 245static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 246static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 247static int ti_init_rx_ring_std (struct ti_softc *); 248static void ti_free_rx_ring_std (struct ti_softc *); 249static int ti_init_rx_ring_jumbo (struct ti_softc *); 250static void ti_free_rx_ring_jumbo (struct ti_softc *); 251static int ti_init_rx_ring_mini (struct ti_softc *); 252static void ti_free_rx_ring_mini (struct ti_softc *); 253static void ti_free_tx_ring (struct ti_softc *); 254static int ti_init_tx_ring (struct ti_softc *); 255 256static int ti_64bitslot_war (struct ti_softc *); 257static int ti_chipinit (struct ti_softc *); 258static int ti_gibinit (struct ti_softc *); 259 260#ifdef TI_JUMBO_HDRSPLIT 261static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 262 int pkt_len, int idx); 263#endif /* TI_JUMBO_HDRSPLIT */ 264 265static device_method_t ti_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, ti_probe), 268 DEVMETHOD(device_attach, ti_attach), 269 DEVMETHOD(device_detach, ti_detach), 270 DEVMETHOD(device_shutdown, ti_shutdown), 271 { 0, 0 } 272}; 273 274static driver_t ti_driver = { 275 "ti", 276 ti_methods, 277 sizeof(struct ti_softc) 278}; 279 280static devclass_t ti_devclass; 281 282DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 283MODULE_DEPEND(ti, pci, 1, 1, 1); 284MODULE_DEPEND(ti, ether, 1, 1, 1); 285 286/* 287 * Send an instruction or address to the EEPROM, check for ACK. 288 */ 289static u_int32_t ti_eeprom_putbyte(sc, byte) 290 struct ti_softc *sc; 291 int byte; 292{ 293 register int i, ack = 0; 294 295 /* 296 * Make sure we're in TX mode. 297 */ 298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 299 300 /* 301 * Feed in each bit and stobe the clock. 302 */ 303 for (i = 0x80; i; i >>= 1) { 304 if (byte & i) { 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 306 } else { 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 308 } 309 DELAY(1); 310 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 311 DELAY(1); 312 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 313 } 314 315 /* 316 * Turn off TX mode. 317 */ 318 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 319 320 /* 321 * Check for ack. 322 */ 323 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 324 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 327 return(ack); 328} 329 330/* 331 * Read a byte of data stored in the EEPROM at address 'addr.' 332 * We have to send two address bytes since the EEPROM can hold 333 * more than 256 bytes of data. 334 */ 335static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 336 struct ti_softc *sc; 337 int addr; 338 u_int8_t *dest; 339{ 340 register int i; 341 u_int8_t byte = 0; 342 343 EEPROM_START; 344 345 /* 346 * Send write control code to EEPROM. 347 */ 348 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 349 printf("ti%d: failed to send write command, status: %x\n", 350 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return(1); 352 } 353 354 /* 355 * Send first byte of address of byte we want to read. 356 */ 357 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 358 printf("ti%d: failed to send address, status: %x\n", 359 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 360 return(1); 361 } 362 /* 363 * Send second byte address of byte we want to read. 364 */ 365 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 366 printf("ti%d: failed to send address, status: %x\n", 367 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 368 return(1); 369 } 370 371 EEPROM_STOP; 372 EEPROM_START; 373 /* 374 * Send read control code to EEPROM. 375 */ 376 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 377 printf("ti%d: failed to send read command, status: %x\n", 378 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 379 return(1); 380 } 381 382 /* 383 * Start reading bits from EEPROM. 384 */ 385 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 386 for (i = 0x80; i; i >>= 1) { 387 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 388 DELAY(1); 389 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 390 byte |= i; 391 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 392 DELAY(1); 393 } 394 395 EEPROM_STOP; 396 397 /* 398 * No ACK generated for read, so just return byte. 399 */ 400 401 *dest = byte; 402 403 return(0); 404} 405 406/* 407 * Read a sequence of bytes from the EEPROM. 408 */ 409static int 410ti_read_eeprom(sc, dest, off, cnt) 411 struct ti_softc *sc; 412 caddr_t dest; 413 int off; 414 int cnt; 415{ 416 int err = 0, i; 417 u_int8_t byte = 0; 418 419 for (i = 0; i < cnt; i++) { 420 err = ti_eeprom_getbyte(sc, off + i, &byte); 421 if (err) 422 break; 423 *(dest + i) = byte; 424 } 425 426 return(err ? 1 : 0); 427} 428 429/* 430 * NIC memory access function. Can be used to either clear a section 431 * of NIC local memory or (if buf is non-NULL) copy data into it. 432 */ 433static void 434ti_mem(sc, addr, len, buf) 435 struct ti_softc *sc; 436 u_int32_t addr, len; 437 caddr_t buf; 438{ 439 int segptr, segsize, cnt; 440 caddr_t ti_winbase, ptr; 441 442 segptr = addr; 443 cnt = len; 444 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 445 ptr = buf; 446 447 while(cnt) { 448 if (cnt < TI_WINLEN) 449 segsize = cnt; 450 else 451 segsize = TI_WINLEN - (segptr % TI_WINLEN); 452 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 453 if (buf == NULL) 454 bzero((char *)ti_winbase + (segptr & 455 (TI_WINLEN - 1)), segsize); 456 else { 457 bcopy((char *)ptr, (char *)ti_winbase + 458 (segptr & (TI_WINLEN - 1)), segsize); 459 ptr += segsize; 460 } 461 segptr += segsize; 462 cnt -= segsize; 463 } 464 465 return; 466} 467 468static int 469ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 470 struct ti_softc *sc; 471 u_int32_t tigon_addr, len; 472 caddr_t buf; 473 int useraddr, readdata; 474{ 475 int segptr, segsize, cnt; 476 caddr_t ptr; 477 u_int32_t origwin; 478 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 479 int resid, segresid; 480 int first_pass; 481 482 /* 483 * At the moment, we don't handle non-aligned cases, we just bail. 484 * If this proves to be a problem, it will be fixed. 485 */ 486 if ((readdata == 0) 487 && (tigon_addr & 0x3)) { 488 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 489 "word-aligned\n", sc->ti_unit, tigon_addr); 490 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 491 "supported\n", sc->ti_unit); 492 return(EINVAL); 493 } 494 495 segptr = tigon_addr & ~0x3; 496 segresid = tigon_addr - segptr; 497 498 /* 499 * This is the non-aligned amount left over that we'll need to 500 * copy. 501 */ 502 resid = len & 0x3; 503 504 /* Add in the left over amount at the front of the buffer */ 505 resid += segresid; 506 507 cnt = len & ~0x3; 508 /* 509 * If resid + segresid is >= 4, add multiples of 4 to the count and 510 * decrease the residual by that much. 511 */ 512 cnt += resid & ~0x3; 513 resid -= resid & ~0x3; 514 515 ptr = buf; 516 517 first_pass = 1; 518 519 /* 520 * Make sure we aren't interrupted while we're changing the window 521 * pointer. 522 */ 523 TI_LOCK(sc); 524 525 /* 526 * Save the old window base value. 527 */ 528 origwin = CSR_READ_4(sc, TI_WINBASE); 529 530 while(cnt) { 531 bus_size_t ti_offset; 532 533 if (cnt < TI_WINLEN) 534 segsize = cnt; 535 else 536 segsize = TI_WINLEN - (segptr % TI_WINLEN); 537 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 538 539 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 540 541 if (readdata) { 542 543 bus_space_read_region_4(sc->ti_btag, 544 sc->ti_bhandle, ti_offset, 545 (u_int32_t *)tmparray, 546 segsize >> 2); 547 if (useraddr) { 548 /* 549 * Yeah, this is a little on the kludgy 550 * side, but at least this code is only 551 * used for debugging. 552 */ 553 ti_bcopy_swap(tmparray, tmparray2, segsize, 554 TI_SWAP_NTOH); 555 556 if (first_pass) { 557 copyout(&tmparray2[segresid], ptr, 558 segsize - segresid); 559 first_pass = 0; 560 } else 561 copyout(tmparray2, ptr, segsize); 562 } else { 563 if (first_pass) { 564 565 ti_bcopy_swap(tmparray, tmparray2, 566 segsize, TI_SWAP_NTOH); 567 bcopy(&tmparray2[segresid], ptr, 568 segsize - segresid); 569 first_pass = 0; 570 } else 571 ti_bcopy_swap(tmparray, ptr, segsize, 572 TI_SWAP_NTOH); 573 } 574 575 } else { 576 if (useraddr) { 577 copyin(ptr, tmparray2, segsize); 578 ti_bcopy_swap(tmparray2, tmparray, segsize, 579 TI_SWAP_HTON); 580 } else 581 ti_bcopy_swap(ptr, tmparray, segsize, 582 TI_SWAP_HTON); 583 584 bus_space_write_region_4(sc->ti_btag, 585 sc->ti_bhandle, ti_offset, 586 (u_int32_t *)tmparray, 587 segsize >> 2); 588 } 589 segptr += segsize; 590 ptr += segsize; 591 cnt -= segsize; 592 } 593 594 /* 595 * Handle leftover, non-word-aligned bytes. 596 */ 597 if (resid != 0) { 598 u_int32_t tmpval, tmpval2; 599 bus_size_t ti_offset; 600 601 /* 602 * Set the segment pointer. 603 */ 604 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 605 606 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 607 608 /* 609 * First, grab whatever is in our source/destination. 610 * We'll obviously need this for reads, but also for 611 * writes, since we'll be doing read/modify/write. 612 */ 613 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 614 ti_offset, &tmpval, 1); 615 616 /* 617 * Next, translate this from little-endian to big-endian 618 * (at least on i386 boxes). 619 */ 620 tmpval2 = ntohl(tmpval); 621 622 if (readdata) { 623 /* 624 * If we're reading, just copy the leftover number 625 * of bytes from the host byte order buffer to 626 * the user's buffer. 627 */ 628 if (useraddr) 629 copyout(&tmpval2, ptr, resid); 630 else 631 bcopy(&tmpval2, ptr, resid); 632 } else { 633 /* 634 * If we're writing, first copy the bytes to be 635 * written into the network byte order buffer, 636 * leaving the rest of the buffer with whatever was 637 * originally in there. Then, swap the bytes 638 * around into host order and write them out. 639 * 640 * XXX KDM the read side of this has been verified 641 * to work, but the write side of it has not been 642 * verified. So user beware. 643 */ 644 if (useraddr) 645 copyin(ptr, &tmpval2, resid); 646 else 647 bcopy(ptr, &tmpval2, resid); 648 649 tmpval = htonl(tmpval2); 650 651 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 652 ti_offset, &tmpval, 1); 653 } 654 } 655 656 CSR_WRITE_4(sc, TI_WINBASE, origwin); 657 658 TI_UNLOCK(sc); 659 660 return(0); 661} 662 663static int 664ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 665 struct ti_softc *sc; 666 u_int32_t tigon_addr, len; 667 caddr_t buf; 668 int useraddr, readdata; 669 int cpu; 670{ 671 u_int32_t segptr; 672 int cnt; 673 u_int32_t tmpval, tmpval2; 674 caddr_t ptr; 675 676 /* 677 * At the moment, we don't handle non-aligned cases, we just bail. 678 * If this proves to be a problem, it will be fixed. 679 */ 680 if (tigon_addr & 0x3) { 681 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 682 "word-aligned\n", sc->ti_unit, tigon_addr); 683 return(EINVAL); 684 } 685 686 if (len & 0x3) { 687 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 688 "word-aligned\n", sc->ti_unit, len); 689 return(EINVAL); 690 } 691 692 segptr = tigon_addr; 693 cnt = len; 694 ptr = buf; 695 696 TI_LOCK(sc); 697 698 while (cnt) { 699 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 700 701 if (readdata) { 702 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 703 704 tmpval = ntohl(tmpval2); 705 706 /* 707 * Note: I've used this debugging interface 708 * extensively with Alteon's 12.3.15 firmware, 709 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 710 * 711 * When you compile the firmware without 712 * optimization, which is necessary sometimes in 713 * order to properly step through it, you sometimes 714 * read out a bogus value of 0xc0017c instead of 715 * whatever was supposed to be in that scratchpad 716 * location. That value is on the stack somewhere, 717 * but I've never been able to figure out what was 718 * causing the problem. 719 * 720 * The address seems to pop up in random places, 721 * often not in the same place on two subsequent 722 * reads. 723 * 724 * In any case, the underlying data doesn't seem 725 * to be affected, just the value read out. 726 * 727 * KDM, 3/7/2000 728 */ 729 730 if (tmpval2 == 0xc0017c) 731 printf("ti%d: found 0xc0017c at %#x " 732 "(tmpval2)\n", sc->ti_unit, segptr); 733 734 if (tmpval == 0xc0017c) 735 printf("ti%d: found 0xc0017c at %#x " 736 "(tmpval)\n", sc->ti_unit, segptr); 737 738 if (useraddr) 739 copyout(&tmpval, ptr, 4); 740 else 741 bcopy(&tmpval, ptr, 4); 742 } else { 743 if (useraddr) 744 copyin(ptr, &tmpval2, 4); 745 else 746 bcopy(ptr, &tmpval2, 4); 747 748 tmpval = htonl(tmpval2); 749 750 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 751 } 752 753 cnt -= 4; 754 segptr += 4; 755 ptr += 4; 756 } 757 758 TI_UNLOCK(sc); 759 760 return(0); 761} 762 763static int 764ti_bcopy_swap(src, dst, len, swap_type) 765 const void *src; 766 void *dst; 767 size_t len; 768 ti_swap_type swap_type; 769{ 770 const u_int8_t *tmpsrc; 771 u_int8_t *tmpdst; 772 size_t tmplen; 773 774 if (len & 0x3) { 775 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 776 len); 777 return(-1); 778 } 779 780 tmpsrc = src; 781 tmpdst = dst; 782 tmplen = len; 783 784 while (tmplen) { 785 if (swap_type == TI_SWAP_NTOH) 786 *(u_int32_t *)tmpdst = 787 ntohl(*(const u_int32_t *)tmpsrc); 788 else 789 *(u_int32_t *)tmpdst = 790 htonl(*(const u_int32_t *)tmpsrc); 791 792 tmpsrc += 4; 793 tmpdst += 4; 794 tmplen -= 4; 795 } 796 797 return(0); 798} 799 800/* 801 * Load firmware image into the NIC. Check that the firmware revision 802 * is acceptable and see if we want the firmware for the Tigon 1 or 803 * Tigon 2. 804 */ 805static void 806ti_loadfw(sc) 807 struct ti_softc *sc; 808{ 809 switch(sc->ti_hwrev) { 810 case TI_HWREV_TIGON: 811 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 812 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 813 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 814 printf("ti%d: firmware revision mismatch; want " 815 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 816 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 817 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 818 tigonFwReleaseMinor, tigonFwReleaseFix); 819 return; 820 } 821 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 822 (caddr_t)tigonFwText); 823 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 824 (caddr_t)tigonFwData); 825 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 826 (caddr_t)tigonFwRodata); 827 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 828 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 829 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 830 break; 831 case TI_HWREV_TIGON_II: 832 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 833 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 834 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 835 printf("ti%d: firmware revision mismatch; want " 836 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 837 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 838 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 839 tigon2FwReleaseMinor, tigon2FwReleaseFix); 840 return; 841 } 842 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 843 (caddr_t)tigon2FwText); 844 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 845 (caddr_t)tigon2FwData); 846 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 847 (caddr_t)tigon2FwRodata); 848 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 849 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 850 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 851 break; 852 default: 853 printf("ti%d: can't load firmware: unknown hardware rev\n", 854 sc->ti_unit); 855 break; 856 } 857 858 return; 859} 860 861/* 862 * Send the NIC a command via the command ring. 863 */ 864static void 865ti_cmd(sc, cmd) 866 struct ti_softc *sc; 867 struct ti_cmd_desc *cmd; 868{ 869 u_int32_t index; 870 871 if (sc->ti_rdata->ti_cmd_ring == NULL) 872 return; 873 874 index = sc->ti_cmd_saved_prodidx; 875 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 876 TI_INC(index, TI_CMD_RING_CNT); 877 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 878 sc->ti_cmd_saved_prodidx = index; 879 880 return; 881} 882 883/* 884 * Send the NIC an extended command. The 'len' parameter specifies the 885 * number of command slots to include after the initial command. 886 */ 887static void 888ti_cmd_ext(sc, cmd, arg, len) 889 struct ti_softc *sc; 890 struct ti_cmd_desc *cmd; 891 caddr_t arg; 892 int len; 893{ 894 u_int32_t index; 895 register int i; 896 897 if (sc->ti_rdata->ti_cmd_ring == NULL) 898 return; 899 900 index = sc->ti_cmd_saved_prodidx; 901 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 902 TI_INC(index, TI_CMD_RING_CNT); 903 for (i = 0; i < len; i++) { 904 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 905 *(u_int32_t *)(&arg[i * 4])); 906 TI_INC(index, TI_CMD_RING_CNT); 907 } 908 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 909 sc->ti_cmd_saved_prodidx = index; 910 911 return; 912} 913 914/* 915 * Handle events that have triggered interrupts. 916 */ 917static void 918ti_handle_events(sc) 919 struct ti_softc *sc; 920{ 921 struct ti_event_desc *e; 922 923 if (sc->ti_rdata->ti_event_ring == NULL) 924 return; 925 926 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 927 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 928 switch(e->ti_event) { 929 case TI_EV_LINKSTAT_CHANGED: 930 sc->ti_linkstat = e->ti_code; 931 if (e->ti_code == TI_EV_CODE_LINK_UP) 932 printf("ti%d: 10/100 link up\n", sc->ti_unit); 933 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 934 printf("ti%d: gigabit link up\n", sc->ti_unit); 935 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 936 printf("ti%d: link down\n", sc->ti_unit); 937 break; 938 case TI_EV_ERROR: 939 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 940 printf("ti%d: invalid command\n", sc->ti_unit); 941 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 942 printf("ti%d: unknown command\n", sc->ti_unit); 943 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 944 printf("ti%d: bad config data\n", sc->ti_unit); 945 break; 946 case TI_EV_FIRMWARE_UP: 947 ti_init2(sc); 948 break; 949 case TI_EV_STATS_UPDATED: 950 ti_stats_update(sc); 951 break; 952 case TI_EV_RESET_JUMBO_RING: 953 case TI_EV_MCAST_UPDATED: 954 /* Who cares. */ 955 break; 956 default: 957 printf("ti%d: unknown event: %d\n", 958 sc->ti_unit, e->ti_event); 959 break; 960 } 961 /* Advance the consumer index. */ 962 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 963 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 964 } 965 966 return; 967} 968 969#ifdef TI_PRIVATE_JUMBOS 970 971/* 972 * Memory management for the jumbo receive ring is a pain in the 973 * butt. We need to allocate at least 9018 bytes of space per frame, 974 * _and_ it has to be contiguous (unless you use the extended 975 * jumbo descriptor format). Using malloc() all the time won't 976 * work: malloc() allocates memory in powers of two, which means we 977 * would end up wasting a considerable amount of space by allocating 978 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 979 * to do our own memory management. 980 * 981 * The driver needs to allocate a contiguous chunk of memory at boot 982 * time. We then chop this up ourselves into 9K pieces and use them 983 * as external mbuf storage. 984 * 985 * One issue here is how much memory to allocate. The jumbo ring has 986 * 256 slots in it, but at 9K per slot than can consume over 2MB of 987 * RAM. This is a bit much, especially considering we also need 988 * RAM for the standard ring and mini ring (on the Tigon 2). To 989 * save space, we only actually allocate enough memory for 64 slots 990 * by default, which works out to between 500 and 600K. This can 991 * be tuned by changing a #define in if_tireg.h. 992 */ 993 994static int 995ti_alloc_jumbo_mem(sc) 996 struct ti_softc *sc; 997{ 998 caddr_t ptr; 999 register int i; 1000 struct ti_jpool_entry *entry; 1001 1002 /* Grab a big chunk o' storage. */ 1003 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1004 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1005 1006 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1007 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1008 return(ENOBUFS); 1009 } 1010 1011 SLIST_INIT(&sc->ti_jfree_listhead); 1012 SLIST_INIT(&sc->ti_jinuse_listhead); 1013 1014 /* 1015 * Now divide it up into 9K pieces and save the addresses 1016 * in an array. 1017 */ 1018 ptr = sc->ti_cdata.ti_jumbo_buf; 1019 for (i = 0; i < TI_JSLOTS; i++) { 1020 sc->ti_cdata.ti_jslots[i] = ptr; 1021 ptr += TI_JLEN; 1022 entry = malloc(sizeof(struct ti_jpool_entry), 1023 M_DEVBUF, M_NOWAIT); 1024 if (entry == NULL) { 1025 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1026 M_DEVBUF); 1027 sc->ti_cdata.ti_jumbo_buf = NULL; 1028 printf("ti%d: no memory for jumbo " 1029 "buffer queue!\n", sc->ti_unit); 1030 return(ENOBUFS); 1031 } 1032 entry->slot = i; 1033 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1034 } 1035 1036 return(0); 1037} 1038 1039/* 1040 * Allocate a jumbo buffer. 1041 */ 1042static void *ti_jalloc(sc) 1043 struct ti_softc *sc; 1044{ 1045 struct ti_jpool_entry *entry; 1046 1047 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1048 1049 if (entry == NULL) { 1050 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1051 return(NULL); 1052 } 1053 1054 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1055 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1056 return(sc->ti_cdata.ti_jslots[entry->slot]); 1057} 1058 1059/* 1060 * Release a jumbo buffer. 1061 */ 1062static void 1063ti_jfree(buf, args) 1064 void *buf; 1065 void *args; 1066{ 1067 struct ti_softc *sc; 1068 int i; 1069 struct ti_jpool_entry *entry; 1070 1071 /* Extract the softc struct pointer. */ 1072 sc = (struct ti_softc *)args; 1073 1074 if (sc == NULL) 1075 panic("ti_jfree: didn't get softc pointer!"); 1076 1077 /* calculate the slot this buffer belongs to */ 1078 i = ((vm_offset_t)buf 1079 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1080 1081 if ((i < 0) || (i >= TI_JSLOTS)) 1082 panic("ti_jfree: asked to free buffer that we don't manage!"); 1083 1084 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1085 if (entry == NULL) 1086 panic("ti_jfree: buffer not in use!"); 1087 entry->slot = i; 1088 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1089 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1090 1091 return; 1092} 1093 1094#endif /* TI_PRIVATE_JUMBOS */ 1095 1096/* 1097 * Intialize a standard receive ring descriptor. 1098 */ 1099static int 1100ti_newbuf_std(sc, i, m) 1101 struct ti_softc *sc; 1102 int i; 1103 struct mbuf *m; 1104{ 1105 struct mbuf *m_new = NULL; 1106 struct ti_rx_desc *r; 1107 1108 if (m == NULL) { 1109 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1110 if (m_new == NULL) 1111 return(ENOBUFS); 1112 1113 MCLGET(m_new, M_DONTWAIT); 1114 if (!(m_new->m_flags & M_EXT)) { 1115 m_freem(m_new); 1116 return(ENOBUFS); 1117 } 1118 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1119 } else { 1120 m_new = m; 1121 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1122 m_new->m_data = m_new->m_ext.ext_buf; 1123 } 1124 1125 m_adj(m_new, ETHER_ALIGN); 1126 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1127 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1128 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1129 r->ti_type = TI_BDTYPE_RECV_BD; 1130 r->ti_flags = 0; 1131 if (sc->arpcom.ac_if.if_hwassist) 1132 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1133 r->ti_len = m_new->m_len; 1134 r->ti_idx = i; 1135 1136 return(0); 1137} 1138 1139/* 1140 * Intialize a mini receive ring descriptor. This only applies to 1141 * the Tigon 2. 1142 */ 1143static int 1144ti_newbuf_mini(sc, i, m) 1145 struct ti_softc *sc; 1146 int i; 1147 struct mbuf *m; 1148{ 1149 struct mbuf *m_new = NULL; 1150 struct ti_rx_desc *r; 1151 1152 if (m == NULL) { 1153 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1154 if (m_new == NULL) { 1155 return(ENOBUFS); 1156 } 1157 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1158 } else { 1159 m_new = m; 1160 m_new->m_data = m_new->m_pktdat; 1161 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1162 } 1163 1164 m_adj(m_new, ETHER_ALIGN); 1165 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1166 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1167 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1168 r->ti_type = TI_BDTYPE_RECV_BD; 1169 r->ti_flags = TI_BDFLAG_MINI_RING; 1170 if (sc->arpcom.ac_if.if_hwassist) 1171 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1172 r->ti_len = m_new->m_len; 1173 r->ti_idx = i; 1174 1175 return(0); 1176} 1177 1178#ifdef TI_PRIVATE_JUMBOS 1179 1180/* 1181 * Initialize a jumbo receive ring descriptor. This allocates 1182 * a jumbo buffer from the pool managed internally by the driver. 1183 */ 1184static int 1185ti_newbuf_jumbo(sc, i, m) 1186 struct ti_softc *sc; 1187 int i; 1188 struct mbuf *m; 1189{ 1190 struct mbuf *m_new = NULL; 1191 struct ti_rx_desc *r; 1192 1193 if (m == NULL) { 1194 caddr_t *buf = NULL; 1195 1196 /* Allocate the mbuf. */ 1197 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1198 if (m_new == NULL) { 1199 return(ENOBUFS); 1200 } 1201 1202 /* Allocate the jumbo buffer */ 1203 buf = ti_jalloc(sc); 1204 if (buf == NULL) { 1205 m_freem(m_new); 1206 printf("ti%d: jumbo allocation failed " 1207 "-- packet dropped!\n", sc->ti_unit); 1208 return(ENOBUFS); 1209 } 1210 1211 /* Attach the buffer to the mbuf. */ 1212 m_new->m_data = (void *) buf; 1213 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1214 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1215 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1216 } else { 1217 m_new = m; 1218 m_new->m_data = m_new->m_ext.ext_buf; 1219 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1220 } 1221 1222 m_adj(m_new, ETHER_ALIGN); 1223 /* Set up the descriptor. */ 1224 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1225 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1226 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1227 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1228 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1229 if (sc->arpcom.ac_if.if_hwassist) 1230 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1231 r->ti_len = m_new->m_len; 1232 r->ti_idx = i; 1233 1234 return(0); 1235} 1236 1237#else 1238#include <vm/vm_page.h> 1239 1240#if (PAGE_SIZE == 4096) 1241#define NPAYLOAD 2 1242#else 1243#define NPAYLOAD 1 1244#endif 1245 1246#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1247#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1248#define NFS_HDR_LEN (UDP_HDR_LEN) 1249static int HDR_LEN = TCP_HDR_LEN; 1250 1251 1252 /* 1253 * Initialize a jumbo receive ring descriptor. This allocates 1254 * a jumbo buffer from the pool managed internally by the driver. 1255 */ 1256static int 1257ti_newbuf_jumbo(sc, idx, m_old) 1258 struct ti_softc *sc; 1259 int idx; 1260 struct mbuf *m_old; 1261{ 1262 struct mbuf *cur, *m_new = NULL; 1263 struct mbuf *m[3] = {NULL, NULL, NULL}; 1264 struct ti_rx_desc_ext *r; 1265 vm_page_t frame; 1266 /* 1 extra buf to make nobufs easy*/ 1267 caddr_t buf[3] = {NULL, NULL, NULL}; 1268 int i; 1269 1270 if (m_old != NULL) { 1271 m_new = m_old; 1272 cur = m_old->m_next; 1273 for (i = 0; i <= NPAYLOAD; i++){ 1274 m[i] = cur; 1275 cur = cur->m_next; 1276 } 1277 } else { 1278 /* Allocate the mbufs. */ 1279 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1280 if (m_new == NULL) { 1281 printf("ti%d: mbuf allocation failed " 1282 "-- packet dropped!\n", sc->ti_unit); 1283 goto nobufs; 1284 } 1285 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1286 if (m[NPAYLOAD] == NULL) { 1287 printf("ti%d: cluster mbuf allocation failed " 1288 "-- packet dropped!\n", sc->ti_unit); 1289 goto nobufs; 1290 } 1291 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1292 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1293 printf("ti%d: mbuf allocation failed " 1294 "-- packet dropped!\n", sc->ti_unit); 1295 goto nobufs; 1296 } 1297 m[NPAYLOAD]->m_len = MCLBYTES; 1298 1299 for (i = 0; i < NPAYLOAD; i++){ 1300 MGET(m[i], M_DONTWAIT, MT_DATA); 1301 if (m[i] == NULL) { 1302 printf("ti%d: mbuf allocation failed " 1303 "-- packet dropped!\n", sc->ti_unit); 1304 goto nobufs; 1305 } 1306 if (!(frame = jumbo_pg_alloc())){ 1307 printf("ti%d: buffer allocation failed " 1308 "-- packet dropped!\n", sc->ti_unit); 1309 printf(" index %d page %d\n", idx, i); 1310 goto nobufs; 1311 } 1312 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1313 } 1314 for (i = 0; i < NPAYLOAD; i++){ 1315 /* Attach the buffer to the mbuf. */ 1316 m[i]->m_data = (void *)buf[i]; 1317 m[i]->m_len = PAGE_SIZE; 1318 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1319 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1320 m[i]->m_next = m[i+1]; 1321 } 1322 /* link the buffers to the header */ 1323 m_new->m_next = m[0]; 1324 m_new->m_data += ETHER_ALIGN; 1325 if (sc->ti_hdrsplit) 1326 m_new->m_len = MHLEN - ETHER_ALIGN; 1327 else 1328 m_new->m_len = HDR_LEN; 1329 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1330 } 1331 1332 /* Set up the descriptor. */ 1333 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1334 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1335 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1336 r->ti_len0 = m_new->m_len; 1337 1338 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1339 r->ti_len1 = PAGE_SIZE; 1340 1341 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1342 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1343 1344 if (PAGE_SIZE == 4096) { 1345 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1346 r->ti_len3 = MCLBYTES; 1347 } else { 1348 r->ti_len3 = 0; 1349 } 1350 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1351 1352 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1353 1354 if (sc->arpcom.ac_if.if_hwassist) 1355 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1356 1357 r->ti_idx = idx; 1358 1359 return(0); 1360 1361 nobufs: 1362 1363 /* 1364 * Warning! : 1365 * This can only be called before the mbufs are strung together. 1366 * If the mbufs are strung together, m_freem() will free the chain, 1367 * so that the later mbufs will be freed multiple times. 1368 */ 1369 if (m_new) 1370 m_freem(m_new); 1371 1372 for(i = 0; i < 3; i++){ 1373 if (m[i]) 1374 m_freem(m[i]); 1375 if (buf[i]) 1376 jumbo_pg_free((vm_offset_t)buf[i]); 1377 } 1378 return ENOBUFS; 1379} 1380#endif 1381 1382 1383 1384/* 1385 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1386 * that's 1MB or memory, which is a lot. For now, we fill only the first 1387 * 256 ring entries and hope that our CPU is fast enough to keep up with 1388 * the NIC. 1389 */ 1390static int 1391ti_init_rx_ring_std(sc) 1392 struct ti_softc *sc; 1393{ 1394 register int i; 1395 struct ti_cmd_desc cmd; 1396 1397 for (i = 0; i < TI_SSLOTS; i++) { 1398 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1399 return(ENOBUFS); 1400 }; 1401 1402 TI_UPDATE_STDPROD(sc, i - 1); 1403 sc->ti_std = i - 1; 1404 1405 return(0); 1406} 1407 1408static void 1409ti_free_rx_ring_std(sc) 1410 struct ti_softc *sc; 1411{ 1412 register int i; 1413 1414 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1415 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1416 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1417 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1418 } 1419 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1420 sizeof(struct ti_rx_desc)); 1421 } 1422 1423 return; 1424} 1425 1426static int 1427ti_init_rx_ring_jumbo(sc) 1428 struct ti_softc *sc; 1429{ 1430 register int i; 1431 struct ti_cmd_desc cmd; 1432 1433 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1434 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1435 return(ENOBUFS); 1436 }; 1437 1438 TI_UPDATE_JUMBOPROD(sc, i - 1); 1439 sc->ti_jumbo = i - 1; 1440 1441 return(0); 1442} 1443 1444static void 1445ti_free_rx_ring_jumbo(sc) 1446 struct ti_softc *sc; 1447{ 1448 register int i; 1449 1450 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1451 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1452 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1453 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1454 } 1455 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1456 sizeof(struct ti_rx_desc)); 1457 } 1458 1459 return; 1460} 1461 1462static int 1463ti_init_rx_ring_mini(sc) 1464 struct ti_softc *sc; 1465{ 1466 register int i; 1467 1468 for (i = 0; i < TI_MSLOTS; i++) { 1469 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1470 return(ENOBUFS); 1471 }; 1472 1473 TI_UPDATE_MINIPROD(sc, i - 1); 1474 sc->ti_mini = i - 1; 1475 1476 return(0); 1477} 1478 1479static void 1480ti_free_rx_ring_mini(sc) 1481 struct ti_softc *sc; 1482{ 1483 register int i; 1484 1485 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1486 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1487 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1488 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1489 } 1490 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1491 sizeof(struct ti_rx_desc)); 1492 } 1493 1494 return; 1495} 1496 1497static void 1498ti_free_tx_ring(sc) 1499 struct ti_softc *sc; 1500{ 1501 register int i; 1502 1503 if (sc->ti_rdata->ti_tx_ring == NULL) 1504 return; 1505 1506 for (i = 0; i < TI_TX_RING_CNT; i++) { 1507 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1508 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1509 sc->ti_cdata.ti_tx_chain[i] = NULL; 1510 } 1511 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1512 sizeof(struct ti_tx_desc)); 1513 } 1514 1515 return; 1516} 1517 1518static int 1519ti_init_tx_ring(sc) 1520 struct ti_softc *sc; 1521{ 1522 sc->ti_txcnt = 0; 1523 sc->ti_tx_saved_considx = 0; 1524 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1525 return(0); 1526} 1527 1528/* 1529 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1530 * but we have to support the old way too so that Tigon 1 cards will 1531 * work. 1532 */ 1533static void 1534ti_add_mcast(sc, addr) 1535 struct ti_softc *sc; 1536 struct ether_addr *addr; 1537{ 1538 struct ti_cmd_desc cmd; 1539 u_int16_t *m; 1540 u_int32_t ext[2] = {0, 0}; 1541 1542 m = (u_int16_t *)&addr->octet[0]; 1543 1544 switch(sc->ti_hwrev) { 1545 case TI_HWREV_TIGON: 1546 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1547 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1548 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1549 break; 1550 case TI_HWREV_TIGON_II: 1551 ext[0] = htons(m[0]); 1552 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1553 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1554 break; 1555 default: 1556 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1557 break; 1558 } 1559 1560 return; 1561} 1562 1563static void 1564ti_del_mcast(sc, addr) 1565 struct ti_softc *sc; 1566 struct ether_addr *addr; 1567{ 1568 struct ti_cmd_desc cmd; 1569 u_int16_t *m; 1570 u_int32_t ext[2] = {0, 0}; 1571 1572 m = (u_int16_t *)&addr->octet[0]; 1573 1574 switch(sc->ti_hwrev) { 1575 case TI_HWREV_TIGON: 1576 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1577 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1578 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1579 break; 1580 case TI_HWREV_TIGON_II: 1581 ext[0] = htons(m[0]); 1582 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1583 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1584 break; 1585 default: 1586 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1587 break; 1588 } 1589 1590 return; 1591} 1592 1593/* 1594 * Configure the Tigon's multicast address filter. 1595 * 1596 * The actual multicast table management is a bit of a pain, thanks to 1597 * slight brain damage on the part of both Alteon and us. With our 1598 * multicast code, we are only alerted when the multicast address table 1599 * changes and at that point we only have the current list of addresses: 1600 * we only know the current state, not the previous state, so we don't 1601 * actually know what addresses were removed or added. The firmware has 1602 * state, but we can't get our grubby mits on it, and there is no 'delete 1603 * all multicast addresses' command. Hence, we have to maintain our own 1604 * state so we know what addresses have been programmed into the NIC at 1605 * any given time. 1606 */ 1607static void 1608ti_setmulti(sc) 1609 struct ti_softc *sc; 1610{ 1611 struct ifnet *ifp; 1612 struct ifmultiaddr *ifma; 1613 struct ti_cmd_desc cmd; 1614 struct ti_mc_entry *mc; 1615 u_int32_t intrs; 1616 1617 ifp = &sc->arpcom.ac_if; 1618 1619 if (ifp->if_flags & IFF_ALLMULTI) { 1620 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1621 return; 1622 } else { 1623 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1624 } 1625 1626 /* Disable interrupts. */ 1627 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1628 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1629 1630 /* First, zot all the existing filters. */ 1631 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1632 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1633 ti_del_mcast(sc, &mc->mc_addr); 1634 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1635 free(mc, M_DEVBUF); 1636 } 1637 1638 /* Now program new ones. */ 1639 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1640 if (ifma->ifma_addr->sa_family != AF_LINK) 1641 continue; 1642 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1643 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1644 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1645 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1646 ti_add_mcast(sc, &mc->mc_addr); 1647 } 1648 1649 /* Re-enable interrupts. */ 1650 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1651 1652 return; 1653} 1654 1655/* 1656 * Check to see if the BIOS has configured us for a 64 bit slot when 1657 * we aren't actually in one. If we detect this condition, we can work 1658 * around it on the Tigon 2 by setting a bit in the PCI state register, 1659 * but for the Tigon 1 we must give up and abort the interface attach. 1660 */ 1661static int ti_64bitslot_war(sc) 1662 struct ti_softc *sc; 1663{ 1664 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1665 CSR_WRITE_4(sc, 0x600, 0); 1666 CSR_WRITE_4(sc, 0x604, 0); 1667 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1668 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1669 if (sc->ti_hwrev == TI_HWREV_TIGON) 1670 return(EINVAL); 1671 else { 1672 TI_SETBIT(sc, TI_PCI_STATE, 1673 TI_PCISTATE_32BIT_BUS); 1674 return(0); 1675 } 1676 } 1677 } 1678 1679 return(0); 1680} 1681 1682/* 1683 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1684 * self-test results. 1685 */ 1686static int 1687ti_chipinit(sc) 1688 struct ti_softc *sc; 1689{ 1690 u_int32_t cacheline; 1691 u_int32_t pci_writemax = 0; 1692 u_int32_t hdrsplit; 1693 1694 /* Initialize link to down state. */ 1695 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1696 1697 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1698 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1699 else 1700 sc->arpcom.ac_if.if_hwassist = 0; 1701 1702 /* Set endianness before we access any non-PCI registers. */ 1703#if BYTE_ORDER == BIG_ENDIAN 1704 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1705 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1706#else 1707 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1708 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1709#endif 1710 1711 /* Check the ROM failed bit to see if self-tests passed. */ 1712 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1713 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1714 return(ENODEV); 1715 } 1716 1717 /* Halt the CPU. */ 1718 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1719 1720 /* Figure out the hardware revision. */ 1721 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1722 case TI_REV_TIGON_I: 1723 sc->ti_hwrev = TI_HWREV_TIGON; 1724 break; 1725 case TI_REV_TIGON_II: 1726 sc->ti_hwrev = TI_HWREV_TIGON_II; 1727 break; 1728 default: 1729 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1730 return(ENODEV); 1731 } 1732 1733 /* Do special setup for Tigon 2. */ 1734 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1735 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1736 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1737 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1738 } 1739 1740 /* 1741 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1742 * can't do header splitting. 1743 */ 1744#ifdef TI_JUMBO_HDRSPLIT 1745 if (sc->ti_hwrev != TI_HWREV_TIGON) 1746 sc->ti_hdrsplit = 1; 1747 else 1748 printf("ti%d: can't do header splitting on a Tigon I board\n", 1749 sc->ti_unit); 1750#endif /* TI_JUMBO_HDRSPLIT */ 1751 1752 /* Set up the PCI state register. */ 1753 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1754 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1755 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1756 } 1757 1758 /* Clear the read/write max DMA parameters. */ 1759 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1760 TI_PCISTATE_READ_MAXDMA)); 1761 1762 /* Get cache line size. */ 1763 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1764 1765 /* 1766 * If the system has set enabled the PCI memory write 1767 * and invalidate command in the command register, set 1768 * the write max parameter accordingly. This is necessary 1769 * to use MWI with the Tigon 2. 1770 */ 1771 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1772 switch(cacheline) { 1773 case 1: 1774 case 4: 1775 case 8: 1776 case 16: 1777 case 32: 1778 case 64: 1779 break; 1780 default: 1781 /* Disable PCI memory write and invalidate. */ 1782 if (bootverbose) 1783 printf("ti%d: cache line size %d not " 1784 "supported; disabling PCI MWI\n", 1785 sc->ti_unit, cacheline); 1786 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1787 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1788 break; 1789 } 1790 } 1791 1792#ifdef __brokenalpha__ 1793 /* 1794 * From the Alteon sample driver: 1795 * Must insure that we do not cross an 8K (bytes) boundary 1796 * for DMA reads. Our highest limit is 1K bytes. This is a 1797 * restriction on some ALPHA platforms with early revision 1798 * 21174 PCI chipsets, such as the AlphaPC 164lx 1799 */ 1800 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1801#else 1802 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1803#endif 1804 1805 /* This sets the min dma param all the way up (0xff). */ 1806 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1807 1808 if (sc->ti_hdrsplit) 1809 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1810 else 1811 hdrsplit = 0; 1812 1813 /* Configure DMA variables. */ 1814#if BYTE_ORDER == BIG_ENDIAN 1815 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1816 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1817 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1818 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1819#else /* BYTE_ORDER */ 1820 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1821 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1822 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1823#endif /* BYTE_ORDER */ 1824 1825 /* 1826 * Only allow 1 DMA channel to be active at a time. 1827 * I don't think this is a good idea, but without it 1828 * the firmware racks up lots of nicDmaReadRingFull 1829 * errors. This is not compatible with hardware checksums. 1830 */ 1831 if (sc->arpcom.ac_if.if_hwassist == 0) 1832 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1833 1834 /* Recommended settings from Tigon manual. */ 1835 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1836 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1837 1838 if (ti_64bitslot_war(sc)) { 1839 printf("ti%d: bios thinks we're in a 64 bit slot, " 1840 "but we aren't", sc->ti_unit); 1841 return(EINVAL); 1842 } 1843 1844 return(0); 1845} 1846 1847/* 1848 * Initialize the general information block and firmware, and 1849 * start the CPU(s) running. 1850 */ 1851static int 1852ti_gibinit(sc) 1853 struct ti_softc *sc; 1854{ 1855 struct ti_rcb *rcb; 1856 int i; 1857 struct ifnet *ifp; 1858 1859 ifp = &sc->arpcom.ac_if; 1860 1861 /* Disable interrupts for now. */ 1862 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1863 1864 /* Tell the chip where to find the general information block. */ 1865 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1866 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1867 1868 /* Load the firmware into SRAM. */ 1869 ti_loadfw(sc); 1870 1871 /* Set up the contents of the general info and ring control blocks. */ 1872 1873 /* Set up the event ring and producer pointer. */ 1874 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1875 1876 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1877 rcb->ti_flags = 0; 1878 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1879 vtophys(&sc->ti_ev_prodidx); 1880 sc->ti_ev_prodidx.ti_idx = 0; 1881 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1882 sc->ti_ev_saved_considx = 0; 1883 1884 /* Set up the command ring and producer mailbox. */ 1885 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1886 1887 sc->ti_rdata->ti_cmd_ring = 1888 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1889 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1890 rcb->ti_flags = 0; 1891 rcb->ti_max_len = 0; 1892 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1893 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1894 } 1895 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1896 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1897 sc->ti_cmd_saved_prodidx = 0; 1898 1899 /* 1900 * Assign the address of the stats refresh buffer. 1901 * We re-use the current stats buffer for this to 1902 * conserve memory. 1903 */ 1904 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1905 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1906 1907 /* Set up the standard receive ring. */ 1908 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1909 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1910 rcb->ti_max_len = TI_FRAMELEN; 1911 rcb->ti_flags = 0; 1912 if (sc->arpcom.ac_if.if_hwassist) 1913 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1914 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1915 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1916 1917 /* Set up the jumbo receive ring. */ 1918 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1919 TI_HOSTADDR(rcb->ti_hostaddr) = 1920 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1921 1922#ifdef TI_PRIVATE_JUMBOS 1923 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1924 rcb->ti_flags = 0; 1925#else 1926 rcb->ti_max_len = PAGE_SIZE; 1927 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1928#endif 1929 if (sc->arpcom.ac_if.if_hwassist) 1930 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1931 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1932 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1933 1934 /* 1935 * Set up the mini ring. Only activated on the 1936 * Tigon 2 but the slot in the config block is 1937 * still there on the Tigon 1. 1938 */ 1939 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1940 TI_HOSTADDR(rcb->ti_hostaddr) = 1941 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1942 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1943 if (sc->ti_hwrev == TI_HWREV_TIGON) 1944 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1945 else 1946 rcb->ti_flags = 0; 1947 if (sc->arpcom.ac_if.if_hwassist) 1948 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1949 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1950 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1951 1952 /* 1953 * Set up the receive return ring. 1954 */ 1955 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1956 TI_HOSTADDR(rcb->ti_hostaddr) = 1957 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1958 rcb->ti_flags = 0; 1959 rcb->ti_max_len = TI_RETURN_RING_CNT; 1960 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1961 vtophys(&sc->ti_return_prodidx); 1962 1963 /* 1964 * Set up the tx ring. Note: for the Tigon 2, we have the option 1965 * of putting the transmit ring in the host's address space and 1966 * letting the chip DMA it instead of leaving the ring in the NIC's 1967 * memory and accessing it through the shared memory region. We 1968 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1969 * so we have to revert to the shared memory scheme if we detect 1970 * a Tigon 1 chip. 1971 */ 1972 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1973 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1974 sc->ti_rdata->ti_tx_ring_nic = 1975 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1976 } 1977 bzero((char *)sc->ti_rdata->ti_tx_ring, 1978 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1979 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1980 if (sc->ti_hwrev == TI_HWREV_TIGON) 1981 rcb->ti_flags = 0; 1982 else 1983 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1984 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1985 if (sc->arpcom.ac_if.if_hwassist) 1986 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1987 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1988 rcb->ti_max_len = TI_TX_RING_CNT; 1989 if (sc->ti_hwrev == TI_HWREV_TIGON) 1990 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1991 else 1992 TI_HOSTADDR(rcb->ti_hostaddr) = 1993 vtophys(&sc->ti_rdata->ti_tx_ring); 1994 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1995 vtophys(&sc->ti_tx_considx); 1996 1997 /* Set up tuneables */ 1998#if 0 1999 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2000 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2001 (sc->ti_rx_coal_ticks / 10)); 2002 else 2003#endif 2004 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2005 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2006 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2007 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2008 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2009 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2010 2011 /* Turn interrupts on. */ 2012 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2013 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2014 2015 /* Start CPU. */ 2016 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2017 2018 return(0); 2019} 2020 2021/* 2022 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2023 * against our list and return its name if we find a match. 2024 */ 2025static int 2026ti_probe(dev) 2027 device_t dev; 2028{ 2029 struct ti_type *t; 2030 2031 t = ti_devs; 2032 2033 while(t->ti_name != NULL) { 2034 if ((pci_get_vendor(dev) == t->ti_vid) && 2035 (pci_get_device(dev) == t->ti_did)) { 2036 device_set_desc(dev, t->ti_name); 2037 return(0); 2038 } 2039 t++; 2040 } 2041 2042 return(ENXIO); 2043} 2044 2045static int 2046ti_attach(dev) 2047 device_t dev; 2048{ 2049 struct ifnet *ifp; 2050 struct ti_softc *sc; 2051 int unit, error = 0, rid; 2052 2053 sc = device_get_softc(dev); 2054 unit = device_get_unit(dev); 2055 2056 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2057 MTX_DEF | MTX_RECURSE); 2058 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2059 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | 2060 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2061 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2062 2063 /* 2064 * Map control/status registers. 2065 */ 2066 pci_enable_busmaster(dev); 2067 2068 rid = TI_PCI_LOMEM; 2069 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2070 RF_ACTIVE|PCI_RF_DENSE); 2071 2072 if (sc->ti_res == NULL) { 2073 printf ("ti%d: couldn't map memory\n", unit); 2074 error = ENXIO; 2075 goto fail; 2076 } 2077 2078 sc->ti_btag = rman_get_bustag(sc->ti_res); 2079 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2080 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2081 2082 /* Allocate interrupt */ 2083 rid = 0; 2084 2085 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2086 RF_SHAREABLE | RF_ACTIVE); 2087 2088 if (sc->ti_irq == NULL) { 2089 printf("ti%d: couldn't map interrupt\n", unit); 2090 error = ENXIO; 2091 goto fail; 2092 } 2093 2094 sc->ti_unit = unit; 2095 2096 if (ti_chipinit(sc)) { 2097 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2098 error = ENXIO; 2099 goto fail; 2100 } 2101 2102 /* Zero out the NIC's on-board SRAM. */ 2103 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2104 2105 /* Init again -- zeroing memory may have clobbered some registers. */ 2106 if (ti_chipinit(sc)) { 2107 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2108 error = ENXIO; 2109 goto fail; 2110 } 2111 2112 /* 2113 * Get station address from the EEPROM. Note: the manual states 2114 * that the MAC address is at offset 0x8c, however the data is 2115 * stored as two longwords (since that's how it's loaded into 2116 * the NIC). This means the MAC address is actually preceded 2117 * by two zero bytes. We need to skip over those. 2118 */ 2119 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2120 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2121 printf("ti%d: failed to read station address\n", unit); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 2126 /* Allocate the general information block and ring buffers. */ 2127 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2128 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2129 2130 if (sc->ti_rdata == NULL) { 2131 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2132 error = ENXIO; 2133 goto fail; 2134 } 2135 2136 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2137 2138 /* Try to allocate memory for jumbo buffers. */ 2139#ifdef TI_PRIVATE_JUMBOS 2140 if (ti_alloc_jumbo_mem(sc)) { 2141 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145#else 2146 if (!jumbo_vm_init()) { 2147 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2148 error = ENOMEM; 2149 goto fail; 2150 } 2151#endif 2152 2153 /* 2154 * We really need a better way to tell a 1000baseTX card 2155 * from a 1000baseSX one, since in theory there could be 2156 * OEMed 1000baseTX cards from lame vendors who aren't 2157 * clever enough to change the PCI ID. For the moment 2158 * though, the AceNIC is the only copper card available. 2159 */ 2160 if (pci_get_vendor(dev) == ALT_VENDORID && 2161 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2162 sc->ti_copper = 1; 2163 /* Ok, it's not the only copper card available. */ 2164 if (pci_get_vendor(dev) == NG_VENDORID && 2165 pci_get_device(dev) == NG_DEVICEID_GA620T) 2166 sc->ti_copper = 1; 2167 2168 /* Set default tuneable values. */ 2169 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2170#if 0 2171 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2172#endif 2173 sc->ti_rx_coal_ticks = 170; 2174 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2175 sc->ti_rx_max_coal_bds = 64; 2176#if 0 2177 sc->ti_tx_max_coal_bds = 128; 2178#endif 2179 sc->ti_tx_max_coal_bds = 32; 2180 sc->ti_tx_buf_ratio = 21; 2181 2182 /* Set up ifnet structure */ 2183 ifp = &sc->arpcom.ac_if; 2184 ifp->if_softc = sc; 2185 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2186 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2187 tis[unit] = sc; 2188 ifp->if_ioctl = ti_ioctl; 2189 ifp->if_start = ti_start; 2190 ifp->if_watchdog = ti_watchdog; 2191 ifp->if_init = ti_init; 2192 ifp->if_mtu = ETHERMTU; 2193 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2194 2195 /* Set up ifmedia support. */ 2196 if (sc->ti_copper) { 2197 /* 2198 * Copper cards allow manual 10/100 mode selection, 2199 * but not manual 1000baseTX mode selection. Why? 2200 * Becuase currently there's no way to specify the 2201 * master/slave setting through the firmware interface, 2202 * so Alteon decided to just bag it and handle it 2203 * via autonegotiation. 2204 */ 2205 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2206 ifmedia_add(&sc->ifmedia, 2207 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2208 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2209 ifmedia_add(&sc->ifmedia, 2210 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2211 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2212 ifmedia_add(&sc->ifmedia, 2213 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2214 } else { 2215 /* Fiber cards don't support 10/100 modes. */ 2216 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2217 ifmedia_add(&sc->ifmedia, 2218 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2219 } 2220 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2221 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2222 2223 /* 2224 * We're assuming here that card initialization is a sequential 2225 * thing. If it isn't, multiple cards probing at the same time 2226 * could stomp on the list of softcs here. 2227 */ 2228 2229 /* Register the device */ 2230 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2231 0600, "ti%d", sc->ti_unit); 2232 sc->dev->si_drv1 = sc; 2233 2234 /* 2235 * Call MI attach routine. 2236 */ 2237 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2238 2239 /* Hook interrupt last to avoid having to lock softc */ 2240 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2241 ti_intr, sc, &sc->ti_intrhand); 2242 2243 if (error) { 2244 printf("ti%d: couldn't set up irq\n", unit); 2245 ether_ifdetach(ifp); 2246 goto fail; 2247 } 2248 2249fail: 2250 if (sc && error) 2251 ti_detach(dev); 2252 2253 return(error); 2254} 2255 2256/* 2257 * Shutdown hardware and free up resources. This can be called any 2258 * time after the mutex has been initialized. It is called in both 2259 * the error case in attach and the normal detach case so it needs 2260 * to be careful about only freeing resources that have actually been 2261 * allocated. 2262 */ 2263static int 2264ti_detach(dev) 2265 device_t dev; 2266{ 2267 struct ti_softc *sc; 2268 struct ifnet *ifp; 2269 2270 sc = device_get_softc(dev); 2271 destroy_dev(sc->dev); 2272 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2273 TI_LOCK(sc); 2274 ifp = &sc->arpcom.ac_if; 2275 2276 /* These should only be active if attach succeeded */ 2277 if (device_is_attached(dev)) { 2278 ti_stop(sc); 2279 ether_ifdetach(ifp); 2280 bus_generic_detach(dev); 2281 } 2282 ifmedia_removeall(&sc->ifmedia); 2283 2284 if (sc->ti_intrhand) 2285 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2286 if (sc->ti_irq) 2287 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2288 if (sc->ti_res) { 2289 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2290 sc->ti_res); 2291 } 2292 2293#ifdef TI_PRIVATE_JUMBOS 2294 if (sc->ti_cdata.ti_jumbo_buf) 2295 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2296#endif 2297 if (sc->ti_rdata) 2298 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2299 2300 TI_UNLOCK(sc); 2301 mtx_destroy(&sc->ti_mtx); 2302 2303 return(0); 2304} 2305 2306#ifdef TI_JUMBO_HDRSPLIT 2307/* 2308 * If hdr_len is 0, that means that header splitting wasn't done on 2309 * this packet for some reason. The two most likely reasons are that 2310 * the protocol isn't a supported protocol for splitting, or this 2311 * packet had a fragment offset that wasn't 0. 2312 * 2313 * The header length, if it is non-zero, will always be the length of 2314 * the headers on the packet, but that length could be longer than the 2315 * first mbuf. So we take the minimum of the two as the actual 2316 * length. 2317 */ 2318static __inline void 2319ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2320{ 2321 int i = 0; 2322 int lengths[4] = {0, 0, 0, 0}; 2323 struct mbuf *m, *mp; 2324 2325 if (hdr_len != 0) 2326 top->m_len = min(hdr_len, top->m_len); 2327 pkt_len -= top->m_len; 2328 lengths[i++] = top->m_len; 2329 2330 mp = top; 2331 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2332 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2333 pkt_len -= m->m_len; 2334 lengths[i++] = m->m_len; 2335 mp = m; 2336 } 2337 2338#if 0 2339 if (hdr_len != 0) 2340 printf("got split packet: "); 2341 else 2342 printf("got non-split packet: "); 2343 2344 printf("%d,%d,%d,%d = %d\n", lengths[0], 2345 lengths[1], lengths[2], lengths[3], 2346 lengths[0] + lengths[1] + lengths[2] + 2347 lengths[3]); 2348#endif 2349 2350 if (pkt_len) 2351 panic("header splitting didn't"); 2352 2353 if (m) { 2354 m_freem(m); 2355 mp->m_next = NULL; 2356 2357 } 2358 if (mp->m_next != NULL) 2359 panic("ti_hdr_split: last mbuf in chain should be null"); 2360} 2361#endif /* TI_JUMBO_HDRSPLIT */ 2362 2363/* 2364 * Frame reception handling. This is called if there's a frame 2365 * on the receive return list. 2366 * 2367 * Note: we have to be able to handle three possibilities here: 2368 * 1) the frame is from the mini receive ring (can only happen) 2369 * on Tigon 2 boards) 2370 * 2) the frame is from the jumbo recieve ring 2371 * 3) the frame is from the standard receive ring 2372 */ 2373 2374static void 2375ti_rxeof(sc) 2376 struct ti_softc *sc; 2377{ 2378 struct ifnet *ifp; 2379 struct ti_cmd_desc cmd; 2380 2381 TI_LOCK_ASSERT(sc); 2382 2383 ifp = &sc->arpcom.ac_if; 2384 2385 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2386 struct ti_rx_desc *cur_rx; 2387 u_int32_t rxidx; 2388 struct mbuf *m = NULL; 2389 u_int16_t vlan_tag = 0; 2390 int have_tag = 0; 2391 2392 cur_rx = 2393 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2394 rxidx = cur_rx->ti_idx; 2395 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2396 2397 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2398 have_tag = 1; 2399 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2400 } 2401 2402 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2403 2404 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2405 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2406 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2407 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2408 ifp->if_ierrors++; 2409 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2410 continue; 2411 } 2412 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2413 ifp->if_ierrors++; 2414 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2415 continue; 2416 } 2417#ifdef TI_PRIVATE_JUMBOS 2418 m->m_len = cur_rx->ti_len; 2419#else /* TI_PRIVATE_JUMBOS */ 2420#ifdef TI_JUMBO_HDRSPLIT 2421 if (sc->ti_hdrsplit) 2422 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2423 cur_rx->ti_len, rxidx); 2424 else 2425#endif /* TI_JUMBO_HDRSPLIT */ 2426 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2427#endif /* TI_PRIVATE_JUMBOS */ 2428 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2429 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2430 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2431 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2432 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2433 ifp->if_ierrors++; 2434 ti_newbuf_mini(sc, sc->ti_mini, m); 2435 continue; 2436 } 2437 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2438 ifp->if_ierrors++; 2439 ti_newbuf_mini(sc, sc->ti_mini, m); 2440 continue; 2441 } 2442 m->m_len = cur_rx->ti_len; 2443 } else { 2444 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2445 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2446 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2447 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2448 ifp->if_ierrors++; 2449 ti_newbuf_std(sc, sc->ti_std, m); 2450 continue; 2451 } 2452 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2453 ifp->if_ierrors++; 2454 ti_newbuf_std(sc, sc->ti_std, m); 2455 continue; 2456 } 2457 m->m_len = cur_rx->ti_len; 2458 } 2459 2460 m->m_pkthdr.len = cur_rx->ti_len; 2461 ifp->if_ipackets++; 2462 m->m_pkthdr.rcvif = ifp; 2463 2464 if (ifp->if_hwassist) { 2465 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2466 CSUM_DATA_VALID; 2467 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2468 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2469 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2470 } 2471 2472 /* 2473 * If we received a packet with a vlan tag, 2474 * tag it before passing the packet upward. 2475 */ 2476 if (have_tag) 2477 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2478 TI_UNLOCK(sc); 2479 (*ifp->if_input)(ifp, m); 2480 TI_LOCK(sc); 2481 } 2482 2483 /* Only necessary on the Tigon 1. */ 2484 if (sc->ti_hwrev == TI_HWREV_TIGON) 2485 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2486 sc->ti_rx_saved_considx); 2487 2488 TI_UPDATE_STDPROD(sc, sc->ti_std); 2489 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2490 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2491 2492 return; 2493} 2494 2495static void 2496ti_txeof(sc) 2497 struct ti_softc *sc; 2498{ 2499 struct ti_tx_desc *cur_tx = NULL; 2500 struct ifnet *ifp; 2501 2502 ifp = &sc->arpcom.ac_if; 2503 2504 /* 2505 * Go through our tx ring and free mbufs for those 2506 * frames that have been sent. 2507 */ 2508 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2509 u_int32_t idx = 0; 2510 2511 idx = sc->ti_tx_saved_considx; 2512 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2513 if (idx > 383) 2514 CSR_WRITE_4(sc, TI_WINBASE, 2515 TI_TX_RING_BASE + 6144); 2516 else if (idx > 255) 2517 CSR_WRITE_4(sc, TI_WINBASE, 2518 TI_TX_RING_BASE + 4096); 2519 else if (idx > 127) 2520 CSR_WRITE_4(sc, TI_WINBASE, 2521 TI_TX_RING_BASE + 2048); 2522 else 2523 CSR_WRITE_4(sc, TI_WINBASE, 2524 TI_TX_RING_BASE); 2525 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2526 } else 2527 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2528 if (cur_tx->ti_flags & TI_BDFLAG_END) 2529 ifp->if_opackets++; 2530 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2531 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2532 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2533 } 2534 sc->ti_txcnt--; 2535 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2536 ifp->if_timer = 0; 2537 } 2538 2539 if (cur_tx != NULL) 2540 ifp->if_flags &= ~IFF_OACTIVE; 2541 2542 return; 2543} 2544 2545static void 2546ti_intr(xsc) 2547 void *xsc; 2548{ 2549 struct ti_softc *sc; 2550 struct ifnet *ifp; 2551 2552 sc = xsc; 2553 TI_LOCK(sc); 2554 ifp = &sc->arpcom.ac_if; 2555 2556/*#ifdef notdef*/ 2557 /* Avoid this for now -- checking this register is expensive. */ 2558 /* Make sure this is really our interrupt. */ 2559 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2560 TI_UNLOCK(sc); 2561 return; 2562 } 2563/*#endif*/ 2564 2565 /* Ack interrupt and stop others from occuring. */ 2566 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2567 2568 if (ifp->if_flags & IFF_RUNNING) { 2569 /* Check RX return ring producer/consumer */ 2570 ti_rxeof(sc); 2571 2572 /* Check TX ring producer/consumer */ 2573 ti_txeof(sc); 2574 } 2575 2576 ti_handle_events(sc); 2577 2578 /* Re-enable interrupts. */ 2579 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2580 2581 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2582 ti_start(ifp); 2583 2584 TI_UNLOCK(sc); 2585 2586 return; 2587} 2588 2589static void 2590ti_stats_update(sc) 2591 struct ti_softc *sc; 2592{ 2593 struct ifnet *ifp; 2594 2595 ifp = &sc->arpcom.ac_if; 2596 2597 ifp->if_collisions += 2598 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2599 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2600 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2601 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2602 ifp->if_collisions; 2603 2604 return; 2605} 2606 2607/* 2608 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2609 * pointers to descriptors. 2610 */ 2611static int 2612ti_encap(sc, m_head, txidx) 2613 struct ti_softc *sc; 2614 struct mbuf *m_head; 2615 u_int32_t *txidx; 2616{ 2617 struct ti_tx_desc *f = NULL; 2618 struct mbuf *m; 2619 u_int32_t frag, cur, cnt = 0; 2620 u_int16_t csum_flags = 0; 2621 struct m_tag *mtag; 2622 2623 m = m_head; 2624 cur = frag = *txidx; 2625 2626 if (m_head->m_pkthdr.csum_flags) { 2627 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2628 csum_flags |= TI_BDFLAG_IP_CKSUM; 2629 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2630 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2631 if (m_head->m_flags & M_LASTFRAG) 2632 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2633 else if (m_head->m_flags & M_FRAG) 2634 csum_flags |= TI_BDFLAG_IP_FRAG; 2635 } 2636 2637 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2638 2639 /* 2640 * Start packing the mbufs in this chain into 2641 * the fragment pointers. Stop when we run out 2642 * of fragments or hit the end of the mbuf chain. 2643 */ 2644 for (m = m_head; m != NULL; m = m->m_next) { 2645 if (m->m_len != 0) { 2646 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2647 if (frag > 383) 2648 CSR_WRITE_4(sc, TI_WINBASE, 2649 TI_TX_RING_BASE + 6144); 2650 else if (frag > 255) 2651 CSR_WRITE_4(sc, TI_WINBASE, 2652 TI_TX_RING_BASE + 4096); 2653 else if (frag > 127) 2654 CSR_WRITE_4(sc, TI_WINBASE, 2655 TI_TX_RING_BASE + 2048); 2656 else 2657 CSR_WRITE_4(sc, TI_WINBASE, 2658 TI_TX_RING_BASE); 2659 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2660 } else 2661 f = &sc->ti_rdata->ti_tx_ring[frag]; 2662 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2663 break; 2664 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2665 f->ti_len = m->m_len; 2666 f->ti_flags = csum_flags; 2667 2668 if (mtag != NULL) { 2669 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2670 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2671 } else { 2672 f->ti_vlan_tag = 0; 2673 } 2674 2675 /* 2676 * Sanity check: avoid coming within 16 descriptors 2677 * of the end of the ring. 2678 */ 2679 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2680 return(ENOBUFS); 2681 cur = frag; 2682 TI_INC(frag, TI_TX_RING_CNT); 2683 cnt++; 2684 } 2685 } 2686 2687 if (m != NULL) 2688 return(ENOBUFS); 2689 2690 if (frag == sc->ti_tx_saved_considx) 2691 return(ENOBUFS); 2692 2693 if (sc->ti_hwrev == TI_HWREV_TIGON) 2694 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2695 TI_BDFLAG_END; 2696 else 2697 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2698 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2699 sc->ti_txcnt += cnt; 2700 2701 *txidx = frag; 2702 2703 return(0); 2704} 2705 2706/* 2707 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2708 * to the mbuf data regions directly in the transmit descriptors. 2709 */ 2710static void 2711ti_start(ifp) 2712 struct ifnet *ifp; 2713{ 2714 struct ti_softc *sc; 2715 struct mbuf *m_head = NULL; 2716 u_int32_t prodidx = 0; 2717 2718 sc = ifp->if_softc; 2719 TI_LOCK(sc); 2720 2721 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2722 2723 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2724 IF_DEQUEUE(&ifp->if_snd, m_head); 2725 if (m_head == NULL) 2726 break; 2727 2728 /* 2729 * XXX 2730 * safety overkill. If this is a fragmented packet chain 2731 * with delayed TCP/UDP checksums, then only encapsulate 2732 * it if we have enough descriptors to handle the entire 2733 * chain at once. 2734 * (paranoia -- may not actually be needed) 2735 */ 2736 if (m_head->m_flags & M_FIRSTFRAG && 2737 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2738 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2739 m_head->m_pkthdr.csum_data + 16) { 2740 IF_PREPEND(&ifp->if_snd, m_head); 2741 ifp->if_flags |= IFF_OACTIVE; 2742 break; 2743 } 2744 } 2745 2746 /* 2747 * Pack the data into the transmit ring. If we 2748 * don't have room, set the OACTIVE flag and wait 2749 * for the NIC to drain the ring. 2750 */ 2751 if (ti_encap(sc, m_head, &prodidx)) { 2752 IF_PREPEND(&ifp->if_snd, m_head); 2753 ifp->if_flags |= IFF_OACTIVE; 2754 break; 2755 } 2756 2757 /* 2758 * If there's a BPF listener, bounce a copy of this frame 2759 * to him. 2760 */ 2761 BPF_MTAP(ifp, m_head); 2762 } 2763 2764 /* Transmit */ 2765 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2766 2767 /* 2768 * Set a timeout in case the chip goes out to lunch. 2769 */ 2770 ifp->if_timer = 5; 2771 TI_UNLOCK(sc); 2772 2773 return; 2774} 2775 2776static void 2777ti_init(xsc) 2778 void *xsc; 2779{ 2780 struct ti_softc *sc = xsc; 2781 2782 /* Cancel pending I/O and flush buffers. */ 2783 ti_stop(sc); 2784 2785 TI_LOCK(sc); 2786 /* Init the gen info block, ring control blocks and firmware. */ 2787 if (ti_gibinit(sc)) { 2788 printf("ti%d: initialization failure\n", sc->ti_unit); 2789 TI_UNLOCK(sc); 2790 return; 2791 } 2792 2793 TI_UNLOCK(sc); 2794 2795 return; 2796} 2797 2798static void ti_init2(sc) 2799 struct ti_softc *sc; 2800{ 2801 struct ti_cmd_desc cmd; 2802 struct ifnet *ifp; 2803 u_int16_t *m; 2804 struct ifmedia *ifm; 2805 int tmp; 2806 2807 ifp = &sc->arpcom.ac_if; 2808 2809 /* Specify MTU and interface index. */ 2810 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 2811 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2812 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 2813 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2814 2815 /* Load our MAC address. */ 2816 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2817 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2818 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2819 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2820 2821 /* Enable or disable promiscuous mode as needed. */ 2822 if (ifp->if_flags & IFF_PROMISC) { 2823 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2824 } else { 2825 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2826 } 2827 2828 /* Program multicast filter. */ 2829 ti_setmulti(sc); 2830 2831 /* 2832 * If this is a Tigon 1, we should tell the 2833 * firmware to use software packet filtering. 2834 */ 2835 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2836 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2837 } 2838 2839 /* Init RX ring. */ 2840 ti_init_rx_ring_std(sc); 2841 2842 /* Init jumbo RX ring. */ 2843 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2844 ti_init_rx_ring_jumbo(sc); 2845 2846 /* 2847 * If this is a Tigon 2, we can also configure the 2848 * mini ring. 2849 */ 2850 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2851 ti_init_rx_ring_mini(sc); 2852 2853 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2854 sc->ti_rx_saved_considx = 0; 2855 2856 /* Init TX ring. */ 2857 ti_init_tx_ring(sc); 2858 2859 /* Tell firmware we're alive. */ 2860 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2861 2862 /* Enable host interrupts. */ 2863 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2864 2865 ifp->if_flags |= IFF_RUNNING; 2866 ifp->if_flags &= ~IFF_OACTIVE; 2867 2868 /* 2869 * Make sure to set media properly. We have to do this 2870 * here since we have to issue commands in order to set 2871 * the link negotiation and we can't issue commands until 2872 * the firmware is running. 2873 */ 2874 ifm = &sc->ifmedia; 2875 tmp = ifm->ifm_media; 2876 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2877 ti_ifmedia_upd(ifp); 2878 ifm->ifm_media = tmp; 2879 2880 return; 2881} 2882 2883/* 2884 * Set media options. 2885 */ 2886static int 2887ti_ifmedia_upd(ifp) 2888 struct ifnet *ifp; 2889{ 2890 struct ti_softc *sc; 2891 struct ifmedia *ifm; 2892 struct ti_cmd_desc cmd; 2893 u_int32_t flowctl; 2894 2895 sc = ifp->if_softc; 2896 ifm = &sc->ifmedia; 2897 2898 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2899 return(EINVAL); 2900 2901 flowctl = 0; 2902 2903 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2904 case IFM_AUTO: 2905 /* 2906 * Transmit flow control doesn't work on the Tigon 1. 2907 */ 2908 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2909 2910 /* 2911 * Transmit flow control can also cause problems on the 2912 * Tigon 2, apparantly with both the copper and fiber 2913 * boards. The symptom is that the interface will just 2914 * hang. This was reproduced with Alteon 180 switches. 2915 */ 2916#if 0 2917 if (sc->ti_hwrev != TI_HWREV_TIGON) 2918 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2919#endif 2920 2921 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2922 TI_GLNK_FULL_DUPLEX| flowctl | 2923 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2924 2925 flowctl = TI_LNK_RX_FLOWCTL_Y; 2926#if 0 2927 if (sc->ti_hwrev != TI_HWREV_TIGON) 2928 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2929#endif 2930 2931 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2932 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 2933 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2934 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2935 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2936 break; 2937 case IFM_1000_SX: 2938 case IFM_1000_T: 2939 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2940#if 0 2941 if (sc->ti_hwrev != TI_HWREV_TIGON) 2942 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2943#endif 2944 2945 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2946 flowctl |TI_GLNK_ENB); 2947 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2948 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2949 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2950 } 2951 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2952 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2953 break; 2954 case IFM_100_FX: 2955 case IFM_10_FL: 2956 case IFM_100_TX: 2957 case IFM_10_T: 2958 flowctl = TI_LNK_RX_FLOWCTL_Y; 2959#if 0 2960 if (sc->ti_hwrev != TI_HWREV_TIGON) 2961 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2962#endif 2963 2964 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2965 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 2966 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2967 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2968 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2969 } else { 2970 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2971 } 2972 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2973 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2974 } else { 2975 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2976 } 2977 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2978 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2979 break; 2980 } 2981 2982 return(0); 2983} 2984 2985/* 2986 * Report current media status. 2987 */ 2988static void 2989ti_ifmedia_sts(ifp, ifmr) 2990 struct ifnet *ifp; 2991 struct ifmediareq *ifmr; 2992{ 2993 struct ti_softc *sc; 2994 u_int32_t media = 0; 2995 2996 sc = ifp->if_softc; 2997 2998 ifmr->ifm_status = IFM_AVALID; 2999 ifmr->ifm_active = IFM_ETHER; 3000 3001 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3002 return; 3003 3004 ifmr->ifm_status |= IFM_ACTIVE; 3005 3006 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3007 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3008 if (sc->ti_copper) 3009 ifmr->ifm_active |= IFM_1000_T; 3010 else 3011 ifmr->ifm_active |= IFM_1000_SX; 3012 if (media & TI_GLNK_FULL_DUPLEX) 3013 ifmr->ifm_active |= IFM_FDX; 3014 else 3015 ifmr->ifm_active |= IFM_HDX; 3016 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3017 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3018 if (sc->ti_copper) { 3019 if (media & TI_LNK_100MB) 3020 ifmr->ifm_active |= IFM_100_TX; 3021 if (media & TI_LNK_10MB) 3022 ifmr->ifm_active |= IFM_10_T; 3023 } else { 3024 if (media & TI_LNK_100MB) 3025 ifmr->ifm_active |= IFM_100_FX; 3026 if (media & TI_LNK_10MB) 3027 ifmr->ifm_active |= IFM_10_FL; 3028 } 3029 if (media & TI_LNK_FULL_DUPLEX) 3030 ifmr->ifm_active |= IFM_FDX; 3031 if (media & TI_LNK_HALF_DUPLEX) 3032 ifmr->ifm_active |= IFM_HDX; 3033 } 3034 3035 return; 3036} 3037 3038static int 3039ti_ioctl(ifp, command, data) 3040 struct ifnet *ifp; 3041 u_long command; 3042 caddr_t data; 3043{ 3044 struct ti_softc *sc = ifp->if_softc; 3045 struct ifreq *ifr = (struct ifreq *) data; 3046 int mask, error = 0; 3047 struct ti_cmd_desc cmd; 3048 3049 TI_LOCK(sc); 3050 3051 switch(command) { 3052 case SIOCSIFMTU: 3053 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3054 error = EINVAL; 3055 else { 3056 ifp->if_mtu = ifr->ifr_mtu; 3057 ti_init(sc); 3058 } 3059 break; 3060 case SIOCSIFFLAGS: 3061 if (ifp->if_flags & IFF_UP) { 3062 /* 3063 * If only the state of the PROMISC flag changed, 3064 * then just use the 'set promisc mode' command 3065 * instead of reinitializing the entire NIC. Doing 3066 * a full re-init means reloading the firmware and 3067 * waiting for it to start up, which may take a 3068 * second or two. 3069 */ 3070 if (ifp->if_flags & IFF_RUNNING && 3071 ifp->if_flags & IFF_PROMISC && 3072 !(sc->ti_if_flags & IFF_PROMISC)) { 3073 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3074 TI_CMD_CODE_PROMISC_ENB, 0); 3075 } else if (ifp->if_flags & IFF_RUNNING && 3076 !(ifp->if_flags & IFF_PROMISC) && 3077 sc->ti_if_flags & IFF_PROMISC) { 3078 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3079 TI_CMD_CODE_PROMISC_DIS, 0); 3080 } else 3081 ti_init(sc); 3082 } else { 3083 if (ifp->if_flags & IFF_RUNNING) { 3084 ti_stop(sc); 3085 } 3086 } 3087 sc->ti_if_flags = ifp->if_flags; 3088 error = 0; 3089 break; 3090 case SIOCADDMULTI: 3091 case SIOCDELMULTI: 3092 if (ifp->if_flags & IFF_RUNNING) { 3093 ti_setmulti(sc); 3094 error = 0; 3095 } 3096 break; 3097 case SIOCSIFMEDIA: 3098 case SIOCGIFMEDIA: 3099 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3100 break; 3101 case SIOCSIFCAP: 3102 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3103 if (mask & IFCAP_HWCSUM) { 3104 if (IFCAP_HWCSUM & ifp->if_capenable) 3105 ifp->if_capenable &= ~IFCAP_HWCSUM; 3106 else 3107 ifp->if_capenable |= IFCAP_HWCSUM; 3108 if (ifp->if_flags & IFF_RUNNING) 3109 ti_init(sc); 3110 } 3111 error = 0; 3112 break; 3113 default: 3114 error = ether_ioctl(ifp, command, data); 3115 break; 3116 } 3117 3118 TI_UNLOCK(sc); 3119 3120 return(error); 3121} 3122 3123static int 3124ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3125{ 3126 struct ti_softc *sc; 3127 3128 sc = dev->si_drv1; 3129 if (sc == NULL) 3130 return(ENODEV); 3131 3132 TI_LOCK(sc); 3133 sc->ti_flags |= TI_FLAG_DEBUGING; 3134 TI_UNLOCK(sc); 3135 3136 return(0); 3137} 3138 3139static int 3140ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3141{ 3142 struct ti_softc *sc; 3143 3144 sc = dev->si_drv1; 3145 if (sc == NULL) 3146 return(ENODEV); 3147 3148 TI_LOCK(sc); 3149 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3150 TI_UNLOCK(sc); 3151 3152 return(0); 3153} 3154 3155/* 3156 * This ioctl routine goes along with the Tigon character device. 3157 */ 3158static int 3159ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3160{ 3161 int error; 3162 struct ti_softc *sc; 3163 3164 sc = dev->si_drv1; 3165 if (sc == NULL) 3166 return(ENODEV); 3167 3168 error = 0; 3169 3170 switch(cmd) { 3171 case TIIOCGETSTATS: 3172 { 3173 struct ti_stats *outstats; 3174 3175 outstats = (struct ti_stats *)addr; 3176 3177 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3178 sizeof(struct ti_stats)); 3179 break; 3180 } 3181 case TIIOCGETPARAMS: 3182 { 3183 struct ti_params *params; 3184 3185 params = (struct ti_params *)addr; 3186 3187 params->ti_stat_ticks = sc->ti_stat_ticks; 3188 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3189 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3190 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3191 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3192 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3193 params->param_mask = TI_PARAM_ALL; 3194 3195 error = 0; 3196 3197 break; 3198 } 3199 case TIIOCSETPARAMS: 3200 { 3201 struct ti_params *params; 3202 3203 params = (struct ti_params *)addr; 3204 3205 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3206 sc->ti_stat_ticks = params->ti_stat_ticks; 3207 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3208 } 3209 3210 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3211 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3212 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3213 sc->ti_rx_coal_ticks); 3214 } 3215 3216 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3217 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3218 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3219 sc->ti_tx_coal_ticks); 3220 } 3221 3222 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3223 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3224 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3225 sc->ti_rx_max_coal_bds); 3226 } 3227 3228 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3229 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3230 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3231 sc->ti_tx_max_coal_bds); 3232 } 3233 3234 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3235 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3236 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3237 sc->ti_tx_buf_ratio); 3238 } 3239 3240 error = 0; 3241 3242 break; 3243 } 3244 case TIIOCSETTRACE: { 3245 ti_trace_type trace_type; 3246 3247 trace_type = *(ti_trace_type *)addr; 3248 3249 /* 3250 * Set tracing to whatever the user asked for. Setting 3251 * this register to 0 should have the effect of disabling 3252 * tracing. 3253 */ 3254 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3255 3256 error = 0; 3257 3258 break; 3259 } 3260 case TIIOCGETTRACE: { 3261 struct ti_trace_buf *trace_buf; 3262 u_int32_t trace_start, cur_trace_ptr, trace_len; 3263 3264 trace_buf = (struct ti_trace_buf *)addr; 3265 3266 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3267 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3268 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3269 3270#if 0 3271 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3272 "trace_len = %d\n", sc->ti_unit, trace_start, 3273 cur_trace_ptr, trace_len); 3274 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3275 trace_buf->buf_len); 3276#endif 3277 3278 error = ti_copy_mem(sc, trace_start, min(trace_len, 3279 trace_buf->buf_len), 3280 (caddr_t)trace_buf->buf, 1, 1); 3281 3282 if (error == 0) { 3283 trace_buf->fill_len = min(trace_len, 3284 trace_buf->buf_len); 3285 if (cur_trace_ptr < trace_start) 3286 trace_buf->cur_trace_ptr = 3287 trace_start - cur_trace_ptr; 3288 else 3289 trace_buf->cur_trace_ptr = 3290 cur_trace_ptr - trace_start; 3291 } else 3292 trace_buf->fill_len = 0; 3293 3294 3295 break; 3296 } 3297 3298 /* 3299 * For debugging, five ioctls are needed: 3300 * ALT_ATTACH 3301 * ALT_READ_TG_REG 3302 * ALT_WRITE_TG_REG 3303 * ALT_READ_TG_MEM 3304 * ALT_WRITE_TG_MEM 3305 */ 3306 case ALT_ATTACH: 3307 /* 3308 * From what I can tell, Alteon's Solaris Tigon driver 3309 * only has one character device, so you have to attach 3310 * to the Tigon board you're interested in. This seems 3311 * like a not-so-good way to do things, since unless you 3312 * subsequently specify the unit number of the device 3313 * you're interested in in every ioctl, you'll only be 3314 * able to debug one board at a time. 3315 */ 3316 error = 0; 3317 break; 3318 case ALT_READ_TG_MEM: 3319 case ALT_WRITE_TG_MEM: 3320 { 3321 struct tg_mem *mem_param; 3322 u_int32_t sram_end, scratch_end; 3323 3324 mem_param = (struct tg_mem *)addr; 3325 3326 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3327 sram_end = TI_END_SRAM_I; 3328 scratch_end = TI_END_SCRATCH_I; 3329 } else { 3330 sram_end = TI_END_SRAM_II; 3331 scratch_end = TI_END_SCRATCH_II; 3332 } 3333 3334 /* 3335 * For now, we'll only handle accessing regular SRAM, 3336 * nothing else. 3337 */ 3338 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3339 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3340 /* 3341 * In this instance, we always copy to/from user 3342 * space, so the user space argument is set to 1. 3343 */ 3344 error = ti_copy_mem(sc, mem_param->tgAddr, 3345 mem_param->len, 3346 mem_param->userAddr, 1, 3347 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3348 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3349 && (mem_param->tgAddr <= scratch_end)) { 3350 error = ti_copy_scratch(sc, mem_param->tgAddr, 3351 mem_param->len, 3352 mem_param->userAddr, 1, 3353 (cmd == ALT_READ_TG_MEM) ? 3354 1 : 0, TI_PROCESSOR_A); 3355 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3356 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3357 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3358 printf("ti%d: invalid memory range for " 3359 "Tigon I\n", sc->ti_unit); 3360 error = EINVAL; 3361 break; 3362 } 3363 error = ti_copy_scratch(sc, mem_param->tgAddr - 3364 TI_SCRATCH_DEBUG_OFF, 3365 mem_param->len, 3366 mem_param->userAddr, 1, 3367 (cmd == ALT_READ_TG_MEM) ? 3368 1 : 0, TI_PROCESSOR_B); 3369 } else { 3370 printf("ti%d: memory address %#x len %d is out of " 3371 "supported range\n", sc->ti_unit, 3372 mem_param->tgAddr, mem_param->len); 3373 error = EINVAL; 3374 } 3375 3376 break; 3377 } 3378 case ALT_READ_TG_REG: 3379 case ALT_WRITE_TG_REG: 3380 { 3381 struct tg_reg *regs; 3382 u_int32_t tmpval; 3383 3384 regs = (struct tg_reg *)addr; 3385 3386 /* 3387 * Make sure the address in question isn't out of range. 3388 */ 3389 if (regs->addr > TI_REG_MAX) { 3390 error = EINVAL; 3391 break; 3392 } 3393 if (cmd == ALT_READ_TG_REG) { 3394 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3395 regs->addr, &tmpval, 1); 3396 regs->data = ntohl(tmpval); 3397#if 0 3398 if ((regs->addr == TI_CPU_STATE) 3399 || (regs->addr == TI_CPU_CTL_B)) { 3400 printf("ti%d: register %#x = %#x\n", 3401 sc->ti_unit, regs->addr, tmpval); 3402 } 3403#endif 3404 } else { 3405 tmpval = htonl(regs->data); 3406 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3407 regs->addr, &tmpval, 1); 3408 } 3409 3410 break; 3411 } 3412 default: 3413 error = ENOTTY; 3414 break; 3415 } 3416 return(error); 3417} 3418 3419static void 3420ti_watchdog(ifp) 3421 struct ifnet *ifp; 3422{ 3423 struct ti_softc *sc; 3424 3425 sc = ifp->if_softc; 3426 TI_LOCK(sc); 3427 3428 /* 3429 * When we're debugging, the chip is often stopped for long periods 3430 * of time, and that would normally cause the watchdog timer to fire. 3431 * Since that impedes debugging, we don't want to do that. 3432 */ 3433 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3434 TI_UNLOCK(sc); 3435 return; 3436 } 3437 3438 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3439 ti_stop(sc); 3440 ti_init(sc); 3441 3442 ifp->if_oerrors++; 3443 TI_UNLOCK(sc); 3444 3445 return; 3446} 3447 3448/* 3449 * Stop the adapter and free any mbufs allocated to the 3450 * RX and TX lists. 3451 */ 3452static void 3453ti_stop(sc) 3454 struct ti_softc *sc; 3455{ 3456 struct ifnet *ifp; 3457 struct ti_cmd_desc cmd; 3458 3459 TI_LOCK(sc); 3460 3461 ifp = &sc->arpcom.ac_if; 3462 3463 /* Disable host interrupts. */ 3464 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3465 /* 3466 * Tell firmware we're shutting down. 3467 */ 3468 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3469 3470 /* Halt and reinitialize. */ 3471 ti_chipinit(sc); 3472 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3473 ti_chipinit(sc); 3474 3475 /* Free the RX lists. */ 3476 ti_free_rx_ring_std(sc); 3477 3478 /* Free jumbo RX list. */ 3479 ti_free_rx_ring_jumbo(sc); 3480 3481 /* Free mini RX list. */ 3482 ti_free_rx_ring_mini(sc); 3483 3484 /* Free TX buffers. */ 3485 ti_free_tx_ring(sc); 3486 3487 sc->ti_ev_prodidx.ti_idx = 0; 3488 sc->ti_return_prodidx.ti_idx = 0; 3489 sc->ti_tx_considx.ti_idx = 0; 3490 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3491 3492 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3493 TI_UNLOCK(sc); 3494 3495 return; 3496} 3497 3498/* 3499 * Stop all chip I/O so that the kernel's probe routines don't 3500 * get confused by errant DMAs when rebooting. 3501 */ 3502static void 3503ti_shutdown(dev) 3504 device_t dev; 3505{ 3506 struct ti_softc *sc; 3507 3508 sc = device_get_softc(dev); 3509 TI_LOCK(sc); 3510 ti_chipinit(sc); 3511 TI_UNLOCK(sc); 3512 3513 return; 3514} 3515