if_gem.c revision 148368
1119418Sobrien/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 3108832Stmm * Copyright (c) 2001-2003 Thomas Moestl 491398Stmm * All rights reserved. 591398Stmm * 691398Stmm * Redistribution and use in source and binary forms, with or without 791398Stmm * modification, are permitted provided that the following conditions 891398Stmm * are met: 991398Stmm * 1. Redistributions of source code must retain the above copyright 1091398Stmm * notice, this list of conditions and the following disclaimer. 1191398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1291398Stmm * notice, this list of conditions and the following disclaimer in the 1391398Stmm * documentation and/or other materials provided with the distribution. 1491398Stmm * 1591398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1691398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1791398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1891398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1991398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2091398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2191398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2291398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2391398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2491398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2591398Stmm * SUCH DAMAGE. 2691398Stmm * 2799726Sbenno * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 2891398Stmm */ 2991398Stmm 30119418Sobrien#include <sys/cdefs.h> 31119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 148368 2005-07-24 18:12:31Z marius $"); 32119418Sobrien 3391398Stmm/* 3491398Stmm * Driver for Sun GEM ethernet controllers. 3591398Stmm */ 3691398Stmm 37115030Stmm#if 0 3891398Stmm#define GEM_DEBUG 39115030Stmm#endif 4091398Stmm 41148368Smarius#if 0 /* XXX: In case of emergency, re-enable this. */ 42148368Smarius#define GEM_RINT_TIMEOUT 43148368Smarius#endif 44148368Smarius 4591398Stmm#include <sys/param.h> 4691398Stmm#include <sys/systm.h> 4791398Stmm#include <sys/bus.h> 4891398Stmm#include <sys/callout.h> 4995533Smike#include <sys/endian.h> 5091398Stmm#include <sys/mbuf.h> 5191398Stmm#include <sys/malloc.h> 5291398Stmm#include <sys/kernel.h> 53130026Sphk#include <sys/module.h> 5491398Stmm#include <sys/socket.h> 5591398Stmm#include <sys/sockio.h> 5691398Stmm 57105982Stmm#include <net/bpf.h> 5891398Stmm#include <net/ethernet.h> 5991398Stmm#include <net/if.h> 6091398Stmm#include <net/if_arp.h> 6191398Stmm#include <net/if_dl.h> 6291398Stmm#include <net/if_media.h> 63147256Sbrooks#include <net/if_types.h> 6491398Stmm 6591398Stmm#include <machine/bus.h> 6691398Stmm 6791398Stmm#include <dev/mii/mii.h> 6891398Stmm#include <dev/mii/miivar.h> 6991398Stmm 70119355Simp#include <dev/gem/if_gemreg.h> 71119355Simp#include <dev/gem/if_gemvar.h> 7291398Stmm 7391398Stmm#define TRIES 10000 7491398Stmm 7592739Salfredstatic void gem_start(struct ifnet *); 7692739Salfredstatic void gem_stop(struct ifnet *, int); 7792739Salfredstatic int gem_ioctl(struct ifnet *, u_long, caddr_t); 7892739Salfredstatic void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 79108832Stmmstatic void gem_txdma_callback(void *, bus_dma_segment_t *, int, 80108832Stmm bus_size_t, int); 8192739Salfredstatic void gem_tick(void *); 8292739Salfredstatic void gem_watchdog(struct ifnet *); 8392739Salfredstatic void gem_init(void *); 8492739Salfredstatic void gem_init_regs(struct gem_softc *sc); 8592739Salfredstatic int gem_ringsize(int sz); 8692739Salfredstatic int gem_meminit(struct gem_softc *); 87108832Stmmstatic int gem_load_txmbuf(struct gem_softc *, struct mbuf *); 8892739Salfredstatic void gem_mifinit(struct gem_softc *); 8992739Salfredstatic int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 9092739Salfred u_int32_t clr, u_int32_t set); 9192739Salfredstatic int gem_reset_rx(struct gem_softc *); 9292739Salfredstatic int gem_reset_tx(struct gem_softc *); 9392739Salfredstatic int gem_disable_rx(struct gem_softc *); 9492739Salfredstatic int gem_disable_tx(struct gem_softc *); 9592739Salfredstatic void gem_rxdrain(struct gem_softc *); 9692739Salfredstatic int gem_add_rxbuf(struct gem_softc *, int); 9792739Salfredstatic void gem_setladrf(struct gem_softc *); 9891398Stmm 9992739Salfredstruct mbuf *gem_get(struct gem_softc *, int, int); 10092739Salfredstatic void gem_eint(struct gem_softc *, u_int); 10192739Salfredstatic void gem_rint(struct gem_softc *); 102148368Smarius#ifdef GEM_RINT_TIMEOUT 10393045Stmmstatic void gem_rint_timeout(void *); 104100587Sjake#endif 10592739Salfredstatic void gem_tint(struct gem_softc *); 10691398Stmm#ifdef notyet 10792739Salfredstatic void gem_power(int, void *); 10891398Stmm#endif 10991398Stmm 11091398Stmmdevclass_t gem_devclass; 11191398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 11291398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1); 11391398Stmm 11491398Stmm#ifdef GEM_DEBUG 11591398Stmm#include <sys/ktr.h> 11691398Stmm#define KTR_GEM KTR_CT2 11791398Stmm#endif 11891398Stmm 119115030Stmm#define GEM_NSEGS GEM_NTXDESC 12091398Stmm 12191398Stmm/* 12291398Stmm * gem_attach: 12391398Stmm * 12491398Stmm * Attach a Gem interface to the system. 12591398Stmm */ 12691398Stmmint 12791398Stmmgem_attach(sc) 12891398Stmm struct gem_softc *sc; 12991398Stmm{ 130147256Sbrooks struct ifnet *ifp; 13191398Stmm struct mii_softc *child; 13291398Stmm int i, error; 13399726Sbenno u_int32_t v; 13491398Stmm 135147256Sbrooks ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 136147256Sbrooks if (ifp == NULL) 137147256Sbrooks return (ENOSPC); 138147256Sbrooks 13991398Stmm /* Make sure the chip is stopped. */ 14091398Stmm ifp->if_softc = sc; 14191398Stmm gem_reset(sc); 14291398Stmm 14391398Stmm error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 14491398Stmm BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS, 145117126Sscottl BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag); 14691398Stmm if (error) 147147256Sbrooks goto fail_ifnet; 14891398Stmm 14991398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 15091398Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 151117126Sscottl 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL, 152108832Stmm &sc->sc_rdmatag); 15391398Stmm if (error) 154108832Stmm goto fail_ptag; 15591398Stmm 156108832Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 157108832Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 158115030Stmm GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT, 159117126Sscottl BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 160108832Stmm if (error) 161108832Stmm goto fail_rtag; 162108832Stmm 16391398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 16491398Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 16591398Stmm sizeof(struct gem_control_data), 1, 16691398Stmm sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 167117126Sscottl busdma_lock_mutex, &Giant, &sc->sc_cdmatag); 16891398Stmm if (error) 169108832Stmm goto fail_ttag; 17091398Stmm 17191398Stmm /* 17291398Stmm * Allocate the control data structures, and create and load the 17391398Stmm * DMA map for it. 17491398Stmm */ 17591398Stmm if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 17691398Stmm (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 17791398Stmm device_printf(sc->sc_dev, "unable to allocate control data," 17891398Stmm " error = %d\n", error); 179108832Stmm goto fail_ctag; 18091398Stmm } 18191398Stmm 18291398Stmm sc->sc_cddma = 0; 18391398Stmm if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 18491398Stmm sc->sc_control_data, sizeof(struct gem_control_data), 18591398Stmm gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 18691398Stmm device_printf(sc->sc_dev, "unable to load control data DMA " 18791398Stmm "map, error = %d\n", error); 188108832Stmm goto fail_cmem; 18991398Stmm } 19091398Stmm 19191398Stmm /* 19291398Stmm * Initialize the transmit job descriptors. 19391398Stmm */ 19491398Stmm STAILQ_INIT(&sc->sc_txfreeq); 19591398Stmm STAILQ_INIT(&sc->sc_txdirtyq); 19691398Stmm 19791398Stmm /* 19891398Stmm * Create the transmit buffer DMA maps. 19991398Stmm */ 20091398Stmm error = ENOMEM; 20191398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 20291398Stmm struct gem_txsoft *txs; 20391398Stmm 20491398Stmm txs = &sc->sc_txsoft[i]; 20591398Stmm txs->txs_mbuf = NULL; 20691398Stmm txs->txs_ndescs = 0; 207108832Stmm if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 20891398Stmm &txs->txs_dmamap)) != 0) { 20991398Stmm device_printf(sc->sc_dev, "unable to create tx DMA map " 21091398Stmm "%d, error = %d\n", i, error); 211108832Stmm goto fail_txd; 21291398Stmm } 21391398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 21491398Stmm } 21591398Stmm 21691398Stmm /* 21791398Stmm * Create the receive buffer DMA maps. 21891398Stmm */ 21991398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 220108832Stmm if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 22191398Stmm &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 22291398Stmm device_printf(sc->sc_dev, "unable to create rx DMA map " 22391398Stmm "%d, error = %d\n", i, error); 224108832Stmm goto fail_rxd; 22591398Stmm } 22691398Stmm sc->sc_rxsoft[i].rxs_mbuf = NULL; 22791398Stmm } 22891398Stmm 22991398Stmm gem_mifinit(sc); 23091398Stmm 23191398Stmm if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 23291398Stmm gem_mediastatus)) != 0) { 23391398Stmm device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 234108832Stmm goto fail_rxd; 23591398Stmm } 23691398Stmm sc->sc_mii = device_get_softc(sc->sc_miibus); 23791398Stmm 23891398Stmm /* 23991398Stmm * From this point forward, the attachment cannot fail. A failure 24091398Stmm * before this point releases all resources that may have been 24191398Stmm * allocated. 24291398Stmm */ 24391398Stmm 24499726Sbenno /* Get RX FIFO size */ 24599726Sbenno sc->sc_rxfifosize = 64 * 24699726Sbenno bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 24799726Sbenno 24899726Sbenno /* Get TX FIFO size */ 24999726Sbenno v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 250128588Stmm device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 251128588Stmm sc->sc_rxfifosize / 1024, v / 16); 25299726Sbenno 25391398Stmm /* Initialize ifnet structure. */ 25491398Stmm ifp->if_softc = sc; 255121816Sbrooks if_initname(ifp, device_get_name(sc->sc_dev), 256121816Sbrooks device_get_unit(sc->sc_dev)); 25791398Stmm ifp->if_mtu = ETHERMTU; 258133687Srwatson ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 259133687Srwatson IFF_NEEDSGIANT; 26091398Stmm ifp->if_start = gem_start; 26191398Stmm ifp->if_ioctl = gem_ioctl; 26291398Stmm ifp->if_watchdog = gem_watchdog; 26391398Stmm ifp->if_init = gem_init; 26491398Stmm ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 26591398Stmm /* 26691398Stmm * Walk along the list of attached MII devices and 26791398Stmm * establish an `MII instance' to `phy number' 26891398Stmm * mapping. We'll use this mapping in media change 26991398Stmm * requests to determine which phy to use to program 27091398Stmm * the MIF configuration register. 27191398Stmm */ 27291398Stmm for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 27391398Stmm child = LIST_NEXT(child, mii_list)) { 27491398Stmm /* 27591398Stmm * Note: we support just two PHYs: the built-in 27691398Stmm * internal device and an external on the MII 27791398Stmm * connector. 27891398Stmm */ 27991398Stmm if (child->mii_phy > 1 || child->mii_inst > 1) { 28091398Stmm device_printf(sc->sc_dev, "cannot accomodate " 28191398Stmm "MII device %s at phy %d, instance %d\n", 28291398Stmm device_get_name(child->mii_dev), 28391398Stmm child->mii_phy, child->mii_inst); 28491398Stmm continue; 28591398Stmm } 28691398Stmm 28791398Stmm sc->sc_phys[child->mii_inst] = child->mii_phy; 28891398Stmm } 28991398Stmm 29091398Stmm /* 29191398Stmm * Now select and activate the PHY we will use. 29291398Stmm * 29391398Stmm * The order of preference is External (MDI1), 29491398Stmm * Internal (MDI0), Serial Link (no MII). 29591398Stmm */ 29691398Stmm if (sc->sc_phys[1]) { 29791398Stmm#ifdef GEM_DEBUG 29891398Stmm printf("using external phy\n"); 29991398Stmm#endif 30091398Stmm sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 30191398Stmm } else { 30291398Stmm#ifdef GEM_DEBUG 30391398Stmm printf("using internal phy\n"); 30491398Stmm#endif 30591398Stmm sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 30691398Stmm } 30791398Stmm bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 30891398Stmm sc->sc_mif_config); 30991398Stmm /* Attach the interface. */ 310147256Sbrooks ether_ifattach(ifp, sc->sc_enaddr); 31191398Stmm 31291398Stmm#if notyet 31391398Stmm /* 31491398Stmm * Add a suspend hook to make sure we come back up after a 31591398Stmm * resume. 31691398Stmm */ 31791398Stmm sc->sc_powerhook = powerhook_establish(gem_power, sc); 31891398Stmm if (sc->sc_powerhook == NULL) 31991398Stmm device_printf(sc->sc_dev, "WARNING: unable to establish power " 32091398Stmm "hook\n"); 32191398Stmm#endif 32291398Stmm 32391398Stmm callout_init(&sc->sc_tick_ch, 0); 324148368Smarius#ifdef GEM_RINT_TIMEOUT 32593045Stmm callout_init(&sc->sc_rx_ch, 0); 326148368Smarius#endif 32791398Stmm return (0); 32891398Stmm 32991398Stmm /* 33091398Stmm * Free any resources we've allocated during the failed attach 33191398Stmm * attempt. Do this in reverse order and fall through. 33291398Stmm */ 333108832Stmmfail_rxd: 33491398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 33591398Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 336108832Stmm bus_dmamap_destroy(sc->sc_rdmatag, 33791398Stmm sc->sc_rxsoft[i].rxs_dmamap); 33891398Stmm } 339108832Stmmfail_txd: 34091398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 34191398Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 342108832Stmm bus_dmamap_destroy(sc->sc_tdmatag, 34391398Stmm sc->sc_txsoft[i].txs_dmamap); 34491398Stmm } 345108832Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 346108832Stmmfail_cmem: 34791398Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 34891398Stmm sc->sc_cddmamap); 349108832Stmmfail_ctag: 35091398Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 351108832Stmmfail_ttag: 352108832Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 353108832Stmmfail_rtag: 354108832Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 355108832Stmmfail_ptag: 35691398Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 357147256Sbrooksfail_ifnet: 358147256Sbrooks if_free(ifp); 35991398Stmm return (error); 36091398Stmm} 36191398Stmm 362108964Stmmvoid 363108964Stmmgem_detach(sc) 364108964Stmm struct gem_softc *sc; 365108964Stmm{ 366147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 367108964Stmm int i; 368108964Stmm 369147317Sbrooks gem_stop(ifp, 1); 370108964Stmm ether_ifdetach(ifp); 371147256Sbrooks if_free(ifp); 372108964Stmm device_delete_child(sc->sc_dev, sc->sc_miibus); 373108964Stmm 374108964Stmm for (i = 0; i < GEM_NRXDESC; i++) { 375108964Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 376108964Stmm bus_dmamap_destroy(sc->sc_rdmatag, 377108964Stmm sc->sc_rxsoft[i].rxs_dmamap); 378108964Stmm } 379108964Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 380108964Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 381108964Stmm bus_dmamap_destroy(sc->sc_tdmatag, 382108964Stmm sc->sc_txsoft[i].txs_dmamap); 383108964Stmm } 384109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 385109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE); 386108964Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 387108964Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 388108964Stmm sc->sc_cddmamap); 389108964Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 390108964Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 391108964Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 392108964Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 393108964Stmm} 394108964Stmm 395108964Stmmvoid 396108964Stmmgem_suspend(sc) 397108964Stmm struct gem_softc *sc; 398108964Stmm{ 399147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 400108964Stmm 401108964Stmm gem_stop(ifp, 0); 402108964Stmm} 403108964Stmm 404108964Stmmvoid 405108964Stmmgem_resume(sc) 406108964Stmm struct gem_softc *sc; 407108964Stmm{ 408147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 409108964Stmm 410108964Stmm if (ifp->if_flags & IFF_UP) 411108964Stmm gem_init(ifp); 412108964Stmm} 413108964Stmm 41491398Stmmstatic void 41591398Stmmgem_cddma_callback(xsc, segs, nsegs, error) 41691398Stmm void *xsc; 41791398Stmm bus_dma_segment_t *segs; 41891398Stmm int nsegs; 41991398Stmm int error; 42091398Stmm{ 42191398Stmm struct gem_softc *sc = (struct gem_softc *)xsc; 42291398Stmm 42391398Stmm if (error != 0) 42491398Stmm return; 42591398Stmm if (nsegs != 1) { 42691398Stmm /* can't happen... */ 42791398Stmm panic("gem_cddma_callback: bad control buffer segment count"); 42891398Stmm } 42991398Stmm sc->sc_cddma = segs[0].ds_addr; 43091398Stmm} 43191398Stmm 43291398Stmmstatic void 433108832Stmmgem_txdma_callback(xsc, segs, nsegs, totsz, error) 43491398Stmm void *xsc; 43591398Stmm bus_dma_segment_t *segs; 43691398Stmm int nsegs; 437108832Stmm bus_size_t totsz; 43891398Stmm int error; 43991398Stmm{ 440108832Stmm struct gem_txdma *txd = (struct gem_txdma *)xsc; 441108832Stmm struct gem_softc *sc = txd->txd_sc; 442108832Stmm struct gem_txsoft *txs = txd->txd_txs; 443108832Stmm bus_size_t len = 0; 444108832Stmm uint64_t flags = 0; 445108832Stmm int seg, nexttx; 44691398Stmm 44791398Stmm if (error != 0) 44891398Stmm return; 449108832Stmm /* 450108832Stmm * Ensure we have enough descriptors free to describe 451108832Stmm * the packet. Note, we always reserve one descriptor 452108832Stmm * at the end of the ring as a termination point, to 453108832Stmm * prevent wrap-around. 454108832Stmm */ 455108832Stmm if (nsegs > sc->sc_txfree - 1) { 456108832Stmm txs->txs_ndescs = -1; 457108832Stmm return; 458108832Stmm } 459108832Stmm txs->txs_ndescs = nsegs; 46091398Stmm 461108832Stmm nexttx = txs->txs_firstdesc; 46291398Stmm /* 46391398Stmm * Initialize the transmit descriptors. 46491398Stmm */ 46591398Stmm for (seg = 0; seg < nsegs; 466108832Stmm seg++, nexttx = GEM_NEXTTX(nexttx)) { 467115030Stmm#ifdef GEM_DEBUG 46891398Stmm CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 469108832Stmm "%lx, addr %#lx (%#lx)", seg, nexttx, 47091398Stmm segs[seg].ds_len, segs[seg].ds_addr, 471108832Stmm GEM_DMA_WRITE(sc, segs[seg].ds_addr)); 472115030Stmm#endif 473108832Stmm 474108832Stmm if (segs[seg].ds_len == 0) 475108832Stmm continue; 476108832Stmm sc->sc_txdescs[nexttx].gd_addr = 477108832Stmm GEM_DMA_WRITE(sc, segs[seg].ds_addr); 478108832Stmm KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE, 479108832Stmm ("gem_txdma_callback: segment size too large!")); 48091398Stmm flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 481108832Stmm if (len == 0) { 482115030Stmm#ifdef GEM_DEBUG 48391398Stmm CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 484108832Stmm "tx %d", seg, nexttx); 485115030Stmm#endif 48691398Stmm flags |= GEM_TD_START_OF_PACKET; 487108832Stmm if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 488108832Stmm sc->sc_txwin = 0; 48999726Sbenno flags |= GEM_TD_INTERRUPT_ME; 49099726Sbenno } 49191398Stmm } 492108832Stmm if (len + segs[seg].ds_len == totsz) { 493115030Stmm#ifdef GEM_DEBUG 49491398Stmm CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 495108832Stmm "tx %d", seg, nexttx); 496115030Stmm#endif 49791398Stmm flags |= GEM_TD_END_OF_PACKET; 49891398Stmm } 499108832Stmm sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags); 500108832Stmm txs->txs_lastdesc = nexttx; 501108832Stmm len += segs[seg].ds_len; 50291398Stmm } 503108832Stmm KASSERT((flags & GEM_TD_END_OF_PACKET) != 0, 504108832Stmm ("gem_txdma_callback: missed end of packet!")); 50591398Stmm} 50691398Stmm 50791398Stmmstatic void 50891398Stmmgem_tick(arg) 50991398Stmm void *arg; 51091398Stmm{ 51191398Stmm struct gem_softc *sc = arg; 51291398Stmm int s; 51391398Stmm 51491398Stmm s = splnet(); 51591398Stmm mii_tick(sc->sc_mii); 51691398Stmm splx(s); 51791398Stmm 51891398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 51991398Stmm} 52091398Stmm 52191398Stmmstatic int 52291398Stmmgem_bitwait(sc, r, clr, set) 52391398Stmm struct gem_softc *sc; 52491398Stmm bus_addr_t r; 52591398Stmm u_int32_t clr; 52691398Stmm u_int32_t set; 52791398Stmm{ 52891398Stmm int i; 52991398Stmm u_int32_t reg; 53091398Stmm 53191398Stmm for (i = TRIES; i--; DELAY(100)) { 53291398Stmm reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 53391398Stmm if ((r & clr) == 0 && (r & set) == set) 53491398Stmm return (1); 53591398Stmm } 53691398Stmm return (0); 53791398Stmm} 53891398Stmm 53991398Stmmvoid 54091398Stmmgem_reset(sc) 54191398Stmm struct gem_softc *sc; 54291398Stmm{ 54391398Stmm bus_space_tag_t t = sc->sc_bustag; 54491398Stmm bus_space_handle_t h = sc->sc_h; 54591398Stmm int s; 54691398Stmm 54791398Stmm s = splnet(); 548115030Stmm#ifdef GEM_DEBUG 54991398Stmm CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 550115030Stmm#endif 55191398Stmm gem_reset_rx(sc); 55291398Stmm gem_reset_tx(sc); 55391398Stmm 55491398Stmm /* Do a full reset */ 55591398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 55691398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 55791398Stmm device_printf(sc->sc_dev, "cannot reset device\n"); 55891398Stmm splx(s); 55991398Stmm} 56091398Stmm 56191398Stmm 56291398Stmm/* 56391398Stmm * gem_rxdrain: 56491398Stmm * 56591398Stmm * Drain the receive queue. 56691398Stmm */ 56791398Stmmstatic void 56891398Stmmgem_rxdrain(sc) 56991398Stmm struct gem_softc *sc; 57091398Stmm{ 57191398Stmm struct gem_rxsoft *rxs; 57291398Stmm int i; 57391398Stmm 57491398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 57591398Stmm rxs = &sc->sc_rxsoft[i]; 57691398Stmm if (rxs->rxs_mbuf != NULL) { 577109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 578109648Stmm BUS_DMASYNC_POSTREAD); 579108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 58091398Stmm m_freem(rxs->rxs_mbuf); 58191398Stmm rxs->rxs_mbuf = NULL; 58291398Stmm } 58391398Stmm } 58491398Stmm} 58591398Stmm 58691398Stmm/* 58791398Stmm * Reset the whole thing. 58891398Stmm */ 58991398Stmmstatic void 59091398Stmmgem_stop(ifp, disable) 59191398Stmm struct ifnet *ifp; 59291398Stmm int disable; 59391398Stmm{ 59491398Stmm struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 59591398Stmm struct gem_txsoft *txs; 59691398Stmm 597115030Stmm#ifdef GEM_DEBUG 59891398Stmm CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 599115030Stmm#endif 60091398Stmm 60191398Stmm callout_stop(&sc->sc_tick_ch); 60291398Stmm 60391398Stmm /* XXX - Should we reset these instead? */ 60491398Stmm gem_disable_tx(sc); 60591398Stmm gem_disable_rx(sc); 60691398Stmm 60791398Stmm /* 60891398Stmm * Release any queued transmit buffers. 60991398Stmm */ 61091398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 61191398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 61291398Stmm if (txs->txs_ndescs != 0) { 613109648Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 614109648Stmm BUS_DMASYNC_POSTWRITE); 615108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 61691398Stmm if (txs->txs_mbuf != NULL) { 61791398Stmm m_freem(txs->txs_mbuf); 61891398Stmm txs->txs_mbuf = NULL; 61991398Stmm } 62091398Stmm } 62191398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 62291398Stmm } 62391398Stmm 62491398Stmm if (disable) 62591398Stmm gem_rxdrain(sc); 62691398Stmm 62791398Stmm /* 62891398Stmm * Mark the interface down and cancel the watchdog timer. 62991398Stmm */ 63091398Stmm ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 63191398Stmm ifp->if_timer = 0; 63291398Stmm} 63391398Stmm 63491398Stmm/* 63591398Stmm * Reset the receiver 63691398Stmm */ 63791398Stmmint 63891398Stmmgem_reset_rx(sc) 63991398Stmm struct gem_softc *sc; 64091398Stmm{ 64191398Stmm bus_space_tag_t t = sc->sc_bustag; 64291398Stmm bus_space_handle_t h = sc->sc_h; 64391398Stmm 64491398Stmm /* 64591398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 64691398Stmm * disable DMA first. 64791398Stmm */ 64891398Stmm gem_disable_rx(sc); 64991398Stmm bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 65091398Stmm /* Wait till it finishes */ 65191398Stmm if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 65291398Stmm device_printf(sc->sc_dev, "cannot disable read dma\n"); 65391398Stmm 65491398Stmm /* Wait 5ms extra. */ 65591398Stmm DELAY(5000); 65691398Stmm 65791398Stmm /* Finally, reset the ERX */ 65891398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 65991398Stmm /* Wait till it finishes */ 66091398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 66191398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 66291398Stmm return (1); 66391398Stmm } 66491398Stmm return (0); 66591398Stmm} 66691398Stmm 66791398Stmm 66891398Stmm/* 66991398Stmm * Reset the transmitter 67091398Stmm */ 67191398Stmmstatic int 67291398Stmmgem_reset_tx(sc) 67391398Stmm struct gem_softc *sc; 67491398Stmm{ 67591398Stmm bus_space_tag_t t = sc->sc_bustag; 67691398Stmm bus_space_handle_t h = sc->sc_h; 67791398Stmm int i; 67891398Stmm 67991398Stmm /* 68091398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 68191398Stmm * disable DMA first. 68291398Stmm */ 68391398Stmm gem_disable_tx(sc); 68491398Stmm bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 68591398Stmm /* Wait till it finishes */ 68691398Stmm if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 68791398Stmm device_printf(sc->sc_dev, "cannot disable read dma\n"); 68891398Stmm 68991398Stmm /* Wait 5ms extra. */ 69091398Stmm DELAY(5000); 69191398Stmm 69291398Stmm /* Finally, reset the ETX */ 69391398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 69491398Stmm /* Wait till it finishes */ 69591398Stmm for (i = TRIES; i--; DELAY(100)) 69691398Stmm if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 69791398Stmm break; 69891398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 69991398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 70091398Stmm return (1); 70191398Stmm } 70291398Stmm return (0); 70391398Stmm} 70491398Stmm 70591398Stmm/* 70691398Stmm * disable receiver. 70791398Stmm */ 70891398Stmmstatic int 70991398Stmmgem_disable_rx(sc) 71091398Stmm struct gem_softc *sc; 71191398Stmm{ 71291398Stmm bus_space_tag_t t = sc->sc_bustag; 71391398Stmm bus_space_handle_t h = sc->sc_h; 71491398Stmm u_int32_t cfg; 71591398Stmm 71691398Stmm /* Flip the enable bit */ 71791398Stmm cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 71891398Stmm cfg &= ~GEM_MAC_RX_ENABLE; 71991398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 72091398Stmm 72191398Stmm /* Wait for it to finish */ 72291398Stmm return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 72391398Stmm} 72491398Stmm 72591398Stmm/* 72691398Stmm * disable transmitter. 72791398Stmm */ 72891398Stmmstatic int 72991398Stmmgem_disable_tx(sc) 73091398Stmm struct gem_softc *sc; 73191398Stmm{ 73291398Stmm bus_space_tag_t t = sc->sc_bustag; 73391398Stmm bus_space_handle_t h = sc->sc_h; 73491398Stmm u_int32_t cfg; 73591398Stmm 73691398Stmm /* Flip the enable bit */ 73791398Stmm cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 73891398Stmm cfg &= ~GEM_MAC_TX_ENABLE; 73991398Stmm bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 74091398Stmm 74191398Stmm /* Wait for it to finish */ 74291398Stmm return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 74391398Stmm} 74491398Stmm 74591398Stmm/* 74691398Stmm * Initialize interface. 74791398Stmm */ 74891398Stmmstatic int 74991398Stmmgem_meminit(sc) 75091398Stmm struct gem_softc *sc; 75191398Stmm{ 75291398Stmm struct gem_rxsoft *rxs; 75391398Stmm int i, error; 75491398Stmm 75591398Stmm /* 75691398Stmm * Initialize the transmit descriptor ring. 75791398Stmm */ 75891398Stmm memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 75991398Stmm for (i = 0; i < GEM_NTXDESC; i++) { 76091398Stmm sc->sc_txdescs[i].gd_flags = 0; 76191398Stmm sc->sc_txdescs[i].gd_addr = 0; 76291398Stmm } 763108832Stmm sc->sc_txfree = GEM_MAXTXFREE; 76491398Stmm sc->sc_txnext = 0; 76599726Sbenno sc->sc_txwin = 0; 76691398Stmm 76791398Stmm /* 76891398Stmm * Initialize the receive descriptor and receive job 76991398Stmm * descriptor rings. 77091398Stmm */ 77191398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 77291398Stmm rxs = &sc->sc_rxsoft[i]; 77391398Stmm if (rxs->rxs_mbuf == NULL) { 77491398Stmm if ((error = gem_add_rxbuf(sc, i)) != 0) { 77591398Stmm device_printf(sc->sc_dev, "unable to " 77691398Stmm "allocate or map rx buffer %d, error = " 77791398Stmm "%d\n", i, error); 77891398Stmm /* 77991398Stmm * XXX Should attempt to run with fewer receive 78091398Stmm * XXX buffers instead of just failing. 78191398Stmm */ 78291398Stmm gem_rxdrain(sc); 78391398Stmm return (1); 78491398Stmm } 78591398Stmm } else 78691398Stmm GEM_INIT_RXDESC(sc, i); 78791398Stmm } 78891398Stmm sc->sc_rxptr = 0; 789109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 790109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 79191398Stmm 79291398Stmm return (0); 79391398Stmm} 79491398Stmm 79591398Stmmstatic int 79691398Stmmgem_ringsize(sz) 79791398Stmm int sz; 79891398Stmm{ 79991398Stmm int v = 0; 80091398Stmm 80191398Stmm switch (sz) { 80291398Stmm case 32: 80391398Stmm v = GEM_RING_SZ_32; 80491398Stmm break; 80591398Stmm case 64: 80691398Stmm v = GEM_RING_SZ_64; 80791398Stmm break; 80891398Stmm case 128: 80991398Stmm v = GEM_RING_SZ_128; 81091398Stmm break; 81191398Stmm case 256: 81291398Stmm v = GEM_RING_SZ_256; 81391398Stmm break; 81491398Stmm case 512: 81591398Stmm v = GEM_RING_SZ_512; 81691398Stmm break; 81791398Stmm case 1024: 81891398Stmm v = GEM_RING_SZ_1024; 81991398Stmm break; 82091398Stmm case 2048: 82191398Stmm v = GEM_RING_SZ_2048; 82291398Stmm break; 82391398Stmm case 4096: 82491398Stmm v = GEM_RING_SZ_4096; 82591398Stmm break; 82691398Stmm case 8192: 82791398Stmm v = GEM_RING_SZ_8192; 82891398Stmm break; 82991398Stmm default: 83091398Stmm printf("gem: invalid Receive Descriptor ring size\n"); 83191398Stmm break; 83291398Stmm } 83391398Stmm return (v); 83491398Stmm} 83591398Stmm 83691398Stmm/* 83791398Stmm * Initialization of interface; set up initialization block 83891398Stmm * and transmit/receive descriptor rings. 83991398Stmm */ 84091398Stmmstatic void 84191398Stmmgem_init(xsc) 84291398Stmm void *xsc; 84391398Stmm{ 84491398Stmm struct gem_softc *sc = (struct gem_softc *)xsc; 845147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 84691398Stmm bus_space_tag_t t = sc->sc_bustag; 84791398Stmm bus_space_handle_t h = sc->sc_h; 84891398Stmm int s; 84991398Stmm u_int32_t v; 85091398Stmm 85191398Stmm s = splnet(); 85291398Stmm 853115030Stmm#ifdef GEM_DEBUG 85491398Stmm CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 855115030Stmm#endif 85691398Stmm /* 85791398Stmm * Initialization sequence. The numbered steps below correspond 85891398Stmm * to the sequence outlined in section 6.3.5.1 in the Ethernet 85991398Stmm * Channel Engine manual (part of the PCIO manual). 86091398Stmm * See also the STP2002-STQ document from Sun Microsystems. 86191398Stmm */ 86291398Stmm 86391398Stmm /* step 1 & 2. Reset the Ethernet Channel */ 864147256Sbrooks gem_stop(sc->sc_ifp, 0); 86591398Stmm gem_reset(sc); 866115030Stmm#ifdef GEM_DEBUG 86791398Stmm CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 868115030Stmm#endif 86991398Stmm 87091398Stmm /* Re-initialize the MIF */ 87191398Stmm gem_mifinit(sc); 87291398Stmm 87391398Stmm /* step 3. Setup data structures in host memory */ 87491398Stmm gem_meminit(sc); 87591398Stmm 87691398Stmm /* step 4. TX MAC registers & counters */ 87791398Stmm gem_init_regs(sc); 87891398Stmm /* XXX: VLAN code from NetBSD temporarily removed. */ 87991398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 88091398Stmm (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 88191398Stmm 88291398Stmm /* step 5. RX MAC registers & counters */ 88391398Stmm gem_setladrf(sc); 88491398Stmm 88591398Stmm /* step 6 & 7. Program Descriptor Ring Base Addresses */ 88691398Stmm /* NOTE: we use only 32-bit DMA addresses here. */ 88791398Stmm bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 88891398Stmm bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 88991398Stmm 89091398Stmm bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 89191398Stmm bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 892115030Stmm#ifdef GEM_DEBUG 89391398Stmm CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 89491398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 895115030Stmm#endif 89691398Stmm 89791398Stmm /* step 8. Global Configuration & Interrupt Mask */ 89891398Stmm bus_space_write_4(t, h, GEM_INTMASK, 89991398Stmm ~(GEM_INTR_TX_INTME| 90091398Stmm GEM_INTR_TX_EMPTY| 90191398Stmm GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 90291398Stmm GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 90391398Stmm GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 90491398Stmm GEM_INTR_BERR)); 90599726Sbenno bus_space_write_4(t, h, GEM_MAC_RX_MASK, 90699726Sbenno GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 90791398Stmm bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 90891398Stmm bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 90991398Stmm 91091398Stmm /* step 9. ETX Configuration: use mostly default values */ 91191398Stmm 91291398Stmm /* Enable DMA */ 91391398Stmm v = gem_ringsize(GEM_NTXDESC /*XXX*/); 91491398Stmm bus_space_write_4(t, h, GEM_TX_CONFIG, 91591398Stmm v|GEM_TX_CONFIG_TXDMA_EN| 91691398Stmm ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 91791398Stmm 91891398Stmm /* step 10. ERX Configuration */ 91991398Stmm 92091398Stmm /* Encode Receive Descriptor ring size: four possible values */ 92191398Stmm v = gem_ringsize(GEM_NRXDESC /*XXX*/); 92291398Stmm 92391398Stmm /* Enable DMA */ 92491398Stmm bus_space_write_4(t, h, GEM_RX_CONFIG, 92591398Stmm v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 92691398Stmm (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 92791398Stmm (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 92891398Stmm /* 92999726Sbenno * The following value is for an OFF Threshold of about 3/4 full 93099726Sbenno * and an ON Threshold of 1/4 full. 93191398Stmm */ 93299726Sbenno bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 93399726Sbenno (3 * sc->sc_rxfifosize / 256) | 93499726Sbenno ( (sc->sc_rxfifosize / 256) << 12)); 93599726Sbenno bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 93691398Stmm 93791398Stmm /* step 11. Configure Media */ 93899726Sbenno mii_mediachg(sc->sc_mii); 93991398Stmm 94091398Stmm /* step 12. RX_MAC Configuration Register */ 94191398Stmm v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 94291398Stmm v |= GEM_MAC_RX_ENABLE; 94391398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 94491398Stmm 94591398Stmm /* step 14. Issue Transmit Pending command */ 94691398Stmm 94791398Stmm /* step 15. Give the reciever a swift kick */ 94891398Stmm bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 94991398Stmm 95091398Stmm /* Start the one second timer. */ 95191398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 95291398Stmm 95391398Stmm ifp->if_flags |= IFF_RUNNING; 95491398Stmm ifp->if_flags &= ~IFF_OACTIVE; 95591398Stmm ifp->if_timer = 0; 95699726Sbenno sc->sc_ifflags = ifp->if_flags; 95791398Stmm splx(s); 95891398Stmm} 95991398Stmm 96091398Stmmstatic int 961108832Stmmgem_load_txmbuf(sc, m0) 96291398Stmm struct gem_softc *sc; 96391398Stmm struct mbuf *m0; 96491398Stmm{ 96591398Stmm struct gem_txdma txd; 96691398Stmm struct gem_txsoft *txs; 967108832Stmm int error; 96891398Stmm 969108832Stmm /* Get a work queue entry. */ 970108832Stmm if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 971108832Stmm /* Ran out of descriptors. */ 972108832Stmm return (-1); 973108832Stmm } 97491398Stmm txd.txd_sc = sc; 975108832Stmm txd.txd_txs = txs; 976108832Stmm txs->txs_firstdesc = sc->sc_txnext; 977108832Stmm error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0, 978108832Stmm gem_txdma_callback, &txd, BUS_DMA_NOWAIT); 979108832Stmm if (error != 0) 980108832Stmm goto fail; 981108832Stmm if (txs->txs_ndescs == -1) { 982108832Stmm error = -1; 983108832Stmm goto fail; 98491398Stmm } 98591398Stmm 986108832Stmm /* Sync the DMA map. */ 987108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 988108832Stmm BUS_DMASYNC_PREWRITE); 98991398Stmm 990115030Stmm#ifdef GEM_DEBUG 991108832Stmm CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 992108832Stmm "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 993108832Stmm txs->txs_ndescs); 994115030Stmm#endif 995108832Stmm STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 996108832Stmm STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 997148368Smarius txs->txs_mbuf = m0; 99891398Stmm 999108832Stmm sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1000108832Stmm sc->sc_txfree -= txs->txs_ndescs; 1001108832Stmm return (0); 100291398Stmm 1003108832Stmmfail: 1004115030Stmm#ifdef GEM_DEBUG 1005108832Stmm CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error); 1006115030Stmm#endif 1007108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1008108832Stmm return (error); 100991398Stmm} 101091398Stmm 101191398Stmmstatic void 101291398Stmmgem_init_regs(sc) 101391398Stmm struct gem_softc *sc; 101491398Stmm{ 101591398Stmm bus_space_tag_t t = sc->sc_bustag; 101691398Stmm bus_space_handle_t h = sc->sc_h; 1017147256Sbrooks const u_char *laddr = IFP2ENADDR(sc->sc_ifp); 101899726Sbenno u_int32_t v; 101991398Stmm 102091398Stmm /* These regs are not cleared on reset */ 102191398Stmm if (!sc->sc_inited) { 102291398Stmm 102391398Stmm /* Wooo. Magic values. */ 102491398Stmm bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 102591398Stmm bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 102691398Stmm bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 102791398Stmm 102891398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 102991398Stmm /* Max frame and max burst size */ 103091398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 103199726Sbenno ETHER_MAX_LEN | (0x2000<<16)); 103299726Sbenno 103391398Stmm bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 103491398Stmm bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 103591398Stmm bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 103691398Stmm /* Dunno.... */ 103791398Stmm bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 103891398Stmm bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 103999726Sbenno ((laddr[5]<<8)|laddr[4])&0x3ff); 104099726Sbenno 104191398Stmm /* Secondary MAC addr set to 0:0:0:0:0:0 */ 104291398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 104391398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 104491398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 104599726Sbenno 104699726Sbenno /* MAC control addr set to 01:80:c2:00:00:01 */ 104791398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 104891398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 104991398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 105091398Stmm 105191398Stmm /* MAC filter addr set to 0:0:0:0:0:0 */ 105291398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 105391398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 105491398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 105591398Stmm 105691398Stmm bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 105791398Stmm bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 105891398Stmm 105991398Stmm sc->sc_inited = 1; 106091398Stmm } 106191398Stmm 106291398Stmm /* Counters need to be zeroed */ 106391398Stmm bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 106491398Stmm bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 106591398Stmm bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 106691398Stmm bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 106791398Stmm bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 106891398Stmm bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 106991398Stmm bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 107091398Stmm bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 107191398Stmm bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 107291398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 107391398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 107491398Stmm 107591398Stmm /* Un-pause stuff */ 107691398Stmm#if 0 107791398Stmm bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 107891398Stmm#else 107991398Stmm bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 108091398Stmm#endif 108191398Stmm 108291398Stmm /* 108391398Stmm * Set the station address. 108491398Stmm */ 108599726Sbenno bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 108699726Sbenno bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 108799726Sbenno bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 108899726Sbenno 108999726Sbenno /* 109099726Sbenno * Enable MII outputs. Enable GMII if there is a gigabit PHY. 109199726Sbenno */ 109299726Sbenno sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 109399726Sbenno v = GEM_MAC_XIF_TX_MII_ENA; 109499726Sbenno if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 109599726Sbenno v |= GEM_MAC_XIF_FDPLX_LED; 109699726Sbenno if (sc->sc_flags & GEM_GIGABIT) 109799726Sbenno v |= GEM_MAC_XIF_GMII_MODE; 109899726Sbenno } 109999726Sbenno bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 110091398Stmm} 110191398Stmm 110291398Stmmstatic void 110391398Stmmgem_start(ifp) 110491398Stmm struct ifnet *ifp; 110591398Stmm{ 110691398Stmm struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1107108832Stmm struct mbuf *m0 = NULL; 1108115030Stmm int firsttx, ntx = 0, ofree, txmfail; 110991398Stmm 111091398Stmm if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 111191398Stmm return; 111291398Stmm 111391398Stmm /* 111491398Stmm * Remember the previous number of free descriptors and 111591398Stmm * the first descriptor we'll use. 111691398Stmm */ 111791398Stmm ofree = sc->sc_txfree; 111891398Stmm firsttx = sc->sc_txnext; 111991398Stmm 1120115030Stmm#ifdef GEM_DEBUG 112191398Stmm CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 112291398Stmm device_get_name(sc->sc_dev), ofree, firsttx); 1123115030Stmm#endif 112491398Stmm 112591398Stmm /* 112691398Stmm * Loop through the send queue, setting up transmit descriptors 112791398Stmm * until we drain the queue, or use up all available transmit 112891398Stmm * descriptors. 112991398Stmm */ 113091398Stmm txmfail = 0; 1131115030Stmm do { 113291398Stmm /* 113391398Stmm * Grab a packet off the queue. 113491398Stmm */ 113591398Stmm IF_DEQUEUE(&ifp->if_snd, m0); 113691398Stmm if (m0 == NULL) 113791398Stmm break; 113891398Stmm 1139108832Stmm txmfail = gem_load_txmbuf(sc, m0); 114091398Stmm if (txmfail > 0) { 1141108832Stmm /* Drop the mbuf and complain. */ 1142108832Stmm printf("gem_start: error %d while loading mbuf dma " 1143108832Stmm "map\n", txmfail); 1144108832Stmm continue; 114591398Stmm } 1146108832Stmm /* Not enough descriptors. */ 1147108832Stmm if (txmfail == -1) { 1148108832Stmm if (sc->sc_txfree == GEM_MAXTXFREE) 1149108832Stmm panic("gem_start: mbuf chain too long!"); 115091398Stmm IF_PREPEND(&ifp->if_snd, m0); 115191398Stmm break; 115291398Stmm } 115391398Stmm 1154115030Stmm ntx++; 1155108832Stmm /* Kick the transmitter. */ 1156115030Stmm#ifdef GEM_DEBUG 1157108832Stmm CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1158108832Stmm device_get_name(sc->sc_dev), sc->sc_txnext); 1159115030Stmm#endif 1160108832Stmm bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1161108832Stmm sc->sc_txnext); 1162108832Stmm 1163105982Stmm if (ifp->if_bpf != NULL) 1164106950Smux bpf_mtap(ifp->if_bpf, m0); 1165115030Stmm } while (1); 116691398Stmm 116791398Stmm if (txmfail == -1 || sc->sc_txfree == 0) { 1168108832Stmm /* No more slots left; notify upper layer. */ 116991398Stmm ifp->if_flags |= IFF_OACTIVE; 117091398Stmm } 117191398Stmm 117291398Stmm if (ntx > 0) { 1173109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1174109648Stmm 1175115030Stmm#ifdef GEM_DEBUG 1176108832Stmm CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1177108832Stmm device_get_name(sc->sc_dev), firsttx); 1178115030Stmm#endif 117991398Stmm 118091398Stmm /* Set a watchdog timer in case the chip flakes out. */ 118191398Stmm ifp->if_timer = 5; 1182115030Stmm#ifdef GEM_DEBUG 118391398Stmm CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 118491398Stmm device_get_name(sc->sc_dev), ifp->if_timer); 1185115030Stmm#endif 118691398Stmm } 118791398Stmm} 118891398Stmm 118991398Stmm/* 119091398Stmm * Transmit interrupt. 119191398Stmm */ 119291398Stmmstatic void 119391398Stmmgem_tint(sc) 119491398Stmm struct gem_softc *sc; 119591398Stmm{ 1196147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 119791398Stmm bus_space_tag_t t = sc->sc_bustag; 119891398Stmm bus_space_handle_t mac = sc->sc_h; 119991398Stmm struct gem_txsoft *txs; 120091398Stmm int txlast; 120199726Sbenno int progress = 0; 120291398Stmm 120391398Stmm 1204115030Stmm#ifdef GEM_DEBUG 120591398Stmm CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 1206115030Stmm#endif 120791398Stmm 120891398Stmm /* 120991398Stmm * Unload collision counters 121091398Stmm */ 121191398Stmm ifp->if_collisions += 121291398Stmm bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 121391398Stmm bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 121491398Stmm bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 121591398Stmm bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 121691398Stmm 121791398Stmm /* 121891398Stmm * then clear the hardware counters. 121991398Stmm */ 122091398Stmm bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 122191398Stmm bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 122291398Stmm bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 122391398Stmm bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 122491398Stmm 122591398Stmm /* 122691398Stmm * Go through our Tx list and free mbufs for those 122791398Stmm * frames that have been transmitted. 122891398Stmm */ 1229109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 123091398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 123191398Stmm 123291398Stmm#ifdef GEM_DEBUG 123391398Stmm if (ifp->if_flags & IFF_DEBUG) { 123491398Stmm int i; 123591398Stmm printf(" txsoft %p transmit chain:\n", txs); 123691398Stmm for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 123791398Stmm printf("descriptor %d: ", i); 123891398Stmm printf("gd_flags: 0x%016llx\t", (long long) 123991398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 124091398Stmm printf("gd_addr: 0x%016llx\n", (long long) 124191398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 124291398Stmm if (i == txs->txs_lastdesc) 124391398Stmm break; 124491398Stmm } 124591398Stmm } 124691398Stmm#endif 124791398Stmm 124891398Stmm /* 124991398Stmm * In theory, we could harveast some descriptors before 125091398Stmm * the ring is empty, but that's a bit complicated. 125191398Stmm * 125291398Stmm * GEM_TX_COMPLETION points to the last descriptor 125391398Stmm * processed +1. 125491398Stmm */ 125591398Stmm txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1256115030Stmm#ifdef GEM_DEBUG 125791398Stmm CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 125891398Stmm "txs->txs_lastdesc = %d, txlast = %d", 125991398Stmm txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1260115030Stmm#endif 126191398Stmm if (txs->txs_firstdesc <= txs->txs_lastdesc) { 126291398Stmm if ((txlast >= txs->txs_firstdesc) && 126391398Stmm (txlast <= txs->txs_lastdesc)) 126491398Stmm break; 126591398Stmm } else { 126691398Stmm /* Ick -- this command wraps */ 126791398Stmm if ((txlast >= txs->txs_firstdesc) || 126891398Stmm (txlast <= txs->txs_lastdesc)) 126991398Stmm break; 127091398Stmm } 127191398Stmm 1272115030Stmm#ifdef GEM_DEBUG 127391398Stmm CTR0(KTR_GEM, "gem_tint: releasing a desc"); 1274115030Stmm#endif 127591398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 127691398Stmm 127791398Stmm sc->sc_txfree += txs->txs_ndescs; 127891398Stmm 1279108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 128091398Stmm BUS_DMASYNC_POSTWRITE); 1281108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 128291398Stmm if (txs->txs_mbuf != NULL) { 128391398Stmm m_freem(txs->txs_mbuf); 128491398Stmm txs->txs_mbuf = NULL; 128591398Stmm } 128691398Stmm 128791398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 128891398Stmm 128991398Stmm ifp->if_opackets++; 129099726Sbenno progress = 1; 129191398Stmm } 129291398Stmm 1293115030Stmm#ifdef GEM_DEBUG 129491398Stmm CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 129591398Stmm "GEM_TX_DATA_PTR %llx " 129691398Stmm "GEM_TX_COMPLETION %x", 129791398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 129891398Stmm ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 129991398Stmm GEM_TX_DATA_PTR_HI) << 32) | 130091398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, 130191398Stmm GEM_TX_DATA_PTR_LO), 130291398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 1303115030Stmm#endif 130491398Stmm 130599726Sbenno if (progress) { 130699726Sbenno if (sc->sc_txfree == GEM_NTXDESC - 1) 130799726Sbenno sc->sc_txwin = 0; 130891398Stmm 130999726Sbenno /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 131099726Sbenno ifp->if_flags &= ~IFF_OACTIVE; 131199726Sbenno gem_start(ifp); 131291398Stmm 131399726Sbenno if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 131499726Sbenno ifp->if_timer = 0; 131599726Sbenno } 131699726Sbenno 1317115030Stmm#ifdef GEM_DEBUG 131891398Stmm CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 131991398Stmm device_get_name(sc->sc_dev), ifp->if_timer); 1320115030Stmm#endif 132191398Stmm} 132291398Stmm 1323148368Smarius#ifdef GEM_RINT_TIMEOUT 132493045Stmmstatic void 132593045Stmmgem_rint_timeout(arg) 132693045Stmm void *arg; 132793045Stmm{ 132893045Stmm 132993045Stmm gem_rint((struct gem_softc *)arg); 133093045Stmm} 1331100587Sjake#endif 133293045Stmm 133391398Stmm/* 133491398Stmm * Receive interrupt. 133591398Stmm */ 133691398Stmmstatic void 133791398Stmmgem_rint(sc) 133891398Stmm struct gem_softc *sc; 133991398Stmm{ 1340147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 134191398Stmm bus_space_tag_t t = sc->sc_bustag; 134291398Stmm bus_space_handle_t h = sc->sc_h; 134391398Stmm struct gem_rxsoft *rxs; 134491398Stmm struct mbuf *m; 134591398Stmm u_int64_t rxstat; 134699726Sbenno u_int32_t rxcomp; 134799726Sbenno int i, len, progress = 0; 134891398Stmm 1349148368Smarius#ifdef GEM_RINT_TIMEOUT 135093045Stmm callout_stop(&sc->sc_rx_ch); 1351148368Smarius#endif 1352115030Stmm#ifdef GEM_DEBUG 135391398Stmm CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 1354115030Stmm#endif 135599726Sbenno 135691398Stmm /* 135799726Sbenno * Read the completion register once. This limits 135899726Sbenno * how long the following loop can execute. 135999726Sbenno */ 136099726Sbenno rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 136199726Sbenno 1362115030Stmm#ifdef GEM_DEBUG 136391398Stmm CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 136499726Sbenno sc->sc_rxptr, rxcomp); 1365115030Stmm#endif 1366109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 136799726Sbenno for (i = sc->sc_rxptr; i != rxcomp; 136891398Stmm i = GEM_NEXTRX(i)) { 136991398Stmm rxs = &sc->sc_rxsoft[i]; 137091398Stmm 137191398Stmm rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 137291398Stmm 137391398Stmm if (rxstat & GEM_RD_OWN) { 1374148368Smarius#ifdef GEM_RINT_TIMEOUT 137591398Stmm /* 137693045Stmm * The descriptor is still marked as owned, although 137793045Stmm * it is supposed to have completed. This has been 137893045Stmm * observed on some machines. Just exiting here 137993045Stmm * might leave the packet sitting around until another 138093045Stmm * one arrives to trigger a new interrupt, which is 138193045Stmm * generally undesirable, so set up a timeout. 138291398Stmm */ 138393045Stmm callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 138493045Stmm gem_rint_timeout, sc); 138599726Sbenno#endif 138691398Stmm break; 138791398Stmm } 138891398Stmm 138999726Sbenno progress++; 139099726Sbenno ifp->if_ipackets++; 139199726Sbenno 139291398Stmm if (rxstat & GEM_RD_BAD_CRC) { 139399726Sbenno ifp->if_ierrors++; 139491398Stmm device_printf(sc->sc_dev, "receive error: CRC error\n"); 139591398Stmm GEM_INIT_RXDESC(sc, i); 139691398Stmm continue; 139791398Stmm } 139891398Stmm 139991398Stmm#ifdef GEM_DEBUG 140091398Stmm if (ifp->if_flags & IFF_DEBUG) { 140191398Stmm printf(" rxsoft %p descriptor %d: ", rxs, i); 140291398Stmm printf("gd_flags: 0x%016llx\t", (long long) 140391398Stmm GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 140491398Stmm printf("gd_addr: 0x%016llx\n", (long long) 140591398Stmm GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 140691398Stmm } 140791398Stmm#endif 140891398Stmm 140991398Stmm /* 141091398Stmm * No errors; receive the packet. Note the Gem 141191398Stmm * includes the CRC with every packet. 141291398Stmm */ 141391398Stmm len = GEM_RD_BUFLEN(rxstat); 141491398Stmm 141591398Stmm /* 141691398Stmm * Allocate a new mbuf cluster. If that fails, we are 141791398Stmm * out of memory, and must drop the packet and recycle 141891398Stmm * the buffer that's already attached to this descriptor. 141991398Stmm */ 142091398Stmm m = rxs->rxs_mbuf; 142191398Stmm if (gem_add_rxbuf(sc, i) != 0) { 142291398Stmm ifp->if_ierrors++; 142391398Stmm GEM_INIT_RXDESC(sc, i); 142491398Stmm continue; 142591398Stmm } 142691398Stmm m->m_data += 2; /* We're already off by two */ 142791398Stmm 142891398Stmm m->m_pkthdr.rcvif = ifp; 142991398Stmm m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 143091398Stmm 143191398Stmm /* Pass it on. */ 1432106937Ssam (*ifp->if_input)(ifp, m); 143391398Stmm } 143491398Stmm 143599726Sbenno if (progress) { 1436109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 143799726Sbenno /* Update the receive pointer. */ 143899726Sbenno if (i == sc->sc_rxptr) { 143999726Sbenno device_printf(sc->sc_dev, "rint: ring wrap\n"); 144099726Sbenno } 144199726Sbenno sc->sc_rxptr = i; 144299726Sbenno bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 144399726Sbenno } 144491398Stmm 1445115030Stmm#ifdef GEM_DEBUG 144691398Stmm CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 144791398Stmm sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 1448115030Stmm#endif 144991398Stmm} 145091398Stmm 145191398Stmm 145291398Stmm/* 145391398Stmm * gem_add_rxbuf: 145491398Stmm * 145591398Stmm * Add a receive buffer to the indicated descriptor. 145691398Stmm */ 145791398Stmmstatic int 145891398Stmmgem_add_rxbuf(sc, idx) 145991398Stmm struct gem_softc *sc; 146091398Stmm int idx; 146191398Stmm{ 146291398Stmm struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 146391398Stmm struct mbuf *m; 1464148368Smarius bus_dma_segment_t segs[1]; 1465148368Smarius int error, nsegs; 146691398Stmm 1467111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 146891398Stmm if (m == NULL) 146991398Stmm return (ENOBUFS); 1470108832Stmm m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 147191398Stmm 147291398Stmm#ifdef GEM_DEBUG 147391398Stmm /* bzero the packet to check dma */ 147491398Stmm memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 147591398Stmm#endif 147691398Stmm 1477109648Stmm if (rxs->rxs_mbuf != NULL) { 1478109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1479109648Stmm BUS_DMASYNC_POSTREAD); 1480108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1481109648Stmm } 148291398Stmm 148391398Stmm rxs->rxs_mbuf = m; 148491398Stmm 1485148368Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1486148368Smarius m, segs, &nsegs, BUS_DMA_NOWAIT); 1487148368Smarius /* If nsegs is wrong then the stack is corrupt. */ 1488148368Smarius KASSERT(nsegs == 1, ("Too many segments returned!")); 1489148368Smarius if (error != 0) { 149091398Stmm device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 149191398Stmm "%d\n", idx, error); 1492148368Smarius m_freem(m); 1493148368Smarius return (ENOBUFS); 149491398Stmm } 1495148368Smarius rxs->rxs_paddr = segs[0].ds_addr; 149691398Stmm 1497108832Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 149891398Stmm 149991398Stmm GEM_INIT_RXDESC(sc, idx); 150091398Stmm 150191398Stmm return (0); 150291398Stmm} 150391398Stmm 150491398Stmm 150591398Stmmstatic void 150691398Stmmgem_eint(sc, status) 150791398Stmm struct gem_softc *sc; 150891398Stmm u_int status; 150991398Stmm{ 151091398Stmm 151191398Stmm if ((status & GEM_INTR_MIF) != 0) { 151291398Stmm device_printf(sc->sc_dev, "XXXlink status changed\n"); 151391398Stmm return; 151491398Stmm } 151591398Stmm 151691398Stmm device_printf(sc->sc_dev, "status=%x\n", status); 151791398Stmm} 151891398Stmm 151991398Stmm 152091398Stmmvoid 152191398Stmmgem_intr(v) 152291398Stmm void *v; 152391398Stmm{ 152491398Stmm struct gem_softc *sc = (struct gem_softc *)v; 152591398Stmm bus_space_tag_t t = sc->sc_bustag; 152691398Stmm bus_space_handle_t seb = sc->sc_h; 152791398Stmm u_int32_t status; 152891398Stmm 152991398Stmm status = bus_space_read_4(t, seb, GEM_STATUS); 1530115030Stmm#ifdef GEM_DEBUG 153191398Stmm CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 153291398Stmm device_get_name(sc->sc_dev), (status>>19), 153391398Stmm (u_int)status); 1534115030Stmm#endif 153591398Stmm 153691398Stmm if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 153791398Stmm gem_eint(sc, status); 153891398Stmm 153991398Stmm if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 154091398Stmm gem_tint(sc); 154191398Stmm 154291398Stmm if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 154391398Stmm gem_rint(sc); 154491398Stmm 154591398Stmm /* We should eventually do more than just print out error stats. */ 154691398Stmm if (status & GEM_INTR_TX_MAC) { 154791398Stmm int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 154891398Stmm if (txstat & ~GEM_MAC_TX_XMIT_DONE) 154999726Sbenno device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 155099726Sbenno txstat); 155197240Stmm if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 155297240Stmm gem_init(sc); 155391398Stmm } 155491398Stmm if (status & GEM_INTR_RX_MAC) { 155591398Stmm int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 155691398Stmm if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 155799726Sbenno device_printf(sc->sc_dev, "MAC rx fault, status %x\n", 155899726Sbenno rxstat); 155997240Stmm if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0) 156097240Stmm gem_init(sc); 156191398Stmm } 156291398Stmm} 156391398Stmm 156491398Stmm 156591398Stmmstatic void 156691398Stmmgem_watchdog(ifp) 156791398Stmm struct ifnet *ifp; 156891398Stmm{ 156991398Stmm struct gem_softc *sc = ifp->if_softc; 157091398Stmm 1571115030Stmm#ifdef GEM_DEBUG 157291398Stmm CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 157391398Stmm "GEM_MAC_RX_CONFIG %x", 157491398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 157591398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 157691398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 157791398Stmm CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 157891398Stmm "GEM_MAC_TX_CONFIG %x", 157991398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 158091398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 158191398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 1582115030Stmm#endif 158391398Stmm 158491398Stmm device_printf(sc->sc_dev, "device timeout\n"); 158591398Stmm ++ifp->if_oerrors; 158691398Stmm 158791398Stmm /* Try to get more packets going. */ 1588148368Smarius gem_init(ifp); 158991398Stmm} 159091398Stmm 159191398Stmm/* 159291398Stmm * Initialize the MII Management Interface 159391398Stmm */ 159491398Stmmstatic void 159591398Stmmgem_mifinit(sc) 159691398Stmm struct gem_softc *sc; 159791398Stmm{ 159891398Stmm bus_space_tag_t t = sc->sc_bustag; 159991398Stmm bus_space_handle_t mif = sc->sc_h; 160091398Stmm 160191398Stmm /* Configure the MIF in frame mode */ 160291398Stmm sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 160391398Stmm sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 160491398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 160591398Stmm} 160691398Stmm 160791398Stmm/* 160891398Stmm * MII interface 160991398Stmm * 161091398Stmm * The GEM MII interface supports at least three different operating modes: 161191398Stmm * 161291398Stmm * Bitbang mode is implemented using data, clock and output enable registers. 161391398Stmm * 161491398Stmm * Frame mode is implemented by loading a complete frame into the frame 161591398Stmm * register and polling the valid bit for completion. 161691398Stmm * 161791398Stmm * Polling mode uses the frame register but completion is indicated by 161891398Stmm * an interrupt. 161991398Stmm * 162091398Stmm */ 162191398Stmmint 162291398Stmmgem_mii_readreg(dev, phy, reg) 162391398Stmm device_t dev; 162491398Stmm int phy, reg; 162591398Stmm{ 162691398Stmm struct gem_softc *sc = device_get_softc(dev); 162791398Stmm bus_space_tag_t t = sc->sc_bustag; 162891398Stmm bus_space_handle_t mif = sc->sc_h; 162991398Stmm int n; 163091398Stmm u_int32_t v; 163191398Stmm 163291398Stmm#ifdef GEM_DEBUG_PHY 163391398Stmm printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 163491398Stmm#endif 163591398Stmm 163691398Stmm#if 0 163791398Stmm /* Select the desired PHY in the MIF configuration register */ 163891398Stmm v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 163991398Stmm /* Clear PHY select bit */ 164091398Stmm v &= ~GEM_MIF_CONFIG_PHY_SEL; 164191398Stmm if (phy == GEM_PHYAD_EXTERNAL) 164291398Stmm /* Set PHY select bit to get at external device */ 164391398Stmm v |= GEM_MIF_CONFIG_PHY_SEL; 164491398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 164591398Stmm#endif 164691398Stmm 164791398Stmm /* Construct the frame command */ 164891398Stmm v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 164991398Stmm GEM_MIF_FRAME_READ; 165091398Stmm 165191398Stmm bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 165291398Stmm for (n = 0; n < 100; n++) { 165391398Stmm DELAY(1); 165491398Stmm v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 165591398Stmm if (v & GEM_MIF_FRAME_TA0) 165691398Stmm return (v & GEM_MIF_FRAME_DATA); 165791398Stmm } 165891398Stmm 165991398Stmm device_printf(sc->sc_dev, "mii_read timeout\n"); 166091398Stmm return (0); 166191398Stmm} 166291398Stmm 166391398Stmmint 166491398Stmmgem_mii_writereg(dev, phy, reg, val) 166591398Stmm device_t dev; 166691398Stmm int phy, reg, val; 166791398Stmm{ 166891398Stmm struct gem_softc *sc = device_get_softc(dev); 166991398Stmm bus_space_tag_t t = sc->sc_bustag; 167091398Stmm bus_space_handle_t mif = sc->sc_h; 167191398Stmm int n; 167291398Stmm u_int32_t v; 167391398Stmm 167491398Stmm#ifdef GEM_DEBUG_PHY 167591398Stmm printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 167691398Stmm#endif 167791398Stmm 167891398Stmm#if 0 167991398Stmm /* Select the desired PHY in the MIF configuration register */ 168091398Stmm v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 168191398Stmm /* Clear PHY select bit */ 168291398Stmm v &= ~GEM_MIF_CONFIG_PHY_SEL; 168391398Stmm if (phy == GEM_PHYAD_EXTERNAL) 168491398Stmm /* Set PHY select bit to get at external device */ 168591398Stmm v |= GEM_MIF_CONFIG_PHY_SEL; 168691398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 168791398Stmm#endif 168891398Stmm /* Construct the frame command */ 168991398Stmm v = GEM_MIF_FRAME_WRITE | 169091398Stmm (phy << GEM_MIF_PHY_SHIFT) | 169191398Stmm (reg << GEM_MIF_REG_SHIFT) | 169291398Stmm (val & GEM_MIF_FRAME_DATA); 169391398Stmm 169491398Stmm bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 169591398Stmm for (n = 0; n < 100; n++) { 169691398Stmm DELAY(1); 169791398Stmm v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 169891398Stmm if (v & GEM_MIF_FRAME_TA0) 169991398Stmm return (1); 170091398Stmm } 170191398Stmm 170291398Stmm device_printf(sc->sc_dev, "mii_write timeout\n"); 170391398Stmm return (0); 170491398Stmm} 170591398Stmm 170691398Stmmvoid 170791398Stmmgem_mii_statchg(dev) 170891398Stmm device_t dev; 170991398Stmm{ 171091398Stmm struct gem_softc *sc = device_get_softc(dev); 171191398Stmm#ifdef GEM_DEBUG 171291398Stmm int instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 171391398Stmm#endif 171491398Stmm bus_space_tag_t t = sc->sc_bustag; 171591398Stmm bus_space_handle_t mac = sc->sc_h; 171691398Stmm u_int32_t v; 171791398Stmm 171891398Stmm#ifdef GEM_DEBUG 171991398Stmm if (sc->sc_debug) 172091398Stmm printf("gem_mii_statchg: status change: phy = %d\n", 172191398Stmm sc->sc_phys[instance]); 172291398Stmm#endif 172391398Stmm 172491398Stmm /* Set tx full duplex options */ 172591398Stmm bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 172691398Stmm DELAY(10000); /* reg must be cleared and delay before changing. */ 172791398Stmm v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 172891398Stmm GEM_MAC_TX_ENABLE; 172991398Stmm if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 173091398Stmm v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 173191398Stmm } 173291398Stmm bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 173391398Stmm 173491398Stmm /* XIF Configuration */ 173591398Stmm v = GEM_MAC_XIF_LINK_LED; 173691398Stmm v |= GEM_MAC_XIF_TX_MII_ENA; 173799726Sbenno 173891398Stmm /* If an external transceiver is connected, enable its MII drivers */ 173991398Stmm sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 174091398Stmm if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 174191398Stmm /* External MII needs echo disable if half duplex. */ 174291398Stmm if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 174391398Stmm /* turn on full duplex LED */ 174491398Stmm v |= GEM_MAC_XIF_FDPLX_LED; 174599726Sbenno else 174699726Sbenno /* half duplex -- disable echo */ 174799726Sbenno v |= GEM_MAC_XIF_ECHO_DISABL; 174899726Sbenno 174999726Sbenno if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 175099726Sbenno v |= GEM_MAC_XIF_GMII_MODE; 175199726Sbenno else 175299726Sbenno v &= ~GEM_MAC_XIF_GMII_MODE; 175391398Stmm } else { 175491398Stmm /* Internal MII needs buf enable */ 175591398Stmm v |= GEM_MAC_XIF_MII_BUF_ENA; 175691398Stmm } 175791398Stmm bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 175891398Stmm} 175991398Stmm 176091398Stmmint 176191398Stmmgem_mediachange(ifp) 176291398Stmm struct ifnet *ifp; 176391398Stmm{ 176491398Stmm struct gem_softc *sc = ifp->if_softc; 176591398Stmm 176691398Stmm /* XXX Add support for serial media. */ 176791398Stmm 176891398Stmm return (mii_mediachg(sc->sc_mii)); 176991398Stmm} 177091398Stmm 177191398Stmmvoid 177291398Stmmgem_mediastatus(ifp, ifmr) 177391398Stmm struct ifnet *ifp; 177491398Stmm struct ifmediareq *ifmr; 177591398Stmm{ 177691398Stmm struct gem_softc *sc = ifp->if_softc; 177791398Stmm 177891398Stmm if ((ifp->if_flags & IFF_UP) == 0) 177991398Stmm return; 178091398Stmm 178191398Stmm mii_pollstat(sc->sc_mii); 178291398Stmm ifmr->ifm_active = sc->sc_mii->mii_media_active; 178391398Stmm ifmr->ifm_status = sc->sc_mii->mii_media_status; 178491398Stmm} 178591398Stmm 178691398Stmm/* 178791398Stmm * Process an ioctl request. 178891398Stmm */ 178991398Stmmstatic int 179091398Stmmgem_ioctl(ifp, cmd, data) 179191398Stmm struct ifnet *ifp; 179291398Stmm u_long cmd; 179391398Stmm caddr_t data; 179491398Stmm{ 179591398Stmm struct gem_softc *sc = ifp->if_softc; 179691398Stmm struct ifreq *ifr = (struct ifreq *)data; 179791398Stmm int s, error = 0; 179891398Stmm 179991398Stmm switch (cmd) { 180091398Stmm case SIOCSIFADDR: 180191398Stmm case SIOCGIFADDR: 180291398Stmm case SIOCSIFMTU: 180391398Stmm error = ether_ioctl(ifp, cmd, data); 180491398Stmm break; 180591398Stmm case SIOCSIFFLAGS: 180691398Stmm if (ifp->if_flags & IFF_UP) { 180799726Sbenno if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC) 180891398Stmm gem_setladrf(sc); 180991398Stmm else 181091398Stmm gem_init(sc); 181191398Stmm } else { 181291398Stmm if (ifp->if_flags & IFF_RUNNING) 181391398Stmm gem_stop(ifp, 0); 181491398Stmm } 181599726Sbenno sc->sc_ifflags = ifp->if_flags; 181691398Stmm error = 0; 181791398Stmm break; 181891398Stmm case SIOCADDMULTI: 181991398Stmm case SIOCDELMULTI: 182091398Stmm gem_setladrf(sc); 182191398Stmm error = 0; 182291398Stmm break; 182391398Stmm case SIOCGIFMEDIA: 182491398Stmm case SIOCSIFMEDIA: 182591398Stmm error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 182691398Stmm break; 182791398Stmm default: 1828108832Stmm error = ENOTTY; 182991398Stmm break; 183091398Stmm } 183191398Stmm 183291398Stmm /* Try to get things going again */ 183391398Stmm if (ifp->if_flags & IFF_UP) 183491398Stmm gem_start(ifp); 183591398Stmm splx(s); 183691398Stmm return (error); 183791398Stmm} 183891398Stmm 183991398Stmm/* 184091398Stmm * Set up the logical address filter. 184191398Stmm */ 184291398Stmmstatic void 184391398Stmmgem_setladrf(sc) 184491398Stmm struct gem_softc *sc; 184591398Stmm{ 1846147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 184791398Stmm struct ifmultiaddr *inm; 184891398Stmm bus_space_tag_t t = sc->sc_bustag; 184991398Stmm bus_space_handle_t h = sc->sc_h; 185091398Stmm u_int32_t crc; 185191398Stmm u_int32_t hash[16]; 185291398Stmm u_int32_t v; 185399726Sbenno int i; 185491398Stmm 185591398Stmm /* Get current RX configuration */ 185691398Stmm v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 185791398Stmm 185899726Sbenno /* 185999726Sbenno * Turn off promiscuous mode, promiscuous group mode (all multicast), 186099726Sbenno * and hash filter. Depending on the case, the right bit will be 186199726Sbenno * enabled. 186299726Sbenno */ 186399726Sbenno v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 186499726Sbenno GEM_MAC_RX_PROMISC_GRP); 186599726Sbenno 186691398Stmm if ((ifp->if_flags & IFF_PROMISC) != 0) { 186799726Sbenno /* Turn on promiscuous mode */ 186891398Stmm v |= GEM_MAC_RX_PROMISCUOUS; 186991398Stmm goto chipit; 187091398Stmm } 187191398Stmm if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 187291398Stmm hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 187391398Stmm ifp->if_flags |= IFF_ALLMULTI; 187499726Sbenno v |= GEM_MAC_RX_PROMISC_GRP; 187591398Stmm goto chipit; 187691398Stmm } 187791398Stmm 187891398Stmm /* 187991398Stmm * Set up multicast address filter by passing all multicast addresses 188099726Sbenno * through a crc generator, and then using the high order 8 bits as an 188199726Sbenno * index into the 256 bit logical address filter. The high order 4 188299726Sbenno * bits selects the word, while the other 4 bits select the bit within 188399726Sbenno * the word (where bit 0 is the MSB). 188491398Stmm */ 188591398Stmm 188699726Sbenno /* Clear hash table */ 188799726Sbenno memset(hash, 0, sizeof(hash)); 188899726Sbenno 1889147256Sbrooks TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 189091398Stmm if (inm->ifma_addr->sa_family != AF_LINK) 189191398Stmm continue; 1892130288Smarius crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1893130288Smarius inm->ifma_addr), ETHER_ADDR_LEN); 189491398Stmm 189591398Stmm /* Just want the 8 most significant bits. */ 189691398Stmm crc >>= 24; 189791398Stmm 189891398Stmm /* Set the corresponding bit in the filter. */ 189999726Sbenno hash[crc >> 4] |= 1 << (15 - (crc & 15)); 190091398Stmm } 190191398Stmm 190299726Sbenno v |= GEM_MAC_RX_HASH_FILTER; 190399726Sbenno ifp->if_flags &= ~IFF_ALLMULTI; 190499726Sbenno 190599726Sbenno /* Now load the hash table into the chip (if we are using it) */ 190699726Sbenno for (i = 0; i < 16; i++) { 190799726Sbenno bus_space_write_4(t, h, 190899726Sbenno GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 190999726Sbenno hash[i]); 191099726Sbenno } 191199726Sbenno 191291398Stmmchipit: 191391398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 191491398Stmm} 1915