if_ffec.c revision 256806
1256806Sian/*- 2256806Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3256806Sian * All rights reserved. 4256806Sian * 5256806Sian * Redistribution and use in source and binary forms, with or without 6256806Sian * modification, are permitted provided that the following conditions 7256806Sian * are met: 8256806Sian * 1. Redistributions of source code must retain the above copyright 9256806Sian * notice, this list of conditions and the following disclaimer. 10256806Sian * 2. Redistributions in binary form must reproduce the above copyright 11256806Sian * notice, this list of conditions and the following disclaimer in the 12256806Sian * documentation and/or other materials provided with the distribution. 13256806Sian * 14256806Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15256806Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16256806Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17256806Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18256806Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19256806Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20256806Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21256806Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22256806Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23256806Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24256806Sian * SUCH DAMAGE. 25256806Sian * 26256806Sian */ 27256806Sian 28256806Sian#include <sys/cdefs.h> 29256806Sian__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffec.c 256806 2013-10-20 21:07:38Z ian $"); 30256806Sian 31256806Sian/* 32256806Sian * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33256806Sian * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34256806Sian * but the driver doesn't currently use any of the ENET advanced features other 35256806Sian * than enabling gigabit. 36256806Sian * 37256806Sian * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38256806Sian * (netgraph/ng_fec.c), so we use 'ffec'. 39256806Sian * 40256806Sian * Requires an FDT entry with at least these properties: 41256806Sian * fec: ethernet@02188000 { 42256806Sian * compatible = "fsl,imxNN-fec"; 43256806Sian * reg = <0x02188000 0x4000>; 44256806Sian * interrupts = <150 151>; 45256806Sian * phy-mode = "rgmii"; 46256806Sian * phy-disable-preamble; // optional 47256806Sian * }; 48256806Sian * The second interrupt number is for IEEE-1588, and is not currently used; it 49256806Sian * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50256806Sian * There is also an optional property, phy-disable-preamble, which if present 51256806Sian * will disable the preamble bits, cutting the size of each mdio transaction 52256806Sian * (and thus the busy-wait time) in half. 53256806Sian */ 54256806Sian 55256806Sian#include <sys/param.h> 56256806Sian#include <sys/systm.h> 57256806Sian#include <sys/bus.h> 58256806Sian#include <sys/endian.h> 59256806Sian#include <sys/kernel.h> 60256806Sian#include <sys/lock.h> 61256806Sian#include <sys/malloc.h> 62256806Sian#include <sys/mbuf.h> 63256806Sian#include <sys/module.h> 64256806Sian#include <sys/mutex.h> 65256806Sian#include <sys/rman.h> 66256806Sian#include <sys/socket.h> 67256806Sian#include <sys/sockio.h> 68256806Sian#include <sys/sysctl.h> 69256806Sian 70256806Sian#include <machine/bus.h> 71256806Sian 72256806Sian#include <net/bpf.h> 73256806Sian#include <net/if.h> 74256806Sian#include <net/ethernet.h> 75256806Sian#include <net/if_dl.h> 76256806Sian#include <net/if_media.h> 77256806Sian#include <net/if_types.h> 78256806Sian#include <net/if_var.h> 79256806Sian#include <net/if_vlan_var.h> 80256806Sian 81256806Sian#include <dev/ffec/if_ffecreg.h> 82256806Sian#include <dev/ofw/ofw_bus.h> 83256806Sian#include <dev/ofw/ofw_bus_subr.h> 84256806Sian#include <dev/mii/mii.h> 85256806Sian#include <dev/mii/miivar.h> 86256806Sian#include "miibus_if.h" 87256806Sian 88256806Sian/* 89256806Sian * Driver data and defines. 90256806Sian */ 91256806Sian#define RX_DESC_COUNT 64 92256806Sian#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 93256806Sian#define TX_DESC_COUNT 64 94256806Sian#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 95256806Sian 96256806Sian#define WATCHDOG_TIMEOUT_SECS 5 97256806Sian#define STATS_HARVEST_INTERVAL 3 98256806Sian 99256806Sianstruct ffec_bufmap { 100256806Sian struct mbuf *mbuf; 101256806Sian bus_dmamap_t map; 102256806Sian}; 103256806Sian 104256806Sianenum { 105256806Sian PHY_CONN_UNKNOWN, 106256806Sian PHY_CONN_MII, 107256806Sian PHY_CONN_RMII, 108256806Sian PHY_CONN_RGMII 109256806Sian}; 110256806Sian 111256806Sianenum { 112256806Sian FECTYPE_GENERIC, 113256806Sian FECTYPE_IMX51, 114256806Sian FECTYPE_IMX53, 115256806Sian FECTYPE_IMX6, 116256806Sian}; 117256806Sian 118256806Sianstruct ffec_softc { 119256806Sian device_t dev; 120256806Sian device_t miibus; 121256806Sian struct mii_data * mii_softc; 122256806Sian struct ifnet *ifp; 123256806Sian int if_flags; 124256806Sian struct mtx mtx; 125256806Sian struct resource *irq_res; 126256806Sian struct resource *mem_res; 127256806Sian void * intr_cookie; 128256806Sian struct callout ffec_callout; 129256806Sian uint8_t phy_conn_type; 130256806Sian uint8_t fectype; 131256806Sian boolean_t link_is_up; 132256806Sian boolean_t is_attached; 133256806Sian boolean_t is_detaching; 134256806Sian int tx_watchdog_count; 135256806Sian int stats_harvest_count; 136256806Sian 137256806Sian bus_dma_tag_t rxdesc_tag; 138256806Sian bus_dmamap_t rxdesc_map; 139256806Sian struct ffec_hwdesc *rxdesc_ring; 140256806Sian bus_addr_t rxdesc_ring_paddr; 141256806Sian bus_dma_tag_t rxbuf_tag; 142256806Sian struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 143256806Sian uint32_t rx_idx; 144256806Sian 145256806Sian bus_dma_tag_t txdesc_tag; 146256806Sian bus_dmamap_t txdesc_map; 147256806Sian struct ffec_hwdesc *txdesc_ring; 148256806Sian bus_addr_t txdesc_ring_paddr; 149256806Sian bus_dma_tag_t txbuf_tag; 150256806Sian struct ffec_bufmap txbuf_map[RX_DESC_COUNT]; 151256806Sian uint32_t tx_idx_head; 152256806Sian uint32_t tx_idx_tail; 153256806Sian int txcount; 154256806Sian}; 155256806Sian 156256806Sian#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 157256806Sian#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 158256806Sian#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 159256806Sian device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 160256806Sian#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 161256806Sian#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 162256806Sian#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 163256806Sian 164256806Sianstatic void ffec_init_locked(struct ffec_softc *sc); 165256806Sianstatic void ffec_stop_locked(struct ffec_softc *sc); 166256806Sianstatic void ffec_txstart_locked(struct ffec_softc *sc); 167256806Sianstatic void ffec_txfinish_locked(struct ffec_softc *sc); 168256806Sian 169256806Sianstatic inline uint16_t 170256806SianRD2(struct ffec_softc *sc, bus_size_t off) 171256806Sian{ 172256806Sian 173256806Sian return (bus_read_2(sc->mem_res, off)); 174256806Sian} 175256806Sian 176256806Sianstatic inline void 177256806SianWR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 178256806Sian{ 179256806Sian 180256806Sian bus_write_2(sc->mem_res, off, val); 181256806Sian} 182256806Sian 183256806Sianstatic inline uint32_t 184256806SianRD4(struct ffec_softc *sc, bus_size_t off) 185256806Sian{ 186256806Sian 187256806Sian return (bus_read_4(sc->mem_res, off)); 188256806Sian} 189256806Sian 190256806Sianstatic inline void 191256806SianWR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 192256806Sian{ 193256806Sian 194256806Sian bus_write_4(sc->mem_res, off, val); 195256806Sian} 196256806Sian 197256806Sianstatic inline uint32_t 198256806Siannext_rxidx(struct ffec_softc *sc, uint32_t curidx) 199256806Sian{ 200256806Sian 201256806Sian return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 202256806Sian} 203256806Sian 204256806Sianstatic inline uint32_t 205256806Siannext_txidx(struct ffec_softc *sc, uint32_t curidx) 206256806Sian{ 207256806Sian 208256806Sian return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 209256806Sian} 210256806Sian 211256806Sianstatic void 212256806Sianffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 213256806Sian{ 214256806Sian 215256806Sian if (error != 0) 216256806Sian return; 217256806Sian *(bus_addr_t *)arg = segs[0].ds_addr; 218256806Sian} 219256806Sian 220256806Sianstatic void 221256806Sianffec_miigasket_setup(struct ffec_softc *sc) 222256806Sian{ 223256806Sian uint32_t ifmode; 224256806Sian 225256806Sian /* 226256806Sian * We only need the gasket for MII and RMII connections on certain SoCs. 227256806Sian */ 228256806Sian 229256806Sian switch (sc->fectype) 230256806Sian { 231256806Sian case FECTYPE_IMX53: 232256806Sian break; 233256806Sian default: 234256806Sian return; 235256806Sian } 236256806Sian 237256806Sian switch (sc->phy_conn_type) 238256806Sian { 239256806Sian case PHY_CONN_MII: 240256806Sian ifmode = 0; 241256806Sian break; 242256806Sian case PHY_CONN_RMII: 243256806Sian ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 244256806Sian break; 245256806Sian default: 246256806Sian return; 247256806Sian } 248256806Sian 249256806Sian /* 250256806Sian * Disable the gasket, configure for either MII or RMII, then enable. 251256806Sian */ 252256806Sian 253256806Sian WR2(sc, FEC_MIIGSK_ENR, 0); 254256806Sian while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 255256806Sian continue; 256256806Sian 257256806Sian WR2(sc, FEC_MIIGSK_CFGR, ifmode); 258256806Sian 259256806Sian WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 260256806Sian while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 261256806Sian continue; 262256806Sian} 263256806Sian 264256806Sianstatic boolean_t 265256806Sianffec_miibus_iowait(struct ffec_softc *sc) 266256806Sian{ 267256806Sian uint32_t timeout; 268256806Sian 269256806Sian for (timeout = 10000; timeout != 0; --timeout) 270256806Sian if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 271256806Sian return (true); 272256806Sian 273256806Sian return (false); 274256806Sian} 275256806Sian 276256806Sianstatic int 277256806Sianffec_miibus_readreg(device_t dev, int phy, int reg) 278256806Sian{ 279256806Sian struct ffec_softc *sc; 280256806Sian int val; 281256806Sian 282256806Sian sc = device_get_softc(dev); 283256806Sian 284256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 285256806Sian 286256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 287256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 288256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 289256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 290256806Sian 291256806Sian if (!ffec_miibus_iowait(sc)) { 292256806Sian device_printf(dev, "timeout waiting for mii read\n"); 293256806Sian return (-1); /* All-ones is a symptom of bad mdio. */ 294256806Sian } 295256806Sian 296256806Sian val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 297256806Sian 298256806Sian return (val); 299256806Sian} 300256806Sian 301256806Sianstatic int 302256806Sianffec_miibus_writereg(device_t dev, int phy, int reg, int val) 303256806Sian{ 304256806Sian struct ffec_softc *sc; 305256806Sian 306256806Sian sc = device_get_softc(dev); 307256806Sian 308256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 309256806Sian 310256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 311256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 312256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 313256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 314256806Sian (val & FEC_MMFR_DATA_MASK)); 315256806Sian 316256806Sian if (!ffec_miibus_iowait(sc)) { 317256806Sian device_printf(dev, "timeout waiting for mii write\n"); 318256806Sian return (-1); 319256806Sian } 320256806Sian 321256806Sian return (0); 322256806Sian} 323256806Sian 324256806Sianstatic void 325256806Sianffec_miibus_statchg(device_t dev) 326256806Sian{ 327256806Sian struct ffec_softc *sc; 328256806Sian struct mii_data *mii; 329256806Sian uint32_t ecr, rcr, tcr; 330256806Sian 331256806Sian /* 332256806Sian * Called by the MII bus driver when the PHY establishes link to set the 333256806Sian * MAC interface registers. 334256806Sian */ 335256806Sian 336256806Sian sc = device_get_softc(dev); 337256806Sian 338256806Sian FFEC_ASSERT_LOCKED(sc); 339256806Sian 340256806Sian mii = sc->mii_softc; 341256806Sian 342256806Sian if (mii->mii_media_status & IFM_ACTIVE) 343256806Sian sc->link_is_up = true; 344256806Sian else 345256806Sian sc->link_is_up = false; 346256806Sian 347256806Sian ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 348256806Sian rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 349256806Sian FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 350256806Sian tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 351256806Sian 352256806Sian rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 353256806Sian switch (sc->phy_conn_type) { 354256806Sian case PHY_CONN_MII: 355256806Sian break; 356256806Sian case PHY_CONN_RMII: 357256806Sian rcr |= FEC_RCR_RMII_MODE; 358256806Sian break; 359256806Sian case PHY_CONN_RGMII: 360256806Sian rcr |= FEC_RCR_RGMII_EN; 361256806Sian break; 362256806Sian } 363256806Sian 364256806Sian switch (IFM_SUBTYPE(mii->mii_media_active)) { 365256806Sian case IFM_1000_T: 366256806Sian case IFM_1000_SX: 367256806Sian ecr |= FEC_ECR_SPEED; 368256806Sian break; 369256806Sian case IFM_100_TX: 370256806Sian /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 371256806Sian break; 372256806Sian case IFM_10_T: 373256806Sian rcr |= FEC_RCR_RMII_10T; 374256806Sian break; 375256806Sian case IFM_NONE: 376256806Sian sc->link_is_up = false; 377256806Sian return; 378256806Sian default: 379256806Sian sc->link_is_up = false; 380256806Sian device_printf(dev, "Unsupported media %u\n", 381256806Sian IFM_SUBTYPE(mii->mii_media_active)); 382256806Sian return; 383256806Sian } 384256806Sian 385256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 386256806Sian tcr |= FEC_TCR_FDEN; 387256806Sian else 388256806Sian rcr |= FEC_RCR_DRT; 389256806Sian 390256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 391256806Sian rcr |= FEC_RCR_FCE; 392256806Sian 393256806Sian WR4(sc, FEC_RCR_REG, rcr); 394256806Sian WR4(sc, FEC_TCR_REG, tcr); 395256806Sian WR4(sc, FEC_ECR_REG, ecr); 396256806Sian} 397256806Sian 398256806Sianstatic void 399256806Sianffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 400256806Sian{ 401256806Sian struct ffec_softc *sc; 402256806Sian struct mii_data *mii; 403256806Sian 404256806Sian 405256806Sian sc = ifp->if_softc; 406256806Sian mii = sc->mii_softc; 407256806Sian FFEC_LOCK(sc); 408256806Sian mii_pollstat(mii); 409256806Sian ifmr->ifm_active = mii->mii_media_active; 410256806Sian ifmr->ifm_status = mii->mii_media_status; 411256806Sian FFEC_UNLOCK(sc); 412256806Sian} 413256806Sian 414256806Sianstatic int 415256806Sianffec_media_change_locked(struct ffec_softc *sc) 416256806Sian{ 417256806Sian 418256806Sian return (mii_mediachg(sc->mii_softc)); 419256806Sian} 420256806Sian 421256806Sianstatic int 422256806Sianffec_media_change(struct ifnet * ifp) 423256806Sian{ 424256806Sian struct ffec_softc *sc; 425256806Sian int error; 426256806Sian 427256806Sian sc = ifp->if_softc; 428256806Sian 429256806Sian FFEC_LOCK(sc); 430256806Sian error = ffec_media_change_locked(sc); 431256806Sian FFEC_UNLOCK(sc); 432256806Sian return (error); 433256806Sian} 434256806Sian 435256806Sianstatic void ffec_clear_stats(struct ffec_softc *sc) 436256806Sian{ 437256806Sian 438256806Sian WR4(sc, FEC_RMON_R_PACKETS, 0); 439256806Sian WR4(sc, FEC_RMON_R_MC_PKT, 0); 440256806Sian WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 441256806Sian WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 442256806Sian WR4(sc, FEC_RMON_R_OVERSIZE, 0); 443256806Sian WR4(sc, FEC_RMON_R_FRAG, 0); 444256806Sian WR4(sc, FEC_RMON_R_JAB, 0); 445256806Sian WR4(sc, FEC_RMON_T_PACKETS, 0); 446256806Sian WR4(sc, FEC_RMON_T_MC_PKT, 0); 447256806Sian WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 448256806Sian WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 449256806Sian WR4(sc, FEC_RMON_T_OVERSIZE , 0); 450256806Sian WR4(sc, FEC_RMON_T_FRAG, 0); 451256806Sian WR4(sc, FEC_RMON_T_JAB, 0); 452256806Sian WR4(sc, FEC_RMON_T_COL, 0); 453256806Sian} 454256806Sian 455256806Sianstatic void 456256806Sianffec_harvest_stats(struct ffec_softc *sc) 457256806Sian{ 458256806Sian struct ifnet *ifp; 459256806Sian 460256806Sian /* We don't need to harvest too often. */ 461256806Sian if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 462256806Sian return; 463256806Sian 464256806Sian /* 465256806Sian * Try to avoid harvesting unless the IDLE flag is on, but if it has 466256806Sian * been too long just go ahead and do it anyway, the worst that'll 467256806Sian * happen is we'll lose a packet count or two as we clear at the end. 468256806Sian */ 469256806Sian if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 470256806Sian ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 471256806Sian return; 472256806Sian 473256806Sian sc->stats_harvest_count = 0; 474256806Sian ifp = sc->ifp; 475256806Sian 476256806Sian ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS); 477256806Sian ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT); 478256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_CRC_ALIGN); 479256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_UNDERSIZE); 480256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_OVERSIZE); 481256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_FRAG); 482256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_JAB); 483256806Sian 484256806Sian ifp->if_opackets += RD4(sc, FEC_RMON_T_PACKETS); 485256806Sian ifp->if_omcasts += RD4(sc, FEC_RMON_T_MC_PKT); 486256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_CRC_ALIGN); 487256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_UNDERSIZE); 488256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_OVERSIZE ); 489256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_FRAG); 490256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_JAB); 491256806Sian 492256806Sian ifp->if_collisions += RD4(sc, FEC_RMON_T_COL); 493256806Sian 494256806Sian ffec_clear_stats(sc); 495256806Sian} 496256806Sian 497256806Sianstatic void 498256806Sianffec_tick(void *arg) 499256806Sian{ 500256806Sian struct ffec_softc *sc; 501256806Sian struct ifnet *ifp; 502256806Sian int link_was_up; 503256806Sian 504256806Sian sc = arg; 505256806Sian 506256806Sian FFEC_ASSERT_LOCKED(sc); 507256806Sian 508256806Sian ifp = sc->ifp; 509256806Sian 510256806Sian if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 511256806Sian return; 512256806Sian 513256806Sian /* 514256806Sian * Typical tx watchdog. If this fires it indicates that we enqueued 515256806Sian * packets for output and never got a txdone interrupt for them. Maybe 516256806Sian * it's a missed interrupt somehow, just pretend we got one. 517256806Sian */ 518256806Sian if (sc->tx_watchdog_count > 0) { 519256806Sian if (--sc->tx_watchdog_count == 0) { 520256806Sian ffec_txfinish_locked(sc); 521256806Sian } 522256806Sian } 523256806Sian 524256806Sian /* Gather stats from hardware counters. */ 525256806Sian ffec_harvest_stats(sc); 526256806Sian 527256806Sian /* Check the media status. */ 528256806Sian link_was_up = sc->link_is_up; 529256806Sian mii_tick(sc->mii_softc); 530256806Sian if (sc->link_is_up && !link_was_up) 531256806Sian ffec_txstart_locked(sc); 532256806Sian 533256806Sian /* Schedule another check one second from now. */ 534256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 535256806Sian} 536256806Sian 537256806Sianinline static uint32_t 538256806Sianffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 539256806Sian uint32_t len) 540256806Sian{ 541256806Sian uint32_t nidx; 542256806Sian uint32_t flags; 543256806Sian 544256806Sian nidx = next_txidx(sc, idx); 545256806Sian 546256806Sian /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 547256806Sian if (paddr == 0 || len == 0) { 548256806Sian flags = 0; 549256806Sian --sc->txcount; 550256806Sian } else { 551256806Sian flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 552256806Sian ++sc->txcount; 553256806Sian } 554256806Sian if (nidx == 0) 555256806Sian flags |= FEC_TXDESC_WRAP; 556256806Sian 557256806Sian /* 558256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 559256806Sian * tag to indicate that, so the cast to uint32_t should never lose 560256806Sian * significant bits. 561256806Sian */ 562256806Sian sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 563256806Sian sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 564256806Sian 565256806Sian return (nidx); 566256806Sian} 567256806Sian 568256806Sianstatic int 569256806Sianffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 570256806Sian{ 571256806Sian struct mbuf * m; 572256806Sian int error, nsegs; 573256806Sian struct bus_dma_segment seg; 574256806Sian 575256806Sian if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 576256806Sian return (ENOMEM); 577256806Sian *mp = m; 578256806Sian 579256806Sian error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 580256806Sian m, &seg, &nsegs, 0); 581256806Sian if (error != 0) { 582256806Sian return (ENOMEM); 583256806Sian } 584256806Sian bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 585256806Sian BUS_DMASYNC_PREWRITE); 586256806Sian 587256806Sian sc->txbuf_map[idx].mbuf = m; 588256806Sian ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 589256806Sian 590256806Sian return (0); 591256806Sian 592256806Sian} 593256806Sian 594256806Sianstatic void 595256806Sianffec_txstart_locked(struct ffec_softc *sc) 596256806Sian{ 597256806Sian struct ifnet *ifp; 598256806Sian struct mbuf *m; 599256806Sian int enqueued; 600256806Sian 601256806Sian FFEC_ASSERT_LOCKED(sc); 602256806Sian 603256806Sian if (!sc->link_is_up) 604256806Sian return; 605256806Sian 606256806Sian ifp = sc->ifp; 607256806Sian 608256806Sian if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 609256806Sian return; 610256806Sian 611256806Sian enqueued = 0; 612256806Sian 613256806Sian for (;;) { 614256806Sian if (sc->txcount == (TX_DESC_COUNT-1)) { 615256806Sian ifp->if_drv_flags |= IFF_DRV_OACTIVE; 616256806Sian break; 617256806Sian } 618256806Sian IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 619256806Sian if (m == NULL) 620256806Sian break; 621256806Sian if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 622256806Sian IFQ_DRV_PREPEND(&ifp->if_snd, m); 623256806Sian break; 624256806Sian } 625256806Sian BPF_MTAP(ifp, m); 626256806Sian sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 627256806Sian ++enqueued; 628256806Sian } 629256806Sian 630256806Sian if (enqueued != 0) { 631256806Sian WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 632256806Sian sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 633256806Sian } 634256806Sian} 635256806Sian 636256806Sianstatic void 637256806Sianffec_txstart(struct ifnet *ifp) 638256806Sian{ 639256806Sian struct ffec_softc *sc = ifp->if_softc; 640256806Sian 641256806Sian FFEC_LOCK(sc); 642256806Sian ffec_txstart_locked(sc); 643256806Sian FFEC_UNLOCK(sc); 644256806Sian} 645256806Sian 646256806Sianstatic void 647256806Sianffec_txfinish_locked(struct ffec_softc *sc) 648256806Sian{ 649256806Sian struct ifnet *ifp; 650256806Sian struct ffec_hwdesc *desc; 651256806Sian struct ffec_bufmap *bmap; 652256806Sian boolean_t retired_buffer; 653256806Sian 654256806Sian FFEC_ASSERT_LOCKED(sc); 655256806Sian 656256806Sian ifp = sc->ifp; 657256806Sian retired_buffer = false; 658256806Sian while (sc->tx_idx_tail != sc->tx_idx_head) { 659256806Sian desc = &sc->txdesc_ring[sc->tx_idx_tail]; 660256806Sian if (desc->flags_len & FEC_TXDESC_READY) 661256806Sian break; 662256806Sian retired_buffer = true; 663256806Sian bmap = &sc->txbuf_map[sc->tx_idx_tail]; 664256806Sian bus_dmamap_sync(sc->txbuf_tag, bmap->map, 665256806Sian BUS_DMASYNC_POSTWRITE); 666256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 667256806Sian m_freem(bmap->mbuf); 668256806Sian bmap->mbuf = NULL; 669256806Sian ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 670256806Sian sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 671256806Sian } 672256806Sian 673256806Sian /* 674256806Sian * If we retired any buffers, there will be open tx slots available in 675256806Sian * the descriptor ring, go try to start some new output. 676256806Sian */ 677256806Sian if (retired_buffer) { 678256806Sian ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 679256806Sian ffec_txstart_locked(sc); 680256806Sian } 681256806Sian 682256806Sian /* If there are no buffers outstanding, muzzle the watchdog. */ 683256806Sian if (sc->tx_idx_tail == sc->tx_idx_head) { 684256806Sian sc->tx_watchdog_count = 0; 685256806Sian } 686256806Sian} 687256806Sian 688256806Sianinline static uint32_t 689256806Sianffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 690256806Sian{ 691256806Sian uint32_t nidx; 692256806Sian 693256806Sian /* 694256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 695256806Sian * tag to indicate that, so the cast to uint32_t should never lose 696256806Sian * significant bits. 697256806Sian */ 698256806Sian nidx = next_rxidx(sc, idx); 699256806Sian sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 700256806Sian sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 701256806Sian ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 702256806Sian 703256806Sian return (nidx); 704256806Sian} 705256806Sian 706256806Sianstatic int 707256806Sianffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 708256806Sian{ 709256806Sian int error, nsegs; 710256806Sian struct bus_dma_segment seg; 711256806Sian 712256806Sian /* 713256806Sian * We need to leave at least ETHER_ALIGN bytes free at the beginning of 714256806Sian * the buffer to allow the data to be re-aligned after receiving it (by 715256806Sian * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 716256806Sian * have to ensure that the beginning of the buffer is aligned to the 717256806Sian * hardware's requirements. 718256806Sian */ 719256806Sian m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 720256806Sian 721256806Sian error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 722256806Sian m, &seg, &nsegs, 0); 723256806Sian if (error != 0) { 724256806Sian return (error); 725256806Sian } 726256806Sian 727256806Sian bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 728256806Sian BUS_DMASYNC_PREREAD); 729256806Sian 730256806Sian sc->rxbuf_map[idx].mbuf = m; 731256806Sian ffec_setup_rxdesc(sc, idx, seg.ds_addr); 732256806Sian 733256806Sian return (0); 734256806Sian} 735256806Sian 736256806Sianstatic struct mbuf * 737256806Sianffec_alloc_mbufcl(struct ffec_softc *sc) 738256806Sian{ 739256806Sian struct mbuf *m; 740256806Sian 741256806Sian m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 742256806Sian m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 743256806Sian 744256806Sian return (m); 745256806Sian} 746256806Sian 747256806Sianstatic void 748256806Sianffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 749256806Sian{ 750256806Sian struct mbuf *m, *newmbuf; 751256806Sian struct ffec_bufmap *bmap; 752256806Sian uint8_t *dst, *src; 753256806Sian int error; 754256806Sian 755256806Sian /* 756256806Sian * First try to get a new mbuf to plug into this slot in the rx ring. 757256806Sian * If that fails, drop the current packet and recycle the current 758256806Sian * mbuf, which is still mapped and loaded. 759256806Sian */ 760256806Sian if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 761256806Sian ++sc->ifp->if_iqdrops; 762256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 763256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 764256806Sian return; 765256806Sian } 766256806Sian 767256806Sian /* 768256806Sian * Unfortunately, the protocol headers need to be aligned on a 32-bit 769256806Sian * boundary for the upper layers. The hardware requires receive 770256806Sian * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 771256806Sian * leaving the protocol header unaligned. We used m_adj() after 772256806Sian * allocating the buffer to leave empty space at the start of the 773256806Sian * buffer, now we'll use the alignment agnostic bcopy() routine to 774256806Sian * shuffle all the data backwards 2 bytes and adjust m_data. 775256806Sian * 776256806Sian * XXX imx6 hardware is able to do this 2-byte alignment by setting the 777256806Sian * SHIFT16 bit in the RACC register. Older hardware doesn't have that 778256806Sian * feature, but for them could we speed this up by copying just the 779256806Sian * protocol headers into their own small mbuf then chaining the cluster 780256806Sian * to it? That way we'd only need to copy like 64 bytes or whatever 781256806Sian * the biggest header is, instead of the whole 1530ish-byte frame. 782256806Sian */ 783256806Sian 784256806Sian FFEC_UNLOCK(sc); 785256806Sian 786256806Sian bmap = &sc->rxbuf_map[sc->rx_idx]; 787256806Sian len -= ETHER_CRC_LEN; 788256806Sian bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 789256806Sian bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 790256806Sian m = bmap->mbuf; 791256806Sian bmap->mbuf = NULL; 792256806Sian m->m_len = len; 793256806Sian m->m_pkthdr.len = len; 794256806Sian m->m_pkthdr.rcvif = sc->ifp; 795256806Sian 796256806Sian src = mtod(m, uint8_t*); 797256806Sian dst = src - ETHER_ALIGN; 798256806Sian bcopy(src, dst, len); 799256806Sian m->m_data = dst; 800256806Sian sc->ifp->if_input(sc->ifp, m); 801256806Sian 802256806Sian FFEC_LOCK(sc); 803256806Sian 804256806Sian if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 805256806Sian device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 806256806Sian /* XXX Now what? We've got a hole in the rx ring. */ 807256806Sian } 808256806Sian 809256806Sian} 810256806Sian 811256806Sianstatic void 812256806Sianffec_rxfinish_locked(struct ffec_softc *sc) 813256806Sian{ 814256806Sian struct ffec_hwdesc *desc; 815256806Sian int len; 816256806Sian boolean_t produced_empty_buffer; 817256806Sian 818256806Sian FFEC_ASSERT_LOCKED(sc); 819256806Sian 820256806Sian produced_empty_buffer = false; 821256806Sian for (;;) { 822256806Sian desc = &sc->rxdesc_ring[sc->rx_idx]; 823256806Sian if (desc->flags_len & FEC_RXDESC_EMPTY) 824256806Sian break; 825256806Sian produced_empty_buffer = true; 826256806Sian len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 827256806Sian if (len < 64) { 828256806Sian /* 829256806Sian * Just recycle the descriptor and continue. . 830256806Sian */ 831256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 832256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 833256806Sian } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 834256806Sian /* 835256806Sian * The entire frame is not in this buffer. Impossible. 836256806Sian * Recycle the descriptor and continue. 837256806Sian * 838256806Sian * XXX what's the right way to handle this? Probably we 839256806Sian * should stop/init the hardware because this should 840256806Sian * just really never happen when we have buffers bigger 841256806Sian * than the maximum frame size. 842256806Sian */ 843256806Sian device_printf(sc->dev, 844256806Sian "fec_rxfinish: received frame without LAST bit set"); 845256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 846256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 847256806Sian } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 848256806Sian /* 849256806Sian * Something went wrong with receiving the frame, we 850256806Sian * don't care what (the hardware has counted the error 851256806Sian * in the stats registers already), we just reuse the 852256806Sian * same mbuf, which is still dma-mapped, by resetting 853256806Sian * the rx descriptor. 854256806Sian */ 855256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 856256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 857256806Sian } else { 858256806Sian /* 859256806Sian * Normal case: a good frame all in one buffer. 860256806Sian */ 861256806Sian ffec_rxfinish_onebuf(sc, len); 862256806Sian } 863256806Sian sc->rx_idx = next_rxidx(sc, sc->rx_idx); 864256806Sian } 865256806Sian 866256806Sian if (produced_empty_buffer) { 867256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 868256806Sian } 869256806Sian} 870256806Sian 871256806Sianstatic void 872256806Sianffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 873256806Sian{ 874256806Sian uint32_t palr, paur, rnd; 875256806Sian 876256806Sian /* 877256806Sian * Try to recover a MAC address from the running hardware. If there's 878256806Sian * something non-zero there, assume the bootloader did the right thing 879256806Sian * and just use it. 880256806Sian * 881256806Sian * Otherwise, set the address to a convenient locally assigned address, 882256806Sian * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 883256806Sian * assigned bit set, and the broadcast/multicast bit clear. 884256806Sian */ 885256806Sian palr = RD4(sc, FEC_PALR_REG); 886256806Sian paur = RD4(sc, FEC_PAUR_REG); 887256806Sian if ((palr | paur) != 0) { 888256806Sian hwaddr[0] = palr >> 24; 889256806Sian hwaddr[1] = palr >> 16; 890256806Sian hwaddr[2] = palr >> 8; 891256806Sian hwaddr[3] = palr >> 0; 892256806Sian hwaddr[4] = paur >> 24; 893256806Sian hwaddr[5] = paur >> 16; 894256806Sian return; 895256806Sian } else { 896256806Sian rnd = arc4random() & 0x00ffffff; 897256806Sian hwaddr[0] = 'b'; 898256806Sian hwaddr[1] = 's'; 899256806Sian hwaddr[2] = 'd'; 900256806Sian hwaddr[3] = rnd >> 16; 901256806Sian hwaddr[4] = rnd >> 8; 902256806Sian hwaddr[5] = rnd >> 0; 903256806Sian } 904256806Sian 905256806Sian if (bootverbose) { 906256806Sian device_printf(sc->dev, 907256806Sian "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 908256806Sian hwaddr[0], hwaddr[1], hwaddr[2], 909256806Sian hwaddr[3], hwaddr[4], hwaddr[5]); 910256806Sian } 911256806Sian} 912256806Sian 913256806Sianstatic void 914256806Sianffec_setup_rxfilter(struct ffec_softc *sc) 915256806Sian{ 916256806Sian struct ifnet *ifp; 917256806Sian struct ifmultiaddr *ifma; 918256806Sian uint8_t *eaddr; 919256806Sian uint32_t crc; 920256806Sian uint64_t ghash, ihash; 921256806Sian 922256806Sian FFEC_ASSERT_LOCKED(sc); 923256806Sian 924256806Sian ifp = sc->ifp; 925256806Sian 926256806Sian /* 927256806Sian * Set the multicast (group) filter hash. 928256806Sian */ 929256806Sian if ((ifp->if_flags & IFF_ALLMULTI)) 930256806Sian ghash = 0xffffffffffffffffLLU; 931256806Sian else { 932256806Sian ghash = 0; 933256806Sian if_maddr_rlock(ifp); 934256806Sian TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 935256806Sian if (ifma->ifma_addr->sa_family != AF_LINK) 936256806Sian continue; 937256806Sian crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 938256806Sian ifma->ifma_addr), ETHER_ADDR_LEN); 939256806Sian ghash |= 1 << (crc & 0x3f); 940256806Sian } 941256806Sian if_maddr_runlock(ifp); 942256806Sian } 943256806Sian WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 944256806Sian WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 945256806Sian 946256806Sian /* 947256806Sian * Set the individual address filter hash. 948256806Sian * 949256806Sian * XXX Is 0 the right value when promiscuous is off? This hw feature 950256806Sian * seems to support the concept of MAC address aliases, does such a 951256806Sian * thing even exist? 952256806Sian */ 953256806Sian if ((ifp->if_flags & IFF_PROMISC)) 954256806Sian ihash = 0xffffffffffffffffLLU; 955256806Sian else { 956256806Sian ihash = 0; 957256806Sian } 958256806Sian WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 959256806Sian WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 960256806Sian 961256806Sian /* 962256806Sian * Set the primary address. 963256806Sian */ 964256806Sian eaddr = IF_LLADDR(ifp); 965256806Sian WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 966256806Sian (eaddr[2] << 8) | eaddr[3]); 967256806Sian WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 968256806Sian} 969256806Sian 970256806Sianstatic void 971256806Sianffec_stop_locked(struct ffec_softc *sc) 972256806Sian{ 973256806Sian struct ifnet *ifp; 974256806Sian struct ffec_hwdesc *desc; 975256806Sian struct ffec_bufmap *bmap; 976256806Sian int idx; 977256806Sian 978256806Sian FFEC_ASSERT_LOCKED(sc); 979256806Sian 980256806Sian ifp = sc->ifp; 981256806Sian ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 982256806Sian sc->tx_watchdog_count = 0; 983256806Sian sc->stats_harvest_count = 0; 984256806Sian 985256806Sian /* 986256806Sian * Stop the hardware, mask all interrupts, and clear all current 987256806Sian * interrupt status bits. 988256806Sian */ 989256806Sian WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 990256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 991256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 992256806Sian 993256806Sian /* 994256806Sian * Stop the media-check callout. Do not use callout_drain() because 995256806Sian * we're holding a mutex the callout acquires, and if it's currently 996256806Sian * waiting to acquire it, we'd deadlock. If it is waiting now, the 997256806Sian * ffec_tick() routine will return without doing anything when it sees 998256806Sian * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 999256806Sian */ 1000256806Sian callout_stop(&sc->ffec_callout); 1001256806Sian 1002256806Sian /* 1003256806Sian * Discard all untransmitted buffers. Each buffer is simply freed; 1004256806Sian * it's as if the bits were transmitted and then lost on the wire. 1005256806Sian * 1006256806Sian * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1007256806Sian * back on the queue for when we get restarted later? 1008256806Sian */ 1009256806Sian idx = sc->tx_idx_tail; 1010256806Sian while (idx != sc->tx_idx_head) { 1011256806Sian desc = &sc->txdesc_ring[idx]; 1012256806Sian bmap = &sc->txbuf_map[idx]; 1013256806Sian if (desc->buf_paddr != 0) { 1014256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1015256806Sian m_freem(bmap->mbuf); 1016256806Sian bmap->mbuf = NULL; 1017256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1018256806Sian } 1019256806Sian idx = next_txidx(sc, idx); 1020256806Sian } 1021256806Sian 1022256806Sian /* 1023256806Sian * Discard all unprocessed receive buffers. This amounts to just 1024256806Sian * pretending that nothing ever got received into them. We reuse the 1025256806Sian * mbuf already mapped for each desc, simply turning the EMPTY flags 1026256806Sian * back on so they'll get reused when we start up again. 1027256806Sian */ 1028256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1029256806Sian desc = &sc->rxdesc_ring[idx]; 1030256806Sian ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1031256806Sian } 1032256806Sian} 1033256806Sian 1034256806Sianstatic void 1035256806Sianffec_init_locked(struct ffec_softc *sc) 1036256806Sian{ 1037256806Sian struct ifnet *ifp = sc->ifp; 1038256806Sian uint32_t maxbuf, maxfl, regval; 1039256806Sian 1040256806Sian FFEC_ASSERT_LOCKED(sc); 1041256806Sian 1042256806Sian /* 1043256806Sian * The hardware has a limit of 0x7ff as the max frame length (see 1044256806Sian * comments for MRBR below), and we use mbuf clusters as receive 1045256806Sian * buffers, and we currently are designed to receive an entire frame 1046256806Sian * into a single buffer. 1047256806Sian * 1048256806Sian * We start with a MCLBYTES-sized cluster, but we have to offset into 1049256806Sian * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1050256806Sian * and then that value has to be rounded up to the hardware's DMA 1051256806Sian * alignment requirements, so all in all our buffer is that much smaller 1052256806Sian * than MCLBYTES. 1053256806Sian * 1054256806Sian * The resulting value is used as the frame truncation length and the 1055256806Sian * max buffer receive buffer size for now. It'll become more complex 1056256806Sian * when we support jumbo frames and receiving fragments of them into 1057256806Sian * separate buffers. 1058256806Sian */ 1059256806Sian maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1060256806Sian maxfl = min(maxbuf, 0x7ff); 1061256806Sian 1062256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1063256806Sian return; 1064256806Sian 1065256806Sian /* Mask all interrupts and clear all current interrupt status bits. */ 1066256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1067256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1068256806Sian 1069256806Sian /* 1070256806Sian * Go set up palr/puar, galr/gaur, ialr/iaur. 1071256806Sian */ 1072256806Sian ffec_setup_rxfilter(sc); 1073256806Sian 1074256806Sian /* 1075256806Sian * TFWR - Transmit FIFO watermark register. 1076256806Sian * 1077256806Sian * Set the transmit fifo watermark register to "store and forward" mode 1078256806Sian * and also set a threshold of 128 bytes in the fifo before transmission 1079256806Sian * of a frame begins (to avoid dma underruns). Recent FEC hardware 1080256806Sian * supports STRFWD and when that bit is set, the watermark level in the 1081256806Sian * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1082256806Sian * to that bit is innocuous, and the TWFR bits get used instead. 1083256806Sian */ 1084256806Sian WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1085256806Sian 1086256806Sian /* RCR - Receive control register. 1087256806Sian * 1088256806Sian * Set max frame length + clean out anything left from u-boot. 1089256806Sian */ 1090256806Sian WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1091256806Sian 1092256806Sian /* 1093256806Sian * TCR - Transmit control register. 1094256806Sian * 1095256806Sian * Clean out anything left from u-boot. Any necessary values are set in 1096256806Sian * ffec_miibus_statchg() based on the media type. 1097256806Sian */ 1098256806Sian WR4(sc, FEC_TCR_REG, 0); 1099256806Sian 1100256806Sian /* 1101256806Sian * OPD - Opcode/pause duration. 1102256806Sian * 1103256806Sian * XXX These magic numbers come from u-boot. 1104256806Sian */ 1105256806Sian WR4(sc, FEC_OPD_REG, 0x00010020); 1106256806Sian 1107256806Sian /* 1108256806Sian * FRSR - Fifo receive start register. 1109256806Sian * 1110256806Sian * This register does not exist on imx6, it is present on earlier 1111256806Sian * hardware. The u-boot code sets this to a non-default value that's 32 1112256806Sian * bytes larger than the default, with no clue as to why. The default 1113256806Sian * value should work fine, so there's no code to init it here. 1114256806Sian */ 1115256806Sian 1116256806Sian /* 1117256806Sian * MRBR - Max RX buffer size. 1118256806Sian * 1119256806Sian * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1120256806Sian * but the datasheet says no such thing for imx6. On the imx6, setting 1121256806Sian * this to 2K without setting EN1588 resulted in a crazy runaway 1122256806Sian * receive loop in the hardware, where every rx descriptor in the ring 1123256806Sian * had its EMPTY flag cleared, no completion or error flags set, and a 1124256806Sian * length of zero. I think maybe you can only exceed it when EN1588 is 1125256806Sian * set, like maybe that's what enables jumbo frames, because in general 1126256806Sian * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1127256806Sian * compatible" flag. 1128256806Sian */ 1129256806Sian WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1130256806Sian 1131256806Sian /* 1132256806Sian * FTRL - Frame truncation length. 1133256806Sian * 1134256806Sian * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1135256806Sian */ 1136256806Sian WR4(sc, FEC_FTRL_REG, maxfl); 1137256806Sian 1138256806Sian /* 1139256806Sian * RDSR / TDSR descriptor ring pointers. 1140256806Sian * 1141256806Sian * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1142256806Sian * internal current descriptor index values for both rings, so we zero 1143256806Sian * our index values as well. 1144256806Sian */ 1145256806Sian sc->rx_idx = 0; 1146256806Sian sc->tx_idx_head = sc->tx_idx_tail = 0; 1147256806Sian sc->txcount = 0; 1148256806Sian WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1149256806Sian WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1150256806Sian 1151256806Sian /* 1152256806Sian * EIM - interrupt mask register. 1153256806Sian * 1154256806Sian * We always enable the same set of interrupts while running; unlike 1155256806Sian * some drivers there's no need to change the mask on the fly depending 1156256806Sian * on what operations are in progress. 1157256806Sian */ 1158256806Sian WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1159256806Sian 1160256806Sian /* 1161256806Sian * MIBC - MIB control (hardware stats). 1162256806Sian */ 1163256806Sian regval = RD4(sc, FEC_MIBC_REG); 1164256806Sian WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1165256806Sian ffec_clear_stats(sc); 1166256806Sian WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1167256806Sian 1168256806Sian /* 1169256806Sian * ECR - Ethernet control register. 1170256806Sian * 1171256806Sian * This must happen after all the other config registers are set. If 1172256806Sian * we're running on little-endian hardware, also set the flag for byte- 1173256806Sian * swapping descriptor ring entries. This flag doesn't exist on older 1174256806Sian * hardware, but it can be safely set -- the bit position it occupies 1175256806Sian * was unused. 1176256806Sian */ 1177256806Sian regval = RD4(sc, FEC_ECR_REG); 1178256806Sian#if _BYTE_ORDER == _LITTLE_ENDIAN 1179256806Sian regval |= FEC_ECR_DBSWP; 1180256806Sian#endif 1181256806Sian regval |= FEC_ECR_ETHEREN; 1182256806Sian WR4(sc, FEC_ECR_REG, regval); 1183256806Sian 1184256806Sian ifp->if_drv_flags |= IFF_DRV_RUNNING; 1185256806Sian 1186256806Sian /* 1187256806Sian * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1188256806Sian * set up the remaining config registers based on the current media. 1189256806Sian */ 1190256806Sian mii_mediachg(sc->mii_softc); 1191256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1192256806Sian 1193256806Sian /* 1194256806Sian * Tell the hardware that receive buffers are available. They were made 1195256806Sian * available in ffec_attach() or ffec_stop(). 1196256806Sian */ 1197256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1198256806Sian} 1199256806Sian 1200256806Sianstatic void 1201256806Sianffec_init(void *if_softc) 1202256806Sian{ 1203256806Sian struct ffec_softc *sc = if_softc; 1204256806Sian 1205256806Sian FFEC_LOCK(sc); 1206256806Sian ffec_init_locked(sc); 1207256806Sian FFEC_UNLOCK(sc); 1208256806Sian} 1209256806Sian 1210256806Sianstatic void 1211256806Sianffec_intr(void *arg) 1212256806Sian{ 1213256806Sian struct ffec_softc *sc; 1214256806Sian uint32_t ier; 1215256806Sian 1216256806Sian sc = arg; 1217256806Sian 1218256806Sian FFEC_LOCK(sc); 1219256806Sian 1220256806Sian ier = RD4(sc, FEC_IER_REG); 1221256806Sian 1222256806Sian if (ier & FEC_IER_TXF) { 1223256806Sian WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1224256806Sian ffec_txfinish_locked(sc); 1225256806Sian } 1226256806Sian 1227256806Sian if (ier & FEC_IER_RXF) { 1228256806Sian WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1229256806Sian ffec_rxfinish_locked(sc); 1230256806Sian } 1231256806Sian 1232256806Sian /* 1233256806Sian * We actually don't care about most errors, because the hardware copes 1234256806Sian * with them just fine, discarding the incoming bad frame, or forcing a 1235256806Sian * bad CRC onto an outgoing bad frame, and counting the errors in the 1236256806Sian * stats registers. The one that really matters is EBERR (DMA bus 1237256806Sian * error) because the hardware automatically clears ECR[ETHEREN] and we 1238256806Sian * have to restart it here. It should never happen. 1239256806Sian */ 1240256806Sian if (ier & FEC_IER_EBERR) { 1241256806Sian WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1242256806Sian device_printf(sc->dev, 1243256806Sian "Ethernet DMA error, restarting controller.\n"); 1244256806Sian ffec_stop_locked(sc); 1245256806Sian ffec_init_locked(sc); 1246256806Sian } 1247256806Sian 1248256806Sian FFEC_UNLOCK(sc); 1249256806Sian 1250256806Sian} 1251256806Sian 1252256806Sianstatic int 1253256806Sianffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1254256806Sian{ 1255256806Sian struct ffec_softc *sc; 1256256806Sian struct mii_data *mii; 1257256806Sian struct ifreq *ifr; 1258256806Sian int mask, error; 1259256806Sian 1260256806Sian sc = ifp->if_softc; 1261256806Sian ifr = (struct ifreq *)data; 1262256806Sian 1263256806Sian error = 0; 1264256806Sian switch (cmd) { 1265256806Sian case SIOCSIFFLAGS: 1266256806Sian FFEC_LOCK(sc); 1267256806Sian if (ifp->if_flags & IFF_UP) { 1268256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1269256806Sian if ((ifp->if_flags ^ sc->if_flags) & 1270256806Sian (IFF_PROMISC | IFF_ALLMULTI)) 1271256806Sian ffec_setup_rxfilter(sc); 1272256806Sian } else { 1273256806Sian if (!sc->is_detaching) 1274256806Sian ffec_init_locked(sc); 1275256806Sian } 1276256806Sian } else { 1277256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1278256806Sian ffec_stop_locked(sc); 1279256806Sian } 1280256806Sian sc->if_flags = ifp->if_flags; 1281256806Sian FFEC_UNLOCK(sc); 1282256806Sian break; 1283256806Sian 1284256806Sian case SIOCADDMULTI: 1285256806Sian case SIOCDELMULTI: 1286256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1287256806Sian FFEC_LOCK(sc); 1288256806Sian ffec_setup_rxfilter(sc); 1289256806Sian FFEC_UNLOCK(sc); 1290256806Sian } 1291256806Sian break; 1292256806Sian 1293256806Sian case SIOCSIFMEDIA: 1294256806Sian case SIOCGIFMEDIA: 1295256806Sian mii = sc->mii_softc; 1296256806Sian error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1297256806Sian break; 1298256806Sian 1299256806Sian case SIOCSIFCAP: 1300256806Sian mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1301256806Sian if (mask & IFCAP_VLAN_MTU) { 1302256806Sian /* No work to do except acknowledge the change took. */ 1303256806Sian ifp->if_capenable ^= IFCAP_VLAN_MTU; 1304256806Sian } 1305256806Sian break; 1306256806Sian 1307256806Sian default: 1308256806Sian error = ether_ioctl(ifp, cmd, data); 1309256806Sian break; 1310256806Sian } 1311256806Sian 1312256806Sian return (error); 1313256806Sian} 1314256806Sian 1315256806Sianstatic int 1316256806Sianffec_detach(device_t dev) 1317256806Sian{ 1318256806Sian struct ffec_softc *sc; 1319256806Sian bus_dmamap_t map; 1320256806Sian int idx; 1321256806Sian 1322256806Sian /* 1323256806Sian * NB: This function can be called internally to unwind a failure to 1324256806Sian * attach. Make sure a resource got allocated/created before destroying. 1325256806Sian */ 1326256806Sian 1327256806Sian sc = device_get_softc(dev); 1328256806Sian 1329256806Sian if (sc->is_attached) { 1330256806Sian FFEC_LOCK(sc); 1331256806Sian sc->is_detaching = true; 1332256806Sian ffec_stop_locked(sc); 1333256806Sian FFEC_UNLOCK(sc); 1334256806Sian callout_drain(&sc->ffec_callout); 1335256806Sian ether_ifdetach(sc->ifp); 1336256806Sian } 1337256806Sian 1338256806Sian /* XXX no miibus detach? */ 1339256806Sian 1340256806Sian /* Clean up RX DMA resources and free mbufs. */ 1341256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1342256806Sian if ((map = sc->rxbuf_map[idx].map) != NULL) { 1343256806Sian bus_dmamap_unload(sc->rxbuf_tag, map); 1344256806Sian bus_dmamap_destroy(sc->rxbuf_tag, map); 1345256806Sian m_freem(sc->rxbuf_map[idx].mbuf); 1346256806Sian } 1347256806Sian } 1348256806Sian if (sc->rxbuf_tag != NULL) 1349256806Sian bus_dma_tag_destroy(sc->rxbuf_tag); 1350256806Sian if (sc->rxdesc_map != NULL) { 1351256806Sian bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1352256806Sian bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1353256806Sian } 1354256806Sian if (sc->rxdesc_tag != NULL) 1355256806Sian bus_dma_tag_destroy(sc->rxdesc_tag); 1356256806Sian 1357256806Sian /* Clean up TX DMA resources. */ 1358256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1359256806Sian if ((map = sc->txbuf_map[idx].map) != NULL) { 1360256806Sian /* TX maps are already unloaded. */ 1361256806Sian bus_dmamap_destroy(sc->txbuf_tag, map); 1362256806Sian } 1363256806Sian } 1364256806Sian if (sc->txbuf_tag != NULL) 1365256806Sian bus_dma_tag_destroy(sc->txbuf_tag); 1366256806Sian if (sc->txdesc_map != NULL) { 1367256806Sian bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1368256806Sian bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1369256806Sian } 1370256806Sian if (sc->txdesc_tag != NULL) 1371256806Sian bus_dma_tag_destroy(sc->txdesc_tag); 1372256806Sian 1373256806Sian /* Release bus resources. */ 1374256806Sian if (sc->intr_cookie) 1375256806Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1376256806Sian 1377256806Sian if (sc->irq_res != NULL) 1378256806Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1379256806Sian 1380256806Sian if (sc->mem_res != NULL) 1381256806Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1382256806Sian 1383256806Sian FFEC_LOCK_DESTROY(sc); 1384256806Sian return (0); 1385256806Sian} 1386256806Sian 1387256806Sianstatic int 1388256806Sianffec_attach(device_t dev) 1389256806Sian{ 1390256806Sian struct ffec_softc *sc; 1391256806Sian struct ifnet *ifp = NULL; 1392256806Sian struct mbuf *m; 1393256806Sian phandle_t ofw_node; 1394256806Sian int error, rid; 1395256806Sian uint8_t eaddr[ETHER_ADDR_LEN]; 1396256806Sian char phy_conn_name[32]; 1397256806Sian uint32_t idx, mscr; 1398256806Sian 1399256806Sian sc = device_get_softc(dev); 1400256806Sian sc->dev = dev; 1401256806Sian 1402256806Sian FFEC_LOCK_INIT(sc); 1403256806Sian 1404256806Sian /* 1405256806Sian * There are differences in the implementation and features of the FEC 1406256806Sian * hardware on different SoCs, so figure out what type we are. 1407256806Sian */ 1408256806Sian if (ofw_bus_is_compatible(dev, "fsl,imx51-fec")) 1409256806Sian sc->fectype = FECTYPE_IMX51; 1410256806Sian else if (ofw_bus_is_compatible(dev, "fsl,imx53-fec")) 1411256806Sian sc->fectype = FECTYPE_IMX53; 1412256806Sian else if (ofw_bus_is_compatible(dev, "fsl,imx6q-fec")) 1413256806Sian sc->fectype = FECTYPE_IMX6; 1414256806Sian else 1415256806Sian sc->fectype = FECTYPE_GENERIC; 1416256806Sian 1417256806Sian /* 1418256806Sian * We have to be told what kind of electrical connection exists between 1419256806Sian * the MAC and PHY or we can't operate correctly. 1420256806Sian */ 1421256806Sian if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1422256806Sian device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1423256806Sian error = ENXIO; 1424256806Sian goto out; 1425256806Sian } 1426256806Sian if (OF_searchprop(ofw_node, "phy-mode", 1427256806Sian phy_conn_name, sizeof(phy_conn_name)) != -1) { 1428256806Sian if (strcasecmp(phy_conn_name, "mii") == 0) 1429256806Sian sc->phy_conn_type = PHY_CONN_MII; 1430256806Sian else if (strcasecmp(phy_conn_name, "rmii") == 0) 1431256806Sian sc->phy_conn_type = PHY_CONN_RMII; 1432256806Sian else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1433256806Sian sc->phy_conn_type = PHY_CONN_RGMII; 1434256806Sian } 1435256806Sian if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1436256806Sian device_printf(sc->dev, "No valid 'phy-mode' " 1437256806Sian "property found in FDT data for device.\n"); 1438256806Sian error = ENOATTR; 1439256806Sian goto out; 1440256806Sian } 1441256806Sian 1442256806Sian callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1443256806Sian 1444256806Sian /* Allocate bus resources for accessing the hardware. */ 1445256806Sian rid = 0; 1446256806Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1447256806Sian RF_ACTIVE); 1448256806Sian if (sc->mem_res == NULL) { 1449256806Sian device_printf(dev, "could not allocate memory resources.\n"); 1450256806Sian error = ENOMEM; 1451256806Sian goto out; 1452256806Sian } 1453256806Sian rid = 0; 1454256806Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1455256806Sian RF_ACTIVE); 1456256806Sian if (sc->irq_res == NULL) { 1457256806Sian device_printf(dev, "could not allocate interrupt resources.\n"); 1458256806Sian error = ENOMEM; 1459256806Sian goto out; 1460256806Sian } 1461256806Sian 1462256806Sian /* 1463256806Sian * Set up TX descriptor ring, descriptors, and dma maps. 1464256806Sian */ 1465256806Sian error = bus_dma_tag_create( 1466256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1467256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1468256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1469256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1470256806Sian NULL, NULL, /* filter, filterarg */ 1471256806Sian TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1472256806Sian TX_DESC_SIZE, /* maxsegsize */ 1473256806Sian 0, /* flags */ 1474256806Sian NULL, NULL, /* lockfunc, lockarg */ 1475256806Sian &sc->txdesc_tag); 1476256806Sian if (error != 0) { 1477256806Sian device_printf(sc->dev, 1478256806Sian "could not create TX ring DMA tag.\n"); 1479256806Sian goto out; 1480256806Sian } 1481256806Sian 1482256806Sian error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1483256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1484256806Sian if (error != 0) { 1485256806Sian device_printf(sc->dev, 1486256806Sian "could not allocate TX descriptor ring.\n"); 1487256806Sian goto out; 1488256806Sian } 1489256806Sian 1490256806Sian error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1491256806Sian TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1492256806Sian if (error != 0) { 1493256806Sian device_printf(sc->dev, 1494256806Sian "could not load TX descriptor ring map.\n"); 1495256806Sian goto out; 1496256806Sian } 1497256806Sian 1498256806Sian error = bus_dma_tag_create( 1499256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1500256806Sian FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1501256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1502256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1503256806Sian NULL, NULL, /* filter, filterarg */ 1504256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1505256806Sian MCLBYTES, /* maxsegsize */ 1506256806Sian 0, /* flags */ 1507256806Sian NULL, NULL, /* lockfunc, lockarg */ 1508256806Sian &sc->txbuf_tag); 1509256806Sian if (error != 0) { 1510256806Sian device_printf(sc->dev, 1511256806Sian "could not create TX ring DMA tag.\n"); 1512256806Sian goto out; 1513256806Sian } 1514256806Sian 1515256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1516256806Sian error = bus_dmamap_create(sc->txbuf_tag, 0, 1517256806Sian &sc->txbuf_map[idx].map); 1518256806Sian if (error != 0) { 1519256806Sian device_printf(sc->dev, 1520256806Sian "could not create TX buffer DMA map.\n"); 1521256806Sian goto out; 1522256806Sian } 1523256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1524256806Sian } 1525256806Sian 1526256806Sian /* 1527256806Sian * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1528256806Sian */ 1529256806Sian error = bus_dma_tag_create( 1530256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1531256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1532256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1533256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1534256806Sian NULL, NULL, /* filter, filterarg */ 1535256806Sian RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1536256806Sian RX_DESC_SIZE, /* maxsegsize */ 1537256806Sian 0, /* flags */ 1538256806Sian NULL, NULL, /* lockfunc, lockarg */ 1539256806Sian &sc->rxdesc_tag); 1540256806Sian if (error != 0) { 1541256806Sian device_printf(sc->dev, 1542256806Sian "could not create RX ring DMA tag.\n"); 1543256806Sian goto out; 1544256806Sian } 1545256806Sian 1546256806Sian error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1547256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1548256806Sian if (error != 0) { 1549256806Sian device_printf(sc->dev, 1550256806Sian "could not allocate RX descriptor ring.\n"); 1551256806Sian goto out; 1552256806Sian } 1553256806Sian 1554256806Sian error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1555256806Sian RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1556256806Sian if (error != 0) { 1557256806Sian device_printf(sc->dev, 1558256806Sian "could not load RX descriptor ring map.\n"); 1559256806Sian goto out; 1560256806Sian } 1561256806Sian 1562256806Sian error = bus_dma_tag_create( 1563256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1564256806Sian 1, 0, /* alignment, boundary */ 1565256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1566256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1567256806Sian NULL, NULL, /* filter, filterarg */ 1568256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1569256806Sian MCLBYTES, /* maxsegsize */ 1570256806Sian 0, /* flags */ 1571256806Sian NULL, NULL, /* lockfunc, lockarg */ 1572256806Sian &sc->rxbuf_tag); 1573256806Sian if (error != 0) { 1574256806Sian device_printf(sc->dev, 1575256806Sian "could not create RX buf DMA tag.\n"); 1576256806Sian goto out; 1577256806Sian } 1578256806Sian 1579256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1580256806Sian error = bus_dmamap_create(sc->rxbuf_tag, 0, 1581256806Sian &sc->rxbuf_map[idx].map); 1582256806Sian if (error != 0) { 1583256806Sian device_printf(sc->dev, 1584256806Sian "could not create RX buffer DMA map.\n"); 1585256806Sian goto out; 1586256806Sian } 1587256806Sian if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1588256806Sian device_printf(dev, "Could not alloc mbuf\n"); 1589256806Sian error = ENOMEM; 1590256806Sian goto out; 1591256806Sian } 1592256806Sian if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1593256806Sian device_printf(sc->dev, 1594256806Sian "could not create new RX buffer.\n"); 1595256806Sian goto out; 1596256806Sian } 1597256806Sian } 1598256806Sian 1599256806Sian /* Try to get the MAC address from the hardware before resetting it. */ 1600256806Sian ffec_get_hwaddr(sc, eaddr); 1601256806Sian 1602256806Sian /* Reset the hardware. Disables all interrupts. */ 1603256806Sian WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1604256806Sian 1605256806Sian /* Setup interrupt handler. */ 1606256806Sian error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1607256806Sian NULL, ffec_intr, sc, &sc->intr_cookie); 1608256806Sian if (error != 0) { 1609256806Sian device_printf(dev, "could not setup interrupt handler.\n"); 1610256806Sian goto out; 1611256806Sian } 1612256806Sian 1613256806Sian /* 1614256806Sian * Set up the PHY control register. 1615256806Sian * 1616256806Sian * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1617256806Sian * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1618256806Sian * 1619256806Sian * XXX - Revisit this... 1620256806Sian * 1621256806Sian * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1622256806Sian * code uses 10. Both values seem to work, but I suspect many modern 1623256806Sian * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1624256806Sian * 1625256806Sian * Different imx manuals use confusingly different terminology (things 1626256806Sian * like "system clock" and "internal module clock") with examples that 1627256806Sian * use frequencies that have nothing to do with ethernet, giving the 1628256806Sian * vague impression that maybe the clock in question is the periphclock 1629256806Sian * or something. In fact, on an imx53 development board (FEC), 1630256806Sian * measuring the mdio clock at the pin on the PHY and playing with 1631256806Sian * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1632256806Sian * aka periphclock) and 13 was the right divisor. 1633256806Sian * 1634256806Sian * All in all, it seems likely that 13 is a safe divisor for now, 1635256806Sian * because if we really do need to base it on the peripheral clock 1636256806Sian * speed, then we need a platform-independant get-clock-freq API. 1637256806Sian */ 1638256806Sian mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1639256806Sian if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1640256806Sian mscr |= FEC_MSCR_DIS_PRE; 1641256806Sian if (bootverbose) 1642256806Sian device_printf(dev, "PHY preamble disabled\n"); 1643256806Sian } 1644256806Sian WR4(sc, FEC_MSCR_REG, mscr); 1645256806Sian 1646256806Sian /* Set up the ethernet interface. */ 1647256806Sian sc->ifp = ifp = if_alloc(IFT_ETHER); 1648256806Sian 1649256806Sian ifp->if_softc = sc; 1650256806Sian if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1651256806Sian ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1652256806Sian ifp->if_capabilities = IFCAP_VLAN_MTU; 1653256806Sian ifp->if_capenable = ifp->if_capabilities; 1654256806Sian ifp->if_start = ffec_txstart; 1655256806Sian ifp->if_ioctl = ffec_ioctl; 1656256806Sian ifp->if_init = ffec_init; 1657256806Sian IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1658256806Sian ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1659256806Sian IFQ_SET_READY(&ifp->if_snd); 1660256806Sian ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1661256806Sian 1662256806Sian#if 0 /* XXX The hardware keeps stats we could use for these. */ 1663256806Sian ifp->if_linkmib = &sc->mibdata; 1664256806Sian ifp->if_linkmiblen = sizeof(sc->mibdata); 1665256806Sian#endif 1666256806Sian 1667256806Sian /* Set up the miigasket hardware (if any). */ 1668256806Sian ffec_miigasket_setup(sc); 1669256806Sian 1670256806Sian /* Attach the mii driver. */ 1671256806Sian error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1672256806Sian ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1673256806Sian if (error != 0) { 1674256806Sian device_printf(dev, "PHY attach failed\n"); 1675256806Sian goto out; 1676256806Sian } 1677256806Sian sc->mii_softc = device_get_softc(sc->miibus); 1678256806Sian 1679256806Sian /* All ready to run, attach the ethernet interface. */ 1680256806Sian ether_ifattach(ifp, eaddr); 1681256806Sian sc->is_attached = true; 1682256806Sian 1683256806Sian error = 0; 1684256806Sianout: 1685256806Sian 1686256806Sian if (error != 0) 1687256806Sian ffec_detach(dev); 1688256806Sian 1689256806Sian return (error); 1690256806Sian} 1691256806Sian 1692256806Sianstatic int 1693256806Sianffec_probe(device_t dev) 1694256806Sian{ 1695256806Sian 1696256806Sian if (ofw_bus_is_compatible(dev, "fsl,imx51-fec") || 1697256806Sian ofw_bus_is_compatible(dev, "fsl,imx53-fec")) { 1698256806Sian device_set_desc(dev, "Freescale Fast Ethernet Controller"); 1699256806Sian } else if (ofw_bus_is_compatible(dev, "fsl,imx6q-fec")) { 1700256806Sian device_set_desc(dev, "Freescale Gigabit Ethernet Controller"); 1701256806Sian } else { 1702256806Sian return (ENXIO); 1703256806Sian } 1704256806Sian return (BUS_PROBE_DEFAULT); 1705256806Sian} 1706256806Sian 1707256806Sian 1708256806Sianstatic device_method_t ffec_methods[] = { 1709256806Sian /* Device interface. */ 1710256806Sian DEVMETHOD(device_probe, ffec_probe), 1711256806Sian DEVMETHOD(device_attach, ffec_attach), 1712256806Sian DEVMETHOD(device_detach, ffec_detach), 1713256806Sian 1714256806Sian/* 1715256806Sian DEVMETHOD(device_shutdown, ffec_shutdown), 1716256806Sian DEVMETHOD(device_suspend, ffec_suspend), 1717256806Sian DEVMETHOD(device_resume, ffec_resume), 1718256806Sian*/ 1719256806Sian 1720256806Sian /* MII interface. */ 1721256806Sian DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1722256806Sian DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1723256806Sian DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1724256806Sian 1725256806Sian DEVMETHOD_END 1726256806Sian}; 1727256806Sian 1728256806Sianstatic driver_t ffec_driver = { 1729256806Sian "ffec", 1730256806Sian ffec_methods, 1731256806Sian sizeof(struct ffec_softc) 1732256806Sian}; 1733256806Sian 1734256806Sianstatic devclass_t ffec_devclass; 1735256806Sian 1736256806SianDRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1737256806SianDRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1738256806Sian 1739256806SianMODULE_DEPEND(ffec, ether, 1, 1, 1); 1740256806SianMODULE_DEPEND(ffec, miibus, 1, 1, 1); 1741