if_ffec.c revision 256806
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffec.c 256806 2013-10-20 21:07:38Z ian $"); 30 31/* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/bus.h> 58#include <sys/endian.h> 59#include <sys/kernel.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mbuf.h> 63#include <sys/module.h> 64#include <sys/mutex.h> 65#include <sys/rman.h> 66#include <sys/socket.h> 67#include <sys/sockio.h> 68#include <sys/sysctl.h> 69 70#include <machine/bus.h> 71 72#include <net/bpf.h> 73#include <net/if.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77#include <net/if_types.h> 78#include <net/if_var.h> 79#include <net/if_vlan_var.h> 80 81#include <dev/ffec/if_ffecreg.h> 82#include <dev/ofw/ofw_bus.h> 83#include <dev/ofw/ofw_bus_subr.h> 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86#include "miibus_if.h" 87 88/* 89 * Driver data and defines. 90 */ 91#define RX_DESC_COUNT 64 92#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 93#define TX_DESC_COUNT 64 94#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 95 96#define WATCHDOG_TIMEOUT_SECS 5 97#define STATS_HARVEST_INTERVAL 3 98 99struct ffec_bufmap { 100 struct mbuf *mbuf; 101 bus_dmamap_t map; 102}; 103 104enum { 105 PHY_CONN_UNKNOWN, 106 PHY_CONN_MII, 107 PHY_CONN_RMII, 108 PHY_CONN_RGMII 109}; 110 111enum { 112 FECTYPE_GENERIC, 113 FECTYPE_IMX51, 114 FECTYPE_IMX53, 115 FECTYPE_IMX6, 116}; 117 118struct ffec_softc { 119 device_t dev; 120 device_t miibus; 121 struct mii_data * mii_softc; 122 struct ifnet *ifp; 123 int if_flags; 124 struct mtx mtx; 125 struct resource *irq_res; 126 struct resource *mem_res; 127 void * intr_cookie; 128 struct callout ffec_callout; 129 uint8_t phy_conn_type; 130 uint8_t fectype; 131 boolean_t link_is_up; 132 boolean_t is_attached; 133 boolean_t is_detaching; 134 int tx_watchdog_count; 135 int stats_harvest_count; 136 137 bus_dma_tag_t rxdesc_tag; 138 bus_dmamap_t rxdesc_map; 139 struct ffec_hwdesc *rxdesc_ring; 140 bus_addr_t rxdesc_ring_paddr; 141 bus_dma_tag_t rxbuf_tag; 142 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 143 uint32_t rx_idx; 144 145 bus_dma_tag_t txdesc_tag; 146 bus_dmamap_t txdesc_map; 147 struct ffec_hwdesc *txdesc_ring; 148 bus_addr_t txdesc_ring_paddr; 149 bus_dma_tag_t txbuf_tag; 150 struct ffec_bufmap txbuf_map[RX_DESC_COUNT]; 151 uint32_t tx_idx_head; 152 uint32_t tx_idx_tail; 153 int txcount; 154}; 155 156#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 157#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 158#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 159 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 160#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 161#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 162#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 163 164static void ffec_init_locked(struct ffec_softc *sc); 165static void ffec_stop_locked(struct ffec_softc *sc); 166static void ffec_txstart_locked(struct ffec_softc *sc); 167static void ffec_txfinish_locked(struct ffec_softc *sc); 168 169static inline uint16_t 170RD2(struct ffec_softc *sc, bus_size_t off) 171{ 172 173 return (bus_read_2(sc->mem_res, off)); 174} 175 176static inline void 177WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 178{ 179 180 bus_write_2(sc->mem_res, off, val); 181} 182 183static inline uint32_t 184RD4(struct ffec_softc *sc, bus_size_t off) 185{ 186 187 return (bus_read_4(sc->mem_res, off)); 188} 189 190static inline void 191WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 192{ 193 194 bus_write_4(sc->mem_res, off, val); 195} 196 197static inline uint32_t 198next_rxidx(struct ffec_softc *sc, uint32_t curidx) 199{ 200 201 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 202} 203 204static inline uint32_t 205next_txidx(struct ffec_softc *sc, uint32_t curidx) 206{ 207 208 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 209} 210 211static void 212ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 213{ 214 215 if (error != 0) 216 return; 217 *(bus_addr_t *)arg = segs[0].ds_addr; 218} 219 220static void 221ffec_miigasket_setup(struct ffec_softc *sc) 222{ 223 uint32_t ifmode; 224 225 /* 226 * We only need the gasket for MII and RMII connections on certain SoCs. 227 */ 228 229 switch (sc->fectype) 230 { 231 case FECTYPE_IMX53: 232 break; 233 default: 234 return; 235 } 236 237 switch (sc->phy_conn_type) 238 { 239 case PHY_CONN_MII: 240 ifmode = 0; 241 break; 242 case PHY_CONN_RMII: 243 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 244 break; 245 default: 246 return; 247 } 248 249 /* 250 * Disable the gasket, configure for either MII or RMII, then enable. 251 */ 252 253 WR2(sc, FEC_MIIGSK_ENR, 0); 254 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 255 continue; 256 257 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 258 259 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 260 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 261 continue; 262} 263 264static boolean_t 265ffec_miibus_iowait(struct ffec_softc *sc) 266{ 267 uint32_t timeout; 268 269 for (timeout = 10000; timeout != 0; --timeout) 270 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 271 return (true); 272 273 return (false); 274} 275 276static int 277ffec_miibus_readreg(device_t dev, int phy, int reg) 278{ 279 struct ffec_softc *sc; 280 int val; 281 282 sc = device_get_softc(dev); 283 284 WR4(sc, FEC_IER_REG, FEC_IER_MII); 285 286 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 287 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 288 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 289 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 290 291 if (!ffec_miibus_iowait(sc)) { 292 device_printf(dev, "timeout waiting for mii read\n"); 293 return (-1); /* All-ones is a symptom of bad mdio. */ 294 } 295 296 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 297 298 return (val); 299} 300 301static int 302ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 303{ 304 struct ffec_softc *sc; 305 306 sc = device_get_softc(dev); 307 308 WR4(sc, FEC_IER_REG, FEC_IER_MII); 309 310 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 311 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 312 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 313 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 314 (val & FEC_MMFR_DATA_MASK)); 315 316 if (!ffec_miibus_iowait(sc)) { 317 device_printf(dev, "timeout waiting for mii write\n"); 318 return (-1); 319 } 320 321 return (0); 322} 323 324static void 325ffec_miibus_statchg(device_t dev) 326{ 327 struct ffec_softc *sc; 328 struct mii_data *mii; 329 uint32_t ecr, rcr, tcr; 330 331 /* 332 * Called by the MII bus driver when the PHY establishes link to set the 333 * MAC interface registers. 334 */ 335 336 sc = device_get_softc(dev); 337 338 FFEC_ASSERT_LOCKED(sc); 339 340 mii = sc->mii_softc; 341 342 if (mii->mii_media_status & IFM_ACTIVE) 343 sc->link_is_up = true; 344 else 345 sc->link_is_up = false; 346 347 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 348 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 349 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 350 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 351 352 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 353 switch (sc->phy_conn_type) { 354 case PHY_CONN_MII: 355 break; 356 case PHY_CONN_RMII: 357 rcr |= FEC_RCR_RMII_MODE; 358 break; 359 case PHY_CONN_RGMII: 360 rcr |= FEC_RCR_RGMII_EN; 361 break; 362 } 363 364 switch (IFM_SUBTYPE(mii->mii_media_active)) { 365 case IFM_1000_T: 366 case IFM_1000_SX: 367 ecr |= FEC_ECR_SPEED; 368 break; 369 case IFM_100_TX: 370 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 371 break; 372 case IFM_10_T: 373 rcr |= FEC_RCR_RMII_10T; 374 break; 375 case IFM_NONE: 376 sc->link_is_up = false; 377 return; 378 default: 379 sc->link_is_up = false; 380 device_printf(dev, "Unsupported media %u\n", 381 IFM_SUBTYPE(mii->mii_media_active)); 382 return; 383 } 384 385 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 386 tcr |= FEC_TCR_FDEN; 387 else 388 rcr |= FEC_RCR_DRT; 389 390 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 391 rcr |= FEC_RCR_FCE; 392 393 WR4(sc, FEC_RCR_REG, rcr); 394 WR4(sc, FEC_TCR_REG, tcr); 395 WR4(sc, FEC_ECR_REG, ecr); 396} 397 398static void 399ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 400{ 401 struct ffec_softc *sc; 402 struct mii_data *mii; 403 404 405 sc = ifp->if_softc; 406 mii = sc->mii_softc; 407 FFEC_LOCK(sc); 408 mii_pollstat(mii); 409 ifmr->ifm_active = mii->mii_media_active; 410 ifmr->ifm_status = mii->mii_media_status; 411 FFEC_UNLOCK(sc); 412} 413 414static int 415ffec_media_change_locked(struct ffec_softc *sc) 416{ 417 418 return (mii_mediachg(sc->mii_softc)); 419} 420 421static int 422ffec_media_change(struct ifnet * ifp) 423{ 424 struct ffec_softc *sc; 425 int error; 426 427 sc = ifp->if_softc; 428 429 FFEC_LOCK(sc); 430 error = ffec_media_change_locked(sc); 431 FFEC_UNLOCK(sc); 432 return (error); 433} 434 435static void ffec_clear_stats(struct ffec_softc *sc) 436{ 437 438 WR4(sc, FEC_RMON_R_PACKETS, 0); 439 WR4(sc, FEC_RMON_R_MC_PKT, 0); 440 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 441 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 442 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 443 WR4(sc, FEC_RMON_R_FRAG, 0); 444 WR4(sc, FEC_RMON_R_JAB, 0); 445 WR4(sc, FEC_RMON_T_PACKETS, 0); 446 WR4(sc, FEC_RMON_T_MC_PKT, 0); 447 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 448 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 449 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 450 WR4(sc, FEC_RMON_T_FRAG, 0); 451 WR4(sc, FEC_RMON_T_JAB, 0); 452 WR4(sc, FEC_RMON_T_COL, 0); 453} 454 455static void 456ffec_harvest_stats(struct ffec_softc *sc) 457{ 458 struct ifnet *ifp; 459 460 /* We don't need to harvest too often. */ 461 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 462 return; 463 464 /* 465 * Try to avoid harvesting unless the IDLE flag is on, but if it has 466 * been too long just go ahead and do it anyway, the worst that'll 467 * happen is we'll lose a packet count or two as we clear at the end. 468 */ 469 if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 470 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 471 return; 472 473 sc->stats_harvest_count = 0; 474 ifp = sc->ifp; 475 476 ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS); 477 ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT); 478 ifp->if_ierrors += RD4(sc, FEC_RMON_R_CRC_ALIGN); 479 ifp->if_ierrors += RD4(sc, FEC_RMON_R_UNDERSIZE); 480 ifp->if_ierrors += RD4(sc, FEC_RMON_R_OVERSIZE); 481 ifp->if_ierrors += RD4(sc, FEC_RMON_R_FRAG); 482 ifp->if_ierrors += RD4(sc, FEC_RMON_R_JAB); 483 484 ifp->if_opackets += RD4(sc, FEC_RMON_T_PACKETS); 485 ifp->if_omcasts += RD4(sc, FEC_RMON_T_MC_PKT); 486 ifp->if_oerrors += RD4(sc, FEC_RMON_T_CRC_ALIGN); 487 ifp->if_oerrors += RD4(sc, FEC_RMON_T_UNDERSIZE); 488 ifp->if_oerrors += RD4(sc, FEC_RMON_T_OVERSIZE ); 489 ifp->if_oerrors += RD4(sc, FEC_RMON_T_FRAG); 490 ifp->if_oerrors += RD4(sc, FEC_RMON_T_JAB); 491 492 ifp->if_collisions += RD4(sc, FEC_RMON_T_COL); 493 494 ffec_clear_stats(sc); 495} 496 497static void 498ffec_tick(void *arg) 499{ 500 struct ffec_softc *sc; 501 struct ifnet *ifp; 502 int link_was_up; 503 504 sc = arg; 505 506 FFEC_ASSERT_LOCKED(sc); 507 508 ifp = sc->ifp; 509 510 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 511 return; 512 513 /* 514 * Typical tx watchdog. If this fires it indicates that we enqueued 515 * packets for output and never got a txdone interrupt for them. Maybe 516 * it's a missed interrupt somehow, just pretend we got one. 517 */ 518 if (sc->tx_watchdog_count > 0) { 519 if (--sc->tx_watchdog_count == 0) { 520 ffec_txfinish_locked(sc); 521 } 522 } 523 524 /* Gather stats from hardware counters. */ 525 ffec_harvest_stats(sc); 526 527 /* Check the media status. */ 528 link_was_up = sc->link_is_up; 529 mii_tick(sc->mii_softc); 530 if (sc->link_is_up && !link_was_up) 531 ffec_txstart_locked(sc); 532 533 /* Schedule another check one second from now. */ 534 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 535} 536 537inline static uint32_t 538ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 539 uint32_t len) 540{ 541 uint32_t nidx; 542 uint32_t flags; 543 544 nidx = next_txidx(sc, idx); 545 546 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 547 if (paddr == 0 || len == 0) { 548 flags = 0; 549 --sc->txcount; 550 } else { 551 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 552 ++sc->txcount; 553 } 554 if (nidx == 0) 555 flags |= FEC_TXDESC_WRAP; 556 557 /* 558 * The hardware requires 32-bit physical addresses. We set up the dma 559 * tag to indicate that, so the cast to uint32_t should never lose 560 * significant bits. 561 */ 562 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 563 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 564 565 return (nidx); 566} 567 568static int 569ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 570{ 571 struct mbuf * m; 572 int error, nsegs; 573 struct bus_dma_segment seg; 574 575 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 576 return (ENOMEM); 577 *mp = m; 578 579 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 580 m, &seg, &nsegs, 0); 581 if (error != 0) { 582 return (ENOMEM); 583 } 584 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 585 BUS_DMASYNC_PREWRITE); 586 587 sc->txbuf_map[idx].mbuf = m; 588 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 589 590 return (0); 591 592} 593 594static void 595ffec_txstart_locked(struct ffec_softc *sc) 596{ 597 struct ifnet *ifp; 598 struct mbuf *m; 599 int enqueued; 600 601 FFEC_ASSERT_LOCKED(sc); 602 603 if (!sc->link_is_up) 604 return; 605 606 ifp = sc->ifp; 607 608 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 609 return; 610 611 enqueued = 0; 612 613 for (;;) { 614 if (sc->txcount == (TX_DESC_COUNT-1)) { 615 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 616 break; 617 } 618 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 619 if (m == NULL) 620 break; 621 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 622 IFQ_DRV_PREPEND(&ifp->if_snd, m); 623 break; 624 } 625 BPF_MTAP(ifp, m); 626 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 627 ++enqueued; 628 } 629 630 if (enqueued != 0) { 631 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 632 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 633 } 634} 635 636static void 637ffec_txstart(struct ifnet *ifp) 638{ 639 struct ffec_softc *sc = ifp->if_softc; 640 641 FFEC_LOCK(sc); 642 ffec_txstart_locked(sc); 643 FFEC_UNLOCK(sc); 644} 645 646static void 647ffec_txfinish_locked(struct ffec_softc *sc) 648{ 649 struct ifnet *ifp; 650 struct ffec_hwdesc *desc; 651 struct ffec_bufmap *bmap; 652 boolean_t retired_buffer; 653 654 FFEC_ASSERT_LOCKED(sc); 655 656 ifp = sc->ifp; 657 retired_buffer = false; 658 while (sc->tx_idx_tail != sc->tx_idx_head) { 659 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 660 if (desc->flags_len & FEC_TXDESC_READY) 661 break; 662 retired_buffer = true; 663 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 664 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 665 BUS_DMASYNC_POSTWRITE); 666 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 667 m_freem(bmap->mbuf); 668 bmap->mbuf = NULL; 669 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 670 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 671 } 672 673 /* 674 * If we retired any buffers, there will be open tx slots available in 675 * the descriptor ring, go try to start some new output. 676 */ 677 if (retired_buffer) { 678 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 679 ffec_txstart_locked(sc); 680 } 681 682 /* If there are no buffers outstanding, muzzle the watchdog. */ 683 if (sc->tx_idx_tail == sc->tx_idx_head) { 684 sc->tx_watchdog_count = 0; 685 } 686} 687 688inline static uint32_t 689ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 690{ 691 uint32_t nidx; 692 693 /* 694 * The hardware requires 32-bit physical addresses. We set up the dma 695 * tag to indicate that, so the cast to uint32_t should never lose 696 * significant bits. 697 */ 698 nidx = next_rxidx(sc, idx); 699 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 700 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 701 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 702 703 return (nidx); 704} 705 706static int 707ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 708{ 709 int error, nsegs; 710 struct bus_dma_segment seg; 711 712 /* 713 * We need to leave at least ETHER_ALIGN bytes free at the beginning of 714 * the buffer to allow the data to be re-aligned after receiving it (by 715 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 716 * have to ensure that the beginning of the buffer is aligned to the 717 * hardware's requirements. 718 */ 719 m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 720 721 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 722 m, &seg, &nsegs, 0); 723 if (error != 0) { 724 return (error); 725 } 726 727 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 728 BUS_DMASYNC_PREREAD); 729 730 sc->rxbuf_map[idx].mbuf = m; 731 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 732 733 return (0); 734} 735 736static struct mbuf * 737ffec_alloc_mbufcl(struct ffec_softc *sc) 738{ 739 struct mbuf *m; 740 741 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 742 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 743 744 return (m); 745} 746 747static void 748ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 749{ 750 struct mbuf *m, *newmbuf; 751 struct ffec_bufmap *bmap; 752 uint8_t *dst, *src; 753 int error; 754 755 /* 756 * First try to get a new mbuf to plug into this slot in the rx ring. 757 * If that fails, drop the current packet and recycle the current 758 * mbuf, which is still mapped and loaded. 759 */ 760 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 761 ++sc->ifp->if_iqdrops; 762 ffec_setup_rxdesc(sc, sc->rx_idx, 763 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 764 return; 765 } 766 767 /* 768 * Unfortunately, the protocol headers need to be aligned on a 32-bit 769 * boundary for the upper layers. The hardware requires receive 770 * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 771 * leaving the protocol header unaligned. We used m_adj() after 772 * allocating the buffer to leave empty space at the start of the 773 * buffer, now we'll use the alignment agnostic bcopy() routine to 774 * shuffle all the data backwards 2 bytes and adjust m_data. 775 * 776 * XXX imx6 hardware is able to do this 2-byte alignment by setting the 777 * SHIFT16 bit in the RACC register. Older hardware doesn't have that 778 * feature, but for them could we speed this up by copying just the 779 * protocol headers into their own small mbuf then chaining the cluster 780 * to it? That way we'd only need to copy like 64 bytes or whatever 781 * the biggest header is, instead of the whole 1530ish-byte frame. 782 */ 783 784 FFEC_UNLOCK(sc); 785 786 bmap = &sc->rxbuf_map[sc->rx_idx]; 787 len -= ETHER_CRC_LEN; 788 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 789 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 790 m = bmap->mbuf; 791 bmap->mbuf = NULL; 792 m->m_len = len; 793 m->m_pkthdr.len = len; 794 m->m_pkthdr.rcvif = sc->ifp; 795 796 src = mtod(m, uint8_t*); 797 dst = src - ETHER_ALIGN; 798 bcopy(src, dst, len); 799 m->m_data = dst; 800 sc->ifp->if_input(sc->ifp, m); 801 802 FFEC_LOCK(sc); 803 804 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 805 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 806 /* XXX Now what? We've got a hole in the rx ring. */ 807 } 808 809} 810 811static void 812ffec_rxfinish_locked(struct ffec_softc *sc) 813{ 814 struct ffec_hwdesc *desc; 815 int len; 816 boolean_t produced_empty_buffer; 817 818 FFEC_ASSERT_LOCKED(sc); 819 820 produced_empty_buffer = false; 821 for (;;) { 822 desc = &sc->rxdesc_ring[sc->rx_idx]; 823 if (desc->flags_len & FEC_RXDESC_EMPTY) 824 break; 825 produced_empty_buffer = true; 826 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 827 if (len < 64) { 828 /* 829 * Just recycle the descriptor and continue. . 830 */ 831 ffec_setup_rxdesc(sc, sc->rx_idx, 832 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 833 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 834 /* 835 * The entire frame is not in this buffer. Impossible. 836 * Recycle the descriptor and continue. 837 * 838 * XXX what's the right way to handle this? Probably we 839 * should stop/init the hardware because this should 840 * just really never happen when we have buffers bigger 841 * than the maximum frame size. 842 */ 843 device_printf(sc->dev, 844 "fec_rxfinish: received frame without LAST bit set"); 845 ffec_setup_rxdesc(sc, sc->rx_idx, 846 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 847 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 848 /* 849 * Something went wrong with receiving the frame, we 850 * don't care what (the hardware has counted the error 851 * in the stats registers already), we just reuse the 852 * same mbuf, which is still dma-mapped, by resetting 853 * the rx descriptor. 854 */ 855 ffec_setup_rxdesc(sc, sc->rx_idx, 856 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 857 } else { 858 /* 859 * Normal case: a good frame all in one buffer. 860 */ 861 ffec_rxfinish_onebuf(sc, len); 862 } 863 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 864 } 865 866 if (produced_empty_buffer) { 867 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 868 } 869} 870 871static void 872ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 873{ 874 uint32_t palr, paur, rnd; 875 876 /* 877 * Try to recover a MAC address from the running hardware. If there's 878 * something non-zero there, assume the bootloader did the right thing 879 * and just use it. 880 * 881 * Otherwise, set the address to a convenient locally assigned address, 882 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 883 * assigned bit set, and the broadcast/multicast bit clear. 884 */ 885 palr = RD4(sc, FEC_PALR_REG); 886 paur = RD4(sc, FEC_PAUR_REG); 887 if ((palr | paur) != 0) { 888 hwaddr[0] = palr >> 24; 889 hwaddr[1] = palr >> 16; 890 hwaddr[2] = palr >> 8; 891 hwaddr[3] = palr >> 0; 892 hwaddr[4] = paur >> 24; 893 hwaddr[5] = paur >> 16; 894 return; 895 } else { 896 rnd = arc4random() & 0x00ffffff; 897 hwaddr[0] = 'b'; 898 hwaddr[1] = 's'; 899 hwaddr[2] = 'd'; 900 hwaddr[3] = rnd >> 16; 901 hwaddr[4] = rnd >> 8; 902 hwaddr[5] = rnd >> 0; 903 } 904 905 if (bootverbose) { 906 device_printf(sc->dev, 907 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 908 hwaddr[0], hwaddr[1], hwaddr[2], 909 hwaddr[3], hwaddr[4], hwaddr[5]); 910 } 911} 912 913static void 914ffec_setup_rxfilter(struct ffec_softc *sc) 915{ 916 struct ifnet *ifp; 917 struct ifmultiaddr *ifma; 918 uint8_t *eaddr; 919 uint32_t crc; 920 uint64_t ghash, ihash; 921 922 FFEC_ASSERT_LOCKED(sc); 923 924 ifp = sc->ifp; 925 926 /* 927 * Set the multicast (group) filter hash. 928 */ 929 if ((ifp->if_flags & IFF_ALLMULTI)) 930 ghash = 0xffffffffffffffffLLU; 931 else { 932 ghash = 0; 933 if_maddr_rlock(ifp); 934 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 935 if (ifma->ifma_addr->sa_family != AF_LINK) 936 continue; 937 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 938 ifma->ifma_addr), ETHER_ADDR_LEN); 939 ghash |= 1 << (crc & 0x3f); 940 } 941 if_maddr_runlock(ifp); 942 } 943 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 944 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 945 946 /* 947 * Set the individual address filter hash. 948 * 949 * XXX Is 0 the right value when promiscuous is off? This hw feature 950 * seems to support the concept of MAC address aliases, does such a 951 * thing even exist? 952 */ 953 if ((ifp->if_flags & IFF_PROMISC)) 954 ihash = 0xffffffffffffffffLLU; 955 else { 956 ihash = 0; 957 } 958 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 959 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 960 961 /* 962 * Set the primary address. 963 */ 964 eaddr = IF_LLADDR(ifp); 965 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 966 (eaddr[2] << 8) | eaddr[3]); 967 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 968} 969 970static void 971ffec_stop_locked(struct ffec_softc *sc) 972{ 973 struct ifnet *ifp; 974 struct ffec_hwdesc *desc; 975 struct ffec_bufmap *bmap; 976 int idx; 977 978 FFEC_ASSERT_LOCKED(sc); 979 980 ifp = sc->ifp; 981 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 982 sc->tx_watchdog_count = 0; 983 sc->stats_harvest_count = 0; 984 985 /* 986 * Stop the hardware, mask all interrupts, and clear all current 987 * interrupt status bits. 988 */ 989 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 990 WR4(sc, FEC_IEM_REG, 0x00000000); 991 WR4(sc, FEC_IER_REG, 0xffffffff); 992 993 /* 994 * Stop the media-check callout. Do not use callout_drain() because 995 * we're holding a mutex the callout acquires, and if it's currently 996 * waiting to acquire it, we'd deadlock. If it is waiting now, the 997 * ffec_tick() routine will return without doing anything when it sees 998 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 999 */ 1000 callout_stop(&sc->ffec_callout); 1001 1002 /* 1003 * Discard all untransmitted buffers. Each buffer is simply freed; 1004 * it's as if the bits were transmitted and then lost on the wire. 1005 * 1006 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1007 * back on the queue for when we get restarted later? 1008 */ 1009 idx = sc->tx_idx_tail; 1010 while (idx != sc->tx_idx_head) { 1011 desc = &sc->txdesc_ring[idx]; 1012 bmap = &sc->txbuf_map[idx]; 1013 if (desc->buf_paddr != 0) { 1014 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1015 m_freem(bmap->mbuf); 1016 bmap->mbuf = NULL; 1017 ffec_setup_txdesc(sc, idx, 0, 0); 1018 } 1019 idx = next_txidx(sc, idx); 1020 } 1021 1022 /* 1023 * Discard all unprocessed receive buffers. This amounts to just 1024 * pretending that nothing ever got received into them. We reuse the 1025 * mbuf already mapped for each desc, simply turning the EMPTY flags 1026 * back on so they'll get reused when we start up again. 1027 */ 1028 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1029 desc = &sc->rxdesc_ring[idx]; 1030 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1031 } 1032} 1033 1034static void 1035ffec_init_locked(struct ffec_softc *sc) 1036{ 1037 struct ifnet *ifp = sc->ifp; 1038 uint32_t maxbuf, maxfl, regval; 1039 1040 FFEC_ASSERT_LOCKED(sc); 1041 1042 /* 1043 * The hardware has a limit of 0x7ff as the max frame length (see 1044 * comments for MRBR below), and we use mbuf clusters as receive 1045 * buffers, and we currently are designed to receive an entire frame 1046 * into a single buffer. 1047 * 1048 * We start with a MCLBYTES-sized cluster, but we have to offset into 1049 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1050 * and then that value has to be rounded up to the hardware's DMA 1051 * alignment requirements, so all in all our buffer is that much smaller 1052 * than MCLBYTES. 1053 * 1054 * The resulting value is used as the frame truncation length and the 1055 * max buffer receive buffer size for now. It'll become more complex 1056 * when we support jumbo frames and receiving fragments of them into 1057 * separate buffers. 1058 */ 1059 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1060 maxfl = min(maxbuf, 0x7ff); 1061 1062 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1063 return; 1064 1065 /* Mask all interrupts and clear all current interrupt status bits. */ 1066 WR4(sc, FEC_IEM_REG, 0x00000000); 1067 WR4(sc, FEC_IER_REG, 0xffffffff); 1068 1069 /* 1070 * Go set up palr/puar, galr/gaur, ialr/iaur. 1071 */ 1072 ffec_setup_rxfilter(sc); 1073 1074 /* 1075 * TFWR - Transmit FIFO watermark register. 1076 * 1077 * Set the transmit fifo watermark register to "store and forward" mode 1078 * and also set a threshold of 128 bytes in the fifo before transmission 1079 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1080 * supports STRFWD and when that bit is set, the watermark level in the 1081 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1082 * to that bit is innocuous, and the TWFR bits get used instead. 1083 */ 1084 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1085 1086 /* RCR - Receive control register. 1087 * 1088 * Set max frame length + clean out anything left from u-boot. 1089 */ 1090 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1091 1092 /* 1093 * TCR - Transmit control register. 1094 * 1095 * Clean out anything left from u-boot. Any necessary values are set in 1096 * ffec_miibus_statchg() based on the media type. 1097 */ 1098 WR4(sc, FEC_TCR_REG, 0); 1099 1100 /* 1101 * OPD - Opcode/pause duration. 1102 * 1103 * XXX These magic numbers come from u-boot. 1104 */ 1105 WR4(sc, FEC_OPD_REG, 0x00010020); 1106 1107 /* 1108 * FRSR - Fifo receive start register. 1109 * 1110 * This register does not exist on imx6, it is present on earlier 1111 * hardware. The u-boot code sets this to a non-default value that's 32 1112 * bytes larger than the default, with no clue as to why. The default 1113 * value should work fine, so there's no code to init it here. 1114 */ 1115 1116 /* 1117 * MRBR - Max RX buffer size. 1118 * 1119 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1120 * but the datasheet says no such thing for imx6. On the imx6, setting 1121 * this to 2K without setting EN1588 resulted in a crazy runaway 1122 * receive loop in the hardware, where every rx descriptor in the ring 1123 * had its EMPTY flag cleared, no completion or error flags set, and a 1124 * length of zero. I think maybe you can only exceed it when EN1588 is 1125 * set, like maybe that's what enables jumbo frames, because in general 1126 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1127 * compatible" flag. 1128 */ 1129 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1130 1131 /* 1132 * FTRL - Frame truncation length. 1133 * 1134 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1135 */ 1136 WR4(sc, FEC_FTRL_REG, maxfl); 1137 1138 /* 1139 * RDSR / TDSR descriptor ring pointers. 1140 * 1141 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1142 * internal current descriptor index values for both rings, so we zero 1143 * our index values as well. 1144 */ 1145 sc->rx_idx = 0; 1146 sc->tx_idx_head = sc->tx_idx_tail = 0; 1147 sc->txcount = 0; 1148 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1149 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1150 1151 /* 1152 * EIM - interrupt mask register. 1153 * 1154 * We always enable the same set of interrupts while running; unlike 1155 * some drivers there's no need to change the mask on the fly depending 1156 * on what operations are in progress. 1157 */ 1158 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1159 1160 /* 1161 * MIBC - MIB control (hardware stats). 1162 */ 1163 regval = RD4(sc, FEC_MIBC_REG); 1164 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1165 ffec_clear_stats(sc); 1166 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1167 1168 /* 1169 * ECR - Ethernet control register. 1170 * 1171 * This must happen after all the other config registers are set. If 1172 * we're running on little-endian hardware, also set the flag for byte- 1173 * swapping descriptor ring entries. This flag doesn't exist on older 1174 * hardware, but it can be safely set -- the bit position it occupies 1175 * was unused. 1176 */ 1177 regval = RD4(sc, FEC_ECR_REG); 1178#if _BYTE_ORDER == _LITTLE_ENDIAN 1179 regval |= FEC_ECR_DBSWP; 1180#endif 1181 regval |= FEC_ECR_ETHEREN; 1182 WR4(sc, FEC_ECR_REG, regval); 1183 1184 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1185 1186 /* 1187 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1188 * set up the remaining config registers based on the current media. 1189 */ 1190 mii_mediachg(sc->mii_softc); 1191 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1192 1193 /* 1194 * Tell the hardware that receive buffers are available. They were made 1195 * available in ffec_attach() or ffec_stop(). 1196 */ 1197 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1198} 1199 1200static void 1201ffec_init(void *if_softc) 1202{ 1203 struct ffec_softc *sc = if_softc; 1204 1205 FFEC_LOCK(sc); 1206 ffec_init_locked(sc); 1207 FFEC_UNLOCK(sc); 1208} 1209 1210static void 1211ffec_intr(void *arg) 1212{ 1213 struct ffec_softc *sc; 1214 uint32_t ier; 1215 1216 sc = arg; 1217 1218 FFEC_LOCK(sc); 1219 1220 ier = RD4(sc, FEC_IER_REG); 1221 1222 if (ier & FEC_IER_TXF) { 1223 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1224 ffec_txfinish_locked(sc); 1225 } 1226 1227 if (ier & FEC_IER_RXF) { 1228 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1229 ffec_rxfinish_locked(sc); 1230 } 1231 1232 /* 1233 * We actually don't care about most errors, because the hardware copes 1234 * with them just fine, discarding the incoming bad frame, or forcing a 1235 * bad CRC onto an outgoing bad frame, and counting the errors in the 1236 * stats registers. The one that really matters is EBERR (DMA bus 1237 * error) because the hardware automatically clears ECR[ETHEREN] and we 1238 * have to restart it here. It should never happen. 1239 */ 1240 if (ier & FEC_IER_EBERR) { 1241 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1242 device_printf(sc->dev, 1243 "Ethernet DMA error, restarting controller.\n"); 1244 ffec_stop_locked(sc); 1245 ffec_init_locked(sc); 1246 } 1247 1248 FFEC_UNLOCK(sc); 1249 1250} 1251 1252static int 1253ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1254{ 1255 struct ffec_softc *sc; 1256 struct mii_data *mii; 1257 struct ifreq *ifr; 1258 int mask, error; 1259 1260 sc = ifp->if_softc; 1261 ifr = (struct ifreq *)data; 1262 1263 error = 0; 1264 switch (cmd) { 1265 case SIOCSIFFLAGS: 1266 FFEC_LOCK(sc); 1267 if (ifp->if_flags & IFF_UP) { 1268 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1269 if ((ifp->if_flags ^ sc->if_flags) & 1270 (IFF_PROMISC | IFF_ALLMULTI)) 1271 ffec_setup_rxfilter(sc); 1272 } else { 1273 if (!sc->is_detaching) 1274 ffec_init_locked(sc); 1275 } 1276 } else { 1277 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1278 ffec_stop_locked(sc); 1279 } 1280 sc->if_flags = ifp->if_flags; 1281 FFEC_UNLOCK(sc); 1282 break; 1283 1284 case SIOCADDMULTI: 1285 case SIOCDELMULTI: 1286 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1287 FFEC_LOCK(sc); 1288 ffec_setup_rxfilter(sc); 1289 FFEC_UNLOCK(sc); 1290 } 1291 break; 1292 1293 case SIOCSIFMEDIA: 1294 case SIOCGIFMEDIA: 1295 mii = sc->mii_softc; 1296 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1297 break; 1298 1299 case SIOCSIFCAP: 1300 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1301 if (mask & IFCAP_VLAN_MTU) { 1302 /* No work to do except acknowledge the change took. */ 1303 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1304 } 1305 break; 1306 1307 default: 1308 error = ether_ioctl(ifp, cmd, data); 1309 break; 1310 } 1311 1312 return (error); 1313} 1314 1315static int 1316ffec_detach(device_t dev) 1317{ 1318 struct ffec_softc *sc; 1319 bus_dmamap_t map; 1320 int idx; 1321 1322 /* 1323 * NB: This function can be called internally to unwind a failure to 1324 * attach. Make sure a resource got allocated/created before destroying. 1325 */ 1326 1327 sc = device_get_softc(dev); 1328 1329 if (sc->is_attached) { 1330 FFEC_LOCK(sc); 1331 sc->is_detaching = true; 1332 ffec_stop_locked(sc); 1333 FFEC_UNLOCK(sc); 1334 callout_drain(&sc->ffec_callout); 1335 ether_ifdetach(sc->ifp); 1336 } 1337 1338 /* XXX no miibus detach? */ 1339 1340 /* Clean up RX DMA resources and free mbufs. */ 1341 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1342 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1343 bus_dmamap_unload(sc->rxbuf_tag, map); 1344 bus_dmamap_destroy(sc->rxbuf_tag, map); 1345 m_freem(sc->rxbuf_map[idx].mbuf); 1346 } 1347 } 1348 if (sc->rxbuf_tag != NULL) 1349 bus_dma_tag_destroy(sc->rxbuf_tag); 1350 if (sc->rxdesc_map != NULL) { 1351 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1352 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1353 } 1354 if (sc->rxdesc_tag != NULL) 1355 bus_dma_tag_destroy(sc->rxdesc_tag); 1356 1357 /* Clean up TX DMA resources. */ 1358 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1359 if ((map = sc->txbuf_map[idx].map) != NULL) { 1360 /* TX maps are already unloaded. */ 1361 bus_dmamap_destroy(sc->txbuf_tag, map); 1362 } 1363 } 1364 if (sc->txbuf_tag != NULL) 1365 bus_dma_tag_destroy(sc->txbuf_tag); 1366 if (sc->txdesc_map != NULL) { 1367 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1368 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1369 } 1370 if (sc->txdesc_tag != NULL) 1371 bus_dma_tag_destroy(sc->txdesc_tag); 1372 1373 /* Release bus resources. */ 1374 if (sc->intr_cookie) 1375 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1376 1377 if (sc->irq_res != NULL) 1378 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1379 1380 if (sc->mem_res != NULL) 1381 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1382 1383 FFEC_LOCK_DESTROY(sc); 1384 return (0); 1385} 1386 1387static int 1388ffec_attach(device_t dev) 1389{ 1390 struct ffec_softc *sc; 1391 struct ifnet *ifp = NULL; 1392 struct mbuf *m; 1393 phandle_t ofw_node; 1394 int error, rid; 1395 uint8_t eaddr[ETHER_ADDR_LEN]; 1396 char phy_conn_name[32]; 1397 uint32_t idx, mscr; 1398 1399 sc = device_get_softc(dev); 1400 sc->dev = dev; 1401 1402 FFEC_LOCK_INIT(sc); 1403 1404 /* 1405 * There are differences in the implementation and features of the FEC 1406 * hardware on different SoCs, so figure out what type we are. 1407 */ 1408 if (ofw_bus_is_compatible(dev, "fsl,imx51-fec")) 1409 sc->fectype = FECTYPE_IMX51; 1410 else if (ofw_bus_is_compatible(dev, "fsl,imx53-fec")) 1411 sc->fectype = FECTYPE_IMX53; 1412 else if (ofw_bus_is_compatible(dev, "fsl,imx6q-fec")) 1413 sc->fectype = FECTYPE_IMX6; 1414 else 1415 sc->fectype = FECTYPE_GENERIC; 1416 1417 /* 1418 * We have to be told what kind of electrical connection exists between 1419 * the MAC and PHY or we can't operate correctly. 1420 */ 1421 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1422 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1423 error = ENXIO; 1424 goto out; 1425 } 1426 if (OF_searchprop(ofw_node, "phy-mode", 1427 phy_conn_name, sizeof(phy_conn_name)) != -1) { 1428 if (strcasecmp(phy_conn_name, "mii") == 0) 1429 sc->phy_conn_type = PHY_CONN_MII; 1430 else if (strcasecmp(phy_conn_name, "rmii") == 0) 1431 sc->phy_conn_type = PHY_CONN_RMII; 1432 else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1433 sc->phy_conn_type = PHY_CONN_RGMII; 1434 } 1435 if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1436 device_printf(sc->dev, "No valid 'phy-mode' " 1437 "property found in FDT data for device.\n"); 1438 error = ENOATTR; 1439 goto out; 1440 } 1441 1442 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1443 1444 /* Allocate bus resources for accessing the hardware. */ 1445 rid = 0; 1446 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1447 RF_ACTIVE); 1448 if (sc->mem_res == NULL) { 1449 device_printf(dev, "could not allocate memory resources.\n"); 1450 error = ENOMEM; 1451 goto out; 1452 } 1453 rid = 0; 1454 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1455 RF_ACTIVE); 1456 if (sc->irq_res == NULL) { 1457 device_printf(dev, "could not allocate interrupt resources.\n"); 1458 error = ENOMEM; 1459 goto out; 1460 } 1461 1462 /* 1463 * Set up TX descriptor ring, descriptors, and dma maps. 1464 */ 1465 error = bus_dma_tag_create( 1466 bus_get_dma_tag(dev), /* Parent tag. */ 1467 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1468 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1469 BUS_SPACE_MAXADDR, /* highaddr */ 1470 NULL, NULL, /* filter, filterarg */ 1471 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1472 TX_DESC_SIZE, /* maxsegsize */ 1473 0, /* flags */ 1474 NULL, NULL, /* lockfunc, lockarg */ 1475 &sc->txdesc_tag); 1476 if (error != 0) { 1477 device_printf(sc->dev, 1478 "could not create TX ring DMA tag.\n"); 1479 goto out; 1480 } 1481 1482 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1483 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1484 if (error != 0) { 1485 device_printf(sc->dev, 1486 "could not allocate TX descriptor ring.\n"); 1487 goto out; 1488 } 1489 1490 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1491 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1492 if (error != 0) { 1493 device_printf(sc->dev, 1494 "could not load TX descriptor ring map.\n"); 1495 goto out; 1496 } 1497 1498 error = bus_dma_tag_create( 1499 bus_get_dma_tag(dev), /* Parent tag. */ 1500 FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1501 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1502 BUS_SPACE_MAXADDR, /* highaddr */ 1503 NULL, NULL, /* filter, filterarg */ 1504 MCLBYTES, 1, /* maxsize, nsegments */ 1505 MCLBYTES, /* maxsegsize */ 1506 0, /* flags */ 1507 NULL, NULL, /* lockfunc, lockarg */ 1508 &sc->txbuf_tag); 1509 if (error != 0) { 1510 device_printf(sc->dev, 1511 "could not create TX ring DMA tag.\n"); 1512 goto out; 1513 } 1514 1515 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1516 error = bus_dmamap_create(sc->txbuf_tag, 0, 1517 &sc->txbuf_map[idx].map); 1518 if (error != 0) { 1519 device_printf(sc->dev, 1520 "could not create TX buffer DMA map.\n"); 1521 goto out; 1522 } 1523 ffec_setup_txdesc(sc, idx, 0, 0); 1524 } 1525 1526 /* 1527 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1528 */ 1529 error = bus_dma_tag_create( 1530 bus_get_dma_tag(dev), /* Parent tag. */ 1531 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1532 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1533 BUS_SPACE_MAXADDR, /* highaddr */ 1534 NULL, NULL, /* filter, filterarg */ 1535 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1536 RX_DESC_SIZE, /* maxsegsize */ 1537 0, /* flags */ 1538 NULL, NULL, /* lockfunc, lockarg */ 1539 &sc->rxdesc_tag); 1540 if (error != 0) { 1541 device_printf(sc->dev, 1542 "could not create RX ring DMA tag.\n"); 1543 goto out; 1544 } 1545 1546 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1547 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1548 if (error != 0) { 1549 device_printf(sc->dev, 1550 "could not allocate RX descriptor ring.\n"); 1551 goto out; 1552 } 1553 1554 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1555 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1556 if (error != 0) { 1557 device_printf(sc->dev, 1558 "could not load RX descriptor ring map.\n"); 1559 goto out; 1560 } 1561 1562 error = bus_dma_tag_create( 1563 bus_get_dma_tag(dev), /* Parent tag. */ 1564 1, 0, /* alignment, boundary */ 1565 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1566 BUS_SPACE_MAXADDR, /* highaddr */ 1567 NULL, NULL, /* filter, filterarg */ 1568 MCLBYTES, 1, /* maxsize, nsegments */ 1569 MCLBYTES, /* maxsegsize */ 1570 0, /* flags */ 1571 NULL, NULL, /* lockfunc, lockarg */ 1572 &sc->rxbuf_tag); 1573 if (error != 0) { 1574 device_printf(sc->dev, 1575 "could not create RX buf DMA tag.\n"); 1576 goto out; 1577 } 1578 1579 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1580 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1581 &sc->rxbuf_map[idx].map); 1582 if (error != 0) { 1583 device_printf(sc->dev, 1584 "could not create RX buffer DMA map.\n"); 1585 goto out; 1586 } 1587 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1588 device_printf(dev, "Could not alloc mbuf\n"); 1589 error = ENOMEM; 1590 goto out; 1591 } 1592 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1593 device_printf(sc->dev, 1594 "could not create new RX buffer.\n"); 1595 goto out; 1596 } 1597 } 1598 1599 /* Try to get the MAC address from the hardware before resetting it. */ 1600 ffec_get_hwaddr(sc, eaddr); 1601 1602 /* Reset the hardware. Disables all interrupts. */ 1603 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1604 1605 /* Setup interrupt handler. */ 1606 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1607 NULL, ffec_intr, sc, &sc->intr_cookie); 1608 if (error != 0) { 1609 device_printf(dev, "could not setup interrupt handler.\n"); 1610 goto out; 1611 } 1612 1613 /* 1614 * Set up the PHY control register. 1615 * 1616 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1617 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1618 * 1619 * XXX - Revisit this... 1620 * 1621 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1622 * code uses 10. Both values seem to work, but I suspect many modern 1623 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1624 * 1625 * Different imx manuals use confusingly different terminology (things 1626 * like "system clock" and "internal module clock") with examples that 1627 * use frequencies that have nothing to do with ethernet, giving the 1628 * vague impression that maybe the clock in question is the periphclock 1629 * or something. In fact, on an imx53 development board (FEC), 1630 * measuring the mdio clock at the pin on the PHY and playing with 1631 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1632 * aka periphclock) and 13 was the right divisor. 1633 * 1634 * All in all, it seems likely that 13 is a safe divisor for now, 1635 * because if we really do need to base it on the peripheral clock 1636 * speed, then we need a platform-independant get-clock-freq API. 1637 */ 1638 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1639 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1640 mscr |= FEC_MSCR_DIS_PRE; 1641 if (bootverbose) 1642 device_printf(dev, "PHY preamble disabled\n"); 1643 } 1644 WR4(sc, FEC_MSCR_REG, mscr); 1645 1646 /* Set up the ethernet interface. */ 1647 sc->ifp = ifp = if_alloc(IFT_ETHER); 1648 1649 ifp->if_softc = sc; 1650 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1651 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1652 ifp->if_capabilities = IFCAP_VLAN_MTU; 1653 ifp->if_capenable = ifp->if_capabilities; 1654 ifp->if_start = ffec_txstart; 1655 ifp->if_ioctl = ffec_ioctl; 1656 ifp->if_init = ffec_init; 1657 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1658 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1659 IFQ_SET_READY(&ifp->if_snd); 1660 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1661 1662#if 0 /* XXX The hardware keeps stats we could use for these. */ 1663 ifp->if_linkmib = &sc->mibdata; 1664 ifp->if_linkmiblen = sizeof(sc->mibdata); 1665#endif 1666 1667 /* Set up the miigasket hardware (if any). */ 1668 ffec_miigasket_setup(sc); 1669 1670 /* Attach the mii driver. */ 1671 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1672 ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1673 if (error != 0) { 1674 device_printf(dev, "PHY attach failed\n"); 1675 goto out; 1676 } 1677 sc->mii_softc = device_get_softc(sc->miibus); 1678 1679 /* All ready to run, attach the ethernet interface. */ 1680 ether_ifattach(ifp, eaddr); 1681 sc->is_attached = true; 1682 1683 error = 0; 1684out: 1685 1686 if (error != 0) 1687 ffec_detach(dev); 1688 1689 return (error); 1690} 1691 1692static int 1693ffec_probe(device_t dev) 1694{ 1695 1696 if (ofw_bus_is_compatible(dev, "fsl,imx51-fec") || 1697 ofw_bus_is_compatible(dev, "fsl,imx53-fec")) { 1698 device_set_desc(dev, "Freescale Fast Ethernet Controller"); 1699 } else if (ofw_bus_is_compatible(dev, "fsl,imx6q-fec")) { 1700 device_set_desc(dev, "Freescale Gigabit Ethernet Controller"); 1701 } else { 1702 return (ENXIO); 1703 } 1704 return (BUS_PROBE_DEFAULT); 1705} 1706 1707 1708static device_method_t ffec_methods[] = { 1709 /* Device interface. */ 1710 DEVMETHOD(device_probe, ffec_probe), 1711 DEVMETHOD(device_attach, ffec_attach), 1712 DEVMETHOD(device_detach, ffec_detach), 1713 1714/* 1715 DEVMETHOD(device_shutdown, ffec_shutdown), 1716 DEVMETHOD(device_suspend, ffec_suspend), 1717 DEVMETHOD(device_resume, ffec_resume), 1718*/ 1719 1720 /* MII interface. */ 1721 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1722 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1723 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1724 1725 DEVMETHOD_END 1726}; 1727 1728static driver_t ffec_driver = { 1729 "ffec", 1730 ffec_methods, 1731 sizeof(struct ffec_softc) 1732}; 1733 1734static devclass_t ffec_devclass; 1735 1736DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1737DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1738 1739MODULE_DEPEND(ffec, ether, 1, 1, 1); 1740MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1741