if_etvar.h revision 179895
1179895Sdelphij/*- 2179895Sdelphij * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3179895Sdelphij * 4179895Sdelphij * This code is derived from software contributed to The DragonFly Project 5179895Sdelphij * by Sepherosa Ziehau <sepherosa@gmail.com> 6179895Sdelphij * 7179895Sdelphij * Redistribution and use in source and binary forms, with or without 8179895Sdelphij * modification, are permitted provided that the following conditions 9179895Sdelphij * are met: 10179895Sdelphij * 11179895Sdelphij * 1. Redistributions of source code must retain the above copyright 12179895Sdelphij * notice, this list of conditions and the following disclaimer. 13179895Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 14179895Sdelphij * notice, this list of conditions and the following disclaimer in 15179895Sdelphij * the documentation and/or other materials provided with the 16179895Sdelphij * distribution. 17179895Sdelphij * 3. Neither the name of The DragonFly Project nor the names of its 18179895Sdelphij * contributors may be used to endorse or promote products derived 19179895Sdelphij * from this software without specific, prior written permission. 20179895Sdelphij * 21179895Sdelphij * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22179895Sdelphij * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23179895Sdelphij * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24179895Sdelphij * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25179895Sdelphij * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26179895Sdelphij * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27179895Sdelphij * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28179895Sdelphij * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29179895Sdelphij * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30179895Sdelphij * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31179895Sdelphij * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32179895Sdelphij * SUCH DAMAGE. 33179895Sdelphij * 34179895Sdelphij * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $ 35179895Sdelphij * $FreeBSD: head/sys/dev/et/if_etvar.h 179895 2008-06-20 19:28:33Z delphij $ 36179895Sdelphij */ 37179895Sdelphij 38179895Sdelphij#ifndef _IF_ETVAR_H 39179895Sdelphij#define _IF_ETVAR_H 40179895Sdelphij 41179895Sdelphij/* DragonFly compatibility */ 42179895Sdelphij#define EVL_ENCAPLEN ETHER_VLAN_ENCAP_LEN 43179895Sdelphij 44179895Sdelphij/* 45179895Sdelphij * Allocate the right type of mbuf for the desired total length. 46179895Sdelphij */ 47179895Sdelphijstatic __inline struct mbuf * 48179895Sdelphijm_getl(int len, int how, int type, int flags, int *psize) 49179895Sdelphij{ 50179895Sdelphij struct mbuf *m; 51179895Sdelphij int size; 52179895Sdelphij 53179895Sdelphij if (len >= MINCLSIZE) { 54179895Sdelphij m = m_getcl(how, type, flags); 55179895Sdelphij size = MCLBYTES; 56179895Sdelphij } else if (flags & M_PKTHDR) { 57179895Sdelphij m = m_gethdr(how, type); 58179895Sdelphij size = MHLEN; 59179895Sdelphij } else { 60179895Sdelphij m = m_get(how, type); 61179895Sdelphij size = MLEN; 62179895Sdelphij } 63179895Sdelphij if (psize != NULL) 64179895Sdelphij *psize = size; 65179895Sdelphij return (m); 66179895Sdelphij} 67179895Sdelphij 68179895Sdelphij 69179895Sdelphij#define ET_ALIGN 0x1000 70179895Sdelphij#define ET_NSEG_MAX 32 /* XXX no limit actually */ 71179895Sdelphij#define ET_NSEG_SPARE 8 72179895Sdelphij 73179895Sdelphij#define ET_TX_NDESC 512 74179895Sdelphij#define ET_RX_NDESC 512 75179895Sdelphij#define ET_RX_NRING 2 76179895Sdelphij#define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 77179895Sdelphij 78179895Sdelphij#define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 79179895Sdelphij#define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 80179895Sdelphij#define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 81179895Sdelphij 82179895Sdelphij#define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 83179895Sdelphij ET_MEM_TXSIZE_EX) 84179895Sdelphij#define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 85179895Sdelphij EVL_ENCAPLEN - ETHER_CRC_LEN) 86179895Sdelphij 87179895Sdelphij#define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \ 88179895Sdelphij ETHER_CRC_LEN) 89179895Sdelphij 90179895Sdelphij#define ET_JSLOTS (ET_RX_NDESC + 128) 91179895Sdelphij#define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN) 92179895Sdelphij#define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 93179895Sdelphij 94179895Sdelphij#define CSR_WRITE_4(sc, reg, val) \ 95179895Sdelphij bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 96179895Sdelphij#define CSR_READ_4(sc, reg) \ 97179895Sdelphij bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 98179895Sdelphij 99179895Sdelphij#define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 100179895Sdelphij#define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 101179895Sdelphij 102179895Sdelphijstruct et_txdesc { 103179895Sdelphij uint32_t td_addr_hi; 104179895Sdelphij uint32_t td_addr_lo; 105179895Sdelphij uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 106179895Sdelphij uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 107179895Sdelphij} __packed; 108179895Sdelphij 109179895Sdelphij#define ET_TDCTRL1_LEN __BITS(15, 0) 110179895Sdelphij 111179895Sdelphij#define ET_TDCTRL2_LAST_FRAG __BIT(0) 112179895Sdelphij#define ET_TDCTRL2_FIRST_FRAG __BIT(1) 113179895Sdelphij#define ET_TDCTRL2_INTR __BIT(2) 114179895Sdelphij 115179895Sdelphijstruct et_rxdesc { 116179895Sdelphij uint32_t rd_addr_lo; 117179895Sdelphij uint32_t rd_addr_hi; 118179895Sdelphij uint32_t rd_ctrl; /* ET_RDCTRL_ */ 119179895Sdelphij} __packed; 120179895Sdelphij 121179895Sdelphij#define ET_RDCTRL_BUFIDX __BITS(9, 0) 122179895Sdelphij 123179895Sdelphijstruct et_rxstat { 124179895Sdelphij uint32_t rxst_info1; 125179895Sdelphij uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 126179895Sdelphij} __packed; 127179895Sdelphij 128179895Sdelphij#define ET_RXST_INFO2_LEN __BITS(15, 0) 129179895Sdelphij#define ET_RXST_INFO2_BUFIDX __BITS(25, 16) 130179895Sdelphij#define ET_RXST_INFO2_RINGIDX __BITS(27, 26) 131179895Sdelphij 132179895Sdelphijstruct et_rxstatus { 133179895Sdelphij uint32_t rxs_ring; 134179895Sdelphij uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 135179895Sdelphij} __packed; 136179895Sdelphij 137179895Sdelphij#define ET_RXS_STATRING_INDEX __BITS(27, 16) 138179895Sdelphij#define ET_RXS_STATRING_WRAP __BIT(28) 139179895Sdelphij 140179895Sdelphijstruct et_dmamap_ctx { 141179895Sdelphij int nsegs; 142179895Sdelphij bus_dma_segment_t *segs; 143179895Sdelphij}; 144179895Sdelphij 145179895Sdelphijstruct et_txbuf { 146179895Sdelphij struct mbuf *tb_mbuf; 147179895Sdelphij bus_dmamap_t tb_dmap; 148179895Sdelphij}; 149179895Sdelphij 150179895Sdelphijstruct et_rxbuf { 151179895Sdelphij struct mbuf *rb_mbuf; 152179895Sdelphij bus_dmamap_t rb_dmap; 153179895Sdelphij bus_addr_t rb_paddr; 154179895Sdelphij}; 155179895Sdelphij 156179895Sdelphijstruct et_txstatus_data { 157179895Sdelphij uint32_t *txsd_status; 158179895Sdelphij bus_addr_t txsd_paddr; 159179895Sdelphij bus_dma_tag_t txsd_dtag; 160179895Sdelphij bus_dmamap_t txsd_dmap; 161179895Sdelphij}; 162179895Sdelphij 163179895Sdelphijstruct et_rxstatus_data { 164179895Sdelphij struct et_rxstatus *rxsd_status; 165179895Sdelphij bus_addr_t rxsd_paddr; 166179895Sdelphij bus_dma_tag_t rxsd_dtag; 167179895Sdelphij bus_dmamap_t rxsd_dmap; 168179895Sdelphij}; 169179895Sdelphij 170179895Sdelphijstruct et_rxstat_ring { 171179895Sdelphij struct et_rxstat *rsr_stat; 172179895Sdelphij bus_addr_t rsr_paddr; 173179895Sdelphij bus_dma_tag_t rsr_dtag; 174179895Sdelphij bus_dmamap_t rsr_dmap; 175179895Sdelphij 176179895Sdelphij int rsr_index; 177179895Sdelphij int rsr_wrap; 178179895Sdelphij}; 179179895Sdelphij 180179895Sdelphijstruct et_txdesc_ring { 181179895Sdelphij struct et_txdesc *tr_desc; 182179895Sdelphij bus_addr_t tr_paddr; 183179895Sdelphij bus_dma_tag_t tr_dtag; 184179895Sdelphij bus_dmamap_t tr_dmap; 185179895Sdelphij 186179895Sdelphij int tr_ready_index; 187179895Sdelphij int tr_ready_wrap; 188179895Sdelphij}; 189179895Sdelphij 190179895Sdelphijstruct et_rxdesc_ring { 191179895Sdelphij struct et_rxdesc *rr_desc; 192179895Sdelphij bus_addr_t rr_paddr; 193179895Sdelphij bus_dma_tag_t rr_dtag; 194179895Sdelphij bus_dmamap_t rr_dmap; 195179895Sdelphij 196179895Sdelphij uint32_t rr_posreg; 197179895Sdelphij int rr_index; 198179895Sdelphij int rr_wrap; 199179895Sdelphij}; 200179895Sdelphij 201179895Sdelphijstruct et_txbuf_data { 202179895Sdelphij struct et_txbuf tbd_buf[ET_TX_NDESC]; 203179895Sdelphij 204179895Sdelphij int tbd_start_index; 205179895Sdelphij int tbd_start_wrap; 206179895Sdelphij int tbd_used; 207179895Sdelphij}; 208179895Sdelphij 209179895Sdelphijstruct et_softc; 210179895Sdelphijstruct et_rxbuf_data; 211179895Sdelphijtypedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 212179895Sdelphij 213179895Sdelphijstruct et_rxbuf_data { 214179895Sdelphij struct et_rxbuf rbd_buf[ET_RX_NDESC]; 215179895Sdelphij 216179895Sdelphij struct et_softc *rbd_softc; 217179895Sdelphij struct et_rxdesc_ring *rbd_ring; 218179895Sdelphij 219179895Sdelphij int rbd_bufsize; 220179895Sdelphij et_newbuf_t rbd_newbuf; 221179895Sdelphij}; 222179895Sdelphij 223179895Sdelphijstruct et_softc { 224179895Sdelphij struct ifnet *ifp; 225179895Sdelphij device_t dev; 226179895Sdelphij struct mtx sc_mtx; 227179895Sdelphij device_t sc_miibus; 228179895Sdelphij bus_space_handle_t sc_mem_bh; 229179895Sdelphij bus_space_tag_t sc_mem_bt; 230179895Sdelphij void *sc_irq_handle; 231179895Sdelphij struct resource *sc_irq_res; 232179895Sdelphij struct resource *sc_mem_res; 233179895Sdelphij 234179895Sdelphij struct arpcom arpcom; 235179895Sdelphij int sc_if_flags; 236179895Sdelphij uint32_t sc_flags; /* ET_FLAG_ */ 237179895Sdelphij 238179895Sdelphij int sc_mem_rid; 239179895Sdelphij 240179895Sdelphij int sc_irq_rid; 241179895Sdelphij 242179895Sdelphij struct callout sc_tick; 243179895Sdelphij 244179895Sdelphij int watchdog_timer; 245179895Sdelphij 246179895Sdelphij bus_dma_tag_t sc_dtag; 247179895Sdelphij 248179895Sdelphij struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 249179895Sdelphij struct et_rxstat_ring sc_rxstat_ring; 250179895Sdelphij struct et_rxstatus_data sc_rx_status; 251179895Sdelphij 252179895Sdelphij struct et_txdesc_ring sc_tx_ring; 253179895Sdelphij struct et_txstatus_data sc_tx_status; 254179895Sdelphij 255179895Sdelphij bus_dma_tag_t sc_mbuf_dtag; 256179895Sdelphij bus_dmamap_t sc_mbuf_tmp_dmap; 257179895Sdelphij struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 258179895Sdelphij struct et_txbuf_data sc_tx_data; 259179895Sdelphij 260179895Sdelphij uint32_t sc_tx; 261179895Sdelphij uint32_t sc_tx_intr; 262179895Sdelphij 263179895Sdelphij /* 264179895Sdelphij * Sysctl variables 265179895Sdelphij */ 266179895Sdelphij int sc_rx_intr_npkts; 267179895Sdelphij int sc_rx_intr_delay; 268179895Sdelphij int sc_tx_intr_nsegs; 269179895Sdelphij uint32_t sc_timer; 270179895Sdelphij}; 271179895Sdelphij 272179895Sdelphij#define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 273179895Sdelphij#define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 274179895Sdelphij#define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 275179895Sdelphij 276179895Sdelphij#define ET_FLAG_TXRX_ENABLED 0x1 277179895Sdelphij#define ET_FLAG_JUMBO 0x2 278179895Sdelphij 279179895Sdelphij#endif /* !_IF_ETVAR_H */ 280