if_etvar.h revision 179895 
1/*-
2 * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in
15 *    the documentation and/or other materials provided with the
16 *    distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 *    contributors may be used to endorse or promote products derived
19 *    from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $
35 * $FreeBSD: head/sys/dev/et/if_etvar.h 179895 2008-06-20 19:28:33Z delphij $
36 */
37
38#ifndef _IF_ETVAR_H
39#define _IF_ETVAR_H
40
41/* DragonFly compatibility */
42#define EVL_ENCAPLEN		ETHER_VLAN_ENCAP_LEN
43
44/*
45 * Allocate the right type of mbuf for the desired total length.
46 */
47static __inline struct mbuf *
48m_getl(int len, int how, int type, int flags, int *psize)
49{
50	struct mbuf *m;
51	int size;
52
53	if (len >= MINCLSIZE) {
54		m = m_getcl(how, type, flags);
55		size = MCLBYTES;
56	} else if (flags & M_PKTHDR) {
57		m = m_gethdr(how, type);
58		size = MHLEN;
59	} else {
60		m = m_get(how, type);
61		size = MLEN;
62	}
63	if (psize != NULL)
64		*psize = size;
65	return (m);
66}
67
68
69#define ET_ALIGN		0x1000
70#define ET_NSEG_MAX		32	/* XXX no limit actually */
71#define ET_NSEG_SPARE		8
72
73#define ET_TX_NDESC		512
74#define ET_RX_NDESC		512
75#define ET_RX_NRING		2
76#define ET_RX_NSTAT		(ET_RX_NRING * ET_RX_NDESC)
77
78#define ET_TX_RING_SIZE		(ET_TX_NDESC * sizeof(struct et_txdesc))
79#define ET_RX_RING_SIZE		(ET_RX_NDESC * sizeof(struct et_rxdesc))
80#define ET_RXSTAT_RING_SIZE	(ET_RX_NSTAT * sizeof(struct et_rxstat))
81
82#define ET_JUMBO_FRAMELEN	(ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -	\
83				 ET_MEM_TXSIZE_EX)
84#define ET_JUMBO_MTU		(ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -	\
85				 EVL_ENCAPLEN - ETHER_CRC_LEN)
86
87#define ET_FRAMELEN(mtu)	(ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) +	\
88				 ETHER_CRC_LEN)
89
90#define ET_JSLOTS		(ET_RX_NDESC + 128)
91#define ET_JLEN			(ET_JUMBO_FRAMELEN + ETHER_ALIGN)
92#define ET_JUMBO_MEM_SIZE	(ET_JSLOTS * ET_JLEN)
93
94#define CSR_WRITE_4(sc, reg, val)	\
95	bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
96#define CSR_READ_4(sc, reg)		\
97	bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
98
99#define ET_ADDR_HI(addr)	((uint64_t) (addr) >> 32)
100#define ET_ADDR_LO(addr)	((uint64_t) (addr) & 0xffffffff)
101
102struct et_txdesc {
103	uint32_t	td_addr_hi;
104	uint32_t	td_addr_lo;
105	uint32_t	td_ctrl1;	/* ET_TDCTRL1_ */
106	uint32_t	td_ctrl2;	/* ET_TDCTRL2_ */
107} __packed;
108
109#define ET_TDCTRL1_LEN		__BITS(15, 0)
110
111#define ET_TDCTRL2_LAST_FRAG	__BIT(0)
112#define ET_TDCTRL2_FIRST_FRAG	__BIT(1)
113#define ET_TDCTRL2_INTR		__BIT(2)
114
115struct et_rxdesc {
116	uint32_t	rd_addr_lo;
117	uint32_t	rd_addr_hi;
118	uint32_t	rd_ctrl;	/* ET_RDCTRL_ */
119} __packed;
120
121#define ET_RDCTRL_BUFIDX	__BITS(9, 0)
122
123struct et_rxstat {
124	uint32_t	rxst_info1;
125	uint32_t	rxst_info2;	/* ET_RXST_INFO2_ */
126} __packed;
127
128#define ET_RXST_INFO2_LEN	__BITS(15, 0)
129#define ET_RXST_INFO2_BUFIDX	__BITS(25, 16)
130#define ET_RXST_INFO2_RINGIDX	__BITS(27, 26)
131
132struct et_rxstatus {
133	uint32_t	rxs_ring;
134	uint32_t	rxs_stat_ring;	/* ET_RXS_STATRING_ */
135} __packed;
136
137#define ET_RXS_STATRING_INDEX	__BITS(27, 16)
138#define ET_RXS_STATRING_WRAP	__BIT(28)
139
140struct et_dmamap_ctx {
141	int		nsegs;
142	bus_dma_segment_t *segs;
143};
144
145struct et_txbuf {
146	struct mbuf		*tb_mbuf;
147	bus_dmamap_t		tb_dmap;
148};
149
150struct et_rxbuf {
151	struct mbuf		*rb_mbuf;
152	bus_dmamap_t		rb_dmap;
153	bus_addr_t		rb_paddr;
154};
155
156struct et_txstatus_data {
157	uint32_t		*txsd_status;
158	bus_addr_t		txsd_paddr;
159	bus_dma_tag_t		txsd_dtag;
160	bus_dmamap_t		txsd_dmap;
161};
162
163struct et_rxstatus_data {
164	struct et_rxstatus	*rxsd_status;
165	bus_addr_t		rxsd_paddr;
166	bus_dma_tag_t		rxsd_dtag;
167	bus_dmamap_t		rxsd_dmap;
168};
169
170struct et_rxstat_ring {
171	struct et_rxstat	*rsr_stat;
172	bus_addr_t		rsr_paddr;
173	bus_dma_tag_t		rsr_dtag;
174	bus_dmamap_t		rsr_dmap;
175
176	int			rsr_index;
177	int			rsr_wrap;
178};
179
180struct et_txdesc_ring {
181	struct et_txdesc	*tr_desc;
182	bus_addr_t		tr_paddr;
183	bus_dma_tag_t		tr_dtag;
184	bus_dmamap_t		tr_dmap;
185
186	int			tr_ready_index;
187	int			tr_ready_wrap;
188};
189
190struct et_rxdesc_ring {
191	struct et_rxdesc	*rr_desc;
192	bus_addr_t		rr_paddr;
193	bus_dma_tag_t		rr_dtag;
194	bus_dmamap_t		rr_dmap;
195
196	uint32_t		rr_posreg;
197	int			rr_index;
198	int			rr_wrap;
199};
200
201struct et_txbuf_data {
202	struct et_txbuf		tbd_buf[ET_TX_NDESC];
203
204	int			tbd_start_index;
205	int			tbd_start_wrap;
206	int			tbd_used;
207};
208
209struct et_softc;
210struct et_rxbuf_data;
211typedef int	(*et_newbuf_t)(struct et_rxbuf_data *, int, int);
212
213struct et_rxbuf_data {
214	struct et_rxbuf		rbd_buf[ET_RX_NDESC];
215
216	struct et_softc		*rbd_softc;
217	struct et_rxdesc_ring	*rbd_ring;
218
219	int			rbd_bufsize;
220	et_newbuf_t		rbd_newbuf;
221};
222
223struct et_softc {
224	struct ifnet		*ifp;
225	device_t		dev;
226	struct mtx		sc_mtx;
227	device_t		sc_miibus;
228	bus_space_handle_t	sc_mem_bh;
229	bus_space_tag_t		sc_mem_bt;
230	void			*sc_irq_handle;
231	struct resource		*sc_irq_res;
232	struct resource		*sc_mem_res;
233
234	struct arpcom		arpcom;
235	int			sc_if_flags;
236	uint32_t		sc_flags;	/* ET_FLAG_ */
237
238	int			sc_mem_rid;
239
240	int			sc_irq_rid;
241
242	struct callout		sc_tick;
243
244	int			watchdog_timer;
245
246	bus_dma_tag_t		sc_dtag;
247
248	struct et_rxdesc_ring	sc_rx_ring[ET_RX_NRING];
249	struct et_rxstat_ring	sc_rxstat_ring;
250	struct et_rxstatus_data	sc_rx_status;
251
252	struct et_txdesc_ring	sc_tx_ring;
253	struct et_txstatus_data	sc_tx_status;
254
255	bus_dma_tag_t		sc_mbuf_dtag;
256	bus_dmamap_t		sc_mbuf_tmp_dmap;
257	struct et_rxbuf_data	sc_rx_data[ET_RX_NRING];
258	struct et_txbuf_data	sc_tx_data;
259
260	uint32_t		sc_tx;
261	uint32_t		sc_tx_intr;
262
263	/*
264	 * Sysctl variables
265	 */
266	int			sc_rx_intr_npkts;
267	int			sc_rx_intr_delay;
268	int			sc_tx_intr_nsegs;
269	uint32_t		sc_timer;
270};
271
272#define ET_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
273#define ET_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
274#define ET_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
275
276#define ET_FLAG_TXRX_ENABLED	0x1
277#define ET_FLAG_JUMBO		0x2
278
279#endif	/* !_IF_ETVAR_H */
280