1/*- 2 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $ 35 * $FreeBSD$ 36 */ 37 38#ifndef _IF_ETVAR_H 39#define _IF_ETVAR_H 40 41#define ET_RING_ALIGN 4096 42#define ET_STATUS_ALIGN 8 43#define ET_NSEG_MAX 32 /* XXX no limit actually */ 44#define ET_NSEG_SPARE 4 45 46#define ET_TX_NDESC 512 47#define ET_RX_NDESC 512 48#define ET_RX_NRING 2 49#define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 50 51#define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 52#define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 53#define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 54 55#define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 56 ET_MEM_TXSIZE_EX) 57#define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 58 EVL_ENCAPLEN - ETHER_CRC_LEN) 59 60#define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + \ 61 (mtu) + ETHER_CRC_LEN) 62 63#define ET_JSLOTS (ET_RX_NDESC + 128) 64#define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN) 65#define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 66 67#define CSR_WRITE_4(sc, reg, val) \ 68 bus_write_4((sc)->sc_mem_res, (reg), (val)) 69#define CSR_READ_4(sc, reg) \ 70 bus_read_4((sc)->sc_mem_res, (reg)) 71 72#define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 73#define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 74 75struct et_txdesc { 76 uint32_t td_addr_hi; 77 uint32_t td_addr_lo; 78 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 79 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 80}; 81 82#define ET_TDCTRL1_LEN_MASK 0x0000FFFF 83 84#define ET_TDCTRL2_LAST_FRAG 0x00000001 85#define ET_TDCTRL2_FIRST_FRAG 0x00000002 86#define ET_TDCTRL2_INTR 0x00000004 87#define ET_TDCTRL2_CTRL_WORD 0x00000008 88#define ET_TDCTRL2_HDX_BACKP 0x00000010 89#define ET_TDCTRL2_XMIT_PAUSE 0x00000020 90#define ET_TDCTRL2_FRAME_ERR 0x00000040 91#define ET_TDCTRL2_NO_CRC 0x00000080 92#define ET_TDCTRL2_MAC_OVRRD 0x00000100 93#define ET_TDCTRL2_PAD_PACKET 0x00000200 94#define ET_TDCTRL2_JUMBO_PACKET 0x00000400 95#define ET_TDCTRL2_INS_VLAN 0x00000800 96#define ET_TDCTRL2_CSUM_IP 0x00001000 97#define ET_TDCTRL2_CSUM_TCP 0x00002000 98#define ET_TDCTRL2_CSUM_UDP 0x00004000 99 100struct et_rxdesc { 101 uint32_t rd_addr_lo; 102 uint32_t rd_addr_hi; 103 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 104}; 105 106#define ET_RDCTRL_BUFIDX_MASK 0x000003FF 107 108struct et_rxstat { 109 uint32_t rxst_info1; 110 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 111}; 112 113#define ET_RXST_INFO1_HASH_PASS 0x00000001 114#define ET_RXST_INFO1_IPCSUM 0x00000002 115#define ET_RXST_INFO1_IPCSUM_OK 0x00000004 116#define ET_RXST_INFO1_TCPCSUM 0x00000008 117#define ET_RXST_INFO1_TCPCSUM_OK 0x00000010 118#define ET_RXST_INFO1_WOL 0x00000020 119#define ET_RXST_INFO1_RXMAC_ERR 0x00000040 120#define ET_RXST_INFO1_DROP 0x00000080 121#define ET_RXST_INFO1_FRAME_TRUNC 0x00000100 122#define ET_RXST_INFO1_JUMBO 0x00000200 123#define ET_RXST_INFO1_VLAN 0x00000400 124#define ET_RXST_INFO1_PREV_FRMAE_DROP 0x00010000 125#define ET_RXST_INFO1_SHORT 0x00020000 126#define ET_RXST_INFO1_BAD_CARRIER 0x00040000 127#define ET_RXST_INFO1_CODE_ERR 0x00080000 128#define ET_RXST_INFO1_CRC_ERR 0x00100000 129#define ET_RXST_INFO1_LEN_MISMATCH 0x00200000 130#define ET_RXST_INFO1_TOO_LONG 0x00400000 131#define ET_RXST_INFO1_OK 0x00800000 132#define ET_RXST_INFO1_MULTICAST 0x01000000 133#define ET_RXST_INFO1_BROADCAST 0x02000000 134#define ET_RXST_INFO1_DRIBBLE 0x04000000 135#define ET_RXST_INFO1_CTL_FRAME 0x08000000 136#define ET_RXST_INFO1_PAUSE_FRAME 0x10000000 137#define ET_RXST_INFO1_UNKWN_CTL_FRAME 0x20000000 138#define ET_RXST_INFO1_VLAN_TAG 0x40000000 139#define ET_RXST_INFO1_LONG_EVENT 0x80000000 140 141#define ET_RXST_INFO2_LEN_MASK 0x0000FFFF 142#define ET_RXST_INFO2_LEN_SHIFT 0 143#define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000 144#define ET_RXST_INFO2_BUFIDX_SHIFT 16 145#define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000 146#define ET_RXST_INFO2_RINGIDX_SHIFT 26 147 148struct et_rxstatus { 149 uint32_t rxs_ring; 150 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 151}; 152 153#define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000 154#define ET_RXS_STATRING_INDEX_SHIFT 16 155#define ET_RXS_STATRING_WRAP 0x10000000 156 157struct et_txbuf { 158 struct mbuf *tb_mbuf; 159 bus_dmamap_t tb_dmap; 160}; 161 162struct et_rxbuf { 163 struct mbuf *rb_mbuf; 164 bus_dmamap_t rb_dmap; 165}; 166 167struct et_txstatus_data { 168 uint32_t *txsd_status; 169 bus_addr_t txsd_paddr; 170 bus_dma_tag_t txsd_dtag; 171 bus_dmamap_t txsd_dmap; 172}; 173 174struct et_rxstatus_data { 175 struct et_rxstatus *rxsd_status; 176 bus_addr_t rxsd_paddr; 177 bus_dma_tag_t rxsd_dtag; 178 bus_dmamap_t rxsd_dmap; 179}; 180 181struct et_rxstat_ring { 182 struct et_rxstat *rsr_stat; 183 bus_addr_t rsr_paddr; 184 bus_dma_tag_t rsr_dtag; 185 bus_dmamap_t rsr_dmap; 186 187 int rsr_index; 188 int rsr_wrap; 189}; 190 191struct et_txdesc_ring { 192 struct et_txdesc *tr_desc; 193 bus_addr_t tr_paddr; 194 bus_dma_tag_t tr_dtag; 195 bus_dmamap_t tr_dmap; 196 197 int tr_ready_index; 198 int tr_ready_wrap; 199}; 200 201struct et_rxdesc_ring { 202 struct et_rxdesc *rr_desc; 203 bus_addr_t rr_paddr; 204 bus_dma_tag_t rr_dtag; 205 bus_dmamap_t rr_dmap; 206 207 uint32_t rr_posreg; 208 int rr_index; 209 int rr_wrap; 210}; 211 212struct et_txbuf_data { 213 struct et_txbuf tbd_buf[ET_TX_NDESC]; 214 215 int tbd_start_index; 216 int tbd_start_wrap; 217 int tbd_used; 218}; 219 220struct et_softc; 221struct et_rxbuf_data; 222 223struct et_rxbuf_data { 224 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 225 226 struct et_softc *rbd_softc; 227 struct et_rxdesc_ring *rbd_ring; 228 229 int rbd_bufsize; 230 int (*rbd_newbuf)(struct et_rxbuf_data *, int); 231 void (*rbd_discard)(struct et_rxbuf_data *, int); 232}; 233 234struct et_hw_stats { 235 /* RX/TX stats. */ 236 uint64_t pkts_64; 237 uint64_t pkts_65; 238 uint64_t pkts_128; 239 uint64_t pkts_256; 240 uint64_t pkts_512; 241 uint64_t pkts_1024; 242 uint64_t pkts_1519; 243 /* RX stats. */ 244 uint64_t rx_bytes; 245 uint64_t rx_frames; 246 uint32_t rx_crcerrs; 247 uint64_t rx_mcast; 248 uint64_t rx_bcast; 249 uint32_t rx_control; 250 uint32_t rx_pause; 251 uint32_t rx_unknown_control; 252 uint32_t rx_alignerrs; 253 uint32_t rx_lenerrs; 254 uint32_t rx_codeerrs; 255 uint32_t rx_cserrs; 256 uint32_t rx_runts; 257 uint64_t rx_oversize; 258 uint32_t rx_fragments; 259 uint32_t rx_jabbers; 260 uint32_t rx_drop; 261 /* TX stats. */ 262 uint64_t tx_bytes; 263 uint64_t tx_frames; 264 uint64_t tx_mcast; 265 uint64_t tx_bcast; 266 uint32_t tx_pause; 267 uint32_t tx_deferred; 268 uint32_t tx_excess_deferred; 269 uint32_t tx_single_colls; 270 uint32_t tx_multi_colls; 271 uint32_t tx_late_colls; 272 uint32_t tx_excess_colls; 273 uint32_t tx_total_colls; 274 uint32_t tx_pause_honored; 275 uint32_t tx_drop; 276 uint32_t tx_jabbers; 277 uint32_t tx_crcerrs; 278 uint32_t tx_control; 279 uint64_t tx_oversize; 280 uint32_t tx_undersize; 281 uint32_t tx_fragments; 282}; 283 284struct et_softc { 285 struct ifnet *ifp; 286 device_t dev; 287 struct mtx sc_mtx; 288 device_t sc_miibus; 289 void *sc_irq_handle; 290 struct resource *sc_irq_res; 291 struct resource *sc_mem_res; 292 293 int sc_if_flags; 294 uint32_t sc_flags; /* ET_FLAG_ */ 295 int sc_expcap; 296 297 int sc_mem_rid; 298 299 int sc_irq_rid; 300 301 struct callout sc_tick; 302 303 int watchdog_timer; 304 305 bus_dma_tag_t sc_dtag; 306 307 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 308 struct et_rxstat_ring sc_rxstat_ring; 309 struct et_rxstatus_data sc_rx_status; 310 311 struct et_txdesc_ring sc_tx_ring; 312 struct et_txstatus_data sc_tx_status; 313 314 bus_dma_tag_t sc_mbuf_dtag; 315 bus_dma_tag_t sc_rx_mini_tag; 316 bus_dmamap_t sc_rx_mini_sparemap; 317 bus_dma_tag_t sc_rx_tag; 318 bus_dmamap_t sc_rx_sparemap; 319 bus_dma_tag_t sc_tx_tag; 320 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 321 struct et_txbuf_data sc_tx_data; 322 323 struct et_hw_stats sc_stats; 324 uint32_t sc_tx; 325 uint32_t sc_tx_intr; 326 327 /* 328 * Sysctl variables 329 */ 330 int sc_rx_intr_npkts; 331 int sc_rx_intr_delay; 332 int sc_tx_intr_nsegs; 333 uint32_t sc_timer; 334}; 335 336#define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 337#define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 338#define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 339 340#define ET_FLAG_PCIE 0x0001 341#define ET_FLAG_MSI 0x0002 342#define ET_FLAG_FASTETHER 0x0004 343#define ET_FLAG_TXRX_ENABLED 0x0100 344#define ET_FLAG_JUMBO 0x0200 345#define ET_FLAG_LINK 0x8000 346 347#endif /* !_IF_ETVAR_H */ 348