e1000_mac.c revision 205869
1177867Sjfv/****************************************************************************** 2169240Sjfv 3203049Sjfv Copyright (c) 2001-2010, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 205869 2010-03-29 23:36:34Z jfv $*/ 34169240Sjfv 35169589Sjfv#include "e1000_api.h" 36169240Sjfv 37185353Sjfvstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38190872Sjfvstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39185353Sjfv 40169240Sjfv/** 41177867Sjfv * e1000_init_mac_ops_generic - Initialize MAC function pointers 42177867Sjfv * @hw: pointer to the HW structure 43177867Sjfv * 44177867Sjfv * Setups up the function pointers to no-op functions 45177867Sjfv **/ 46177867Sjfvvoid e1000_init_mac_ops_generic(struct e1000_hw *hw) 47177867Sjfv{ 48177867Sjfv struct e1000_mac_info *mac = &hw->mac; 49177867Sjfv DEBUGFUNC("e1000_init_mac_ops_generic"); 50177867Sjfv 51177867Sjfv /* General Setup */ 52177867Sjfv mac->ops.init_params = e1000_null_ops_generic; 53177867Sjfv mac->ops.init_hw = e1000_null_ops_generic; 54177867Sjfv mac->ops.reset_hw = e1000_null_ops_generic; 55177867Sjfv mac->ops.setup_physical_interface = e1000_null_ops_generic; 56177867Sjfv mac->ops.get_bus_info = e1000_null_ops_generic; 57185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59177867Sjfv mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60177867Sjfv mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61177867Sjfv /* LED */ 62177867Sjfv mac->ops.cleanup_led = e1000_null_ops_generic; 63177867Sjfv mac->ops.setup_led = e1000_null_ops_generic; 64177867Sjfv mac->ops.blink_led = e1000_null_ops_generic; 65177867Sjfv mac->ops.led_on = e1000_null_ops_generic; 66177867Sjfv mac->ops.led_off = e1000_null_ops_generic; 67177867Sjfv /* LINK */ 68177867Sjfv mac->ops.setup_link = e1000_null_ops_generic; 69177867Sjfv mac->ops.get_link_up_info = e1000_null_link_info; 70177867Sjfv mac->ops.check_for_link = e1000_null_ops_generic; 71177867Sjfv mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72177867Sjfv /* Management */ 73177867Sjfv mac->ops.check_mng_mode = e1000_null_mng_mode; 74177867Sjfv mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75177867Sjfv mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76177867Sjfv mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77177867Sjfv /* VLAN, MC, etc. */ 78177867Sjfv mac->ops.update_mc_addr_list = e1000_null_update_mc; 79177867Sjfv mac->ops.clear_vfta = e1000_null_mac_generic; 80177867Sjfv mac->ops.write_vfta = e1000_null_write_vfta; 81177867Sjfv mac->ops.rar_set = e1000_rar_set_generic; 82177867Sjfv mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 83177867Sjfv} 84177867Sjfv 85177867Sjfv/** 86177867Sjfv * e1000_null_ops_generic - No-op function, returns 0 87177867Sjfv * @hw: pointer to the HW structure 88177867Sjfv **/ 89177867Sjfvs32 e1000_null_ops_generic(struct e1000_hw *hw) 90177867Sjfv{ 91177867Sjfv DEBUGFUNC("e1000_null_ops_generic"); 92177867Sjfv return E1000_SUCCESS; 93177867Sjfv} 94177867Sjfv 95177867Sjfv/** 96177867Sjfv * e1000_null_mac_generic - No-op function, return void 97177867Sjfv * @hw: pointer to the HW structure 98177867Sjfv **/ 99177867Sjfvvoid e1000_null_mac_generic(struct e1000_hw *hw) 100177867Sjfv{ 101177867Sjfv DEBUGFUNC("e1000_null_mac_generic"); 102177867Sjfv return; 103177867Sjfv} 104177867Sjfv 105177867Sjfv/** 106177867Sjfv * e1000_null_link_info - No-op function, return 0 107177867Sjfv * @hw: pointer to the HW structure 108177867Sjfv **/ 109177867Sjfvs32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110177867Sjfv{ 111177867Sjfv DEBUGFUNC("e1000_null_link_info"); 112177867Sjfv return E1000_SUCCESS; 113177867Sjfv} 114177867Sjfv 115177867Sjfv/** 116177867Sjfv * e1000_null_mng_mode - No-op function, return FALSE 117177867Sjfv * @hw: pointer to the HW structure 118177867Sjfv **/ 119177867Sjfvbool e1000_null_mng_mode(struct e1000_hw *hw) 120177867Sjfv{ 121177867Sjfv DEBUGFUNC("e1000_null_mng_mode"); 122177867Sjfv return FALSE; 123177867Sjfv} 124177867Sjfv 125177867Sjfv/** 126177867Sjfv * e1000_null_update_mc - No-op function, return void 127177867Sjfv * @hw: pointer to the HW structure 128177867Sjfv **/ 129190872Sjfvvoid e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 130177867Sjfv{ 131177867Sjfv DEBUGFUNC("e1000_null_update_mc"); 132177867Sjfv return; 133177867Sjfv} 134177867Sjfv 135177867Sjfv/** 136177867Sjfv * e1000_null_write_vfta - No-op function, return void 137177867Sjfv * @hw: pointer to the HW structure 138177867Sjfv **/ 139177867Sjfvvoid e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 140177867Sjfv{ 141177867Sjfv DEBUGFUNC("e1000_null_write_vfta"); 142177867Sjfv return; 143177867Sjfv} 144177867Sjfv 145177867Sjfv/** 146177867Sjfv * e1000_null_rar_set - No-op function, return void 147177867Sjfv * @hw: pointer to the HW structure 148177867Sjfv **/ 149177867Sjfvvoid e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 150177867Sjfv{ 151177867Sjfv DEBUGFUNC("e1000_null_rar_set"); 152177867Sjfv return; 153177867Sjfv} 154177867Sjfv 155177867Sjfv/** 156169240Sjfv * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 157169589Sjfv * @hw: pointer to the HW structure 158169240Sjfv * 159169240Sjfv * Determines and stores the system bus information for a particular 160169240Sjfv * network interface. The following bus information is determined and stored: 161169240Sjfv * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 162169240Sjfv **/ 163173788Sjfvs32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 164169240Sjfv{ 165185353Sjfv struct e1000_mac_info *mac = &hw->mac; 166169240Sjfv struct e1000_bus_info *bus = &hw->bus; 167169240Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 168169240Sjfv s32 ret_val = E1000_SUCCESS; 169169240Sjfv 170169240Sjfv DEBUGFUNC("e1000_get_bus_info_pci_generic"); 171169240Sjfv 172169240Sjfv /* PCI or PCI-X? */ 173169240Sjfv bus->type = (status & E1000_STATUS_PCIX_MODE) 174169240Sjfv ? e1000_bus_type_pcix 175169240Sjfv : e1000_bus_type_pci; 176169240Sjfv 177169240Sjfv /* Bus speed */ 178169240Sjfv if (bus->type == e1000_bus_type_pci) { 179169240Sjfv bus->speed = (status & E1000_STATUS_PCI66) 180169240Sjfv ? e1000_bus_speed_66 181169240Sjfv : e1000_bus_speed_33; 182169240Sjfv } else { 183169240Sjfv switch (status & E1000_STATUS_PCIX_SPEED) { 184169240Sjfv case E1000_STATUS_PCIX_SPEED_66: 185169240Sjfv bus->speed = e1000_bus_speed_66; 186169240Sjfv break; 187169240Sjfv case E1000_STATUS_PCIX_SPEED_100: 188169240Sjfv bus->speed = e1000_bus_speed_100; 189169240Sjfv break; 190169240Sjfv case E1000_STATUS_PCIX_SPEED_133: 191169240Sjfv bus->speed = e1000_bus_speed_133; 192169240Sjfv break; 193169240Sjfv default: 194169240Sjfv bus->speed = e1000_bus_speed_reserved; 195169240Sjfv break; 196169240Sjfv } 197169240Sjfv } 198169240Sjfv 199169240Sjfv /* Bus width */ 200169240Sjfv bus->width = (status & E1000_STATUS_BUS64) 201169240Sjfv ? e1000_bus_width_64 202169240Sjfv : e1000_bus_width_32; 203169240Sjfv 204169240Sjfv /* Which PCI(-X) function? */ 205185353Sjfv mac->ops.set_lan_id(hw); 206169240Sjfv 207169240Sjfv return ret_val; 208169240Sjfv} 209169240Sjfv 210169240Sjfv/** 211169240Sjfv * e1000_get_bus_info_pcie_generic - Get PCIe bus information 212169589Sjfv * @hw: pointer to the HW structure 213169240Sjfv * 214169240Sjfv * Determines and stores the system bus information for a particular 215169240Sjfv * network interface. The following bus information is determined and stored: 216169240Sjfv * bus speed, bus width, type (PCIe), and PCIe function. 217169240Sjfv **/ 218173788Sjfvs32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 219169240Sjfv{ 220185353Sjfv struct e1000_mac_info *mac = &hw->mac; 221169240Sjfv struct e1000_bus_info *bus = &hw->bus; 222169240Sjfv s32 ret_val; 223185353Sjfv u16 pcie_link_status; 224169240Sjfv 225169240Sjfv DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 226169240Sjfv 227169240Sjfv bus->type = e1000_bus_type_pci_express; 228169240Sjfv 229169240Sjfv ret_val = e1000_read_pcie_cap_reg(hw, 230169240Sjfv PCIE_LINK_STATUS, 231169240Sjfv &pcie_link_status); 232205869Sjfv if (ret_val) { 233169240Sjfv bus->width = e1000_bus_width_unknown; 234205869Sjfv bus->speed = e1000_bus_speed_unknown; 235205869Sjfv } else { 236205869Sjfv switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 237205869Sjfv case PCIE_LINK_SPEED_2500: 238205869Sjfv bus->speed = e1000_bus_speed_2500; 239205869Sjfv break; 240205869Sjfv case PCIE_LINK_SPEED_5000: 241205869Sjfv bus->speed = e1000_bus_speed_5000; 242205869Sjfv break; 243205869Sjfv default: 244205869Sjfv bus->speed = e1000_bus_speed_unknown; 245205869Sjfv break; 246205869Sjfv } 247205869Sjfv 248181027Sjfv bus->width = (enum e1000_bus_width)((pcie_link_status & 249169240Sjfv PCIE_LINK_WIDTH_MASK) >> 250169240Sjfv PCIE_LINK_WIDTH_SHIFT); 251205869Sjfv } 252169240Sjfv 253185353Sjfv mac->ops.set_lan_id(hw); 254185353Sjfv 255185353Sjfv return E1000_SUCCESS; 256185353Sjfv} 257185353Sjfv 258185353Sjfv/** 259185353Sjfv * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 260185353Sjfv * 261185353Sjfv * @hw: pointer to the HW structure 262185353Sjfv * 263185353Sjfv * Determines the LAN function id by reading memory-mapped registers 264185353Sjfv * and swaps the port value if requested. 265185353Sjfv **/ 266190872Sjfvstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 267185353Sjfv{ 268185353Sjfv struct e1000_bus_info *bus = &hw->bus; 269185353Sjfv u32 reg; 270185353Sjfv 271190872Sjfv /* 272190872Sjfv * The status register reports the correct function number 273190872Sjfv * for the device regardless of function swap state. 274190872Sjfv */ 275185353Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 276185353Sjfv bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 277185353Sjfv} 278185353Sjfv 279185353Sjfv/** 280185353Sjfv * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 281185353Sjfv * @hw: pointer to the HW structure 282185353Sjfv * 283185353Sjfv * Determines the LAN function id by reading PCI config space. 284185353Sjfv **/ 285185353Sjfvvoid e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 286185353Sjfv{ 287185353Sjfv struct e1000_bus_info *bus = &hw->bus; 288185353Sjfv u16 pci_header_type; 289185353Sjfv u32 status; 290185353Sjfv 291169240Sjfv e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 292169240Sjfv if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 293169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 294169240Sjfv bus->func = (status & E1000_STATUS_FUNC_MASK) 295169240Sjfv >> E1000_STATUS_FUNC_SHIFT; 296173788Sjfv } else { 297169240Sjfv bus->func = 0; 298173788Sjfv } 299185353Sjfv} 300169240Sjfv 301185353Sjfv/** 302185353Sjfv * e1000_set_lan_id_single_port - Set LAN id for a single port device 303185353Sjfv * @hw: pointer to the HW structure 304185353Sjfv * 305185353Sjfv * Sets the LAN function id to zero for a single port device. 306185353Sjfv **/ 307185353Sjfvvoid e1000_set_lan_id_single_port(struct e1000_hw *hw) 308185353Sjfv{ 309185353Sjfv struct e1000_bus_info *bus = &hw->bus; 310185353Sjfv 311185353Sjfv bus->func = 0; 312169240Sjfv} 313169240Sjfv 314169240Sjfv/** 315169240Sjfv * e1000_clear_vfta_generic - Clear VLAN filter table 316169589Sjfv * @hw: pointer to the HW structure 317169240Sjfv * 318169240Sjfv * Clears the register array which contains the VLAN filter table by 319169240Sjfv * setting all the values to 0. 320169240Sjfv **/ 321173788Sjfvvoid e1000_clear_vfta_generic(struct e1000_hw *hw) 322169240Sjfv{ 323169240Sjfv u32 offset; 324169240Sjfv 325169240Sjfv DEBUGFUNC("e1000_clear_vfta_generic"); 326169240Sjfv 327169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 328169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 329169240Sjfv E1000_WRITE_FLUSH(hw); 330169240Sjfv } 331169240Sjfv} 332169240Sjfv 333169240Sjfv/** 334169240Sjfv * e1000_write_vfta_generic - Write value to VLAN filter table 335169589Sjfv * @hw: pointer to the HW structure 336169589Sjfv * @offset: register offset in VLAN filter table 337169589Sjfv * @value: register value written to VLAN filter table 338169240Sjfv * 339169240Sjfv * Writes value at the given offset in the register array which stores 340169240Sjfv * the VLAN filter table. 341169240Sjfv **/ 342173788Sjfvvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 343169240Sjfv{ 344169240Sjfv DEBUGFUNC("e1000_write_vfta_generic"); 345169240Sjfv 346169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 347169240Sjfv E1000_WRITE_FLUSH(hw); 348169240Sjfv} 349169240Sjfv 350169240Sjfv/** 351169240Sjfv * e1000_init_rx_addrs_generic - Initialize receive address's 352169589Sjfv * @hw: pointer to the HW structure 353169589Sjfv * @rar_count: receive address registers 354169240Sjfv * 355169240Sjfv * Setups the receive address registers by setting the base receive address 356169240Sjfv * register to the devices MAC address and clearing all the other receive 357169240Sjfv * address registers to 0. 358169240Sjfv **/ 359173788Sjfvvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 360169240Sjfv{ 361169240Sjfv u32 i; 362190872Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 363169240Sjfv 364169240Sjfv DEBUGFUNC("e1000_init_rx_addrs_generic"); 365169240Sjfv 366169240Sjfv /* Setup the receive address */ 367169240Sjfv DEBUGOUT("Programming MAC Address into RAR[0]\n"); 368169240Sjfv 369177867Sjfv hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 370169240Sjfv 371169240Sjfv /* Zero out the other (rar_entry_count - 1) receive addresses */ 372169240Sjfv DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 373190872Sjfv for (i = 1; i < rar_count; i++) 374190872Sjfv hw->mac.ops.rar_set(hw, mac_addr, i); 375169240Sjfv} 376169240Sjfv 377169240Sjfv/** 378173788Sjfv * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 379173788Sjfv * @hw: pointer to the HW structure 380173788Sjfv * 381173788Sjfv * Checks the nvm for an alternate MAC address. An alternate MAC address 382173788Sjfv * can be setup by pre-boot software and must be treated like a permanent 383190872Sjfv * address and must override the actual permanent MAC address. If an 384190872Sjfv * alternate MAC address is found it is programmed into RAR0, replacing 385190872Sjfv * the permanent address that was installed into RAR0 by the Si on reset. 386190872Sjfv * This function will return SUCCESS unless it encounters an error while 387190872Sjfv * reading the EEPROM. 388173788Sjfv **/ 389173788Sjfvs32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 390173788Sjfv{ 391173788Sjfv u32 i; 392173788Sjfv s32 ret_val = E1000_SUCCESS; 393173788Sjfv u16 offset, nvm_alt_mac_addr_offset, nvm_data; 394173788Sjfv u8 alt_mac_addr[ETH_ADDR_LEN]; 395173788Sjfv 396173788Sjfv DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 397173788Sjfv 398177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 399176667Sjfv &nvm_alt_mac_addr_offset); 400173788Sjfv if (ret_val) { 401173788Sjfv DEBUGOUT("NVM Read Error\n"); 402173788Sjfv goto out; 403173788Sjfv } 404173788Sjfv 405173788Sjfv if (nvm_alt_mac_addr_offset == 0xFFFF) { 406190872Sjfv /* There is no Alternate MAC Address */ 407173788Sjfv goto out; 408173788Sjfv } 409173788Sjfv 410173788Sjfv if (hw->bus.func == E1000_FUNC_1) 411190872Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 412200243Sjfv if (hw->bus.func == E1000_FUNC_2) 413200243Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 414200243Sjfv 415200243Sjfv if (hw->bus.func == E1000_FUNC_3) 416200243Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 417173788Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 418173788Sjfv offset = nvm_alt_mac_addr_offset + (i >> 1); 419177867Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 420173788Sjfv if (ret_val) { 421173788Sjfv DEBUGOUT("NVM Read Error\n"); 422173788Sjfv goto out; 423173788Sjfv } 424173788Sjfv 425173788Sjfv alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 426173788Sjfv alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 427173788Sjfv } 428173788Sjfv 429173788Sjfv /* if multicast bit is set, the alternate address will not be used */ 430173788Sjfv if (alt_mac_addr[0] & 0x01) { 431190872Sjfv DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 432173788Sjfv goto out; 433173788Sjfv } 434173788Sjfv 435190872Sjfv /* 436190872Sjfv * We have a valid alternate MAC address, and we want to treat it the 437190872Sjfv * same as the normal permanent MAC address stored by the HW into the 438190872Sjfv * RAR. Do this by mapping this address into RAR0. 439190872Sjfv */ 440190872Sjfv hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 441173788Sjfv 442173788Sjfvout: 443173788Sjfv return ret_val; 444173788Sjfv} 445173788Sjfv 446173788Sjfv/** 447169240Sjfv * e1000_rar_set_generic - Set receive address register 448169589Sjfv * @hw: pointer to the HW structure 449169589Sjfv * @addr: pointer to the receive address 450169589Sjfv * @index: receive address array register 451169240Sjfv * 452169240Sjfv * Sets the receive address array register at index to the address passed 453169240Sjfv * in by addr. 454169240Sjfv **/ 455173788Sjfvvoid e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 456169240Sjfv{ 457169240Sjfv u32 rar_low, rar_high; 458169240Sjfv 459169240Sjfv DEBUGFUNC("e1000_rar_set_generic"); 460169240Sjfv 461173788Sjfv /* 462173788Sjfv * HW expects these in little endian so we reverse the byte order 463169240Sjfv * from network order (big endian) to little endian 464169240Sjfv */ 465169240Sjfv rar_low = ((u32) addr[0] | 466176667Sjfv ((u32) addr[1] << 8) | 467176667Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 468169240Sjfv 469169240Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 470169240Sjfv 471173788Sjfv /* If MAC address zero, no need to set the AV bit */ 472185353Sjfv if (rar_low || rar_high) 473185353Sjfv rar_high |= E1000_RAH_AV; 474169240Sjfv 475190872Sjfv /* 476190872Sjfv * Some bridges will combine consecutive 32-bit writes into 477190872Sjfv * a single burst write, which will malfunction on some parts. 478190872Sjfv * The flushes avoid this. 479190872Sjfv */ 480176667Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 481190872Sjfv E1000_WRITE_FLUSH(hw); 482176667Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 483190872Sjfv E1000_WRITE_FLUSH(hw); 484169240Sjfv} 485169240Sjfv 486169240Sjfv/** 487173788Sjfv * e1000_update_mc_addr_list_generic - Update Multicast addresses 488169589Sjfv * @hw: pointer to the HW structure 489169589Sjfv * @mc_addr_list: array of multicast addresses to program 490169589Sjfv * @mc_addr_count: number of multicast addresses to program 491169240Sjfv * 492190872Sjfv * Updates entire Multicast Table Array. 493169240Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 494169240Sjfv **/ 495173788Sjfvvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 496190872Sjfv u8 *mc_addr_list, u32 mc_addr_count) 497169240Sjfv{ 498190872Sjfv u32 hash_value, hash_bit, hash_reg; 499190872Sjfv int i; 500169240Sjfv 501173788Sjfv DEBUGFUNC("e1000_update_mc_addr_list_generic"); 502169240Sjfv 503190872Sjfv /* clear mta_shadow */ 504190872Sjfv memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 505169240Sjfv 506190872Sjfv /* update mta_shadow from mc_addr_list */ 507190872Sjfv for (i = 0; (u32) i < mc_addr_count; i++) { 508190872Sjfv hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 509190872Sjfv 510190872Sjfv hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 511190872Sjfv hash_bit = hash_value & 0x1F; 512190872Sjfv 513190872Sjfv hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 514190872Sjfv mc_addr_list += (ETH_ADDR_LEN); 515169240Sjfv } 516169240Sjfv 517190872Sjfv /* replace the entire MTA table */ 518190872Sjfv for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 519190872Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 520190872Sjfv E1000_WRITE_FLUSH(hw); 521169240Sjfv} 522169240Sjfv 523169240Sjfv/** 524169240Sjfv * e1000_hash_mc_addr_generic - Generate a multicast hash value 525169589Sjfv * @hw: pointer to the HW structure 526169589Sjfv * @mc_addr: pointer to a multicast address 527169240Sjfv * 528169240Sjfv * Generates a multicast address hash value which is used to determine 529203049Sjfv * the multicast filter table array address and new table value. 530169240Sjfv **/ 531173788Sjfvu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 532169240Sjfv{ 533169240Sjfv u32 hash_value, hash_mask; 534169240Sjfv u8 bit_shift = 0; 535169240Sjfv 536169240Sjfv DEBUGFUNC("e1000_hash_mc_addr_generic"); 537169240Sjfv 538169240Sjfv /* Register count multiplied by bits per register */ 539169240Sjfv hash_mask = (hw->mac.mta_reg_count * 32) - 1; 540169240Sjfv 541173788Sjfv /* 542173788Sjfv * For a mc_filter_type of 0, bit_shift is the number of left-shifts 543173788Sjfv * where 0xFF would still fall within the hash mask. 544173788Sjfv */ 545169240Sjfv while (hash_mask >> bit_shift != 0xFF) 546169240Sjfv bit_shift++; 547169240Sjfv 548173788Sjfv /* 549173788Sjfv * The portion of the address that is used for the hash table 550169240Sjfv * is determined by the mc_filter_type setting. 551169240Sjfv * The algorithm is such that there is a total of 8 bits of shifting. 552169240Sjfv * The bit_shift for a mc_filter_type of 0 represents the number of 553169240Sjfv * left-shifts where the MSB of mc_addr[5] would still fall within 554169240Sjfv * the hash_mask. Case 0 does this exactly. Since there are a total 555169240Sjfv * of 8 bits of shifting, then mc_addr[4] will shift right the 556169240Sjfv * remaining number of bits. Thus 8 - bit_shift. The rest of the 557169240Sjfv * cases are a variation of this algorithm...essentially raising the 558169240Sjfv * number of bits to shift mc_addr[5] left, while still keeping the 559169240Sjfv * 8-bit shifting total. 560173788Sjfv * 561173788Sjfv * For example, given the following Destination MAC Address and an 562169240Sjfv * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 563169240Sjfv * we can see that the bit_shift for case 0 is 4. These are the hash 564169240Sjfv * values resulting from each mc_filter_type... 565169240Sjfv * [0] [1] [2] [3] [4] [5] 566169240Sjfv * 01 AA 00 12 34 56 567169240Sjfv * LSB MSB 568169240Sjfv * 569169240Sjfv * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 570169240Sjfv * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 571169240Sjfv * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 572169240Sjfv * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 573169240Sjfv */ 574169240Sjfv switch (hw->mac.mc_filter_type) { 575185353Sjfv default: 576185353Sjfv case 0: 577185353Sjfv break; 578185353Sjfv case 1: 579185353Sjfv bit_shift += 1; 580185353Sjfv break; 581185353Sjfv case 2: 582185353Sjfv bit_shift += 2; 583185353Sjfv break; 584185353Sjfv case 3: 585185353Sjfv bit_shift += 4; 586185353Sjfv break; 587169240Sjfv } 588169240Sjfv 589169240Sjfv hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 590169240Sjfv (((u16) mc_addr[5]) << bit_shift))); 591169240Sjfv 592169240Sjfv return hash_value; 593169240Sjfv} 594169240Sjfv 595169240Sjfv/** 596169240Sjfv * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 597169589Sjfv * @hw: pointer to the HW structure 598169240Sjfv * 599169240Sjfv * In certain situations, a system BIOS may report that the PCIx maximum 600169240Sjfv * memory read byte count (MMRBC) value is higher than than the actual 601176667Sjfv * value. We check the PCIx command register with the current PCIx status 602176667Sjfv * register. 603169240Sjfv **/ 604173788Sjfvvoid e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 605169240Sjfv{ 606169240Sjfv u16 cmd_mmrbc; 607169240Sjfv u16 pcix_cmd; 608169240Sjfv u16 pcix_stat_hi_word; 609169240Sjfv u16 stat_mmrbc; 610169240Sjfv 611169240Sjfv DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 612169240Sjfv 613169240Sjfv /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 614169240Sjfv if (hw->bus.type != e1000_bus_type_pcix) 615169240Sjfv return; 616169240Sjfv 617169240Sjfv e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 618169240Sjfv e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 619169240Sjfv cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 620176667Sjfv PCIX_COMMAND_MMRBC_SHIFT; 621169240Sjfv stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 622176667Sjfv PCIX_STATUS_HI_MMRBC_SHIFT; 623169240Sjfv if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 624169240Sjfv stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 625169240Sjfv if (cmd_mmrbc > stat_mmrbc) { 626169240Sjfv pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 627169240Sjfv pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 628169240Sjfv e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 629169240Sjfv } 630169240Sjfv} 631169240Sjfv 632169240Sjfv/** 633169240Sjfv * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 634169589Sjfv * @hw: pointer to the HW structure 635169240Sjfv * 636169240Sjfv * Clears the base hardware counters by reading the counter registers. 637169240Sjfv **/ 638173788Sjfvvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 639169240Sjfv{ 640169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 641169240Sjfv 642185353Sjfv E1000_READ_REG(hw, E1000_CRCERRS); 643185353Sjfv E1000_READ_REG(hw, E1000_SYMERRS); 644185353Sjfv E1000_READ_REG(hw, E1000_MPC); 645185353Sjfv E1000_READ_REG(hw, E1000_SCC); 646185353Sjfv E1000_READ_REG(hw, E1000_ECOL); 647185353Sjfv E1000_READ_REG(hw, E1000_MCC); 648185353Sjfv E1000_READ_REG(hw, E1000_LATECOL); 649185353Sjfv E1000_READ_REG(hw, E1000_COLC); 650185353Sjfv E1000_READ_REG(hw, E1000_DC); 651185353Sjfv E1000_READ_REG(hw, E1000_SEC); 652185353Sjfv E1000_READ_REG(hw, E1000_RLEC); 653185353Sjfv E1000_READ_REG(hw, E1000_XONRXC); 654185353Sjfv E1000_READ_REG(hw, E1000_XONTXC); 655185353Sjfv E1000_READ_REG(hw, E1000_XOFFRXC); 656185353Sjfv E1000_READ_REG(hw, E1000_XOFFTXC); 657185353Sjfv E1000_READ_REG(hw, E1000_FCRUC); 658185353Sjfv E1000_READ_REG(hw, E1000_GPRC); 659185353Sjfv E1000_READ_REG(hw, E1000_BPRC); 660185353Sjfv E1000_READ_REG(hw, E1000_MPRC); 661185353Sjfv E1000_READ_REG(hw, E1000_GPTC); 662185353Sjfv E1000_READ_REG(hw, E1000_GORCL); 663185353Sjfv E1000_READ_REG(hw, E1000_GORCH); 664185353Sjfv E1000_READ_REG(hw, E1000_GOTCL); 665185353Sjfv E1000_READ_REG(hw, E1000_GOTCH); 666185353Sjfv E1000_READ_REG(hw, E1000_RNBC); 667185353Sjfv E1000_READ_REG(hw, E1000_RUC); 668185353Sjfv E1000_READ_REG(hw, E1000_RFC); 669185353Sjfv E1000_READ_REG(hw, E1000_ROC); 670185353Sjfv E1000_READ_REG(hw, E1000_RJC); 671185353Sjfv E1000_READ_REG(hw, E1000_TORL); 672185353Sjfv E1000_READ_REG(hw, E1000_TORH); 673185353Sjfv E1000_READ_REG(hw, E1000_TOTL); 674185353Sjfv E1000_READ_REG(hw, E1000_TOTH); 675185353Sjfv E1000_READ_REG(hw, E1000_TPR); 676185353Sjfv E1000_READ_REG(hw, E1000_TPT); 677185353Sjfv E1000_READ_REG(hw, E1000_MPTC); 678185353Sjfv E1000_READ_REG(hw, E1000_BPTC); 679169240Sjfv} 680169240Sjfv 681169240Sjfv/** 682169240Sjfv * e1000_check_for_copper_link_generic - Check for link (Copper) 683169589Sjfv * @hw: pointer to the HW structure 684169240Sjfv * 685169240Sjfv * Checks to see of the link status of the hardware has changed. If a 686169240Sjfv * change in link status has been detected, then we read the PHY registers 687169240Sjfv * to get the current speed/duplex if link exists. 688169240Sjfv **/ 689173788Sjfvs32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 690169240Sjfv{ 691169240Sjfv struct e1000_mac_info *mac = &hw->mac; 692169240Sjfv s32 ret_val; 693173788Sjfv bool link; 694169240Sjfv 695169240Sjfv DEBUGFUNC("e1000_check_for_copper_link"); 696169240Sjfv 697173788Sjfv /* 698173788Sjfv * We only want to go out to the PHY registers to see if Auto-Neg 699169240Sjfv * has completed and/or if our link status has changed. The 700169240Sjfv * get_link_status flag is set upon receiving a Link Status 701169240Sjfv * Change or Rx Sequence Error interrupt. 702169240Sjfv */ 703169240Sjfv if (!mac->get_link_status) { 704169240Sjfv ret_val = E1000_SUCCESS; 705169240Sjfv goto out; 706169240Sjfv } 707169240Sjfv 708173788Sjfv /* 709173788Sjfv * First we want to see if the MII Status Register reports 710169240Sjfv * link. If so, then we want to get the current speed/duplex 711169240Sjfv * of the PHY. 712169240Sjfv */ 713169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 714169240Sjfv if (ret_val) 715169240Sjfv goto out; 716169240Sjfv 717169240Sjfv if (!link) 718169240Sjfv goto out; /* No link detected */ 719169240Sjfv 720169240Sjfv mac->get_link_status = FALSE; 721169240Sjfv 722173788Sjfv /* 723173788Sjfv * Check if there was DownShift, must be checked 724173788Sjfv * immediately after link-up 725173788Sjfv */ 726169240Sjfv e1000_check_downshift_generic(hw); 727169240Sjfv 728173788Sjfv /* 729173788Sjfv * If we are forcing speed/duplex, then we simply return since 730169240Sjfv * we have already determined whether we have link or not. 731169240Sjfv */ 732169240Sjfv if (!mac->autoneg) { 733169240Sjfv ret_val = -E1000_ERR_CONFIG; 734169240Sjfv goto out; 735169240Sjfv } 736169240Sjfv 737173788Sjfv /* 738173788Sjfv * Auto-Neg is enabled. Auto Speed Detection takes care 739169240Sjfv * of MAC speed/duplex configuration. So we only need to 740169240Sjfv * configure Collision Distance in the MAC. 741169240Sjfv */ 742203049Sjfv mac->ops.config_collision_dist(hw); 743169240Sjfv 744173788Sjfv /* 745173788Sjfv * Configure Flow Control now that Auto-Neg has completed. 746169240Sjfv * First, we need to restore the desired flow control 747169240Sjfv * settings because we may have had to re-autoneg with a 748169240Sjfv * different link partner. 749169240Sjfv */ 750169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 751185353Sjfv if (ret_val) 752169240Sjfv DEBUGOUT("Error configuring flow control\n"); 753169240Sjfv 754169240Sjfvout: 755169240Sjfv return ret_val; 756169240Sjfv} 757169240Sjfv 758169240Sjfv/** 759169240Sjfv * e1000_check_for_fiber_link_generic - Check for link (Fiber) 760169589Sjfv * @hw: pointer to the HW structure 761169240Sjfv * 762169240Sjfv * Checks for link up on the hardware. If link is not up and we have 763169240Sjfv * a signal, then we need to force link up. 764169240Sjfv **/ 765173788Sjfvs32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 766169240Sjfv{ 767169240Sjfv struct e1000_mac_info *mac = &hw->mac; 768169240Sjfv u32 rxcw; 769169240Sjfv u32 ctrl; 770169240Sjfv u32 status; 771169240Sjfv s32 ret_val = E1000_SUCCESS; 772169240Sjfv 773169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_generic"); 774169240Sjfv 775169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 776169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 777169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 778169240Sjfv 779173788Sjfv /* 780173788Sjfv * If we don't have link (auto-negotiation failed or link partner 781169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 782169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 783169240Sjfv * are receiving idles or data), we need to force link up. We also 784169240Sjfv * need to give auto-negotiation time to complete, in case the cable 785169240Sjfv * was just plugged in. The autoneg_failed flag does this. 786169240Sjfv */ 787169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 788169240Sjfv if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 789169240Sjfv (!(rxcw & E1000_RXCW_C))) { 790169240Sjfv if (mac->autoneg_failed == 0) { 791169240Sjfv mac->autoneg_failed = 1; 792169240Sjfv goto out; 793169240Sjfv } 794169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 795169240Sjfv 796169240Sjfv /* Disable auto-negotiation in the TXCW register */ 797169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 798169240Sjfv 799169240Sjfv /* Force link-up and also force full-duplex. */ 800169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 801169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 802169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 803169240Sjfv 804169240Sjfv /* Configure Flow Control after forcing link up. */ 805169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 806169240Sjfv if (ret_val) { 807169240Sjfv DEBUGOUT("Error configuring flow control\n"); 808169240Sjfv goto out; 809169240Sjfv } 810169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 811173788Sjfv /* 812173788Sjfv * If we are forcing link and we are receiving /C/ ordered 813169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 814169240Sjfv * and disable forced link in the Device Control register 815169240Sjfv * in an attempt to auto-negotiate with our link partner. 816169240Sjfv */ 817169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 818169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 819169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 820169240Sjfv 821169240Sjfv mac->serdes_has_link = TRUE; 822169240Sjfv } 823169240Sjfv 824169240Sjfvout: 825169240Sjfv return ret_val; 826169240Sjfv} 827169240Sjfv 828169240Sjfv/** 829169240Sjfv * e1000_check_for_serdes_link_generic - Check for link (Serdes) 830169589Sjfv * @hw: pointer to the HW structure 831169240Sjfv * 832169240Sjfv * Checks for link up on the hardware. If link is not up and we have 833169240Sjfv * a signal, then we need to force link up. 834169240Sjfv **/ 835173788Sjfvs32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 836169240Sjfv{ 837169240Sjfv struct e1000_mac_info *mac = &hw->mac; 838169240Sjfv u32 rxcw; 839169240Sjfv u32 ctrl; 840169240Sjfv u32 status; 841169240Sjfv s32 ret_val = E1000_SUCCESS; 842169240Sjfv 843169240Sjfv DEBUGFUNC("e1000_check_for_serdes_link_generic"); 844169240Sjfv 845169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 846169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 847169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 848169240Sjfv 849173788Sjfv /* 850173788Sjfv * If we don't have link (auto-negotiation failed or link partner 851169240Sjfv * cannot auto-negotiate), and our link partner is not trying to 852169240Sjfv * auto-negotiate with us (we are receiving idles or data), 853169240Sjfv * we need to force link up. We also need to give auto-negotiation 854169240Sjfv * time to complete. 855169240Sjfv */ 856169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 857169240Sjfv if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 858169240Sjfv if (mac->autoneg_failed == 0) { 859169240Sjfv mac->autoneg_failed = 1; 860169240Sjfv goto out; 861169240Sjfv } 862169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 863169240Sjfv 864169240Sjfv /* Disable auto-negotiation in the TXCW register */ 865169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 866169240Sjfv 867169240Sjfv /* Force link-up and also force full-duplex. */ 868169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 869169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 870169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 871169240Sjfv 872169240Sjfv /* Configure Flow Control after forcing link up. */ 873169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 874169240Sjfv if (ret_val) { 875169240Sjfv DEBUGOUT("Error configuring flow control\n"); 876169240Sjfv goto out; 877169240Sjfv } 878169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 879173788Sjfv /* 880173788Sjfv * If we are forcing link and we are receiving /C/ ordered 881169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 882169240Sjfv * and disable forced link in the Device Control register 883169240Sjfv * in an attempt to auto-negotiate with our link partner. 884169240Sjfv */ 885169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 886169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 887169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 888169240Sjfv 889169240Sjfv mac->serdes_has_link = TRUE; 890169240Sjfv } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 891173788Sjfv /* 892173788Sjfv * If we force link for non-auto-negotiation switch, check 893169240Sjfv * link status based on MAC synchronization for internal 894169240Sjfv * serdes media type. 895169240Sjfv */ 896169240Sjfv /* SYNCH bit and IV bit are sticky. */ 897169240Sjfv usec_delay(10); 898181027Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 899181027Sjfv if (rxcw & E1000_RXCW_SYNCH) { 900169240Sjfv if (!(rxcw & E1000_RXCW_IV)) { 901169240Sjfv mac->serdes_has_link = TRUE; 902181027Sjfv DEBUGOUT("SERDES: Link up - forced.\n"); 903169240Sjfv } 904169240Sjfv } else { 905169240Sjfv mac->serdes_has_link = FALSE; 906181027Sjfv DEBUGOUT("SERDES: Link down - force failed.\n"); 907169240Sjfv } 908169240Sjfv } 909169240Sjfv 910169240Sjfv if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 911169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 912181027Sjfv if (status & E1000_STATUS_LU) { 913181027Sjfv /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 914181027Sjfv usec_delay(10); 915181027Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 916181027Sjfv if (rxcw & E1000_RXCW_SYNCH) { 917181027Sjfv if (!(rxcw & E1000_RXCW_IV)) { 918181027Sjfv mac->serdes_has_link = TRUE; 919181027Sjfv DEBUGOUT("SERDES: Link up - autoneg " 920181027Sjfv "completed sucessfully.\n"); 921181027Sjfv } else { 922181027Sjfv mac->serdes_has_link = FALSE; 923181027Sjfv DEBUGOUT("SERDES: Link down - invalid" 924181027Sjfv "codewords detected in autoneg.\n"); 925181027Sjfv } 926181027Sjfv } else { 927181027Sjfv mac->serdes_has_link = FALSE; 928181027Sjfv DEBUGOUT("SERDES: Link down - no sync.\n"); 929181027Sjfv } 930181027Sjfv } else { 931181027Sjfv mac->serdes_has_link = FALSE; 932181027Sjfv DEBUGOUT("SERDES: Link down - autoneg failed\n"); 933181027Sjfv } 934169240Sjfv } 935169240Sjfv 936169240Sjfvout: 937169240Sjfv return ret_val; 938169240Sjfv} 939169240Sjfv 940169240Sjfv/** 941169240Sjfv * e1000_setup_link_generic - Setup flow control and link settings 942169589Sjfv * @hw: pointer to the HW structure 943169240Sjfv * 944169240Sjfv * Determines which flow control settings to use, then configures flow 945169240Sjfv * control. Calls the appropriate media-specific link configuration 946169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 947169240Sjfv * should be established. Assumes the hardware has previously been reset 948169240Sjfv * and the transmitter and receiver are not enabled. 949169240Sjfv **/ 950173788Sjfvs32 e1000_setup_link_generic(struct e1000_hw *hw) 951169240Sjfv{ 952169240Sjfv s32 ret_val = E1000_SUCCESS; 953169240Sjfv 954169240Sjfv DEBUGFUNC("e1000_setup_link_generic"); 955169240Sjfv 956173788Sjfv /* 957173788Sjfv * In the case of the phy reset being blocked, we already have a link. 958169240Sjfv * We do not need to set it up again. 959169240Sjfv */ 960200243Sjfv if (e1000_check_reset_block(hw)) 961200243Sjfv goto out; 962169240Sjfv 963173788Sjfv /* 964185353Sjfv * If requested flow control is set to default, set flow control 965185353Sjfv * based on the EEPROM flow control settings. 966173788Sjfv */ 967185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) { 968173788Sjfv ret_val = e1000_set_default_fc_generic(hw); 969173788Sjfv if (ret_val) 970173788Sjfv goto out; 971173788Sjfv } 972169240Sjfv 973173788Sjfv /* 974185353Sjfv * Save off the requested flow control mode for use later. Depending 975185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 976169240Sjfv */ 977185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 978169240Sjfv 979185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 980190872Sjfv hw->fc.current_mode); 981169240Sjfv 982169240Sjfv /* Call the necessary media_type subroutine to configure the link. */ 983177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 984169240Sjfv if (ret_val) 985169240Sjfv goto out; 986169240Sjfv 987173788Sjfv /* 988173788Sjfv * Initialize the flow control address, type, and PAUSE timer 989169240Sjfv * registers to their default values. This is done even if flow 990169240Sjfv * control is disabled, because it does not hurt anything to 991169240Sjfv * initialize these registers. 992169240Sjfv */ 993169240Sjfv DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 994169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 995169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 996169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 997169240Sjfv 998173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 999169240Sjfv 1000169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 1001169240Sjfv 1002169240Sjfvout: 1003169240Sjfv return ret_val; 1004169240Sjfv} 1005169240Sjfv 1006169240Sjfv/** 1007169240Sjfv * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1008169589Sjfv * @hw: pointer to the HW structure 1009169240Sjfv * 1010169240Sjfv * Configures collision distance and flow control for fiber and serdes 1011169240Sjfv * links. Upon successful setup, poll for link. 1012169240Sjfv **/ 1013173788Sjfvs32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1014169240Sjfv{ 1015203049Sjfv struct e1000_mac_info *mac = &hw->mac; 1016169240Sjfv u32 ctrl; 1017169240Sjfv s32 ret_val = E1000_SUCCESS; 1018169240Sjfv 1019169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1020169240Sjfv 1021169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1022169240Sjfv 1023169240Sjfv /* Take the link out of reset */ 1024169240Sjfv ctrl &= ~E1000_CTRL_LRST; 1025169240Sjfv 1026203049Sjfv mac->ops.config_collision_dist(hw); 1027169240Sjfv 1028169240Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1029169240Sjfv if (ret_val) 1030169240Sjfv goto out; 1031169240Sjfv 1032173788Sjfv /* 1033173788Sjfv * Since auto-negotiation is enabled, take the link out of reset (the 1034169240Sjfv * link will be in reset, because we previously reset the chip). This 1035169240Sjfv * will restart auto-negotiation. If auto-negotiation is successful 1036169240Sjfv * then the link-up status bit will be set and the flow control enable 1037169240Sjfv * bits (RFCE and TFCE) will be set according to their negotiated value. 1038169240Sjfv */ 1039169240Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1040169240Sjfv 1041169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1042169240Sjfv E1000_WRITE_FLUSH(hw); 1043169240Sjfv msec_delay(1); 1044169240Sjfv 1045173788Sjfv /* 1046176667Sjfv * For these adapters, the SW definable pin 1 is set when the optics 1047169240Sjfv * detect a signal. If we have a signal, then poll for a "Link-Up" 1048169240Sjfv * indication. 1049169240Sjfv */ 1050173788Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes || 1051169240Sjfv (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1052169240Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1053169240Sjfv } else { 1054169240Sjfv DEBUGOUT("No signal detected\n"); 1055169240Sjfv } 1056169240Sjfv 1057169240Sjfvout: 1058169240Sjfv return ret_val; 1059169240Sjfv} 1060169240Sjfv 1061169240Sjfv/** 1062169240Sjfv * e1000_config_collision_dist_generic - Configure collision distance 1063169589Sjfv * @hw: pointer to the HW structure 1064169240Sjfv * 1065169240Sjfv * Configures the collision distance to the default value and is used 1066203049Sjfv * during link setup. 1067169240Sjfv **/ 1068173788Sjfvvoid e1000_config_collision_dist_generic(struct e1000_hw *hw) 1069169240Sjfv{ 1070169240Sjfv u32 tctl; 1071169240Sjfv 1072169240Sjfv DEBUGFUNC("e1000_config_collision_dist_generic"); 1073169240Sjfv 1074169240Sjfv tctl = E1000_READ_REG(hw, E1000_TCTL); 1075169240Sjfv 1076169240Sjfv tctl &= ~E1000_TCTL_COLD; 1077169240Sjfv tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1078169240Sjfv 1079169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1080169240Sjfv E1000_WRITE_FLUSH(hw); 1081169240Sjfv} 1082169240Sjfv 1083169240Sjfv/** 1084169240Sjfv * e1000_poll_fiber_serdes_link_generic - Poll for link up 1085169589Sjfv * @hw: pointer to the HW structure 1086169240Sjfv * 1087169240Sjfv * Polls for link up by reading the status register, if link fails to come 1088169240Sjfv * up with auto-negotiation, then the link is forced if a signal is detected. 1089169240Sjfv **/ 1090173788Sjfvs32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1091169240Sjfv{ 1092169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1093169240Sjfv u32 i, status; 1094169240Sjfv s32 ret_val = E1000_SUCCESS; 1095169240Sjfv 1096169240Sjfv DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1097169240Sjfv 1098173788Sjfv /* 1099177867Sjfv * If we have a signal (the cable is plugged in, or assumed TRUE for 1100169240Sjfv * serdes media) then poll for a "Link-Up" indication in the Device 1101169240Sjfv * Status Register. Time-out if a link isn't seen in 500 milliseconds 1102169240Sjfv * seconds (Auto-negotiation should complete in less than 500 1103169240Sjfv * milliseconds even if the other end is doing it in SW). 1104169240Sjfv */ 1105169240Sjfv for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1106169240Sjfv msec_delay(10); 1107169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1108169240Sjfv if (status & E1000_STATUS_LU) 1109169240Sjfv break; 1110169240Sjfv } 1111169240Sjfv if (i == FIBER_LINK_UP_LIMIT) { 1112169240Sjfv DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1113169240Sjfv mac->autoneg_failed = 1; 1114173788Sjfv /* 1115173788Sjfv * AutoNeg failed to achieve a link, so we'll call 1116169240Sjfv * mac->check_for_link. This routine will force the 1117169240Sjfv * link up if we detect a signal. This will allow us to 1118169240Sjfv * communicate with non-autonegotiating link partners. 1119169240Sjfv */ 1120203049Sjfv ret_val = mac->ops.check_for_link(hw); 1121169240Sjfv if (ret_val) { 1122169240Sjfv DEBUGOUT("Error while checking for link\n"); 1123169240Sjfv goto out; 1124169240Sjfv } 1125169240Sjfv mac->autoneg_failed = 0; 1126169240Sjfv } else { 1127169240Sjfv mac->autoneg_failed = 0; 1128169240Sjfv DEBUGOUT("Valid Link Found\n"); 1129169240Sjfv } 1130169240Sjfv 1131169240Sjfvout: 1132169240Sjfv return ret_val; 1133169240Sjfv} 1134169240Sjfv 1135169240Sjfv/** 1136169240Sjfv * e1000_commit_fc_settings_generic - Configure flow control 1137169589Sjfv * @hw: pointer to the HW structure 1138169240Sjfv * 1139169240Sjfv * Write the flow control settings to the Transmit Config Word Register (TXCW) 1140169240Sjfv * base on the flow control settings in e1000_mac_info. 1141169240Sjfv **/ 1142173788Sjfvs32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1143169240Sjfv{ 1144169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1145169240Sjfv u32 txcw; 1146169240Sjfv s32 ret_val = E1000_SUCCESS; 1147169240Sjfv 1148169240Sjfv DEBUGFUNC("e1000_commit_fc_settings_generic"); 1149169240Sjfv 1150173788Sjfv /* 1151173788Sjfv * Check for a software override of the flow control settings, and 1152169240Sjfv * setup the device accordingly. If auto-negotiation is enabled, then 1153169240Sjfv * software will have to set the "PAUSE" bits to the correct value in 1154169240Sjfv * the Transmit Config Word Register (TXCW) and re-start auto- 1155169240Sjfv * negotiation. However, if auto-negotiation is disabled, then 1156169240Sjfv * software will have to manually configure the two flow control enable 1157169240Sjfv * bits in the CTRL register. 1158169240Sjfv * 1159169240Sjfv * The possible values of the "fc" parameter are: 1160169240Sjfv * 0: Flow control is completely disabled 1161169240Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 1162169240Sjfv * but not send pause frames). 1163169240Sjfv * 2: Tx flow control is enabled (we can send pause frames but we 1164169240Sjfv * do not support receiving pause frames). 1165173788Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 1166169240Sjfv */ 1167185353Sjfv switch (hw->fc.current_mode) { 1168169240Sjfv case e1000_fc_none: 1169169240Sjfv /* Flow control completely disabled by a software over-ride. */ 1170169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1171169240Sjfv break; 1172169240Sjfv case e1000_fc_rx_pause: 1173173788Sjfv /* 1174173788Sjfv * Rx Flow control is enabled and Tx Flow control is disabled 1175169240Sjfv * by a software over-ride. Since there really isn't a way to 1176173788Sjfv * advertise that we are capable of Rx Pause ONLY, we will 1177203049Sjfv * advertise that we support both symmetric and asymmetric Rx 1178169240Sjfv * PAUSE. Later, we will disable the adapter's ability to send 1179169240Sjfv * PAUSE frames. 1180169240Sjfv */ 1181169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1182169240Sjfv break; 1183169240Sjfv case e1000_fc_tx_pause: 1184173788Sjfv /* 1185173788Sjfv * Tx Flow control is enabled, and Rx Flow control is disabled, 1186169240Sjfv * by a software over-ride. 1187169240Sjfv */ 1188169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1189169240Sjfv break; 1190169240Sjfv case e1000_fc_full: 1191173788Sjfv /* 1192173788Sjfv * Flow control (both Rx and Tx) is enabled by a software 1193169240Sjfv * over-ride. 1194169240Sjfv */ 1195169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1196169240Sjfv break; 1197169240Sjfv default: 1198169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1199169240Sjfv ret_val = -E1000_ERR_CONFIG; 1200169240Sjfv goto out; 1201169240Sjfv break; 1202169240Sjfv } 1203169240Sjfv 1204169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1205169240Sjfv mac->txcw = txcw; 1206169240Sjfv 1207169240Sjfvout: 1208169240Sjfv return ret_val; 1209169240Sjfv} 1210169240Sjfv 1211169240Sjfv/** 1212169240Sjfv * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1213169589Sjfv * @hw: pointer to the HW structure 1214169240Sjfv * 1215169240Sjfv * Sets the flow control high/low threshold (watermark) registers. If 1216169240Sjfv * flow control XON frame transmission is enabled, then set XON frame 1217176667Sjfv * transmission as well. 1218169240Sjfv **/ 1219173788Sjfvs32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1220169240Sjfv{ 1221169240Sjfv u32 fcrtl = 0, fcrth = 0; 1222169240Sjfv 1223169240Sjfv DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1224169240Sjfv 1225173788Sjfv /* 1226173788Sjfv * Set the flow control receive threshold registers. Normally, 1227169240Sjfv * these registers will be set to a default threshold that may be 1228169240Sjfv * adjusted later by the driver's runtime code. However, if the 1229169240Sjfv * ability to transmit pause frames is not enabled, then these 1230169240Sjfv * registers will be set to 0. 1231169240Sjfv */ 1232185353Sjfv if (hw->fc.current_mode & e1000_fc_tx_pause) { 1233173788Sjfv /* 1234173788Sjfv * We need to set up the Receive Threshold high and low water 1235169240Sjfv * marks as well as (optionally) enabling the transmission of 1236169240Sjfv * XON frames. 1237169240Sjfv */ 1238173788Sjfv fcrtl = hw->fc.low_water; 1239173788Sjfv if (hw->fc.send_xon) 1240169240Sjfv fcrtl |= E1000_FCRTL_XONE; 1241169240Sjfv 1242173788Sjfv fcrth = hw->fc.high_water; 1243169240Sjfv } 1244169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1245169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1246169240Sjfv 1247203049Sjfv return E1000_SUCCESS; 1248169240Sjfv} 1249169240Sjfv 1250169240Sjfv/** 1251169240Sjfv * e1000_set_default_fc_generic - Set flow control default values 1252169589Sjfv * @hw: pointer to the HW structure 1253169240Sjfv * 1254169240Sjfv * Read the EEPROM for the default values for flow control and store the 1255169240Sjfv * values. 1256169240Sjfv **/ 1257173788Sjfvs32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1258169240Sjfv{ 1259169240Sjfv s32 ret_val = E1000_SUCCESS; 1260169240Sjfv u16 nvm_data; 1261169240Sjfv 1262169240Sjfv DEBUGFUNC("e1000_set_default_fc_generic"); 1263169240Sjfv 1264173788Sjfv /* 1265173788Sjfv * Read and store word 0x0F of the EEPROM. This word contains bits 1266169240Sjfv * that determine the hardware's default PAUSE (flow control) mode, 1267169240Sjfv * a bit that determines whether the HW defaults to enabling or 1268169240Sjfv * disabling auto-negotiation, and the direction of the 1269169240Sjfv * SW defined pins. If there is no SW over-ride of the flow 1270169240Sjfv * control setting, then the variable hw->fc will 1271169240Sjfv * be initialized based on a value in the EEPROM. 1272169240Sjfv */ 1273177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1274169240Sjfv 1275169240Sjfv if (ret_val) { 1276169240Sjfv DEBUGOUT("NVM Read Error\n"); 1277169240Sjfv goto out; 1278169240Sjfv } 1279169240Sjfv 1280169240Sjfv if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1281185353Sjfv hw->fc.requested_mode = e1000_fc_none; 1282169240Sjfv else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1283169240Sjfv NVM_WORD0F_ASM_DIR) 1284185353Sjfv hw->fc.requested_mode = e1000_fc_tx_pause; 1285169240Sjfv else 1286185353Sjfv hw->fc.requested_mode = e1000_fc_full; 1287169240Sjfv 1288169240Sjfvout: 1289169240Sjfv return ret_val; 1290169240Sjfv} 1291169240Sjfv 1292169240Sjfv/** 1293169240Sjfv * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1294169589Sjfv * @hw: pointer to the HW structure 1295169240Sjfv * 1296169240Sjfv * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1297169240Sjfv * device control register to reflect the adapter settings. TFCE and RFCE 1298169240Sjfv * need to be explicitly set by software when a copper PHY is used because 1299169240Sjfv * autonegotiation is managed by the PHY rather than the MAC. Software must 1300169240Sjfv * also configure these bits when link is forced on a fiber connection. 1301169240Sjfv **/ 1302173788Sjfvs32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1303169240Sjfv{ 1304169240Sjfv u32 ctrl; 1305169240Sjfv s32 ret_val = E1000_SUCCESS; 1306169240Sjfv 1307169240Sjfv DEBUGFUNC("e1000_force_mac_fc_generic"); 1308169240Sjfv 1309169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1310169240Sjfv 1311173788Sjfv /* 1312173788Sjfv * Because we didn't get link via the internal auto-negotiation 1313169240Sjfv * mechanism (we either forced link or we got link via PHY 1314169240Sjfv * auto-neg), we have to manually enable/disable transmit an 1315169240Sjfv * receive flow control. 1316169240Sjfv * 1317169240Sjfv * The "Case" statement below enables/disable flow control 1318185353Sjfv * according to the "hw->fc.current_mode" parameter. 1319169240Sjfv * 1320169240Sjfv * The possible values of the "fc" parameter are: 1321169240Sjfv * 0: Flow control is completely disabled 1322169240Sjfv * 1: Rx flow control is enabled (we can receive pause 1323169240Sjfv * frames but not send pause frames). 1324169240Sjfv * 2: Tx flow control is enabled (we can send pause frames 1325169240Sjfv * frames but we do not receive pause frames). 1326173788Sjfv * 3: Both Rx and Tx flow control (symmetric) is enabled. 1327169240Sjfv * other: No other values should be possible at this point. 1328169240Sjfv */ 1329185353Sjfv DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1330169240Sjfv 1331185353Sjfv switch (hw->fc.current_mode) { 1332169240Sjfv case e1000_fc_none: 1333169240Sjfv ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1334169240Sjfv break; 1335169240Sjfv case e1000_fc_rx_pause: 1336169240Sjfv ctrl &= (~E1000_CTRL_TFCE); 1337169240Sjfv ctrl |= E1000_CTRL_RFCE; 1338169240Sjfv break; 1339169240Sjfv case e1000_fc_tx_pause: 1340169240Sjfv ctrl &= (~E1000_CTRL_RFCE); 1341169240Sjfv ctrl |= E1000_CTRL_TFCE; 1342169240Sjfv break; 1343169240Sjfv case e1000_fc_full: 1344169240Sjfv ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1345169240Sjfv break; 1346169240Sjfv default: 1347169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1348169240Sjfv ret_val = -E1000_ERR_CONFIG; 1349169240Sjfv goto out; 1350169240Sjfv } 1351169240Sjfv 1352169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1353169240Sjfv 1354169240Sjfvout: 1355169240Sjfv return ret_val; 1356169240Sjfv} 1357169240Sjfv 1358169240Sjfv/** 1359169240Sjfv * e1000_config_fc_after_link_up_generic - Configures flow control after link 1360169589Sjfv * @hw: pointer to the HW structure 1361169240Sjfv * 1362169240Sjfv * Checks the status of auto-negotiation after link up to ensure that the 1363169240Sjfv * speed and duplex were not forced. If the link needed to be forced, then 1364169240Sjfv * flow control needs to be forced also. If auto-negotiation is enabled 1365169240Sjfv * and did not fail, then we configure flow control based on our link 1366169240Sjfv * partner. 1367169240Sjfv **/ 1368173788Sjfvs32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1369169240Sjfv{ 1370169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1371169240Sjfv s32 ret_val = E1000_SUCCESS; 1372169240Sjfv u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1373169240Sjfv u16 speed, duplex; 1374169240Sjfv 1375169240Sjfv DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1376169240Sjfv 1377173788Sjfv /* 1378173788Sjfv * Check for the case where we have fiber media and auto-neg failed 1379169240Sjfv * so we had to force link. In this case, we need to force the 1380169240Sjfv * configuration of the MAC to match the "fc" parameter. 1381169240Sjfv */ 1382169240Sjfv if (mac->autoneg_failed) { 1383173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber || 1384173788Sjfv hw->phy.media_type == e1000_media_type_internal_serdes) 1385169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1386169240Sjfv } else { 1387173788Sjfv if (hw->phy.media_type == e1000_media_type_copper) 1388169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1389169240Sjfv } 1390169240Sjfv 1391169240Sjfv if (ret_val) { 1392169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1393169240Sjfv goto out; 1394169240Sjfv } 1395169240Sjfv 1396173788Sjfv /* 1397173788Sjfv * Check for the case where we have copper media and auto-neg is 1398169240Sjfv * enabled. In this case, we need to check and see if Auto-Neg 1399169240Sjfv * has completed, and if so, how the PHY and link partner has 1400169240Sjfv * flow control configured. 1401169240Sjfv */ 1402173788Sjfv if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1403173788Sjfv /* 1404173788Sjfv * Read the MII Status Register and check to see if AutoNeg 1405169240Sjfv * has completed. We read this twice because this reg has 1406169240Sjfv * some "sticky" (latched) bits. 1407169240Sjfv */ 1408185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1409169240Sjfv if (ret_val) 1410169240Sjfv goto out; 1411185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1412169240Sjfv if (ret_val) 1413169240Sjfv goto out; 1414169240Sjfv 1415169240Sjfv if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1416169240Sjfv DEBUGOUT("Copper PHY and Auto Neg " 1417169240Sjfv "has not completed.\n"); 1418169240Sjfv goto out; 1419169240Sjfv } 1420169240Sjfv 1421173788Sjfv /* 1422173788Sjfv * The AutoNeg process has completed, so we now need to 1423169240Sjfv * read both the Auto Negotiation Advertisement 1424169240Sjfv * Register (Address 4) and the Auto_Negotiation Base 1425169240Sjfv * Page Ability Register (Address 5) to determine how 1426169240Sjfv * flow control was negotiated. 1427169240Sjfv */ 1428185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1429176667Sjfv &mii_nway_adv_reg); 1430169240Sjfv if (ret_val) 1431169240Sjfv goto out; 1432185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1433176667Sjfv &mii_nway_lp_ability_reg); 1434169240Sjfv if (ret_val) 1435169240Sjfv goto out; 1436169240Sjfv 1437173788Sjfv /* 1438173788Sjfv * Two bits in the Auto Negotiation Advertisement Register 1439169240Sjfv * (Address 4) and two bits in the Auto Negotiation Base 1440169240Sjfv * Page Ability Register (Address 5) determine flow control 1441169240Sjfv * for both the PHY and the link partner. The following 1442169240Sjfv * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1443169240Sjfv * 1999, describes these PAUSE resolution bits and how flow 1444169240Sjfv * control is determined based upon these settings. 1445169240Sjfv * NOTE: DC = Don't Care 1446169240Sjfv * 1447169240Sjfv * LOCAL DEVICE | LINK PARTNER 1448169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1449169240Sjfv *-------|---------|-------|---------|-------------------- 1450169240Sjfv * 0 | 0 | DC | DC | e1000_fc_none 1451169240Sjfv * 0 | 1 | 0 | DC | e1000_fc_none 1452169240Sjfv * 0 | 1 | 1 | 0 | e1000_fc_none 1453169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1454169240Sjfv * 1 | 0 | 0 | DC | e1000_fc_none 1455169240Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1456169240Sjfv * 1 | 1 | 0 | 0 | e1000_fc_none 1457169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1458169240Sjfv * 1459173788Sjfv * Are both PAUSE bits set to 1? If so, this implies 1460169240Sjfv * Symmetric Flow Control is enabled at both ends. The 1461169240Sjfv * ASM_DIR bits are irrelevant per the spec. 1462169240Sjfv * 1463169240Sjfv * For Symmetric Flow Control: 1464169240Sjfv * 1465169240Sjfv * LOCAL DEVICE | LINK PARTNER 1466169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1467169240Sjfv *-------|---------|-------|---------|-------------------- 1468169240Sjfv * 1 | DC | 1 | DC | E1000_fc_full 1469169240Sjfv * 1470169240Sjfv */ 1471169240Sjfv if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1472169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1473173788Sjfv /* 1474173788Sjfv * Now we need to check if the user selected Rx ONLY 1475169240Sjfv * of pause frames. In this case, we had to advertise 1476200243Sjfv * FULL flow control because we could not advertise Rx 1477169240Sjfv * ONLY. Hence, we must now check to see if we need to 1478169240Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 1479169240Sjfv */ 1480185353Sjfv if (hw->fc.requested_mode == e1000_fc_full) { 1481185353Sjfv hw->fc.current_mode = e1000_fc_full; 1482169240Sjfv DEBUGOUT("Flow Control = FULL.\r\n"); 1483169240Sjfv } else { 1484185353Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1485169240Sjfv DEBUGOUT("Flow Control = " 1486203049Sjfv "Rx PAUSE frames only.\r\n"); 1487169240Sjfv } 1488169240Sjfv } 1489173788Sjfv /* 1490173788Sjfv * For receiving PAUSE frames ONLY. 1491169240Sjfv * 1492169240Sjfv * LOCAL DEVICE | LINK PARTNER 1493169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1494169240Sjfv *-------|---------|-------|---------|-------------------- 1495169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1496169240Sjfv */ 1497169240Sjfv else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1498169240Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1499169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1500169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1501185353Sjfv hw->fc.current_mode = e1000_fc_tx_pause; 1502203049Sjfv DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); 1503169240Sjfv } 1504173788Sjfv /* 1505173788Sjfv * For transmitting PAUSE frames ONLY. 1506169240Sjfv * 1507169240Sjfv * LOCAL DEVICE | LINK PARTNER 1508169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1509169240Sjfv *-------|---------|-------|---------|-------------------- 1510169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1511169240Sjfv */ 1512169240Sjfv else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1513169240Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1514169240Sjfv !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1515169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1516185353Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1517203049Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); 1518173788Sjfv } else { 1519173788Sjfv /* 1520173788Sjfv * Per the IEEE spec, at this point flow control 1521173788Sjfv * should be disabled. 1522173788Sjfv */ 1523185353Sjfv hw->fc.current_mode = e1000_fc_none; 1524169240Sjfv DEBUGOUT("Flow Control = NONE.\r\n"); 1525169240Sjfv } 1526169240Sjfv 1527173788Sjfv /* 1528173788Sjfv * Now we need to do one last check... If we auto- 1529169240Sjfv * negotiated to HALF DUPLEX, flow control should not be 1530169240Sjfv * enabled per IEEE 802.3 spec. 1531169240Sjfv */ 1532177867Sjfv ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1533169240Sjfv if (ret_val) { 1534169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1535169240Sjfv goto out; 1536169240Sjfv } 1537169240Sjfv 1538169240Sjfv if (duplex == HALF_DUPLEX) 1539185353Sjfv hw->fc.current_mode = e1000_fc_none; 1540169240Sjfv 1541173788Sjfv /* 1542173788Sjfv * Now we call a subroutine to actually force the MAC 1543169240Sjfv * controller to use the correct flow control settings. 1544169240Sjfv */ 1545169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1546169240Sjfv if (ret_val) { 1547169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1548169240Sjfv goto out; 1549169240Sjfv } 1550169240Sjfv } 1551169240Sjfv 1552169240Sjfvout: 1553169240Sjfv return ret_val; 1554169240Sjfv} 1555169240Sjfv 1556169240Sjfv/** 1557176667Sjfv * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1558169589Sjfv * @hw: pointer to the HW structure 1559169589Sjfv * @speed: stores the current speed 1560169589Sjfv * @duplex: stores the current duplex 1561169240Sjfv * 1562169240Sjfv * Read the status register for the current speed/duplex and store the current 1563169240Sjfv * speed and duplex for copper connections. 1564169240Sjfv **/ 1565173788Sjfvs32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1566173788Sjfv u16 *duplex) 1567169240Sjfv{ 1568169240Sjfv u32 status; 1569169240Sjfv 1570169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1571169240Sjfv 1572169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1573169240Sjfv if (status & E1000_STATUS_SPEED_1000) { 1574169240Sjfv *speed = SPEED_1000; 1575169240Sjfv DEBUGOUT("1000 Mbs, "); 1576169240Sjfv } else if (status & E1000_STATUS_SPEED_100) { 1577169240Sjfv *speed = SPEED_100; 1578169240Sjfv DEBUGOUT("100 Mbs, "); 1579169240Sjfv } else { 1580169240Sjfv *speed = SPEED_10; 1581169240Sjfv DEBUGOUT("10 Mbs, "); 1582169240Sjfv } 1583169240Sjfv 1584169240Sjfv if (status & E1000_STATUS_FD) { 1585169240Sjfv *duplex = FULL_DUPLEX; 1586169240Sjfv DEBUGOUT("Full Duplex\n"); 1587169240Sjfv } else { 1588169240Sjfv *duplex = HALF_DUPLEX; 1589169240Sjfv DEBUGOUT("Half Duplex\n"); 1590169240Sjfv } 1591169240Sjfv 1592169240Sjfv return E1000_SUCCESS; 1593169240Sjfv} 1594169240Sjfv 1595169240Sjfv/** 1596176667Sjfv * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1597169589Sjfv * @hw: pointer to the HW structure 1598169589Sjfv * @speed: stores the current speed 1599169589Sjfv * @duplex: stores the current duplex 1600169240Sjfv * 1601169240Sjfv * Sets the speed and duplex to gigabit full duplex (the only possible option) 1602169240Sjfv * for fiber/serdes links. 1603169240Sjfv **/ 1604173788Sjfvs32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1605173788Sjfv u16 *speed, u16 *duplex) 1606169240Sjfv{ 1607169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1608169240Sjfv 1609169240Sjfv *speed = SPEED_1000; 1610169240Sjfv *duplex = FULL_DUPLEX; 1611169240Sjfv 1612169240Sjfv return E1000_SUCCESS; 1613169240Sjfv} 1614169240Sjfv 1615169240Sjfv/** 1616169240Sjfv * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1617169589Sjfv * @hw: pointer to the HW structure 1618169240Sjfv * 1619169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 1620169240Sjfv **/ 1621173788Sjfvs32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1622169240Sjfv{ 1623169240Sjfv u32 swsm; 1624169240Sjfv s32 ret_val = E1000_SUCCESS; 1625169240Sjfv s32 timeout = hw->nvm.word_size + 1; 1626169240Sjfv s32 i = 0; 1627169240Sjfv 1628169240Sjfv DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1629169240Sjfv 1630169589Sjfv /* Get the SW semaphore */ 1631169589Sjfv while (i < timeout) { 1632169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1633169589Sjfv if (!(swsm & E1000_SWSM_SMBI)) 1634169589Sjfv break; 1635169589Sjfv 1636169589Sjfv usec_delay(50); 1637169589Sjfv i++; 1638169589Sjfv } 1639169589Sjfv 1640169589Sjfv if (i == timeout) { 1641169589Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1642169589Sjfv ret_val = -E1000_ERR_NVM; 1643169589Sjfv goto out; 1644169589Sjfv } 1645169589Sjfv 1646169240Sjfv /* Get the FW semaphore. */ 1647169240Sjfv for (i = 0; i < timeout; i++) { 1648169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1649169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1650169240Sjfv 1651169240Sjfv /* Semaphore acquired if bit latched */ 1652169240Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1653169240Sjfv break; 1654169240Sjfv 1655169240Sjfv usec_delay(50); 1656169240Sjfv } 1657169240Sjfv 1658169240Sjfv if (i == timeout) { 1659169240Sjfv /* Release semaphores */ 1660169240Sjfv e1000_put_hw_semaphore_generic(hw); 1661169240Sjfv DEBUGOUT("Driver can't access the NVM\n"); 1662169240Sjfv ret_val = -E1000_ERR_NVM; 1663169240Sjfv goto out; 1664169240Sjfv } 1665169240Sjfv 1666169240Sjfvout: 1667169240Sjfv return ret_val; 1668169240Sjfv} 1669169240Sjfv 1670169240Sjfv/** 1671169240Sjfv * e1000_put_hw_semaphore_generic - Release hardware semaphore 1672169589Sjfv * @hw: pointer to the HW structure 1673169240Sjfv * 1674169589Sjfv * Release hardware semaphore used to access the PHY or NVM 1675169240Sjfv **/ 1676173788Sjfvvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1677169240Sjfv{ 1678169240Sjfv u32 swsm; 1679169240Sjfv 1680169240Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1681169240Sjfv 1682169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1683169240Sjfv 1684169589Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1685169240Sjfv 1686169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1687169240Sjfv} 1688169240Sjfv 1689169240Sjfv/** 1690169240Sjfv * e1000_get_auto_rd_done_generic - Check for auto read completion 1691169589Sjfv * @hw: pointer to the HW structure 1692169240Sjfv * 1693169240Sjfv * Check EEPROM for Auto Read done bit. 1694169240Sjfv **/ 1695173788Sjfvs32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1696169240Sjfv{ 1697169240Sjfv s32 i = 0; 1698169240Sjfv s32 ret_val = E1000_SUCCESS; 1699169240Sjfv 1700169240Sjfv DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1701169240Sjfv 1702169240Sjfv while (i < AUTO_READ_DONE_TIMEOUT) { 1703169240Sjfv if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1704169240Sjfv break; 1705169240Sjfv msec_delay(1); 1706169240Sjfv i++; 1707169240Sjfv } 1708169240Sjfv 1709169240Sjfv if (i == AUTO_READ_DONE_TIMEOUT) { 1710169240Sjfv DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1711169240Sjfv ret_val = -E1000_ERR_RESET; 1712169240Sjfv goto out; 1713169240Sjfv } 1714169240Sjfv 1715169240Sjfvout: 1716169240Sjfv return ret_val; 1717169240Sjfv} 1718169240Sjfv 1719169240Sjfv/** 1720169240Sjfv * e1000_valid_led_default_generic - Verify a valid default LED config 1721169589Sjfv * @hw: pointer to the HW structure 1722169589Sjfv * @data: pointer to the NVM (EEPROM) 1723169240Sjfv * 1724169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1725169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1726169240Sjfv **/ 1727173788Sjfvs32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1728169240Sjfv{ 1729169240Sjfv s32 ret_val; 1730169240Sjfv 1731169240Sjfv DEBUGFUNC("e1000_valid_led_default_generic"); 1732169240Sjfv 1733177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1734169240Sjfv if (ret_val) { 1735169240Sjfv DEBUGOUT("NVM Read Error\n"); 1736169240Sjfv goto out; 1737169240Sjfv } 1738169240Sjfv 1739169240Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1740169240Sjfv *data = ID_LED_DEFAULT; 1741169240Sjfv 1742169240Sjfvout: 1743169240Sjfv return ret_val; 1744169240Sjfv} 1745169240Sjfv 1746169240Sjfv/** 1747169240Sjfv * e1000_id_led_init_generic - 1748169589Sjfv * @hw: pointer to the HW structure 1749169240Sjfv * 1750169240Sjfv **/ 1751185353Sjfvs32 e1000_id_led_init_generic(struct e1000_hw *hw) 1752169240Sjfv{ 1753169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1754169240Sjfv s32 ret_val; 1755169240Sjfv const u32 ledctl_mask = 0x000000FF; 1756169240Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1757169240Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1758169240Sjfv u16 data, i, temp; 1759169240Sjfv const u16 led_mask = 0x0F; 1760169240Sjfv 1761169240Sjfv DEBUGFUNC("e1000_id_led_init_generic"); 1762169240Sjfv 1763177867Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1764169240Sjfv if (ret_val) 1765169240Sjfv goto out; 1766169240Sjfv 1767169240Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1768169240Sjfv mac->ledctl_mode1 = mac->ledctl_default; 1769169240Sjfv mac->ledctl_mode2 = mac->ledctl_default; 1770169240Sjfv 1771169240Sjfv for (i = 0; i < 4; i++) { 1772169240Sjfv temp = (data >> (i << 2)) & led_mask; 1773169240Sjfv switch (temp) { 1774169240Sjfv case ID_LED_ON1_DEF2: 1775169240Sjfv case ID_LED_ON1_ON2: 1776169240Sjfv case ID_LED_ON1_OFF2: 1777169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1778169240Sjfv mac->ledctl_mode1 |= ledctl_on << (i << 3); 1779169240Sjfv break; 1780169240Sjfv case ID_LED_OFF1_DEF2: 1781169240Sjfv case ID_LED_OFF1_ON2: 1782169240Sjfv case ID_LED_OFF1_OFF2: 1783169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1784169240Sjfv mac->ledctl_mode1 |= ledctl_off << (i << 3); 1785169240Sjfv break; 1786169240Sjfv default: 1787169240Sjfv /* Do nothing */ 1788169240Sjfv break; 1789169240Sjfv } 1790169240Sjfv switch (temp) { 1791169240Sjfv case ID_LED_DEF1_ON2: 1792169240Sjfv case ID_LED_ON1_ON2: 1793169240Sjfv case ID_LED_OFF1_ON2: 1794169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1795169240Sjfv mac->ledctl_mode2 |= ledctl_on << (i << 3); 1796169240Sjfv break; 1797169240Sjfv case ID_LED_DEF1_OFF2: 1798169240Sjfv case ID_LED_ON1_OFF2: 1799169240Sjfv case ID_LED_OFF1_OFF2: 1800169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1801169240Sjfv mac->ledctl_mode2 |= ledctl_off << (i << 3); 1802169240Sjfv break; 1803169240Sjfv default: 1804169240Sjfv /* Do nothing */ 1805169240Sjfv break; 1806169240Sjfv } 1807169240Sjfv } 1808169240Sjfv 1809169240Sjfvout: 1810169240Sjfv return ret_val; 1811169240Sjfv} 1812169240Sjfv 1813169240Sjfv/** 1814169240Sjfv * e1000_setup_led_generic - Configures SW controllable LED 1815169589Sjfv * @hw: pointer to the HW structure 1816169240Sjfv * 1817169240Sjfv * This prepares the SW controllable LED for use and saves the current state 1818169240Sjfv * of the LED so it can be later restored. 1819169240Sjfv **/ 1820173788Sjfvs32 e1000_setup_led_generic(struct e1000_hw *hw) 1821169240Sjfv{ 1822169240Sjfv u32 ledctl; 1823169240Sjfv s32 ret_val = E1000_SUCCESS; 1824169240Sjfv 1825169240Sjfv DEBUGFUNC("e1000_setup_led_generic"); 1826169240Sjfv 1827177867Sjfv if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1828169240Sjfv ret_val = -E1000_ERR_CONFIG; 1829169240Sjfv goto out; 1830169240Sjfv } 1831169240Sjfv 1832173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1833169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1834169240Sjfv hw->mac.ledctl_default = ledctl; 1835169240Sjfv /* Turn off LED0 */ 1836169240Sjfv ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1837169240Sjfv E1000_LEDCTL_LED0_BLINK | 1838169240Sjfv E1000_LEDCTL_LED0_MODE_MASK); 1839169240Sjfv ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1840169240Sjfv E1000_LEDCTL_LED0_MODE_SHIFT); 1841169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1842173788Sjfv } else if (hw->phy.media_type == e1000_media_type_copper) { 1843169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1844169240Sjfv } 1845169240Sjfv 1846169240Sjfvout: 1847169240Sjfv return ret_val; 1848169240Sjfv} 1849169240Sjfv 1850169240Sjfv/** 1851169240Sjfv * e1000_cleanup_led_generic - Set LED config to default operation 1852169589Sjfv * @hw: pointer to the HW structure 1853169240Sjfv * 1854169240Sjfv * Remove the current LED configuration and set the LED configuration 1855169240Sjfv * to the default value, saved from the EEPROM. 1856169240Sjfv **/ 1857173788Sjfvs32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1858169240Sjfv{ 1859169240Sjfv DEBUGFUNC("e1000_cleanup_led_generic"); 1860169240Sjfv 1861169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1862203049Sjfv return E1000_SUCCESS; 1863169240Sjfv} 1864169240Sjfv 1865169240Sjfv/** 1866169240Sjfv * e1000_blink_led_generic - Blink LED 1867169589Sjfv * @hw: pointer to the HW structure 1868169240Sjfv * 1869176667Sjfv * Blink the LEDs which are set to be on. 1870169240Sjfv **/ 1871173788Sjfvs32 e1000_blink_led_generic(struct e1000_hw *hw) 1872169240Sjfv{ 1873169240Sjfv u32 ledctl_blink = 0; 1874169240Sjfv u32 i; 1875169240Sjfv 1876169240Sjfv DEBUGFUNC("e1000_blink_led_generic"); 1877169240Sjfv 1878173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1879169240Sjfv /* always blink LED0 for PCI-E fiber */ 1880169240Sjfv ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1881169240Sjfv (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1882169240Sjfv } else { 1883173788Sjfv /* 1884173788Sjfv * set the blink bit for each LED that's "on" (0x0E) 1885173788Sjfv * in ledctl_mode2 1886173788Sjfv */ 1887169240Sjfv ledctl_blink = hw->mac.ledctl_mode2; 1888169240Sjfv for (i = 0; i < 4; i++) 1889169240Sjfv if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1890169240Sjfv E1000_LEDCTL_MODE_LED_ON) 1891169240Sjfv ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1892169240Sjfv (i * 8)); 1893169240Sjfv } 1894169240Sjfv 1895169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1896169240Sjfv 1897169240Sjfv return E1000_SUCCESS; 1898169240Sjfv} 1899169240Sjfv 1900169240Sjfv/** 1901169240Sjfv * e1000_led_on_generic - Turn LED on 1902169589Sjfv * @hw: pointer to the HW structure 1903169240Sjfv * 1904169240Sjfv * Turn LED on. 1905169240Sjfv **/ 1906173788Sjfvs32 e1000_led_on_generic(struct e1000_hw *hw) 1907169240Sjfv{ 1908169240Sjfv u32 ctrl; 1909169240Sjfv 1910169240Sjfv DEBUGFUNC("e1000_led_on_generic"); 1911169240Sjfv 1912173788Sjfv switch (hw->phy.media_type) { 1913169240Sjfv case e1000_media_type_fiber: 1914169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1915169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1916169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1917169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1918169240Sjfv break; 1919169240Sjfv case e1000_media_type_copper: 1920169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1921169240Sjfv break; 1922169240Sjfv default: 1923169240Sjfv break; 1924169240Sjfv } 1925169240Sjfv 1926169240Sjfv return E1000_SUCCESS; 1927169240Sjfv} 1928169240Sjfv 1929169240Sjfv/** 1930169240Sjfv * e1000_led_off_generic - Turn LED off 1931169589Sjfv * @hw: pointer to the HW structure 1932169240Sjfv * 1933169240Sjfv * Turn LED off. 1934169240Sjfv **/ 1935173788Sjfvs32 e1000_led_off_generic(struct e1000_hw *hw) 1936169240Sjfv{ 1937169240Sjfv u32 ctrl; 1938169240Sjfv 1939169240Sjfv DEBUGFUNC("e1000_led_off_generic"); 1940169240Sjfv 1941173788Sjfv switch (hw->phy.media_type) { 1942169240Sjfv case e1000_media_type_fiber: 1943169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1944169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1945169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1946169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1947169240Sjfv break; 1948169240Sjfv case e1000_media_type_copper: 1949169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1950169240Sjfv break; 1951169240Sjfv default: 1952169240Sjfv break; 1953169240Sjfv } 1954169240Sjfv 1955169240Sjfv return E1000_SUCCESS; 1956169240Sjfv} 1957169240Sjfv 1958169240Sjfv/** 1959169240Sjfv * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1960169589Sjfv * @hw: pointer to the HW structure 1961169589Sjfv * @no_snoop: bitmap of snoop events 1962169240Sjfv * 1963169240Sjfv * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1964169240Sjfv **/ 1965173788Sjfvvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1966169240Sjfv{ 1967169240Sjfv u32 gcr; 1968169240Sjfv 1969169240Sjfv DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1970169240Sjfv 1971169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 1972169240Sjfv goto out; 1973169240Sjfv 1974169240Sjfv if (no_snoop) { 1975169240Sjfv gcr = E1000_READ_REG(hw, E1000_GCR); 1976169240Sjfv gcr &= ~(PCIE_NO_SNOOP_ALL); 1977169240Sjfv gcr |= no_snoop; 1978169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 1979169240Sjfv } 1980169240Sjfvout: 1981169240Sjfv return; 1982169240Sjfv} 1983169240Sjfv 1984169240Sjfv/** 1985169240Sjfv * e1000_disable_pcie_master_generic - Disables PCI-express master access 1986169589Sjfv * @hw: pointer to the HW structure 1987169240Sjfv * 1988200243Sjfv * Returns E1000_SUCCESS if successful, else returns -10 1989176667Sjfv * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1990169240Sjfv * the master requests to be disabled. 1991169240Sjfv * 1992169240Sjfv * Disables PCI-Express master access and verifies there are no pending 1993169240Sjfv * requests. 1994169240Sjfv **/ 1995173788Sjfvs32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1996169240Sjfv{ 1997169240Sjfv u32 ctrl; 1998169240Sjfv s32 timeout = MASTER_DISABLE_TIMEOUT; 1999169240Sjfv s32 ret_val = E1000_SUCCESS; 2000169240Sjfv 2001169240Sjfv DEBUGFUNC("e1000_disable_pcie_master_generic"); 2002169240Sjfv 2003169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 2004169240Sjfv goto out; 2005169240Sjfv 2006169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2007169240Sjfv ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2008169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2009169240Sjfv 2010169240Sjfv while (timeout) { 2011169240Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & 2012169240Sjfv E1000_STATUS_GIO_MASTER_ENABLE)) 2013169240Sjfv break; 2014169240Sjfv usec_delay(100); 2015169240Sjfv timeout--; 2016169240Sjfv } 2017169240Sjfv 2018169240Sjfv if (!timeout) { 2019169240Sjfv DEBUGOUT("Master requests are pending.\n"); 2020169240Sjfv ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2021169240Sjfv } 2022169240Sjfv 2023169240Sjfvout: 2024169240Sjfv return ret_val; 2025169240Sjfv} 2026169240Sjfv 2027169240Sjfv/** 2028169240Sjfv * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2029169589Sjfv * @hw: pointer to the HW structure 2030169240Sjfv * 2031169240Sjfv * Reset the Adaptive Interframe Spacing throttle to default values. 2032169240Sjfv **/ 2033173788Sjfvvoid e1000_reset_adaptive_generic(struct e1000_hw *hw) 2034169240Sjfv{ 2035169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2036169240Sjfv 2037169240Sjfv DEBUGFUNC("e1000_reset_adaptive_generic"); 2038169240Sjfv 2039169240Sjfv if (!mac->adaptive_ifs) { 2040169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2041169240Sjfv goto out; 2042169240Sjfv } 2043169240Sjfv 2044185353Sjfv mac->current_ifs_val = 0; 2045185353Sjfv mac->ifs_min_val = IFS_MIN; 2046185353Sjfv mac->ifs_max_val = IFS_MAX; 2047185353Sjfv mac->ifs_step_size = IFS_STEP; 2048185353Sjfv mac->ifs_ratio = IFS_RATIO; 2049169240Sjfv 2050169240Sjfv mac->in_ifs_mode = FALSE; 2051169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2052169240Sjfvout: 2053169240Sjfv return; 2054169240Sjfv} 2055169240Sjfv 2056169240Sjfv/** 2057169240Sjfv * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2058169589Sjfv * @hw: pointer to the HW structure 2059169240Sjfv * 2060169240Sjfv * Update the Adaptive Interframe Spacing Throttle value based on the 2061169240Sjfv * time between transmitted packets and time between collisions. 2062169240Sjfv **/ 2063173788Sjfvvoid e1000_update_adaptive_generic(struct e1000_hw *hw) 2064169240Sjfv{ 2065169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2066169240Sjfv 2067169240Sjfv DEBUGFUNC("e1000_update_adaptive_generic"); 2068169240Sjfv 2069169240Sjfv if (!mac->adaptive_ifs) { 2070169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2071169240Sjfv goto out; 2072169240Sjfv } 2073169240Sjfv 2074169240Sjfv if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2075169240Sjfv if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2076169240Sjfv mac->in_ifs_mode = TRUE; 2077169240Sjfv if (mac->current_ifs_val < mac->ifs_max_val) { 2078169240Sjfv if (!mac->current_ifs_val) 2079169240Sjfv mac->current_ifs_val = mac->ifs_min_val; 2080169240Sjfv else 2081169240Sjfv mac->current_ifs_val += 2082169240Sjfv mac->ifs_step_size; 2083169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2084169240Sjfv } 2085169240Sjfv } 2086169240Sjfv } else { 2087169240Sjfv if (mac->in_ifs_mode && 2088169240Sjfv (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2089169240Sjfv mac->current_ifs_val = 0; 2090169240Sjfv mac->in_ifs_mode = FALSE; 2091169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2092169240Sjfv } 2093169240Sjfv } 2094169240Sjfvout: 2095169240Sjfv return; 2096169240Sjfv} 2097169240Sjfv 2098169240Sjfv/** 2099169240Sjfv * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2100169589Sjfv * @hw: pointer to the HW structure 2101169240Sjfv * 2102176667Sjfv * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2103169240Sjfv * set, which is forced to MDI mode only. 2104169240Sjfv **/ 2105200243Sjfvstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2106169240Sjfv{ 2107169240Sjfv s32 ret_val = E1000_SUCCESS; 2108169240Sjfv 2109169240Sjfv DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2110169240Sjfv 2111169240Sjfv if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2112169240Sjfv DEBUGOUT("Invalid MDI setting detected\n"); 2113169240Sjfv hw->phy.mdix = 1; 2114169240Sjfv ret_val = -E1000_ERR_CONFIG; 2115169240Sjfv goto out; 2116169240Sjfv } 2117169240Sjfv 2118169240Sjfvout: 2119169240Sjfv return ret_val; 2120169240Sjfv} 2121169240Sjfv 2122169240Sjfv/** 2123169240Sjfv * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2124169589Sjfv * @hw: pointer to the HW structure 2125169589Sjfv * @reg: 32bit register offset such as E1000_SCTL 2126169589Sjfv * @offset: register offset to write to 2127169589Sjfv * @data: data to write at register offset 2128169240Sjfv * 2129169240Sjfv * Writes an address/data control type register. There are several of these 2130169240Sjfv * and they all have the format address << 8 | data and bit 31 is polled for 2131169240Sjfv * completion. 2132169240Sjfv **/ 2133173788Sjfvs32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2134173788Sjfv u32 offset, u8 data) 2135169240Sjfv{ 2136169240Sjfv u32 i, regvalue = 0; 2137169240Sjfv s32 ret_val = E1000_SUCCESS; 2138169240Sjfv 2139169240Sjfv DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2140169240Sjfv 2141169240Sjfv /* Set up the address and data */ 2142169240Sjfv regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2143169240Sjfv E1000_WRITE_REG(hw, reg, regvalue); 2144169240Sjfv 2145169240Sjfv /* Poll the ready bit to see if the MDI read completed */ 2146169240Sjfv for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2147169240Sjfv usec_delay(5); 2148169240Sjfv regvalue = E1000_READ_REG(hw, reg); 2149169240Sjfv if (regvalue & E1000_GEN_CTL_READY) 2150169240Sjfv break; 2151169240Sjfv } 2152169240Sjfv if (!(regvalue & E1000_GEN_CTL_READY)) { 2153169240Sjfv DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2154169240Sjfv ret_val = -E1000_ERR_PHY; 2155169240Sjfv goto out; 2156169240Sjfv } 2157169240Sjfv 2158169240Sjfvout: 2159169240Sjfv return ret_val; 2160169240Sjfv} 2161