1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42/** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49{ 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 /* VLAN, MC, etc. */ 77 mac->ops.update_mc_addr_list = e1000_null_update_mc; 78 mac->ops.clear_vfta = e1000_null_mac_generic; 79 mac->ops.write_vfta = e1000_null_write_vfta; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82} 83 84/** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89{ 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92} 93 94/** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99{ 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102} 103 104/** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110{ 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113} 114 115/** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120{ 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123} 124 125/** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131{ 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134} 135 136/** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142{ 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145} 146 147/** 148 * e1000_null_rar_set - No-op function, return 0 149 * @hw: pointer to the HW structure 150 **/ 151int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153{ 154 DEBUGFUNC("e1000_null_rar_set"); 155 return E1000_SUCCESS; 156} 157 158/** 159 * e1000_null_set_obff_timer - No-op function, return 0 160 * @hw: pointer to the HW structure 161 **/ 162s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163 u32 E1000_UNUSEDARG a) 164{ 165 DEBUGFUNC("e1000_null_set_obff_timer"); 166 return E1000_SUCCESS; 167} 168 169/** 170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171 * @hw: pointer to the HW structure 172 * 173 * Determines and stores the system bus information for a particular 174 * network interface. The following bus information is determined and stored: 175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176 **/ 177s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178{ 179 struct e1000_mac_info *mac = &hw->mac; 180 struct e1000_bus_info *bus = &hw->bus; 181 u32 status = E1000_READ_REG(hw, E1000_STATUS); 182 s32 ret_val = E1000_SUCCESS; 183 184 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185 186 /* PCI or PCI-X? */ 187 bus->type = (status & E1000_STATUS_PCIX_MODE) 188 ? e1000_bus_type_pcix 189 : e1000_bus_type_pci; 190 191 /* Bus speed */ 192 if (bus->type == e1000_bus_type_pci) { 193 bus->speed = (status & E1000_STATUS_PCI66) 194 ? e1000_bus_speed_66 195 : e1000_bus_speed_33; 196 } else { 197 switch (status & E1000_STATUS_PCIX_SPEED) { 198 case E1000_STATUS_PCIX_SPEED_66: 199 bus->speed = e1000_bus_speed_66; 200 break; 201 case E1000_STATUS_PCIX_SPEED_100: 202 bus->speed = e1000_bus_speed_100; 203 break; 204 case E1000_STATUS_PCIX_SPEED_133: 205 bus->speed = e1000_bus_speed_133; 206 break; 207 default: 208 bus->speed = e1000_bus_speed_reserved; 209 break; 210 } 211 } 212 213 /* Bus width */ 214 bus->width = (status & E1000_STATUS_BUS64) 215 ? e1000_bus_width_64 216 : e1000_bus_width_32; 217 218 /* Which PCI(-X) function? */ 219 mac->ops.set_lan_id(hw); 220 221 return ret_val; 222} 223 224/** 225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226 * @hw: pointer to the HW structure 227 * 228 * Determines and stores the system bus information for a particular 229 * network interface. The following bus information is determined and stored: 230 * bus speed, bus width, type (PCIe), and PCIe function. 231 **/ 232s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233{ 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_bus_info *bus = &hw->bus; 236 s32 ret_val; 237 u16 pcie_link_status; 238 239 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240 241 bus->type = e1000_bus_type_pci_express; 242 243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) { 246 bus->width = e1000_bus_width_unknown; 247 bus->speed = e1000_bus_speed_unknown; 248 } else { 249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250 case PCIE_LINK_SPEED_2500: 251 bus->speed = e1000_bus_speed_2500; 252 break; 253 case PCIE_LINK_SPEED_5000: 254 bus->speed = e1000_bus_speed_5000; 255 break; 256 default: 257 bus->speed = e1000_bus_speed_unknown; 258 break; 259 } 260 261 bus->width = (enum e1000_bus_width)((pcie_link_status & 262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263 } 264 265 mac->ops.set_lan_id(hw); 266 267 return E1000_SUCCESS; 268} 269 270/** 271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272 * 273 * @hw: pointer to the HW structure 274 * 275 * Determines the LAN function id by reading memory-mapped registers 276 * and swaps the port value if requested. 277 **/ 278static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279{ 280 struct e1000_bus_info *bus = &hw->bus; 281 u32 reg; 282 283 /* The status register reports the correct function number 284 * for the device regardless of function swap state. 285 */ 286 reg = E1000_READ_REG(hw, E1000_STATUS); 287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288} 289 290/** 291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292 * @hw: pointer to the HW structure 293 * 294 * Determines the LAN function id by reading PCI config space. 295 **/ 296void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297{ 298 struct e1000_bus_info *bus = &hw->bus; 299 u16 pci_header_type; 300 u32 status; 301 302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304 status = E1000_READ_REG(hw, E1000_STATUS); 305 bus->func = (status & E1000_STATUS_FUNC_MASK) 306 >> E1000_STATUS_FUNC_SHIFT; 307 } else { 308 bus->func = 0; 309 } 310} 311 312/** 313 * e1000_set_lan_id_single_port - Set LAN id for a single port device 314 * @hw: pointer to the HW structure 315 * 316 * Sets the LAN function id to zero for a single port device. 317 **/ 318void e1000_set_lan_id_single_port(struct e1000_hw *hw) 319{ 320 struct e1000_bus_info *bus = &hw->bus; 321 322 bus->func = 0; 323} 324 325/** 326 * e1000_clear_vfta_generic - Clear VLAN filter table 327 * @hw: pointer to the HW structure 328 * 329 * Clears the register array which contains the VLAN filter table by 330 * setting all the values to 0. 331 **/ 332void e1000_clear_vfta_generic(struct e1000_hw *hw) 333{ 334 u32 offset; 335 336 DEBUGFUNC("e1000_clear_vfta_generic"); 337 338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342} 343 344/** 345 * e1000_write_vfta_generic - Write value to VLAN filter table 346 * @hw: pointer to the HW structure 347 * @offset: register offset in VLAN filter table 348 * @value: register value written to VLAN filter table 349 * 350 * Writes value at the given offset in the register array which stores 351 * the VLAN filter table. 352 **/ 353void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354{ 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359} 360 361/** 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setup the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 **/ 370void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371{ 372 u32 i; 373 u8 mac_addr[ETH_ADDR_LEN] = {0}; 374 375 DEBUGFUNC("e1000_init_rx_addrs_generic"); 376 377 /* Setup the receive address */ 378 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379 380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381 382 /* Zero out the other (rar_entry_count - 1) receive addresses */ 383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384 for (i = 1; i < rar_count; i++) 385 hw->mac.ops.rar_set(hw, mac_addr, i); 386} 387 388/** 389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390 * @hw: pointer to the HW structure 391 * 392 * Checks the nvm for an alternate MAC address. An alternate MAC address 393 * can be setup by pre-boot software and must be treated like a permanent 394 * address and must override the actual permanent MAC address. If an 395 * alternate MAC address is found it is programmed into RAR0, replacing 396 * the permanent address that was installed into RAR0 by the Si on reset. 397 * This function will return SUCCESS unless it encounters an error while 398 * reading the EEPROM. 399 **/ 400s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401{ 402 u32 i; 403 s32 ret_val; 404 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405 u8 alt_mac_addr[ETH_ADDR_LEN]; 406 407 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408 409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410 if (ret_val) 411 return ret_val; 412 413 /* not supported on older hardware or 82573 */ 414 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 415 return E1000_SUCCESS; 416 417 /* Alternate MAC address is handled by the option ROM for 82580 418 * and newer. SW support not required. 419 */ 420 if (hw->mac.type >= e1000_82580) 421 return E1000_SUCCESS; 422 423 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 424 &nvm_alt_mac_addr_offset); 425 if (ret_val) { 426 DEBUGOUT("NVM Read Error\n"); 427 return ret_val; 428 } 429 430 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 431 (nvm_alt_mac_addr_offset == 0x0000)) 432 /* There is no Alternate MAC Address */ 433 return E1000_SUCCESS; 434 435 if (hw->bus.func == E1000_FUNC_1) 436 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 437 if (hw->bus.func == E1000_FUNC_2) 438 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 439 440 if (hw->bus.func == E1000_FUNC_3) 441 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 442 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 443 offset = nvm_alt_mac_addr_offset + (i >> 1); 444 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 445 if (ret_val) { 446 DEBUGOUT("NVM Read Error\n"); 447 return ret_val; 448 } 449 450 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 451 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 452 } 453 454 /* if multicast bit is set, the alternate address will not be used */ 455 if (alt_mac_addr[0] & 0x01) { 456 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 457 return E1000_SUCCESS; 458 } 459 460 /* We have a valid alternate MAC address, and we want to treat it the 461 * same as the normal permanent MAC address stored by the HW into the 462 * RAR. Do this by mapping this address into RAR0. 463 */ 464 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 465 466 return E1000_SUCCESS; 467} 468 469/** 470 * e1000_rar_set_generic - Set receive address register 471 * @hw: pointer to the HW structure 472 * @addr: pointer to the receive address 473 * @index: receive address array register 474 * 475 * Sets the receive address array register at index to the address passed 476 * in by addr. 477 **/ 478static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 479{ 480 u32 rar_low, rar_high; 481 482 DEBUGFUNC("e1000_rar_set_generic"); 483 484 /* HW expects these in little endian so we reverse the byte order 485 * from network order (big endian) to little endian 486 */ 487 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 488 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 489 490 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 491 492 /* If MAC address zero, no need to set the AV bit */ 493 if (rar_low || rar_high) 494 rar_high |= E1000_RAH_AV; 495 496 /* Some bridges will combine consecutive 32-bit writes into 497 * a single burst write, which will malfunction on some parts. 498 * The flushes avoid this. 499 */ 500 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 501 E1000_WRITE_FLUSH(hw); 502 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 503 E1000_WRITE_FLUSH(hw); 504 505 return E1000_SUCCESS; 506} 507 508/** 509 * e1000_hash_mc_addr_generic - Generate a multicast hash value 510 * @hw: pointer to the HW structure 511 * @mc_addr: pointer to a multicast address 512 * 513 * Generates a multicast address hash value which is used to determine 514 * the multicast filter table array address and new table value. 515 **/ 516u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 517{ 518 u32 hash_value, hash_mask; 519 u8 bit_shift = 0; 520 521 DEBUGFUNC("e1000_hash_mc_addr_generic"); 522 523 /* Register count multiplied by bits per register */ 524 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 525 526 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 527 * where 0xFF would still fall within the hash mask. 528 */ 529 while (hash_mask >> bit_shift != 0xFF) 530 bit_shift++; 531 532 /* The portion of the address that is used for the hash table 533 * is determined by the mc_filter_type setting. 534 * The algorithm is such that there is a total of 8 bits of shifting. 535 * The bit_shift for a mc_filter_type of 0 represents the number of 536 * left-shifts where the MSB of mc_addr[5] would still fall within 537 * the hash_mask. Case 0 does this exactly. Since there are a total 538 * of 8 bits of shifting, then mc_addr[4] will shift right the 539 * remaining number of bits. Thus 8 - bit_shift. The rest of the 540 * cases are a variation of this algorithm...essentially raising the 541 * number of bits to shift mc_addr[5] left, while still keeping the 542 * 8-bit shifting total. 543 * 544 * For example, given the following Destination MAC Address and an 545 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 546 * we can see that the bit_shift for case 0 is 4. These are the hash 547 * values resulting from each mc_filter_type... 548 * [0] [1] [2] [3] [4] [5] 549 * 01 AA 00 12 34 56 550 * LSB MSB 551 * 552 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 553 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 554 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 555 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 556 */ 557 switch (hw->mac.mc_filter_type) { 558 default: 559 case 0: 560 break; 561 case 1: 562 bit_shift += 1; 563 break; 564 case 2: 565 bit_shift += 2; 566 break; 567 case 3: 568 bit_shift += 4; 569 break; 570 } 571 572 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 573 (((u16) mc_addr[5]) << bit_shift))); 574 575 return hash_value; 576} 577 578/** 579 * e1000_update_mc_addr_list_generic - Update Multicast addresses 580 * @hw: pointer to the HW structure 581 * @mc_addr_list: array of multicast addresses to program 582 * @mc_addr_count: number of multicast addresses to program 583 * 584 * Updates entire Multicast Table Array. 585 * The caller must have a packed mc_addr_list of multicast addresses. 586 **/ 587void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 588 u8 *mc_addr_list, u32 mc_addr_count) 589{ 590 u32 hash_value, hash_bit, hash_reg; 591 int i; 592 593 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 594 595 /* clear mta_shadow */ 596 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 597 598 /* update mta_shadow from mc_addr_list */ 599 for (i = 0; (u32) i < mc_addr_count; i++) { 600 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 601 602 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 603 hash_bit = hash_value & 0x1F; 604 605 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 606 mc_addr_list += (ETH_ADDR_LEN); 607 } 608 609 /* replace the entire MTA table */ 610 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 611 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 612 E1000_WRITE_FLUSH(hw); 613} 614 615/** 616 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 617 * @hw: pointer to the HW structure 618 * 619 * In certain situations, a system BIOS may report that the PCIx maximum 620 * memory read byte count (MMRBC) value is higher than than the actual 621 * value. We check the PCIx command register with the current PCIx status 622 * register. 623 **/ 624void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 625{ 626 u16 cmd_mmrbc; 627 u16 pcix_cmd; 628 u16 pcix_stat_hi_word; 629 u16 stat_mmrbc; 630 631 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 632 633 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 634 if (hw->bus.type != e1000_bus_type_pcix) 635 return; 636 637 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 638 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 639 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 640 PCIX_COMMAND_MMRBC_SHIFT; 641 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 642 PCIX_STATUS_HI_MMRBC_SHIFT; 643 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 644 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 645 if (cmd_mmrbc > stat_mmrbc) { 646 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 647 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 648 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 649 } 650} 651 652/** 653 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 654 * @hw: pointer to the HW structure 655 * 656 * Clears the base hardware counters by reading the counter registers. 657 **/ 658void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 659{ 660 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 661 662 E1000_READ_REG(hw, E1000_CRCERRS); 663 E1000_READ_REG(hw, E1000_SYMERRS); 664 E1000_READ_REG(hw, E1000_MPC); 665 E1000_READ_REG(hw, E1000_SCC); 666 E1000_READ_REG(hw, E1000_ECOL); 667 E1000_READ_REG(hw, E1000_MCC); 668 E1000_READ_REG(hw, E1000_LATECOL); 669 E1000_READ_REG(hw, E1000_COLC); 670 E1000_READ_REG(hw, E1000_DC); 671 E1000_READ_REG(hw, E1000_SEC); 672 E1000_READ_REG(hw, E1000_RLEC); 673 E1000_READ_REG(hw, E1000_XONRXC); 674 E1000_READ_REG(hw, E1000_XONTXC); 675 E1000_READ_REG(hw, E1000_XOFFRXC); 676 E1000_READ_REG(hw, E1000_XOFFTXC); 677 E1000_READ_REG(hw, E1000_FCRUC); 678 E1000_READ_REG(hw, E1000_GPRC); 679 E1000_READ_REG(hw, E1000_BPRC); 680 E1000_READ_REG(hw, E1000_MPRC); 681 E1000_READ_REG(hw, E1000_GPTC); 682 E1000_READ_REG(hw, E1000_GORCL); 683 E1000_READ_REG(hw, E1000_GORCH); 684 E1000_READ_REG(hw, E1000_GOTCL); 685 E1000_READ_REG(hw, E1000_GOTCH); 686 E1000_READ_REG(hw, E1000_RNBC); 687 E1000_READ_REG(hw, E1000_RUC); 688 E1000_READ_REG(hw, E1000_RFC); 689 E1000_READ_REG(hw, E1000_ROC); 690 E1000_READ_REG(hw, E1000_RJC); 691 E1000_READ_REG(hw, E1000_TORL); 692 E1000_READ_REG(hw, E1000_TORH); 693 E1000_READ_REG(hw, E1000_TOTL); 694 E1000_READ_REG(hw, E1000_TOTH); 695 E1000_READ_REG(hw, E1000_TPR); 696 E1000_READ_REG(hw, E1000_TPT); 697 E1000_READ_REG(hw, E1000_MPTC); 698 E1000_READ_REG(hw, E1000_BPTC); 699} 700 701/** 702 * e1000_check_for_copper_link_generic - Check for link (Copper) 703 * @hw: pointer to the HW structure 704 * 705 * Checks to see of the link status of the hardware has changed. If a 706 * change in link status has been detected, then we read the PHY registers 707 * to get the current speed/duplex if link exists. 708 **/ 709s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 710{ 711 struct e1000_mac_info *mac = &hw->mac; 712 s32 ret_val; 713 bool link; 714 715 DEBUGFUNC("e1000_check_for_copper_link"); 716 717 /* We only want to go out to the PHY registers to see if Auto-Neg 718 * has completed and/or if our link status has changed. The 719 * get_link_status flag is set upon receiving a Link Status 720 * Change or Rx Sequence Error interrupt. 721 */ 722 if (!mac->get_link_status) 723 return E1000_SUCCESS; 724 725 /* First we want to see if the MII Status Register reports 726 * link. If so, then we want to get the current speed/duplex 727 * of the PHY. 728 */ 729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730 if (ret_val) 731 return ret_val; 732 733 if (!link) 734 return E1000_SUCCESS; /* No link detected */ 735 736 mac->get_link_status = FALSE; 737 738 /* Check if there was DownShift, must be checked 739 * immediately after link-up 740 */ 741 e1000_check_downshift_generic(hw); 742 743 /* If we are forcing speed/duplex, then we simply return since 744 * we have already determined whether we have link or not. 745 */ 746 if (!mac->autoneg) 747 return -E1000_ERR_CONFIG; 748 749 /* Auto-Neg is enabled. Auto Speed Detection takes care 750 * of MAC speed/duplex configuration. So we only need to 751 * configure Collision Distance in the MAC. 752 */ 753 mac->ops.config_collision_dist(hw); 754 755 /* Configure Flow Control now that Auto-Neg has completed. 756 * First, we need to restore the desired flow control 757 * settings because we may have had to re-autoneg with a 758 * different link partner. 759 */ 760 ret_val = e1000_config_fc_after_link_up_generic(hw); 761 if (ret_val) 762 DEBUGOUT("Error configuring flow control\n"); 763 764 return ret_val; 765} 766 767/** 768 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 769 * @hw: pointer to the HW structure 770 * 771 * Checks for link up on the hardware. If link is not up and we have 772 * a signal, then we need to force link up. 773 **/ 774s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 775{ 776 struct e1000_mac_info *mac = &hw->mac; 777 u32 rxcw; 778 u32 ctrl; 779 u32 status; 780 s32 ret_val; 781 782 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 783 784 ctrl = E1000_READ_REG(hw, E1000_CTRL); 785 status = E1000_READ_REG(hw, E1000_STATUS); 786 rxcw = E1000_READ_REG(hw, E1000_RXCW); 787 788 /* If we don't have link (auto-negotiation failed or link partner 789 * cannot auto-negotiate), the cable is plugged in (we have signal), 790 * and our link partner is not trying to auto-negotiate with us (we 791 * are receiving idles or data), we need to force link up. We also 792 * need to give auto-negotiation time to complete, in case the cable 793 * was just plugged in. The autoneg_failed flag does this. 794 */ 795 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 796 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 797 !(rxcw & E1000_RXCW_C)) { 798 if (!mac->autoneg_failed) { 799 mac->autoneg_failed = TRUE; 800 return E1000_SUCCESS; 801 } 802 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 803 804 /* Disable auto-negotiation in the TXCW register */ 805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 806 807 /* Force link-up and also force full-duplex. */ 808 ctrl = E1000_READ_REG(hw, E1000_CTRL); 809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 811 812 /* Configure Flow Control after forcing link up. */ 813 ret_val = e1000_config_fc_after_link_up_generic(hw); 814 if (ret_val) { 815 DEBUGOUT("Error configuring flow control\n"); 816 return ret_val; 817 } 818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 819 /* If we are forcing link and we are receiving /C/ ordered 820 * sets, re-enable auto-negotiation in the TXCW register 821 * and disable forced link in the Device Control register 822 * in an attempt to auto-negotiate with our link partner. 823 */ 824 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 825 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 827 828 mac->serdes_has_link = TRUE; 829 } 830 831 return E1000_SUCCESS; 832} 833 834/** 835 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 836 * @hw: pointer to the HW structure 837 * 838 * Checks for link up on the hardware. If link is not up and we have 839 * a signal, then we need to force link up. 840 **/ 841s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 842{ 843 struct e1000_mac_info *mac = &hw->mac; 844 u32 rxcw; 845 u32 ctrl; 846 u32 status; 847 s32 ret_val; 848 849 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 850 851 ctrl = E1000_READ_REG(hw, E1000_CTRL); 852 status = E1000_READ_REG(hw, E1000_STATUS); 853 rxcw = E1000_READ_REG(hw, E1000_RXCW); 854 855 /* If we don't have link (auto-negotiation failed or link partner 856 * cannot auto-negotiate), and our link partner is not trying to 857 * auto-negotiate with us (we are receiving idles or data), 858 * we need to force link up. We also need to give auto-negotiation 859 * time to complete. 860 */ 861 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 862 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 863 if (!mac->autoneg_failed) { 864 mac->autoneg_failed = TRUE; 865 return E1000_SUCCESS; 866 } 867 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 868 869 /* Disable auto-negotiation in the TXCW register */ 870 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 871 872 /* Force link-up and also force full-duplex. */ 873 ctrl = E1000_READ_REG(hw, E1000_CTRL); 874 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 876 877 /* Configure Flow Control after forcing link up. */ 878 ret_val = e1000_config_fc_after_link_up_generic(hw); 879 if (ret_val) { 880 DEBUGOUT("Error configuring flow control\n"); 881 return ret_val; 882 } 883 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 884 /* If we are forcing link and we are receiving /C/ ordered 885 * sets, re-enable auto-negotiation in the TXCW register 886 * and disable forced link in the Device Control register 887 * in an attempt to auto-negotiate with our link partner. 888 */ 889 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 890 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 891 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 892 893 mac->serdes_has_link = TRUE; 894 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 895 /* If we force link for non-auto-negotiation switch, check 896 * link status based on MAC synchronization for internal 897 * serdes media type. 898 */ 899 /* SYNCH bit and IV bit are sticky. */ 900 usec_delay(10); 901 rxcw = E1000_READ_REG(hw, E1000_RXCW); 902 if (rxcw & E1000_RXCW_SYNCH) { 903 if (!(rxcw & E1000_RXCW_IV)) { 904 mac->serdes_has_link = TRUE; 905 DEBUGOUT("SERDES: Link up - forced.\n"); 906 } 907 } else { 908 mac->serdes_has_link = FALSE; 909 DEBUGOUT("SERDES: Link down - force failed.\n"); 910 } 911 } 912 913 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 914 status = E1000_READ_REG(hw, E1000_STATUS); 915 if (status & E1000_STATUS_LU) { 916 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 917 usec_delay(10); 918 rxcw = E1000_READ_REG(hw, E1000_RXCW); 919 if (rxcw & E1000_RXCW_SYNCH) { 920 if (!(rxcw & E1000_RXCW_IV)) { 921 mac->serdes_has_link = TRUE; 922 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 923 } else { 924 mac->serdes_has_link = FALSE; 925 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 926 } 927 } else { 928 mac->serdes_has_link = FALSE; 929 DEBUGOUT("SERDES: Link down - no sync.\n"); 930 } 931 } else { 932 mac->serdes_has_link = FALSE; 933 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 934 } 935 } 936 937 return E1000_SUCCESS; 938} 939 940/** 941 * e1000_set_default_fc_generic - Set flow control default values 942 * @hw: pointer to the HW structure 943 * 944 * Read the EEPROM for the default values for flow control and store the 945 * values. 946 **/ 947s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 948{ 949 s32 ret_val; 950 u16 nvm_data; 951 u16 nvm_offset = 0; 952 953 DEBUGFUNC("e1000_set_default_fc_generic"); 954 955 /* Read and store word 0x0F of the EEPROM. This word contains bits 956 * that determine the hardware's default PAUSE (flow control) mode, 957 * a bit that determines whether the HW defaults to enabling or 958 * disabling auto-negotiation, and the direction of the 959 * SW defined pins. If there is no SW over-ride of the flow 960 * control setting, then the variable hw->fc will 961 * be initialized based on a value in the EEPROM. 962 */ 963 if (hw->mac.type == e1000_i350) { 964 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 965 ret_val = hw->nvm.ops.read(hw, 966 NVM_INIT_CONTROL2_REG + 967 nvm_offset, 968 1, &nvm_data); 969 } else { 970 ret_val = hw->nvm.ops.read(hw, 971 NVM_INIT_CONTROL2_REG, 972 1, &nvm_data); 973 } 974 975 976 if (ret_val) { 977 DEBUGOUT("NVM Read Error\n"); 978 return ret_val; 979 } 980 981 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 982 hw->fc.requested_mode = e1000_fc_none; 983 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 984 NVM_WORD0F_ASM_DIR) 985 hw->fc.requested_mode = e1000_fc_tx_pause; 986 else 987 hw->fc.requested_mode = e1000_fc_full; 988 989 return E1000_SUCCESS; 990} 991 992/** 993 * e1000_setup_link_generic - Setup flow control and link settings 994 * @hw: pointer to the HW structure 995 * 996 * Determines which flow control settings to use, then configures flow 997 * control. Calls the appropriate media-specific link configuration 998 * function. Assuming the adapter has a valid link partner, a valid link 999 * should be established. Assumes the hardware has previously been reset 1000 * and the transmitter and receiver are not enabled. 1001 **/ 1002s32 e1000_setup_link_generic(struct e1000_hw *hw) 1003{ 1004 s32 ret_val; 1005 1006 DEBUGFUNC("e1000_setup_link_generic"); 1007 1008 /* In the case of the phy reset being blocked, we already have a link. 1009 * We do not need to set it up again. 1010 */ 1011 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1012 return E1000_SUCCESS; 1013 1014 /* If requested flow control is set to default, set flow control 1015 * based on the EEPROM flow control settings. 1016 */ 1017 if (hw->fc.requested_mode == e1000_fc_default) { 1018 ret_val = e1000_set_default_fc_generic(hw); 1019 if (ret_val) 1020 return ret_val; 1021 } 1022 1023 /* Save off the requested flow control mode for use later. Depending 1024 * on the link partner's capabilities, we may or may not use this mode. 1025 */ 1026 hw->fc.current_mode = hw->fc.requested_mode; 1027 1028 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1029 hw->fc.current_mode); 1030 1031 /* Call the necessary media_type subroutine to configure the link. */ 1032 ret_val = hw->mac.ops.setup_physical_interface(hw); 1033 if (ret_val) 1034 return ret_val; 1035 1036 /* Initialize the flow control address, type, and PAUSE timer 1037 * registers to their default values. This is done even if flow 1038 * control is disabled, because it does not hurt anything to 1039 * initialize these registers. 1040 */ 1041 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1042 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1043 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1044 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1045 1046 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1047 1048 return e1000_set_fc_watermarks_generic(hw); 1049} 1050 1051/** 1052 * e1000_commit_fc_settings_generic - Configure flow control 1053 * @hw: pointer to the HW structure 1054 * 1055 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1056 * base on the flow control settings in e1000_mac_info. 1057 **/ 1058s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1059{ 1060 struct e1000_mac_info *mac = &hw->mac; 1061 u32 txcw; 1062 1063 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1064 1065 /* Check for a software override of the flow control settings, and 1066 * setup the device accordingly. If auto-negotiation is enabled, then 1067 * software will have to set the "PAUSE" bits to the correct value in 1068 * the Transmit Config Word Register (TXCW) and re-start auto- 1069 * negotiation. However, if auto-negotiation is disabled, then 1070 * software will have to manually configure the two flow control enable 1071 * bits in the CTRL register. 1072 * 1073 * The possible values of the "fc" parameter are: 1074 * 0: Flow control is completely disabled 1075 * 1: Rx flow control is enabled (we can receive pause frames, 1076 * but not send pause frames). 1077 * 2: Tx flow control is enabled (we can send pause frames but we 1078 * do not support receiving pause frames). 1079 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1080 */ 1081 switch (hw->fc.current_mode) { 1082 case e1000_fc_none: 1083 /* Flow control completely disabled by a software over-ride. */ 1084 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1085 break; 1086 case e1000_fc_rx_pause: 1087 /* Rx Flow control is enabled and Tx Flow control is disabled 1088 * by a software over-ride. Since there really isn't a way to 1089 * advertise that we are capable of Rx Pause ONLY, we will 1090 * advertise that we support both symmetric and asymmetric Rx 1091 * PAUSE. Later, we will disable the adapter's ability to send 1092 * PAUSE frames. 1093 */ 1094 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1095 break; 1096 case e1000_fc_tx_pause: 1097 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1098 * by a software over-ride. 1099 */ 1100 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1101 break; 1102 case e1000_fc_full: 1103 /* Flow control (both Rx and Tx) is enabled by a software 1104 * over-ride. 1105 */ 1106 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1107 break; 1108 default: 1109 DEBUGOUT("Flow control param set incorrectly\n"); 1110 return -E1000_ERR_CONFIG; 1111 break; 1112 } 1113 1114 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1115 mac->txcw = txcw; 1116 1117 return E1000_SUCCESS; 1118} 1119 1120/** 1121 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1122 * @hw: pointer to the HW structure 1123 * 1124 * Polls for link up by reading the status register, if link fails to come 1125 * up with auto-negotiation, then the link is forced if a signal is detected. 1126 **/ 1127s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1128{ 1129 struct e1000_mac_info *mac = &hw->mac; 1130 u32 i, status; 1131 s32 ret_val; 1132 1133 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1134 1135 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1136 * serdes media) then poll for a "Link-Up" indication in the Device 1137 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1138 * seconds (Auto-negotiation should complete in less than 500 1139 * milliseconds even if the other end is doing it in SW). 1140 */ 1141 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1142 msec_delay(10); 1143 status = E1000_READ_REG(hw, E1000_STATUS); 1144 if (status & E1000_STATUS_LU) 1145 break; 1146 } 1147 if (i == FIBER_LINK_UP_LIMIT) { 1148 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1149 mac->autoneg_failed = TRUE; 1150 /* AutoNeg failed to achieve a link, so we'll call 1151 * mac->check_for_link. This routine will force the 1152 * link up if we detect a signal. This will allow us to 1153 * communicate with non-autonegotiating link partners. 1154 */ 1155 ret_val = mac->ops.check_for_link(hw); 1156 if (ret_val) { 1157 DEBUGOUT("Error while checking for link\n"); 1158 return ret_val; 1159 } 1160 mac->autoneg_failed = FALSE; 1161 } else { 1162 mac->autoneg_failed = FALSE; 1163 DEBUGOUT("Valid Link Found\n"); 1164 } 1165 1166 return E1000_SUCCESS; 1167} 1168 1169/** 1170 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1171 * @hw: pointer to the HW structure 1172 * 1173 * Configures collision distance and flow control for fiber and serdes 1174 * links. Upon successful setup, poll for link. 1175 **/ 1176s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1177{ 1178 u32 ctrl; 1179 s32 ret_val; 1180 1181 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1182 1183 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1184 1185 /* Take the link out of reset */ 1186 ctrl &= ~E1000_CTRL_LRST; 1187 1188 hw->mac.ops.config_collision_dist(hw); 1189 1190 ret_val = e1000_commit_fc_settings_generic(hw); 1191 if (ret_val) 1192 return ret_val; 1193 1194 /* Since auto-negotiation is enabled, take the link out of reset (the 1195 * link will be in reset, because we previously reset the chip). This 1196 * will restart auto-negotiation. If auto-negotiation is successful 1197 * then the link-up status bit will be set and the flow control enable 1198 * bits (RFCE and TFCE) will be set according to their negotiated value. 1199 */ 1200 DEBUGOUT("Auto-negotiation enabled\n"); 1201 1202 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1203 E1000_WRITE_FLUSH(hw); 1204 msec_delay(1); 1205 1206 /* For these adapters, the SW definable pin 1 is set when the optics 1207 * detect a signal. If we have a signal, then poll for a "Link-Up" 1208 * indication. 1209 */ 1210 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1211 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1212 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1213 } else { 1214 DEBUGOUT("No signal detected\n"); 1215 } 1216 1217 return ret_val; 1218} 1219 1220/** 1221 * e1000_config_collision_dist_generic - Configure collision distance 1222 * @hw: pointer to the HW structure 1223 * 1224 * Configures the collision distance to the default value and is used 1225 * during link setup. 1226 **/ 1227static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1228{ 1229 u32 tctl; 1230 1231 DEBUGFUNC("e1000_config_collision_dist_generic"); 1232 1233 tctl = E1000_READ_REG(hw, E1000_TCTL); 1234 1235 tctl &= ~E1000_TCTL_COLD; 1236 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1237 1238 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1239 E1000_WRITE_FLUSH(hw); 1240} 1241 1242/** 1243 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1244 * @hw: pointer to the HW structure 1245 * 1246 * Sets the flow control high/low threshold (watermark) registers. If 1247 * flow control XON frame transmission is enabled, then set XON frame 1248 * transmission as well. 1249 **/ 1250s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1251{ 1252 u32 fcrtl = 0, fcrth = 0; 1253 1254 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1255 1256 /* Set the flow control receive threshold registers. Normally, 1257 * these registers will be set to a default threshold that may be 1258 * adjusted later by the driver's runtime code. However, if the 1259 * ability to transmit pause frames is not enabled, then these 1260 * registers will be set to 0. 1261 */ 1262 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1263 /* We need to set up the Receive Threshold high and low water 1264 * marks as well as (optionally) enabling the transmission of 1265 * XON frames. 1266 */ 1267 fcrtl = hw->fc.low_water; 1268 if (hw->fc.send_xon) 1269 fcrtl |= E1000_FCRTL_XONE; 1270 1271 fcrth = hw->fc.high_water; 1272 } 1273 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1274 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1275 1276 return E1000_SUCCESS; 1277} 1278 1279/** 1280 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1281 * @hw: pointer to the HW structure 1282 * 1283 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1284 * device control register to reflect the adapter settings. TFCE and RFCE 1285 * need to be explicitly set by software when a copper PHY is used because 1286 * autonegotiation is managed by the PHY rather than the MAC. Software must 1287 * also configure these bits when link is forced on a fiber connection. 1288 **/ 1289s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1290{ 1291 u32 ctrl; 1292 1293 DEBUGFUNC("e1000_force_mac_fc_generic"); 1294 1295 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1296 1297 /* Because we didn't get link via the internal auto-negotiation 1298 * mechanism (we either forced link or we got link via PHY 1299 * auto-neg), we have to manually enable/disable transmit an 1300 * receive flow control. 1301 * 1302 * The "Case" statement below enables/disable flow control 1303 * according to the "hw->fc.current_mode" parameter. 1304 * 1305 * The possible values of the "fc" parameter are: 1306 * 0: Flow control is completely disabled 1307 * 1: Rx flow control is enabled (we can receive pause 1308 * frames but not send pause frames). 1309 * 2: Tx flow control is enabled (we can send pause frames 1310 * frames but we do not receive pause frames). 1311 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1312 * other: No other values should be possible at this point. 1313 */ 1314 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1315 1316 switch (hw->fc.current_mode) { 1317 case e1000_fc_none: 1318 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1319 break; 1320 case e1000_fc_rx_pause: 1321 ctrl &= (~E1000_CTRL_TFCE); 1322 ctrl |= E1000_CTRL_RFCE; 1323 break; 1324 case e1000_fc_tx_pause: 1325 ctrl &= (~E1000_CTRL_RFCE); 1326 ctrl |= E1000_CTRL_TFCE; 1327 break; 1328 case e1000_fc_full: 1329 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1330 break; 1331 default: 1332 DEBUGOUT("Flow control param set incorrectly\n"); 1333 return -E1000_ERR_CONFIG; 1334 } 1335 1336 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1337 1338 return E1000_SUCCESS; 1339} 1340 1341/** 1342 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1343 * @hw: pointer to the HW structure 1344 * 1345 * Checks the status of auto-negotiation after link up to ensure that the 1346 * speed and duplex were not forced. If the link needed to be forced, then 1347 * flow control needs to be forced also. If auto-negotiation is enabled 1348 * and did not fail, then we configure flow control based on our link 1349 * partner. 1350 **/ 1351s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1352{ 1353 struct e1000_mac_info *mac = &hw->mac; 1354 s32 ret_val = E1000_SUCCESS; 1355 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1356 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1357 u16 speed, duplex; 1358 1359 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1360 1361 /* Check for the case where we have fiber media and auto-neg failed 1362 * so we had to force link. In this case, we need to force the 1363 * configuration of the MAC to match the "fc" parameter. 1364 */ 1365 if (mac->autoneg_failed) { 1366 if (hw->phy.media_type == e1000_media_type_fiber || 1367 hw->phy.media_type == e1000_media_type_internal_serdes) 1368 ret_val = e1000_force_mac_fc_generic(hw); 1369 } else { 1370 if (hw->phy.media_type == e1000_media_type_copper) 1371 ret_val = e1000_force_mac_fc_generic(hw); 1372 } 1373 1374 if (ret_val) { 1375 DEBUGOUT("Error forcing flow control settings\n"); 1376 return ret_val; 1377 } 1378 1379 /* Check for the case where we have copper media and auto-neg is 1380 * enabled. In this case, we need to check and see if Auto-Neg 1381 * has completed, and if so, how the PHY and link partner has 1382 * flow control configured. 1383 */ 1384 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1385 /* Read the MII Status Register and check to see if AutoNeg 1386 * has completed. We read this twice because this reg has 1387 * some "sticky" (latched) bits. 1388 */ 1389 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1390 if (ret_val) 1391 return ret_val; 1392 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1393 if (ret_val) 1394 return ret_val; 1395 1396 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1397 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1398 return ret_val; 1399 } 1400 1401 /* The AutoNeg process has completed, so we now need to 1402 * read both the Auto Negotiation Advertisement 1403 * Register (Address 4) and the Auto_Negotiation Base 1404 * Page Ability Register (Address 5) to determine how 1405 * flow control was negotiated. 1406 */ 1407 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1408 &mii_nway_adv_reg); 1409 if (ret_val) 1410 return ret_val; 1411 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1412 &mii_nway_lp_ability_reg); 1413 if (ret_val) 1414 return ret_val; 1415 1416 /* Two bits in the Auto Negotiation Advertisement Register 1417 * (Address 4) and two bits in the Auto Negotiation Base 1418 * Page Ability Register (Address 5) determine flow control 1419 * for both the PHY and the link partner. The following 1420 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1421 * 1999, describes these PAUSE resolution bits and how flow 1422 * control is determined based upon these settings. 1423 * NOTE: DC = Don't Care 1424 * 1425 * LOCAL DEVICE | LINK PARTNER 1426 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1427 *-------|---------|-------|---------|-------------------- 1428 * 0 | 0 | DC | DC | e1000_fc_none 1429 * 0 | 1 | 0 | DC | e1000_fc_none 1430 * 0 | 1 | 1 | 0 | e1000_fc_none 1431 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1432 * 1 | 0 | 0 | DC | e1000_fc_none 1433 * 1 | DC | 1 | DC | e1000_fc_full 1434 * 1 | 1 | 0 | 0 | e1000_fc_none 1435 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1436 * 1437 * Are both PAUSE bits set to 1? If so, this implies 1438 * Symmetric Flow Control is enabled at both ends. The 1439 * ASM_DIR bits are irrelevant per the spec. 1440 * 1441 * For Symmetric Flow Control: 1442 * 1443 * LOCAL DEVICE | LINK PARTNER 1444 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1445 *-------|---------|-------|---------|-------------------- 1446 * 1 | DC | 1 | DC | E1000_fc_full 1447 * 1448 */ 1449 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1450 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1451 /* Now we need to check if the user selected Rx ONLY 1452 * of pause frames. In this case, we had to advertise 1453 * FULL flow control because we could not advertise Rx 1454 * ONLY. Hence, we must now check to see if we need to 1455 * turn OFF the TRANSMISSION of PAUSE frames. 1456 */ 1457 if (hw->fc.requested_mode == e1000_fc_full) { 1458 hw->fc.current_mode = e1000_fc_full; 1459 DEBUGOUT("Flow Control = FULL.\n"); 1460 } else { 1461 hw->fc.current_mode = e1000_fc_rx_pause; 1462 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1463 } 1464 } 1465 /* For receiving PAUSE frames ONLY. 1466 * 1467 * LOCAL DEVICE | LINK PARTNER 1468 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1469 *-------|---------|-------|---------|-------------------- 1470 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1471 */ 1472 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1473 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1474 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1475 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1476 hw->fc.current_mode = e1000_fc_tx_pause; 1477 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1478 } 1479 /* For transmitting PAUSE frames ONLY. 1480 * 1481 * LOCAL DEVICE | LINK PARTNER 1482 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1483 *-------|---------|-------|---------|-------------------- 1484 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1485 */ 1486 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1487 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1488 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1489 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1490 hw->fc.current_mode = e1000_fc_rx_pause; 1491 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1492 } else { 1493 /* Per the IEEE spec, at this point flow control 1494 * should be disabled. 1495 */ 1496 hw->fc.current_mode = e1000_fc_none; 1497 DEBUGOUT("Flow Control = NONE.\n"); 1498 } 1499 1500 /* Now we need to do one last check... If we auto- 1501 * negotiated to HALF DUPLEX, flow control should not be 1502 * enabled per IEEE 802.3 spec. 1503 */ 1504 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1505 if (ret_val) { 1506 DEBUGOUT("Error getting link speed and duplex\n"); 1507 return ret_val; 1508 } 1509 1510 if (duplex == HALF_DUPLEX) 1511 hw->fc.current_mode = e1000_fc_none; 1512 1513 /* Now we call a subroutine to actually force the MAC 1514 * controller to use the correct flow control settings. 1515 */ 1516 ret_val = e1000_force_mac_fc_generic(hw); 1517 if (ret_val) { 1518 DEBUGOUT("Error forcing flow control settings\n"); 1519 return ret_val; 1520 } 1521 } 1522 1523 /* Check for the case where we have SerDes media and auto-neg is 1524 * enabled. In this case, we need to check and see if Auto-Neg 1525 * has completed, and if so, how the PHY and link partner has 1526 * flow control configured. 1527 */ 1528 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1529 mac->autoneg) { 1530 /* Read the PCS_LSTS and check to see if AutoNeg 1531 * has completed. 1532 */ 1533 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1534 1535 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1536 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1537 return ret_val; 1538 } 1539 1540 /* The AutoNeg process has completed, so we now need to 1541 * read both the Auto Negotiation Advertisement 1542 * Register (PCS_ANADV) and the Auto_Negotiation Base 1543 * Page Ability Register (PCS_LPAB) to determine how 1544 * flow control was negotiated. 1545 */ 1546 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1547 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1548 1549 /* Two bits in the Auto Negotiation Advertisement Register 1550 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1551 * Page Ability Register (PCS_LPAB) determine flow control 1552 * for both the PHY and the link partner. The following 1553 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1554 * 1999, describes these PAUSE resolution bits and how flow 1555 * control is determined based upon these settings. 1556 * NOTE: DC = Don't Care 1557 * 1558 * LOCAL DEVICE | LINK PARTNER 1559 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1560 *-------|---------|-------|---------|-------------------- 1561 * 0 | 0 | DC | DC | e1000_fc_none 1562 * 0 | 1 | 0 | DC | e1000_fc_none 1563 * 0 | 1 | 1 | 0 | e1000_fc_none 1564 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1565 * 1 | 0 | 0 | DC | e1000_fc_none 1566 * 1 | DC | 1 | DC | e1000_fc_full 1567 * 1 | 1 | 0 | 0 | e1000_fc_none 1568 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1569 * 1570 * Are both PAUSE bits set to 1? If so, this implies 1571 * Symmetric Flow Control is enabled at both ends. The 1572 * ASM_DIR bits are irrelevant per the spec. 1573 * 1574 * For Symmetric Flow Control: 1575 * 1576 * LOCAL DEVICE | LINK PARTNER 1577 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1578 *-------|---------|-------|---------|-------------------- 1579 * 1 | DC | 1 | DC | e1000_fc_full 1580 * 1581 */ 1582 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1583 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1584 /* Now we need to check if the user selected Rx ONLY 1585 * of pause frames. In this case, we had to advertise 1586 * FULL flow control because we could not advertise Rx 1587 * ONLY. Hence, we must now check to see if we need to 1588 * turn OFF the TRANSMISSION of PAUSE frames. 1589 */ 1590 if (hw->fc.requested_mode == e1000_fc_full) { 1591 hw->fc.current_mode = e1000_fc_full; 1592 DEBUGOUT("Flow Control = FULL.\n"); 1593 } else { 1594 hw->fc.current_mode = e1000_fc_rx_pause; 1595 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1596 } 1597 } 1598 /* For receiving PAUSE frames ONLY. 1599 * 1600 * LOCAL DEVICE | LINK PARTNER 1601 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1602 *-------|---------|-------|---------|-------------------- 1603 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1604 */ 1605 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1606 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1607 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1608 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1609 hw->fc.current_mode = e1000_fc_tx_pause; 1610 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1611 } 1612 /* For transmitting PAUSE frames ONLY. 1613 * 1614 * LOCAL DEVICE | LINK PARTNER 1615 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1616 *-------|---------|-------|---------|-------------------- 1617 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1618 */ 1619 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1620 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1621 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1622 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1623 hw->fc.current_mode = e1000_fc_rx_pause; 1624 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1625 } else { 1626 /* Per the IEEE spec, at this point flow control 1627 * should be disabled. 1628 */ 1629 hw->fc.current_mode = e1000_fc_none; 1630 DEBUGOUT("Flow Control = NONE.\n"); 1631 } 1632 1633 /* Now we call a subroutine to actually force the MAC 1634 * controller to use the correct flow control settings. 1635 */ 1636 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1637 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1638 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1639 1640 ret_val = e1000_force_mac_fc_generic(hw); 1641 if (ret_val) { 1642 DEBUGOUT("Error forcing flow control settings\n"); 1643 return ret_val; 1644 } 1645 } 1646 1647 return E1000_SUCCESS; 1648} 1649 1650/** 1651 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1652 * @hw: pointer to the HW structure 1653 * @speed: stores the current speed 1654 * @duplex: stores the current duplex 1655 * 1656 * Read the status register for the current speed/duplex and store the current 1657 * speed and duplex for copper connections. 1658 **/ 1659s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1660 u16 *duplex) 1661{ 1662 u32 status; 1663 1664 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1665 1666 status = E1000_READ_REG(hw, E1000_STATUS); 1667 if (status & E1000_STATUS_SPEED_1000) { 1668 *speed = SPEED_1000; 1669 DEBUGOUT("1000 Mbs, "); 1670 } else if (status & E1000_STATUS_SPEED_100) { 1671 *speed = SPEED_100; 1672 DEBUGOUT("100 Mbs, "); 1673 } else { 1674 *speed = SPEED_10; 1675 DEBUGOUT("10 Mbs, "); 1676 } 1677 1678 if (status & E1000_STATUS_FD) { 1679 *duplex = FULL_DUPLEX; 1680 DEBUGOUT("Full Duplex\n"); 1681 } else { 1682 *duplex = HALF_DUPLEX; 1683 DEBUGOUT("Half Duplex\n"); 1684 } 1685 1686 return E1000_SUCCESS; 1687} 1688 1689/** 1690 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1691 * @hw: pointer to the HW structure 1692 * @speed: stores the current speed 1693 * @duplex: stores the current duplex 1694 * 1695 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1696 * for fiber/serdes links. 1697 **/ 1698s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1699 u16 *speed, u16 *duplex) 1700{ 1701 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1702 1703 *speed = SPEED_1000; 1704 *duplex = FULL_DUPLEX; 1705 1706 return E1000_SUCCESS; 1707} 1708 1709/** 1710 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1711 * @hw: pointer to the HW structure 1712 * 1713 * Acquire the HW semaphore to access the PHY or NVM 1714 **/ 1715s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1716{ 1717 u32 swsm; 1718 s32 timeout = hw->nvm.word_size + 1; 1719 s32 i = 0; 1720 1721 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1722 1723 /* Get the SW semaphore */ 1724 while (i < timeout) { 1725 swsm = E1000_READ_REG(hw, E1000_SWSM); 1726 if (!(swsm & E1000_SWSM_SMBI)) 1727 break; 1728 1729 usec_delay(50); 1730 i++; 1731 } 1732 1733 if (i == timeout) { 1734 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1735 return -E1000_ERR_NVM; 1736 } 1737 1738 /* Get the FW semaphore. */ 1739 for (i = 0; i < timeout; i++) { 1740 swsm = E1000_READ_REG(hw, E1000_SWSM); 1741 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1742 1743 /* Semaphore acquired if bit latched */ 1744 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1745 break; 1746 1747 usec_delay(50); 1748 } 1749 1750 if (i == timeout) { 1751 /* Release semaphores */ 1752 e1000_put_hw_semaphore_generic(hw); 1753 DEBUGOUT("Driver can't access the NVM\n"); 1754 return -E1000_ERR_NVM; 1755 } 1756 1757 return E1000_SUCCESS; 1758} 1759 1760/** 1761 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1762 * @hw: pointer to the HW structure 1763 * 1764 * Release hardware semaphore used to access the PHY or NVM 1765 **/ 1766void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1767{ 1768 u32 swsm; 1769 1770 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1771 1772 swsm = E1000_READ_REG(hw, E1000_SWSM); 1773 1774 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1775 1776 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1777} 1778 1779/** 1780 * e1000_get_auto_rd_done_generic - Check for auto read completion 1781 * @hw: pointer to the HW structure 1782 * 1783 * Check EEPROM for Auto Read done bit. 1784 **/ 1785s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1786{ 1787 s32 i = 0; 1788 1789 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1790 1791 while (i < AUTO_READ_DONE_TIMEOUT) { 1792 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1793 break; 1794 msec_delay(1); 1795 i++; 1796 } 1797 1798 if (i == AUTO_READ_DONE_TIMEOUT) { 1799 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1800 return -E1000_ERR_RESET; 1801 } 1802 1803 return E1000_SUCCESS; 1804} 1805 1806/** 1807 * e1000_valid_led_default_generic - Verify a valid default LED config 1808 * @hw: pointer to the HW structure 1809 * @data: pointer to the NVM (EEPROM) 1810 * 1811 * Read the EEPROM for the current default LED configuration. If the 1812 * LED configuration is not valid, set to a valid LED configuration. 1813 **/ 1814s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1815{ 1816 s32 ret_val; 1817 1818 DEBUGFUNC("e1000_valid_led_default_generic"); 1819 1820 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1821 if (ret_val) { 1822 DEBUGOUT("NVM Read Error\n"); 1823 return ret_val; 1824 } 1825 1826 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1827 *data = ID_LED_DEFAULT; 1828 1829 return E1000_SUCCESS; 1830} 1831 1832/** 1833 * e1000_id_led_init_generic - 1834 * @hw: pointer to the HW structure 1835 * 1836 **/ 1837s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1838{ 1839 struct e1000_mac_info *mac = &hw->mac; 1840 s32 ret_val; 1841 const u32 ledctl_mask = 0x000000FF; 1842 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1843 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1844 u16 data, i, temp; 1845 const u16 led_mask = 0x0F; 1846 1847 DEBUGFUNC("e1000_id_led_init_generic"); 1848 1849 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1850 if (ret_val) 1851 return ret_val; 1852 1853 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1854 mac->ledctl_mode1 = mac->ledctl_default; 1855 mac->ledctl_mode2 = mac->ledctl_default; 1856 1857 for (i = 0; i < 4; i++) { 1858 temp = (data >> (i << 2)) & led_mask; 1859 switch (temp) { 1860 case ID_LED_ON1_DEF2: 1861 case ID_LED_ON1_ON2: 1862 case ID_LED_ON1_OFF2: 1863 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1864 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1865 break; 1866 case ID_LED_OFF1_DEF2: 1867 case ID_LED_OFF1_ON2: 1868 case ID_LED_OFF1_OFF2: 1869 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1870 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1871 break; 1872 default: 1873 /* Do nothing */ 1874 break; 1875 } 1876 switch (temp) { 1877 case ID_LED_DEF1_ON2: 1878 case ID_LED_ON1_ON2: 1879 case ID_LED_OFF1_ON2: 1880 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1881 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1882 break; 1883 case ID_LED_DEF1_OFF2: 1884 case ID_LED_ON1_OFF2: 1885 case ID_LED_OFF1_OFF2: 1886 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1887 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1888 break; 1889 default: 1890 /* Do nothing */ 1891 break; 1892 } 1893 } 1894 1895 return E1000_SUCCESS; 1896} 1897 1898/** 1899 * e1000_setup_led_generic - Configures SW controllable LED 1900 * @hw: pointer to the HW structure 1901 * 1902 * This prepares the SW controllable LED for use and saves the current state 1903 * of the LED so it can be later restored. 1904 **/ 1905s32 e1000_setup_led_generic(struct e1000_hw *hw) 1906{ 1907 u32 ledctl; 1908 1909 DEBUGFUNC("e1000_setup_led_generic"); 1910 1911 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1912 return -E1000_ERR_CONFIG; 1913 1914 if (hw->phy.media_type == e1000_media_type_fiber) { 1915 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1916 hw->mac.ledctl_default = ledctl; 1917 /* Turn off LED0 */ 1918 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1919 E1000_LEDCTL_LED0_MODE_MASK); 1920 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1921 E1000_LEDCTL_LED0_MODE_SHIFT); 1922 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1923 } else if (hw->phy.media_type == e1000_media_type_copper) { 1924 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1925 } 1926 1927 return E1000_SUCCESS; 1928} 1929 1930/** 1931 * e1000_cleanup_led_generic - Set LED config to default operation 1932 * @hw: pointer to the HW structure 1933 * 1934 * Remove the current LED configuration and set the LED configuration 1935 * to the default value, saved from the EEPROM. 1936 **/ 1937s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1938{ 1939 DEBUGFUNC("e1000_cleanup_led_generic"); 1940 1941 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1942 return E1000_SUCCESS; 1943} 1944 1945/** 1946 * e1000_blink_led_generic - Blink LED 1947 * @hw: pointer to the HW structure 1948 * 1949 * Blink the LEDs which are set to be on. 1950 **/ 1951s32 e1000_blink_led_generic(struct e1000_hw *hw) 1952{ 1953 u32 ledctl_blink = 0; 1954 u32 i; 1955 1956 DEBUGFUNC("e1000_blink_led_generic"); 1957 1958 if (hw->phy.media_type == e1000_media_type_fiber) { 1959 /* always blink LED0 for PCI-E fiber */ 1960 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1961 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1962 } else { 1963 /* Set the blink bit for each LED that's "on" (0x0E) 1964 * (or "off" if inverted) in ledctl_mode2. The blink 1965 * logic in hardware only works when mode is set to "on" 1966 * so it must be changed accordingly when the mode is 1967 * "off" and inverted. 1968 */ 1969 ledctl_blink = hw->mac.ledctl_mode2; 1970 for (i = 0; i < 32; i += 8) { 1971 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1972 E1000_LEDCTL_LED0_MODE_MASK; 1973 u32 led_default = hw->mac.ledctl_default >> i; 1974 1975 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1976 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1977 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1978 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1979 ledctl_blink &= 1980 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1981 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1982 E1000_LEDCTL_MODE_LED_ON) << i; 1983 } 1984 } 1985 } 1986 1987 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1988 1989 return E1000_SUCCESS; 1990} 1991 1992/** 1993 * e1000_led_on_generic - Turn LED on 1994 * @hw: pointer to the HW structure 1995 * 1996 * Turn LED on. 1997 **/ 1998s32 e1000_led_on_generic(struct e1000_hw *hw) 1999{ 2000 u32 ctrl; 2001 2002 DEBUGFUNC("e1000_led_on_generic"); 2003 2004 switch (hw->phy.media_type) { 2005 case e1000_media_type_fiber: 2006 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2007 ctrl &= ~E1000_CTRL_SWDPIN0; 2008 ctrl |= E1000_CTRL_SWDPIO0; 2009 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2010 break; 2011 case e1000_media_type_copper: 2012 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2013 break; 2014 default: 2015 break; 2016 } 2017 2018 return E1000_SUCCESS; 2019} 2020 2021/** 2022 * e1000_led_off_generic - Turn LED off 2023 * @hw: pointer to the HW structure 2024 * 2025 * Turn LED off. 2026 **/ 2027s32 e1000_led_off_generic(struct e1000_hw *hw) 2028{ 2029 u32 ctrl; 2030 2031 DEBUGFUNC("e1000_led_off_generic"); 2032 2033 switch (hw->phy.media_type) { 2034 case e1000_media_type_fiber: 2035 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2036 ctrl |= E1000_CTRL_SWDPIN0; 2037 ctrl |= E1000_CTRL_SWDPIO0; 2038 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2039 break; 2040 case e1000_media_type_copper: 2041 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2042 break; 2043 default: 2044 break; 2045 } 2046 2047 return E1000_SUCCESS; 2048} 2049 2050/** 2051 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2052 * @hw: pointer to the HW structure 2053 * @no_snoop: bitmap of snoop events 2054 * 2055 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2056 **/ 2057void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2058{ 2059 u32 gcr; 2060 2061 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2062 2063 if (hw->bus.type != e1000_bus_type_pci_express) 2064 return; 2065 2066 if (no_snoop) { 2067 gcr = E1000_READ_REG(hw, E1000_GCR); 2068 gcr &= ~(PCIE_NO_SNOOP_ALL); 2069 gcr |= no_snoop; 2070 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2071 } 2072} 2073 2074/** 2075 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2076 * @hw: pointer to the HW structure 2077 * 2078 * Returns E1000_SUCCESS if successful, else returns -10 2079 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2080 * the master requests to be disabled. 2081 * 2082 * Disables PCI-Express master access and verifies there are no pending 2083 * requests. 2084 **/ 2085s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2086{ 2087 u32 ctrl; 2088 s32 timeout = MASTER_DISABLE_TIMEOUT; 2089 2090 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2091 2092 if (hw->bus.type != e1000_bus_type_pci_express) 2093 return E1000_SUCCESS; 2094 2095 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2096 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2097 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2098 2099 while (timeout) { 2100 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2101 E1000_STATUS_GIO_MASTER_ENABLE) || 2102 E1000_REMOVED(hw->hw_addr)) 2103 break; 2104 usec_delay(100); 2105 timeout--; 2106 } 2107 2108 if (!timeout) { 2109 DEBUGOUT("Master requests are pending.\n"); 2110 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2111 } 2112 2113 return E1000_SUCCESS; 2114} 2115 2116/** 2117 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2118 * @hw: pointer to the HW structure 2119 * 2120 * Reset the Adaptive Interframe Spacing throttle to default values. 2121 **/ 2122void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2123{ 2124 struct e1000_mac_info *mac = &hw->mac; 2125 2126 DEBUGFUNC("e1000_reset_adaptive_generic"); 2127 2128 if (!mac->adaptive_ifs) { 2129 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2130 return; 2131 } 2132 2133 mac->current_ifs_val = 0; 2134 mac->ifs_min_val = IFS_MIN; 2135 mac->ifs_max_val = IFS_MAX; 2136 mac->ifs_step_size = IFS_STEP; 2137 mac->ifs_ratio = IFS_RATIO; 2138 2139 mac->in_ifs_mode = FALSE; 2140 E1000_WRITE_REG(hw, E1000_AIT, 0); 2141} 2142 2143/** 2144 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2145 * @hw: pointer to the HW structure 2146 * 2147 * Update the Adaptive Interframe Spacing Throttle value based on the 2148 * time between transmitted packets and time between collisions. 2149 **/ 2150void e1000_update_adaptive_generic(struct e1000_hw *hw) 2151{ 2152 struct e1000_mac_info *mac = &hw->mac; 2153 2154 DEBUGFUNC("e1000_update_adaptive_generic"); 2155 2156 if (!mac->adaptive_ifs) { 2157 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2158 return; 2159 } 2160 2161 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2162 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2163 mac->in_ifs_mode = TRUE; 2164 if (mac->current_ifs_val < mac->ifs_max_val) { 2165 if (!mac->current_ifs_val) 2166 mac->current_ifs_val = mac->ifs_min_val; 2167 else 2168 mac->current_ifs_val += 2169 mac->ifs_step_size; 2170 E1000_WRITE_REG(hw, E1000_AIT, 2171 mac->current_ifs_val); 2172 } 2173 } 2174 } else { 2175 if (mac->in_ifs_mode && 2176 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2177 mac->current_ifs_val = 0; 2178 mac->in_ifs_mode = FALSE; 2179 E1000_WRITE_REG(hw, E1000_AIT, 0); 2180 } 2181 } 2182} 2183 2184/** 2185 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2186 * @hw: pointer to the HW structure 2187 * 2188 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2189 * set, which is forced to MDI mode only. 2190 **/ 2191static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2192{ 2193 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2194 2195 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2196 DEBUGOUT("Invalid MDI setting detected\n"); 2197 hw->phy.mdix = 1; 2198 return -E1000_ERR_CONFIG; 2199 } 2200 2201 return E1000_SUCCESS; 2202} 2203 2204/** 2205 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2206 * @hw: pointer to the HW structure 2207 * 2208 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2209 * operation. 2210 **/ 2211s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2212{ 2213 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2214 2215 return E1000_SUCCESS; 2216} 2217 2218/** 2219 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2220 * @hw: pointer to the HW structure 2221 * @reg: 32bit register offset such as E1000_SCTL 2222 * @offset: register offset to write to 2223 * @data: data to write at register offset 2224 * 2225 * Writes an address/data control type register. There are several of these 2226 * and they all have the format address << 8 | data and bit 31 is polled for 2227 * completion. 2228 **/ 2229s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2230 u32 offset, u8 data) 2231{ 2232 u32 i, regvalue = 0; 2233 2234 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2235 2236 /* Set up the address and data */ 2237 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2238 E1000_WRITE_REG(hw, reg, regvalue); 2239 2240 /* Poll the ready bit to see if the MDI read completed */ 2241 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2242 usec_delay(5); 2243 regvalue = E1000_READ_REG(hw, reg); 2244 if (regvalue & E1000_GEN_CTL_READY) 2245 break; 2246 } 2247 if (!(regvalue & E1000_GEN_CTL_READY)) { 2248 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2249 return -E1000_ERR_PHY; 2250 } 2251 2252 return E1000_SUCCESS; 2253} 2254