e1000_mac.c revision 205869
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 205869 2010-03-29 23:36:34Z jfv $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47{ 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.rar_set = e1000_rar_set_generic; 82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 83} 84 85/** 86 * e1000_null_ops_generic - No-op function, returns 0 87 * @hw: pointer to the HW structure 88 **/ 89s32 e1000_null_ops_generic(struct e1000_hw *hw) 90{ 91 DEBUGFUNC("e1000_null_ops_generic"); 92 return E1000_SUCCESS; 93} 94 95/** 96 * e1000_null_mac_generic - No-op function, return void 97 * @hw: pointer to the HW structure 98 **/ 99void e1000_null_mac_generic(struct e1000_hw *hw) 100{ 101 DEBUGFUNC("e1000_null_mac_generic"); 102 return; 103} 104 105/** 106 * e1000_null_link_info - No-op function, return 0 107 * @hw: pointer to the HW structure 108 **/ 109s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110{ 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113} 114 115/** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119bool e1000_null_mng_mode(struct e1000_hw *hw) 120{ 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123} 124 125/** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 130{ 131 DEBUGFUNC("e1000_null_update_mc"); 132 return; 133} 134 135/** 136 * e1000_null_write_vfta - No-op function, return void 137 * @hw: pointer to the HW structure 138 **/ 139void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 140{ 141 DEBUGFUNC("e1000_null_write_vfta"); 142 return; 143} 144 145/** 146 * e1000_null_rar_set - No-op function, return void 147 * @hw: pointer to the HW structure 148 **/ 149void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 150{ 151 DEBUGFUNC("e1000_null_rar_set"); 152 return; 153} 154 155/** 156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 157 * @hw: pointer to the HW structure 158 * 159 * Determines and stores the system bus information for a particular 160 * network interface. The following bus information is determined and stored: 161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 162 **/ 163s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 164{ 165 struct e1000_mac_info *mac = &hw->mac; 166 struct e1000_bus_info *bus = &hw->bus; 167 u32 status = E1000_READ_REG(hw, E1000_STATUS); 168 s32 ret_val = E1000_SUCCESS; 169 170 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 171 172 /* PCI or PCI-X? */ 173 bus->type = (status & E1000_STATUS_PCIX_MODE) 174 ? e1000_bus_type_pcix 175 : e1000_bus_type_pci; 176 177 /* Bus speed */ 178 if (bus->type == e1000_bus_type_pci) { 179 bus->speed = (status & E1000_STATUS_PCI66) 180 ? e1000_bus_speed_66 181 : e1000_bus_speed_33; 182 } else { 183 switch (status & E1000_STATUS_PCIX_SPEED) { 184 case E1000_STATUS_PCIX_SPEED_66: 185 bus->speed = e1000_bus_speed_66; 186 break; 187 case E1000_STATUS_PCIX_SPEED_100: 188 bus->speed = e1000_bus_speed_100; 189 break; 190 case E1000_STATUS_PCIX_SPEED_133: 191 bus->speed = e1000_bus_speed_133; 192 break; 193 default: 194 bus->speed = e1000_bus_speed_reserved; 195 break; 196 } 197 } 198 199 /* Bus width */ 200 bus->width = (status & E1000_STATUS_BUS64) 201 ? e1000_bus_width_64 202 : e1000_bus_width_32; 203 204 /* Which PCI(-X) function? */ 205 mac->ops.set_lan_id(hw); 206 207 return ret_val; 208} 209 210/** 211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 212 * @hw: pointer to the HW structure 213 * 214 * Determines and stores the system bus information for a particular 215 * network interface. The following bus information is determined and stored: 216 * bus speed, bus width, type (PCIe), and PCIe function. 217 **/ 218s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 219{ 220 struct e1000_mac_info *mac = &hw->mac; 221 struct e1000_bus_info *bus = &hw->bus; 222 s32 ret_val; 223 u16 pcie_link_status; 224 225 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 226 227 bus->type = e1000_bus_type_pci_express; 228 229 ret_val = e1000_read_pcie_cap_reg(hw, 230 PCIE_LINK_STATUS, 231 &pcie_link_status); 232 if (ret_val) { 233 bus->width = e1000_bus_width_unknown; 234 bus->speed = e1000_bus_speed_unknown; 235 } else { 236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 237 case PCIE_LINK_SPEED_2500: 238 bus->speed = e1000_bus_speed_2500; 239 break; 240 case PCIE_LINK_SPEED_5000: 241 bus->speed = e1000_bus_speed_5000; 242 break; 243 default: 244 bus->speed = e1000_bus_speed_unknown; 245 break; 246 } 247 248 bus->width = (enum e1000_bus_width)((pcie_link_status & 249 PCIE_LINK_WIDTH_MASK) >> 250 PCIE_LINK_WIDTH_SHIFT); 251 } 252 253 mac->ops.set_lan_id(hw); 254 255 return E1000_SUCCESS; 256} 257 258/** 259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 260 * 261 * @hw: pointer to the HW structure 262 * 263 * Determines the LAN function id by reading memory-mapped registers 264 * and swaps the port value if requested. 265 **/ 266static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 267{ 268 struct e1000_bus_info *bus = &hw->bus; 269 u32 reg; 270 271 /* 272 * The status register reports the correct function number 273 * for the device regardless of function swap state. 274 */ 275 reg = E1000_READ_REG(hw, E1000_STATUS); 276 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 277} 278 279/** 280 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 281 * @hw: pointer to the HW structure 282 * 283 * Determines the LAN function id by reading PCI config space. 284 **/ 285void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 286{ 287 struct e1000_bus_info *bus = &hw->bus; 288 u16 pci_header_type; 289 u32 status; 290 291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 293 status = E1000_READ_REG(hw, E1000_STATUS); 294 bus->func = (status & E1000_STATUS_FUNC_MASK) 295 >> E1000_STATUS_FUNC_SHIFT; 296 } else { 297 bus->func = 0; 298 } 299} 300 301/** 302 * e1000_set_lan_id_single_port - Set LAN id for a single port device 303 * @hw: pointer to the HW structure 304 * 305 * Sets the LAN function id to zero for a single port device. 306 **/ 307void e1000_set_lan_id_single_port(struct e1000_hw *hw) 308{ 309 struct e1000_bus_info *bus = &hw->bus; 310 311 bus->func = 0; 312} 313 314/** 315 * e1000_clear_vfta_generic - Clear VLAN filter table 316 * @hw: pointer to the HW structure 317 * 318 * Clears the register array which contains the VLAN filter table by 319 * setting all the values to 0. 320 **/ 321void e1000_clear_vfta_generic(struct e1000_hw *hw) 322{ 323 u32 offset; 324 325 DEBUGFUNC("e1000_clear_vfta_generic"); 326 327 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 328 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 329 E1000_WRITE_FLUSH(hw); 330 } 331} 332 333/** 334 * e1000_write_vfta_generic - Write value to VLAN filter table 335 * @hw: pointer to the HW structure 336 * @offset: register offset in VLAN filter table 337 * @value: register value written to VLAN filter table 338 * 339 * Writes value at the given offset in the register array which stores 340 * the VLAN filter table. 341 **/ 342void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 343{ 344 DEBUGFUNC("e1000_write_vfta_generic"); 345 346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 347 E1000_WRITE_FLUSH(hw); 348} 349 350/** 351 * e1000_init_rx_addrs_generic - Initialize receive address's 352 * @hw: pointer to the HW structure 353 * @rar_count: receive address registers 354 * 355 * Setups the receive address registers by setting the base receive address 356 * register to the devices MAC address and clearing all the other receive 357 * address registers to 0. 358 **/ 359void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 360{ 361 u32 i; 362 u8 mac_addr[ETH_ADDR_LEN] = {0}; 363 364 DEBUGFUNC("e1000_init_rx_addrs_generic"); 365 366 /* Setup the receive address */ 367 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 368 369 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 370 371 /* Zero out the other (rar_entry_count - 1) receive addresses */ 372 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 373 for (i = 1; i < rar_count; i++) 374 hw->mac.ops.rar_set(hw, mac_addr, i); 375} 376 377/** 378 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 379 * @hw: pointer to the HW structure 380 * 381 * Checks the nvm for an alternate MAC address. An alternate MAC address 382 * can be setup by pre-boot software and must be treated like a permanent 383 * address and must override the actual permanent MAC address. If an 384 * alternate MAC address is found it is programmed into RAR0, replacing 385 * the permanent address that was installed into RAR0 by the Si on reset. 386 * This function will return SUCCESS unless it encounters an error while 387 * reading the EEPROM. 388 **/ 389s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 390{ 391 u32 i; 392 s32 ret_val = E1000_SUCCESS; 393 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 394 u8 alt_mac_addr[ETH_ADDR_LEN]; 395 396 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 397 398 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 399 &nvm_alt_mac_addr_offset); 400 if (ret_val) { 401 DEBUGOUT("NVM Read Error\n"); 402 goto out; 403 } 404 405 if (nvm_alt_mac_addr_offset == 0xFFFF) { 406 /* There is no Alternate MAC Address */ 407 goto out; 408 } 409 410 if (hw->bus.func == E1000_FUNC_1) 411 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 412 if (hw->bus.func == E1000_FUNC_2) 413 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 414 415 if (hw->bus.func == E1000_FUNC_3) 416 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 417 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 418 offset = nvm_alt_mac_addr_offset + (i >> 1); 419 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 420 if (ret_val) { 421 DEBUGOUT("NVM Read Error\n"); 422 goto out; 423 } 424 425 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 426 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 427 } 428 429 /* if multicast bit is set, the alternate address will not be used */ 430 if (alt_mac_addr[0] & 0x01) { 431 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 432 goto out; 433 } 434 435 /* 436 * We have a valid alternate MAC address, and we want to treat it the 437 * same as the normal permanent MAC address stored by the HW into the 438 * RAR. Do this by mapping this address into RAR0. 439 */ 440 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 441 442out: 443 return ret_val; 444} 445 446/** 447 * e1000_rar_set_generic - Set receive address register 448 * @hw: pointer to the HW structure 449 * @addr: pointer to the receive address 450 * @index: receive address array register 451 * 452 * Sets the receive address array register at index to the address passed 453 * in by addr. 454 **/ 455void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 456{ 457 u32 rar_low, rar_high; 458 459 DEBUGFUNC("e1000_rar_set_generic"); 460 461 /* 462 * HW expects these in little endian so we reverse the byte order 463 * from network order (big endian) to little endian 464 */ 465 rar_low = ((u32) addr[0] | 466 ((u32) addr[1] << 8) | 467 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 468 469 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 470 471 /* If MAC address zero, no need to set the AV bit */ 472 if (rar_low || rar_high) 473 rar_high |= E1000_RAH_AV; 474 475 /* 476 * Some bridges will combine consecutive 32-bit writes into 477 * a single burst write, which will malfunction on some parts. 478 * The flushes avoid this. 479 */ 480 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 481 E1000_WRITE_FLUSH(hw); 482 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 483 E1000_WRITE_FLUSH(hw); 484} 485 486/** 487 * e1000_update_mc_addr_list_generic - Update Multicast addresses 488 * @hw: pointer to the HW structure 489 * @mc_addr_list: array of multicast addresses to program 490 * @mc_addr_count: number of multicast addresses to program 491 * 492 * Updates entire Multicast Table Array. 493 * The caller must have a packed mc_addr_list of multicast addresses. 494 **/ 495void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 496 u8 *mc_addr_list, u32 mc_addr_count) 497{ 498 u32 hash_value, hash_bit, hash_reg; 499 int i; 500 501 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 502 503 /* clear mta_shadow */ 504 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 505 506 /* update mta_shadow from mc_addr_list */ 507 for (i = 0; (u32) i < mc_addr_count; i++) { 508 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 509 510 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 511 hash_bit = hash_value & 0x1F; 512 513 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 514 mc_addr_list += (ETH_ADDR_LEN); 515 } 516 517 /* replace the entire MTA table */ 518 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 519 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 520 E1000_WRITE_FLUSH(hw); 521} 522 523/** 524 * e1000_hash_mc_addr_generic - Generate a multicast hash value 525 * @hw: pointer to the HW structure 526 * @mc_addr: pointer to a multicast address 527 * 528 * Generates a multicast address hash value which is used to determine 529 * the multicast filter table array address and new table value. 530 **/ 531u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 532{ 533 u32 hash_value, hash_mask; 534 u8 bit_shift = 0; 535 536 DEBUGFUNC("e1000_hash_mc_addr_generic"); 537 538 /* Register count multiplied by bits per register */ 539 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 540 541 /* 542 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 543 * where 0xFF would still fall within the hash mask. 544 */ 545 while (hash_mask >> bit_shift != 0xFF) 546 bit_shift++; 547 548 /* 549 * The portion of the address that is used for the hash table 550 * is determined by the mc_filter_type setting. 551 * The algorithm is such that there is a total of 8 bits of shifting. 552 * The bit_shift for a mc_filter_type of 0 represents the number of 553 * left-shifts where the MSB of mc_addr[5] would still fall within 554 * the hash_mask. Case 0 does this exactly. Since there are a total 555 * of 8 bits of shifting, then mc_addr[4] will shift right the 556 * remaining number of bits. Thus 8 - bit_shift. The rest of the 557 * cases are a variation of this algorithm...essentially raising the 558 * number of bits to shift mc_addr[5] left, while still keeping the 559 * 8-bit shifting total. 560 * 561 * For example, given the following Destination MAC Address and an 562 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 563 * we can see that the bit_shift for case 0 is 4. These are the hash 564 * values resulting from each mc_filter_type... 565 * [0] [1] [2] [3] [4] [5] 566 * 01 AA 00 12 34 56 567 * LSB MSB 568 * 569 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 570 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 571 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 572 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 573 */ 574 switch (hw->mac.mc_filter_type) { 575 default: 576 case 0: 577 break; 578 case 1: 579 bit_shift += 1; 580 break; 581 case 2: 582 bit_shift += 2; 583 break; 584 case 3: 585 bit_shift += 4; 586 break; 587 } 588 589 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 590 (((u16) mc_addr[5]) << bit_shift))); 591 592 return hash_value; 593} 594 595/** 596 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 597 * @hw: pointer to the HW structure 598 * 599 * In certain situations, a system BIOS may report that the PCIx maximum 600 * memory read byte count (MMRBC) value is higher than than the actual 601 * value. We check the PCIx command register with the current PCIx status 602 * register. 603 **/ 604void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 605{ 606 u16 cmd_mmrbc; 607 u16 pcix_cmd; 608 u16 pcix_stat_hi_word; 609 u16 stat_mmrbc; 610 611 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 612 613 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 614 if (hw->bus.type != e1000_bus_type_pcix) 615 return; 616 617 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 618 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 619 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 620 PCIX_COMMAND_MMRBC_SHIFT; 621 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 622 PCIX_STATUS_HI_MMRBC_SHIFT; 623 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 624 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 625 if (cmd_mmrbc > stat_mmrbc) { 626 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 627 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 628 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 629 } 630} 631 632/** 633 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 634 * @hw: pointer to the HW structure 635 * 636 * Clears the base hardware counters by reading the counter registers. 637 **/ 638void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 639{ 640 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 641 642 E1000_READ_REG(hw, E1000_CRCERRS); 643 E1000_READ_REG(hw, E1000_SYMERRS); 644 E1000_READ_REG(hw, E1000_MPC); 645 E1000_READ_REG(hw, E1000_SCC); 646 E1000_READ_REG(hw, E1000_ECOL); 647 E1000_READ_REG(hw, E1000_MCC); 648 E1000_READ_REG(hw, E1000_LATECOL); 649 E1000_READ_REG(hw, E1000_COLC); 650 E1000_READ_REG(hw, E1000_DC); 651 E1000_READ_REG(hw, E1000_SEC); 652 E1000_READ_REG(hw, E1000_RLEC); 653 E1000_READ_REG(hw, E1000_XONRXC); 654 E1000_READ_REG(hw, E1000_XONTXC); 655 E1000_READ_REG(hw, E1000_XOFFRXC); 656 E1000_READ_REG(hw, E1000_XOFFTXC); 657 E1000_READ_REG(hw, E1000_FCRUC); 658 E1000_READ_REG(hw, E1000_GPRC); 659 E1000_READ_REG(hw, E1000_BPRC); 660 E1000_READ_REG(hw, E1000_MPRC); 661 E1000_READ_REG(hw, E1000_GPTC); 662 E1000_READ_REG(hw, E1000_GORCL); 663 E1000_READ_REG(hw, E1000_GORCH); 664 E1000_READ_REG(hw, E1000_GOTCL); 665 E1000_READ_REG(hw, E1000_GOTCH); 666 E1000_READ_REG(hw, E1000_RNBC); 667 E1000_READ_REG(hw, E1000_RUC); 668 E1000_READ_REG(hw, E1000_RFC); 669 E1000_READ_REG(hw, E1000_ROC); 670 E1000_READ_REG(hw, E1000_RJC); 671 E1000_READ_REG(hw, E1000_TORL); 672 E1000_READ_REG(hw, E1000_TORH); 673 E1000_READ_REG(hw, E1000_TOTL); 674 E1000_READ_REG(hw, E1000_TOTH); 675 E1000_READ_REG(hw, E1000_TPR); 676 E1000_READ_REG(hw, E1000_TPT); 677 E1000_READ_REG(hw, E1000_MPTC); 678 E1000_READ_REG(hw, E1000_BPTC); 679} 680 681/** 682 * e1000_check_for_copper_link_generic - Check for link (Copper) 683 * @hw: pointer to the HW structure 684 * 685 * Checks to see of the link status of the hardware has changed. If a 686 * change in link status has been detected, then we read the PHY registers 687 * to get the current speed/duplex if link exists. 688 **/ 689s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 690{ 691 struct e1000_mac_info *mac = &hw->mac; 692 s32 ret_val; 693 bool link; 694 695 DEBUGFUNC("e1000_check_for_copper_link"); 696 697 /* 698 * We only want to go out to the PHY registers to see if Auto-Neg 699 * has completed and/or if our link status has changed. The 700 * get_link_status flag is set upon receiving a Link Status 701 * Change or Rx Sequence Error interrupt. 702 */ 703 if (!mac->get_link_status) { 704 ret_val = E1000_SUCCESS; 705 goto out; 706 } 707 708 /* 709 * First we want to see if the MII Status Register reports 710 * link. If so, then we want to get the current speed/duplex 711 * of the PHY. 712 */ 713 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 714 if (ret_val) 715 goto out; 716 717 if (!link) 718 goto out; /* No link detected */ 719 720 mac->get_link_status = FALSE; 721 722 /* 723 * Check if there was DownShift, must be checked 724 * immediately after link-up 725 */ 726 e1000_check_downshift_generic(hw); 727 728 /* 729 * If we are forcing speed/duplex, then we simply return since 730 * we have already determined whether we have link or not. 731 */ 732 if (!mac->autoneg) { 733 ret_val = -E1000_ERR_CONFIG; 734 goto out; 735 } 736 737 /* 738 * Auto-Neg is enabled. Auto Speed Detection takes care 739 * of MAC speed/duplex configuration. So we only need to 740 * configure Collision Distance in the MAC. 741 */ 742 mac->ops.config_collision_dist(hw); 743 744 /* 745 * Configure Flow Control now that Auto-Neg has completed. 746 * First, we need to restore the desired flow control 747 * settings because we may have had to re-autoneg with a 748 * different link partner. 749 */ 750 ret_val = e1000_config_fc_after_link_up_generic(hw); 751 if (ret_val) 752 DEBUGOUT("Error configuring flow control\n"); 753 754out: 755 return ret_val; 756} 757 758/** 759 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 760 * @hw: pointer to the HW structure 761 * 762 * Checks for link up on the hardware. If link is not up and we have 763 * a signal, then we need to force link up. 764 **/ 765s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 766{ 767 struct e1000_mac_info *mac = &hw->mac; 768 u32 rxcw; 769 u32 ctrl; 770 u32 status; 771 s32 ret_val = E1000_SUCCESS; 772 773 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 774 775 ctrl = E1000_READ_REG(hw, E1000_CTRL); 776 status = E1000_READ_REG(hw, E1000_STATUS); 777 rxcw = E1000_READ_REG(hw, E1000_RXCW); 778 779 /* 780 * If we don't have link (auto-negotiation failed or link partner 781 * cannot auto-negotiate), the cable is plugged in (we have signal), 782 * and our link partner is not trying to auto-negotiate with us (we 783 * are receiving idles or data), we need to force link up. We also 784 * need to give auto-negotiation time to complete, in case the cable 785 * was just plugged in. The autoneg_failed flag does this. 786 */ 787 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 788 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 789 (!(rxcw & E1000_RXCW_C))) { 790 if (mac->autoneg_failed == 0) { 791 mac->autoneg_failed = 1; 792 goto out; 793 } 794 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 795 796 /* Disable auto-negotiation in the TXCW register */ 797 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 798 799 /* Force link-up and also force full-duplex. */ 800 ctrl = E1000_READ_REG(hw, E1000_CTRL); 801 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 802 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 803 804 /* Configure Flow Control after forcing link up. */ 805 ret_val = e1000_config_fc_after_link_up_generic(hw); 806 if (ret_val) { 807 DEBUGOUT("Error configuring flow control\n"); 808 goto out; 809 } 810 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 811 /* 812 * If we are forcing link and we are receiving /C/ ordered 813 * sets, re-enable auto-negotiation in the TXCW register 814 * and disable forced link in the Device Control register 815 * in an attempt to auto-negotiate with our link partner. 816 */ 817 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 818 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 819 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 820 821 mac->serdes_has_link = TRUE; 822 } 823 824out: 825 return ret_val; 826} 827 828/** 829 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 830 * @hw: pointer to the HW structure 831 * 832 * Checks for link up on the hardware. If link is not up and we have 833 * a signal, then we need to force link up. 834 **/ 835s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 836{ 837 struct e1000_mac_info *mac = &hw->mac; 838 u32 rxcw; 839 u32 ctrl; 840 u32 status; 841 s32 ret_val = E1000_SUCCESS; 842 843 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 844 845 ctrl = E1000_READ_REG(hw, E1000_CTRL); 846 status = E1000_READ_REG(hw, E1000_STATUS); 847 rxcw = E1000_READ_REG(hw, E1000_RXCW); 848 849 /* 850 * If we don't have link (auto-negotiation failed or link partner 851 * cannot auto-negotiate), and our link partner is not trying to 852 * auto-negotiate with us (we are receiving idles or data), 853 * we need to force link up. We also need to give auto-negotiation 854 * time to complete. 855 */ 856 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 857 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 858 if (mac->autoneg_failed == 0) { 859 mac->autoneg_failed = 1; 860 goto out; 861 } 862 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 863 864 /* Disable auto-negotiation in the TXCW register */ 865 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 866 867 /* Force link-up and also force full-duplex. */ 868 ctrl = E1000_READ_REG(hw, E1000_CTRL); 869 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 870 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 871 872 /* Configure Flow Control after forcing link up. */ 873 ret_val = e1000_config_fc_after_link_up_generic(hw); 874 if (ret_val) { 875 DEBUGOUT("Error configuring flow control\n"); 876 goto out; 877 } 878 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 879 /* 880 * If we are forcing link and we are receiving /C/ ordered 881 * sets, re-enable auto-negotiation in the TXCW register 882 * and disable forced link in the Device Control register 883 * in an attempt to auto-negotiate with our link partner. 884 */ 885 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 886 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 887 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 888 889 mac->serdes_has_link = TRUE; 890 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 891 /* 892 * If we force link for non-auto-negotiation switch, check 893 * link status based on MAC synchronization for internal 894 * serdes media type. 895 */ 896 /* SYNCH bit and IV bit are sticky. */ 897 usec_delay(10); 898 rxcw = E1000_READ_REG(hw, E1000_RXCW); 899 if (rxcw & E1000_RXCW_SYNCH) { 900 if (!(rxcw & E1000_RXCW_IV)) { 901 mac->serdes_has_link = TRUE; 902 DEBUGOUT("SERDES: Link up - forced.\n"); 903 } 904 } else { 905 mac->serdes_has_link = FALSE; 906 DEBUGOUT("SERDES: Link down - force failed.\n"); 907 } 908 } 909 910 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 911 status = E1000_READ_REG(hw, E1000_STATUS); 912 if (status & E1000_STATUS_LU) { 913 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 914 usec_delay(10); 915 rxcw = E1000_READ_REG(hw, E1000_RXCW); 916 if (rxcw & E1000_RXCW_SYNCH) { 917 if (!(rxcw & E1000_RXCW_IV)) { 918 mac->serdes_has_link = TRUE; 919 DEBUGOUT("SERDES: Link up - autoneg " 920 "completed sucessfully.\n"); 921 } else { 922 mac->serdes_has_link = FALSE; 923 DEBUGOUT("SERDES: Link down - invalid" 924 "codewords detected in autoneg.\n"); 925 } 926 } else { 927 mac->serdes_has_link = FALSE; 928 DEBUGOUT("SERDES: Link down - no sync.\n"); 929 } 930 } else { 931 mac->serdes_has_link = FALSE; 932 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 933 } 934 } 935 936out: 937 return ret_val; 938} 939 940/** 941 * e1000_setup_link_generic - Setup flow control and link settings 942 * @hw: pointer to the HW structure 943 * 944 * Determines which flow control settings to use, then configures flow 945 * control. Calls the appropriate media-specific link configuration 946 * function. Assuming the adapter has a valid link partner, a valid link 947 * should be established. Assumes the hardware has previously been reset 948 * and the transmitter and receiver are not enabled. 949 **/ 950s32 e1000_setup_link_generic(struct e1000_hw *hw) 951{ 952 s32 ret_val = E1000_SUCCESS; 953 954 DEBUGFUNC("e1000_setup_link_generic"); 955 956 /* 957 * In the case of the phy reset being blocked, we already have a link. 958 * We do not need to set it up again. 959 */ 960 if (e1000_check_reset_block(hw)) 961 goto out; 962 963 /* 964 * If requested flow control is set to default, set flow control 965 * based on the EEPROM flow control settings. 966 */ 967 if (hw->fc.requested_mode == e1000_fc_default) { 968 ret_val = e1000_set_default_fc_generic(hw); 969 if (ret_val) 970 goto out; 971 } 972 973 /* 974 * Save off the requested flow control mode for use later. Depending 975 * on the link partner's capabilities, we may or may not use this mode. 976 */ 977 hw->fc.current_mode = hw->fc.requested_mode; 978 979 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 980 hw->fc.current_mode); 981 982 /* Call the necessary media_type subroutine to configure the link. */ 983 ret_val = hw->mac.ops.setup_physical_interface(hw); 984 if (ret_val) 985 goto out; 986 987 /* 988 * Initialize the flow control address, type, and PAUSE timer 989 * registers to their default values. This is done even if flow 990 * control is disabled, because it does not hurt anything to 991 * initialize these registers. 992 */ 993 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 994 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 995 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 996 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 997 998 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 999 1000 ret_val = e1000_set_fc_watermarks_generic(hw); 1001 1002out: 1003 return ret_val; 1004} 1005 1006/** 1007 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1008 * @hw: pointer to the HW structure 1009 * 1010 * Configures collision distance and flow control for fiber and serdes 1011 * links. Upon successful setup, poll for link. 1012 **/ 1013s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1014{ 1015 struct e1000_mac_info *mac = &hw->mac; 1016 u32 ctrl; 1017 s32 ret_val = E1000_SUCCESS; 1018 1019 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1020 1021 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1022 1023 /* Take the link out of reset */ 1024 ctrl &= ~E1000_CTRL_LRST; 1025 1026 mac->ops.config_collision_dist(hw); 1027 1028 ret_val = e1000_commit_fc_settings_generic(hw); 1029 if (ret_val) 1030 goto out; 1031 1032 /* 1033 * Since auto-negotiation is enabled, take the link out of reset (the 1034 * link will be in reset, because we previously reset the chip). This 1035 * will restart auto-negotiation. If auto-negotiation is successful 1036 * then the link-up status bit will be set and the flow control enable 1037 * bits (RFCE and TFCE) will be set according to their negotiated value. 1038 */ 1039 DEBUGOUT("Auto-negotiation enabled\n"); 1040 1041 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1042 E1000_WRITE_FLUSH(hw); 1043 msec_delay(1); 1044 1045 /* 1046 * For these adapters, the SW definable pin 1 is set when the optics 1047 * detect a signal. If we have a signal, then poll for a "Link-Up" 1048 * indication. 1049 */ 1050 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1051 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1052 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1053 } else { 1054 DEBUGOUT("No signal detected\n"); 1055 } 1056 1057out: 1058 return ret_val; 1059} 1060 1061/** 1062 * e1000_config_collision_dist_generic - Configure collision distance 1063 * @hw: pointer to the HW structure 1064 * 1065 * Configures the collision distance to the default value and is used 1066 * during link setup. 1067 **/ 1068void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1069{ 1070 u32 tctl; 1071 1072 DEBUGFUNC("e1000_config_collision_dist_generic"); 1073 1074 tctl = E1000_READ_REG(hw, E1000_TCTL); 1075 1076 tctl &= ~E1000_TCTL_COLD; 1077 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1078 1079 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1080 E1000_WRITE_FLUSH(hw); 1081} 1082 1083/** 1084 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1085 * @hw: pointer to the HW structure 1086 * 1087 * Polls for link up by reading the status register, if link fails to come 1088 * up with auto-negotiation, then the link is forced if a signal is detected. 1089 **/ 1090s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1091{ 1092 struct e1000_mac_info *mac = &hw->mac; 1093 u32 i, status; 1094 s32 ret_val = E1000_SUCCESS; 1095 1096 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1097 1098 /* 1099 * If we have a signal (the cable is plugged in, or assumed TRUE for 1100 * serdes media) then poll for a "Link-Up" indication in the Device 1101 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1102 * seconds (Auto-negotiation should complete in less than 500 1103 * milliseconds even if the other end is doing it in SW). 1104 */ 1105 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1106 msec_delay(10); 1107 status = E1000_READ_REG(hw, E1000_STATUS); 1108 if (status & E1000_STATUS_LU) 1109 break; 1110 } 1111 if (i == FIBER_LINK_UP_LIMIT) { 1112 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1113 mac->autoneg_failed = 1; 1114 /* 1115 * AutoNeg failed to achieve a link, so we'll call 1116 * mac->check_for_link. This routine will force the 1117 * link up if we detect a signal. This will allow us to 1118 * communicate with non-autonegotiating link partners. 1119 */ 1120 ret_val = mac->ops.check_for_link(hw); 1121 if (ret_val) { 1122 DEBUGOUT("Error while checking for link\n"); 1123 goto out; 1124 } 1125 mac->autoneg_failed = 0; 1126 } else { 1127 mac->autoneg_failed = 0; 1128 DEBUGOUT("Valid Link Found\n"); 1129 } 1130 1131out: 1132 return ret_val; 1133} 1134 1135/** 1136 * e1000_commit_fc_settings_generic - Configure flow control 1137 * @hw: pointer to the HW structure 1138 * 1139 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1140 * base on the flow control settings in e1000_mac_info. 1141 **/ 1142s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1143{ 1144 struct e1000_mac_info *mac = &hw->mac; 1145 u32 txcw; 1146 s32 ret_val = E1000_SUCCESS; 1147 1148 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1149 1150 /* 1151 * Check for a software override of the flow control settings, and 1152 * setup the device accordingly. If auto-negotiation is enabled, then 1153 * software will have to set the "PAUSE" bits to the correct value in 1154 * the Transmit Config Word Register (TXCW) and re-start auto- 1155 * negotiation. However, if auto-negotiation is disabled, then 1156 * software will have to manually configure the two flow control enable 1157 * bits in the CTRL register. 1158 * 1159 * The possible values of the "fc" parameter are: 1160 * 0: Flow control is completely disabled 1161 * 1: Rx flow control is enabled (we can receive pause frames, 1162 * but not send pause frames). 1163 * 2: Tx flow control is enabled (we can send pause frames but we 1164 * do not support receiving pause frames). 1165 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1166 */ 1167 switch (hw->fc.current_mode) { 1168 case e1000_fc_none: 1169 /* Flow control completely disabled by a software over-ride. */ 1170 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1171 break; 1172 case e1000_fc_rx_pause: 1173 /* 1174 * Rx Flow control is enabled and Tx Flow control is disabled 1175 * by a software over-ride. Since there really isn't a way to 1176 * advertise that we are capable of Rx Pause ONLY, we will 1177 * advertise that we support both symmetric and asymmetric Rx 1178 * PAUSE. Later, we will disable the adapter's ability to send 1179 * PAUSE frames. 1180 */ 1181 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1182 break; 1183 case e1000_fc_tx_pause: 1184 /* 1185 * Tx Flow control is enabled, and Rx Flow control is disabled, 1186 * by a software over-ride. 1187 */ 1188 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1189 break; 1190 case e1000_fc_full: 1191 /* 1192 * Flow control (both Rx and Tx) is enabled by a software 1193 * over-ride. 1194 */ 1195 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1196 break; 1197 default: 1198 DEBUGOUT("Flow control param set incorrectly\n"); 1199 ret_val = -E1000_ERR_CONFIG; 1200 goto out; 1201 break; 1202 } 1203 1204 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1205 mac->txcw = txcw; 1206 1207out: 1208 return ret_val; 1209} 1210 1211/** 1212 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1213 * @hw: pointer to the HW structure 1214 * 1215 * Sets the flow control high/low threshold (watermark) registers. If 1216 * flow control XON frame transmission is enabled, then set XON frame 1217 * transmission as well. 1218 **/ 1219s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1220{ 1221 u32 fcrtl = 0, fcrth = 0; 1222 1223 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1224 1225 /* 1226 * Set the flow control receive threshold registers. Normally, 1227 * these registers will be set to a default threshold that may be 1228 * adjusted later by the driver's runtime code. However, if the 1229 * ability to transmit pause frames is not enabled, then these 1230 * registers will be set to 0. 1231 */ 1232 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1233 /* 1234 * We need to set up the Receive Threshold high and low water 1235 * marks as well as (optionally) enabling the transmission of 1236 * XON frames. 1237 */ 1238 fcrtl = hw->fc.low_water; 1239 if (hw->fc.send_xon) 1240 fcrtl |= E1000_FCRTL_XONE; 1241 1242 fcrth = hw->fc.high_water; 1243 } 1244 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1245 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1246 1247 return E1000_SUCCESS; 1248} 1249 1250/** 1251 * e1000_set_default_fc_generic - Set flow control default values 1252 * @hw: pointer to the HW structure 1253 * 1254 * Read the EEPROM for the default values for flow control and store the 1255 * values. 1256 **/ 1257s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1258{ 1259 s32 ret_val = E1000_SUCCESS; 1260 u16 nvm_data; 1261 1262 DEBUGFUNC("e1000_set_default_fc_generic"); 1263 1264 /* 1265 * Read and store word 0x0F of the EEPROM. This word contains bits 1266 * that determine the hardware's default PAUSE (flow control) mode, 1267 * a bit that determines whether the HW defaults to enabling or 1268 * disabling auto-negotiation, and the direction of the 1269 * SW defined pins. If there is no SW over-ride of the flow 1270 * control setting, then the variable hw->fc will 1271 * be initialized based on a value in the EEPROM. 1272 */ 1273 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1274 1275 if (ret_val) { 1276 DEBUGOUT("NVM Read Error\n"); 1277 goto out; 1278 } 1279 1280 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1281 hw->fc.requested_mode = e1000_fc_none; 1282 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1283 NVM_WORD0F_ASM_DIR) 1284 hw->fc.requested_mode = e1000_fc_tx_pause; 1285 else 1286 hw->fc.requested_mode = e1000_fc_full; 1287 1288out: 1289 return ret_val; 1290} 1291 1292/** 1293 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1294 * @hw: pointer to the HW structure 1295 * 1296 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1297 * device control register to reflect the adapter settings. TFCE and RFCE 1298 * need to be explicitly set by software when a copper PHY is used because 1299 * autonegotiation is managed by the PHY rather than the MAC. Software must 1300 * also configure these bits when link is forced on a fiber connection. 1301 **/ 1302s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1303{ 1304 u32 ctrl; 1305 s32 ret_val = E1000_SUCCESS; 1306 1307 DEBUGFUNC("e1000_force_mac_fc_generic"); 1308 1309 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1310 1311 /* 1312 * Because we didn't get link via the internal auto-negotiation 1313 * mechanism (we either forced link or we got link via PHY 1314 * auto-neg), we have to manually enable/disable transmit an 1315 * receive flow control. 1316 * 1317 * The "Case" statement below enables/disable flow control 1318 * according to the "hw->fc.current_mode" parameter. 1319 * 1320 * The possible values of the "fc" parameter are: 1321 * 0: Flow control is completely disabled 1322 * 1: Rx flow control is enabled (we can receive pause 1323 * frames but not send pause frames). 1324 * 2: Tx flow control is enabled (we can send pause frames 1325 * frames but we do not receive pause frames). 1326 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1327 * other: No other values should be possible at this point. 1328 */ 1329 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1330 1331 switch (hw->fc.current_mode) { 1332 case e1000_fc_none: 1333 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1334 break; 1335 case e1000_fc_rx_pause: 1336 ctrl &= (~E1000_CTRL_TFCE); 1337 ctrl |= E1000_CTRL_RFCE; 1338 break; 1339 case e1000_fc_tx_pause: 1340 ctrl &= (~E1000_CTRL_RFCE); 1341 ctrl |= E1000_CTRL_TFCE; 1342 break; 1343 case e1000_fc_full: 1344 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1345 break; 1346 default: 1347 DEBUGOUT("Flow control param set incorrectly\n"); 1348 ret_val = -E1000_ERR_CONFIG; 1349 goto out; 1350 } 1351 1352 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1353 1354out: 1355 return ret_val; 1356} 1357 1358/** 1359 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1360 * @hw: pointer to the HW structure 1361 * 1362 * Checks the status of auto-negotiation after link up to ensure that the 1363 * speed and duplex were not forced. If the link needed to be forced, then 1364 * flow control needs to be forced also. If auto-negotiation is enabled 1365 * and did not fail, then we configure flow control based on our link 1366 * partner. 1367 **/ 1368s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1369{ 1370 struct e1000_mac_info *mac = &hw->mac; 1371 s32 ret_val = E1000_SUCCESS; 1372 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1373 u16 speed, duplex; 1374 1375 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1376 1377 /* 1378 * Check for the case where we have fiber media and auto-neg failed 1379 * so we had to force link. In this case, we need to force the 1380 * configuration of the MAC to match the "fc" parameter. 1381 */ 1382 if (mac->autoneg_failed) { 1383 if (hw->phy.media_type == e1000_media_type_fiber || 1384 hw->phy.media_type == e1000_media_type_internal_serdes) 1385 ret_val = e1000_force_mac_fc_generic(hw); 1386 } else { 1387 if (hw->phy.media_type == e1000_media_type_copper) 1388 ret_val = e1000_force_mac_fc_generic(hw); 1389 } 1390 1391 if (ret_val) { 1392 DEBUGOUT("Error forcing flow control settings\n"); 1393 goto out; 1394 } 1395 1396 /* 1397 * Check for the case where we have copper media and auto-neg is 1398 * enabled. In this case, we need to check and see if Auto-Neg 1399 * has completed, and if so, how the PHY and link partner has 1400 * flow control configured. 1401 */ 1402 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1403 /* 1404 * Read the MII Status Register and check to see if AutoNeg 1405 * has completed. We read this twice because this reg has 1406 * some "sticky" (latched) bits. 1407 */ 1408 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1409 if (ret_val) 1410 goto out; 1411 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1412 if (ret_val) 1413 goto out; 1414 1415 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1416 DEBUGOUT("Copper PHY and Auto Neg " 1417 "has not completed.\n"); 1418 goto out; 1419 } 1420 1421 /* 1422 * The AutoNeg process has completed, so we now need to 1423 * read both the Auto Negotiation Advertisement 1424 * Register (Address 4) and the Auto_Negotiation Base 1425 * Page Ability Register (Address 5) to determine how 1426 * flow control was negotiated. 1427 */ 1428 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1429 &mii_nway_adv_reg); 1430 if (ret_val) 1431 goto out; 1432 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1433 &mii_nway_lp_ability_reg); 1434 if (ret_val) 1435 goto out; 1436 1437 /* 1438 * Two bits in the Auto Negotiation Advertisement Register 1439 * (Address 4) and two bits in the Auto Negotiation Base 1440 * Page Ability Register (Address 5) determine flow control 1441 * for both the PHY and the link partner. The following 1442 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1443 * 1999, describes these PAUSE resolution bits and how flow 1444 * control is determined based upon these settings. 1445 * NOTE: DC = Don't Care 1446 * 1447 * LOCAL DEVICE | LINK PARTNER 1448 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1449 *-------|---------|-------|---------|-------------------- 1450 * 0 | 0 | DC | DC | e1000_fc_none 1451 * 0 | 1 | 0 | DC | e1000_fc_none 1452 * 0 | 1 | 1 | 0 | e1000_fc_none 1453 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1454 * 1 | 0 | 0 | DC | e1000_fc_none 1455 * 1 | DC | 1 | DC | e1000_fc_full 1456 * 1 | 1 | 0 | 0 | e1000_fc_none 1457 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1458 * 1459 * Are both PAUSE bits set to 1? If so, this implies 1460 * Symmetric Flow Control is enabled at both ends. The 1461 * ASM_DIR bits are irrelevant per the spec. 1462 * 1463 * For Symmetric Flow Control: 1464 * 1465 * LOCAL DEVICE | LINK PARTNER 1466 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1467 *-------|---------|-------|---------|-------------------- 1468 * 1 | DC | 1 | DC | E1000_fc_full 1469 * 1470 */ 1471 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1472 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1473 /* 1474 * Now we need to check if the user selected Rx ONLY 1475 * of pause frames. In this case, we had to advertise 1476 * FULL flow control because we could not advertise Rx 1477 * ONLY. Hence, we must now check to see if we need to 1478 * turn OFF the TRANSMISSION of PAUSE frames. 1479 */ 1480 if (hw->fc.requested_mode == e1000_fc_full) { 1481 hw->fc.current_mode = e1000_fc_full; 1482 DEBUGOUT("Flow Control = FULL.\r\n"); 1483 } else { 1484 hw->fc.current_mode = e1000_fc_rx_pause; 1485 DEBUGOUT("Flow Control = " 1486 "Rx PAUSE frames only.\r\n"); 1487 } 1488 } 1489 /* 1490 * For receiving PAUSE frames ONLY. 1491 * 1492 * LOCAL DEVICE | LINK PARTNER 1493 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1494 *-------|---------|-------|---------|-------------------- 1495 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1496 */ 1497 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1498 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1499 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1500 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1501 hw->fc.current_mode = e1000_fc_tx_pause; 1502 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); 1503 } 1504 /* 1505 * For transmitting PAUSE frames ONLY. 1506 * 1507 * LOCAL DEVICE | LINK PARTNER 1508 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1509 *-------|---------|-------|---------|-------------------- 1510 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1511 */ 1512 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1513 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1514 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1515 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1516 hw->fc.current_mode = e1000_fc_rx_pause; 1517 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); 1518 } else { 1519 /* 1520 * Per the IEEE spec, at this point flow control 1521 * should be disabled. 1522 */ 1523 hw->fc.current_mode = e1000_fc_none; 1524 DEBUGOUT("Flow Control = NONE.\r\n"); 1525 } 1526 1527 /* 1528 * Now we need to do one last check... If we auto- 1529 * negotiated to HALF DUPLEX, flow control should not be 1530 * enabled per IEEE 802.3 spec. 1531 */ 1532 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1533 if (ret_val) { 1534 DEBUGOUT("Error getting link speed and duplex\n"); 1535 goto out; 1536 } 1537 1538 if (duplex == HALF_DUPLEX) 1539 hw->fc.current_mode = e1000_fc_none; 1540 1541 /* 1542 * Now we call a subroutine to actually force the MAC 1543 * controller to use the correct flow control settings. 1544 */ 1545 ret_val = e1000_force_mac_fc_generic(hw); 1546 if (ret_val) { 1547 DEBUGOUT("Error forcing flow control settings\n"); 1548 goto out; 1549 } 1550 } 1551 1552out: 1553 return ret_val; 1554} 1555 1556/** 1557 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1558 * @hw: pointer to the HW structure 1559 * @speed: stores the current speed 1560 * @duplex: stores the current duplex 1561 * 1562 * Read the status register for the current speed/duplex and store the current 1563 * speed and duplex for copper connections. 1564 **/ 1565s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1566 u16 *duplex) 1567{ 1568 u32 status; 1569 1570 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1571 1572 status = E1000_READ_REG(hw, E1000_STATUS); 1573 if (status & E1000_STATUS_SPEED_1000) { 1574 *speed = SPEED_1000; 1575 DEBUGOUT("1000 Mbs, "); 1576 } else if (status & E1000_STATUS_SPEED_100) { 1577 *speed = SPEED_100; 1578 DEBUGOUT("100 Mbs, "); 1579 } else { 1580 *speed = SPEED_10; 1581 DEBUGOUT("10 Mbs, "); 1582 } 1583 1584 if (status & E1000_STATUS_FD) { 1585 *duplex = FULL_DUPLEX; 1586 DEBUGOUT("Full Duplex\n"); 1587 } else { 1588 *duplex = HALF_DUPLEX; 1589 DEBUGOUT("Half Duplex\n"); 1590 } 1591 1592 return E1000_SUCCESS; 1593} 1594 1595/** 1596 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1597 * @hw: pointer to the HW structure 1598 * @speed: stores the current speed 1599 * @duplex: stores the current duplex 1600 * 1601 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1602 * for fiber/serdes links. 1603 **/ 1604s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1605 u16 *speed, u16 *duplex) 1606{ 1607 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1608 1609 *speed = SPEED_1000; 1610 *duplex = FULL_DUPLEX; 1611 1612 return E1000_SUCCESS; 1613} 1614 1615/** 1616 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1617 * @hw: pointer to the HW structure 1618 * 1619 * Acquire the HW semaphore to access the PHY or NVM 1620 **/ 1621s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1622{ 1623 u32 swsm; 1624 s32 ret_val = E1000_SUCCESS; 1625 s32 timeout = hw->nvm.word_size + 1; 1626 s32 i = 0; 1627 1628 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1629 1630 /* Get the SW semaphore */ 1631 while (i < timeout) { 1632 swsm = E1000_READ_REG(hw, E1000_SWSM); 1633 if (!(swsm & E1000_SWSM_SMBI)) 1634 break; 1635 1636 usec_delay(50); 1637 i++; 1638 } 1639 1640 if (i == timeout) { 1641 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1642 ret_val = -E1000_ERR_NVM; 1643 goto out; 1644 } 1645 1646 /* Get the FW semaphore. */ 1647 for (i = 0; i < timeout; i++) { 1648 swsm = E1000_READ_REG(hw, E1000_SWSM); 1649 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1650 1651 /* Semaphore acquired if bit latched */ 1652 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1653 break; 1654 1655 usec_delay(50); 1656 } 1657 1658 if (i == timeout) { 1659 /* Release semaphores */ 1660 e1000_put_hw_semaphore_generic(hw); 1661 DEBUGOUT("Driver can't access the NVM\n"); 1662 ret_val = -E1000_ERR_NVM; 1663 goto out; 1664 } 1665 1666out: 1667 return ret_val; 1668} 1669 1670/** 1671 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1672 * @hw: pointer to the HW structure 1673 * 1674 * Release hardware semaphore used to access the PHY or NVM 1675 **/ 1676void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1677{ 1678 u32 swsm; 1679 1680 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1681 1682 swsm = E1000_READ_REG(hw, E1000_SWSM); 1683 1684 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1685 1686 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1687} 1688 1689/** 1690 * e1000_get_auto_rd_done_generic - Check for auto read completion 1691 * @hw: pointer to the HW structure 1692 * 1693 * Check EEPROM for Auto Read done bit. 1694 **/ 1695s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1696{ 1697 s32 i = 0; 1698 s32 ret_val = E1000_SUCCESS; 1699 1700 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1701 1702 while (i < AUTO_READ_DONE_TIMEOUT) { 1703 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1704 break; 1705 msec_delay(1); 1706 i++; 1707 } 1708 1709 if (i == AUTO_READ_DONE_TIMEOUT) { 1710 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1711 ret_val = -E1000_ERR_RESET; 1712 goto out; 1713 } 1714 1715out: 1716 return ret_val; 1717} 1718 1719/** 1720 * e1000_valid_led_default_generic - Verify a valid default LED config 1721 * @hw: pointer to the HW structure 1722 * @data: pointer to the NVM (EEPROM) 1723 * 1724 * Read the EEPROM for the current default LED configuration. If the 1725 * LED configuration is not valid, set to a valid LED configuration. 1726 **/ 1727s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1728{ 1729 s32 ret_val; 1730 1731 DEBUGFUNC("e1000_valid_led_default_generic"); 1732 1733 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1734 if (ret_val) { 1735 DEBUGOUT("NVM Read Error\n"); 1736 goto out; 1737 } 1738 1739 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1740 *data = ID_LED_DEFAULT; 1741 1742out: 1743 return ret_val; 1744} 1745 1746/** 1747 * e1000_id_led_init_generic - 1748 * @hw: pointer to the HW structure 1749 * 1750 **/ 1751s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1752{ 1753 struct e1000_mac_info *mac = &hw->mac; 1754 s32 ret_val; 1755 const u32 ledctl_mask = 0x000000FF; 1756 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1757 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1758 u16 data, i, temp; 1759 const u16 led_mask = 0x0F; 1760 1761 DEBUGFUNC("e1000_id_led_init_generic"); 1762 1763 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1764 if (ret_val) 1765 goto out; 1766 1767 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1768 mac->ledctl_mode1 = mac->ledctl_default; 1769 mac->ledctl_mode2 = mac->ledctl_default; 1770 1771 for (i = 0; i < 4; i++) { 1772 temp = (data >> (i << 2)) & led_mask; 1773 switch (temp) { 1774 case ID_LED_ON1_DEF2: 1775 case ID_LED_ON1_ON2: 1776 case ID_LED_ON1_OFF2: 1777 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1778 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1779 break; 1780 case ID_LED_OFF1_DEF2: 1781 case ID_LED_OFF1_ON2: 1782 case ID_LED_OFF1_OFF2: 1783 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1784 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1785 break; 1786 default: 1787 /* Do nothing */ 1788 break; 1789 } 1790 switch (temp) { 1791 case ID_LED_DEF1_ON2: 1792 case ID_LED_ON1_ON2: 1793 case ID_LED_OFF1_ON2: 1794 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1795 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1796 break; 1797 case ID_LED_DEF1_OFF2: 1798 case ID_LED_ON1_OFF2: 1799 case ID_LED_OFF1_OFF2: 1800 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1801 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1802 break; 1803 default: 1804 /* Do nothing */ 1805 break; 1806 } 1807 } 1808 1809out: 1810 return ret_val; 1811} 1812 1813/** 1814 * e1000_setup_led_generic - Configures SW controllable LED 1815 * @hw: pointer to the HW structure 1816 * 1817 * This prepares the SW controllable LED for use and saves the current state 1818 * of the LED so it can be later restored. 1819 **/ 1820s32 e1000_setup_led_generic(struct e1000_hw *hw) 1821{ 1822 u32 ledctl; 1823 s32 ret_val = E1000_SUCCESS; 1824 1825 DEBUGFUNC("e1000_setup_led_generic"); 1826 1827 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1828 ret_val = -E1000_ERR_CONFIG; 1829 goto out; 1830 } 1831 1832 if (hw->phy.media_type == e1000_media_type_fiber) { 1833 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1834 hw->mac.ledctl_default = ledctl; 1835 /* Turn off LED0 */ 1836 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1837 E1000_LEDCTL_LED0_BLINK | 1838 E1000_LEDCTL_LED0_MODE_MASK); 1839 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1840 E1000_LEDCTL_LED0_MODE_SHIFT); 1841 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1842 } else if (hw->phy.media_type == e1000_media_type_copper) { 1843 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1844 } 1845 1846out: 1847 return ret_val; 1848} 1849 1850/** 1851 * e1000_cleanup_led_generic - Set LED config to default operation 1852 * @hw: pointer to the HW structure 1853 * 1854 * Remove the current LED configuration and set the LED configuration 1855 * to the default value, saved from the EEPROM. 1856 **/ 1857s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1858{ 1859 DEBUGFUNC("e1000_cleanup_led_generic"); 1860 1861 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1862 return E1000_SUCCESS; 1863} 1864 1865/** 1866 * e1000_blink_led_generic - Blink LED 1867 * @hw: pointer to the HW structure 1868 * 1869 * Blink the LEDs which are set to be on. 1870 **/ 1871s32 e1000_blink_led_generic(struct e1000_hw *hw) 1872{ 1873 u32 ledctl_blink = 0; 1874 u32 i; 1875 1876 DEBUGFUNC("e1000_blink_led_generic"); 1877 1878 if (hw->phy.media_type == e1000_media_type_fiber) { 1879 /* always blink LED0 for PCI-E fiber */ 1880 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1881 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1882 } else { 1883 /* 1884 * set the blink bit for each LED that's "on" (0x0E) 1885 * in ledctl_mode2 1886 */ 1887 ledctl_blink = hw->mac.ledctl_mode2; 1888 for (i = 0; i < 4; i++) 1889 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1890 E1000_LEDCTL_MODE_LED_ON) 1891 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1892 (i * 8)); 1893 } 1894 1895 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1896 1897 return E1000_SUCCESS; 1898} 1899 1900/** 1901 * e1000_led_on_generic - Turn LED on 1902 * @hw: pointer to the HW structure 1903 * 1904 * Turn LED on. 1905 **/ 1906s32 e1000_led_on_generic(struct e1000_hw *hw) 1907{ 1908 u32 ctrl; 1909 1910 DEBUGFUNC("e1000_led_on_generic"); 1911 1912 switch (hw->phy.media_type) { 1913 case e1000_media_type_fiber: 1914 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1915 ctrl &= ~E1000_CTRL_SWDPIN0; 1916 ctrl |= E1000_CTRL_SWDPIO0; 1917 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1918 break; 1919 case e1000_media_type_copper: 1920 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1921 break; 1922 default: 1923 break; 1924 } 1925 1926 return E1000_SUCCESS; 1927} 1928 1929/** 1930 * e1000_led_off_generic - Turn LED off 1931 * @hw: pointer to the HW structure 1932 * 1933 * Turn LED off. 1934 **/ 1935s32 e1000_led_off_generic(struct e1000_hw *hw) 1936{ 1937 u32 ctrl; 1938 1939 DEBUGFUNC("e1000_led_off_generic"); 1940 1941 switch (hw->phy.media_type) { 1942 case e1000_media_type_fiber: 1943 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1944 ctrl |= E1000_CTRL_SWDPIN0; 1945 ctrl |= E1000_CTRL_SWDPIO0; 1946 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1947 break; 1948 case e1000_media_type_copper: 1949 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1950 break; 1951 default: 1952 break; 1953 } 1954 1955 return E1000_SUCCESS; 1956} 1957 1958/** 1959 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1960 * @hw: pointer to the HW structure 1961 * @no_snoop: bitmap of snoop events 1962 * 1963 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1964 **/ 1965void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1966{ 1967 u32 gcr; 1968 1969 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1970 1971 if (hw->bus.type != e1000_bus_type_pci_express) 1972 goto out; 1973 1974 if (no_snoop) { 1975 gcr = E1000_READ_REG(hw, E1000_GCR); 1976 gcr &= ~(PCIE_NO_SNOOP_ALL); 1977 gcr |= no_snoop; 1978 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1979 } 1980out: 1981 return; 1982} 1983 1984/** 1985 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1986 * @hw: pointer to the HW structure 1987 * 1988 * Returns E1000_SUCCESS if successful, else returns -10 1989 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1990 * the master requests to be disabled. 1991 * 1992 * Disables PCI-Express master access and verifies there are no pending 1993 * requests. 1994 **/ 1995s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1996{ 1997 u32 ctrl; 1998 s32 timeout = MASTER_DISABLE_TIMEOUT; 1999 s32 ret_val = E1000_SUCCESS; 2000 2001 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2002 2003 if (hw->bus.type != e1000_bus_type_pci_express) 2004 goto out; 2005 2006 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2007 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2008 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2009 2010 while (timeout) { 2011 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2012 E1000_STATUS_GIO_MASTER_ENABLE)) 2013 break; 2014 usec_delay(100); 2015 timeout--; 2016 } 2017 2018 if (!timeout) { 2019 DEBUGOUT("Master requests are pending.\n"); 2020 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2021 } 2022 2023out: 2024 return ret_val; 2025} 2026 2027/** 2028 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2029 * @hw: pointer to the HW structure 2030 * 2031 * Reset the Adaptive Interframe Spacing throttle to default values. 2032 **/ 2033void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2034{ 2035 struct e1000_mac_info *mac = &hw->mac; 2036 2037 DEBUGFUNC("e1000_reset_adaptive_generic"); 2038 2039 if (!mac->adaptive_ifs) { 2040 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2041 goto out; 2042 } 2043 2044 mac->current_ifs_val = 0; 2045 mac->ifs_min_val = IFS_MIN; 2046 mac->ifs_max_val = IFS_MAX; 2047 mac->ifs_step_size = IFS_STEP; 2048 mac->ifs_ratio = IFS_RATIO; 2049 2050 mac->in_ifs_mode = FALSE; 2051 E1000_WRITE_REG(hw, E1000_AIT, 0); 2052out: 2053 return; 2054} 2055 2056/** 2057 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2058 * @hw: pointer to the HW structure 2059 * 2060 * Update the Adaptive Interframe Spacing Throttle value based on the 2061 * time between transmitted packets and time between collisions. 2062 **/ 2063void e1000_update_adaptive_generic(struct e1000_hw *hw) 2064{ 2065 struct e1000_mac_info *mac = &hw->mac; 2066 2067 DEBUGFUNC("e1000_update_adaptive_generic"); 2068 2069 if (!mac->adaptive_ifs) { 2070 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2071 goto out; 2072 } 2073 2074 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2075 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2076 mac->in_ifs_mode = TRUE; 2077 if (mac->current_ifs_val < mac->ifs_max_val) { 2078 if (!mac->current_ifs_val) 2079 mac->current_ifs_val = mac->ifs_min_val; 2080 else 2081 mac->current_ifs_val += 2082 mac->ifs_step_size; 2083 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2084 } 2085 } 2086 } else { 2087 if (mac->in_ifs_mode && 2088 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2089 mac->current_ifs_val = 0; 2090 mac->in_ifs_mode = FALSE; 2091 E1000_WRITE_REG(hw, E1000_AIT, 0); 2092 } 2093 } 2094out: 2095 return; 2096} 2097 2098/** 2099 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2100 * @hw: pointer to the HW structure 2101 * 2102 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2103 * set, which is forced to MDI mode only. 2104 **/ 2105static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2106{ 2107 s32 ret_val = E1000_SUCCESS; 2108 2109 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2110 2111 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2112 DEBUGOUT("Invalid MDI setting detected\n"); 2113 hw->phy.mdix = 1; 2114 ret_val = -E1000_ERR_CONFIG; 2115 goto out; 2116 } 2117 2118out: 2119 return ret_val; 2120} 2121 2122/** 2123 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2124 * @hw: pointer to the HW structure 2125 * @reg: 32bit register offset such as E1000_SCTL 2126 * @offset: register offset to write to 2127 * @data: data to write at register offset 2128 * 2129 * Writes an address/data control type register. There are several of these 2130 * and they all have the format address << 8 | data and bit 31 is polled for 2131 * completion. 2132 **/ 2133s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2134 u32 offset, u8 data) 2135{ 2136 u32 i, regvalue = 0; 2137 s32 ret_val = E1000_SUCCESS; 2138 2139 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2140 2141 /* Set up the address and data */ 2142 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2143 E1000_WRITE_REG(hw, reg, regvalue); 2144 2145 /* Poll the ready bit to see if the MDI read completed */ 2146 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2147 usec_delay(5); 2148 regvalue = E1000_READ_REG(hw, reg); 2149 if (regvalue & E1000_GEN_CTL_READY) 2150 break; 2151 } 2152 if (!(regvalue & E1000_GEN_CTL_READY)) { 2153 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2154 ret_val = -E1000_ERR_PHY; 2155 goto out; 2156 } 2157 2158out: 2159 return ret_val; 2160} 2161