e1000_82571.c revision 228386
1177867Sjfv/****************************************************************************** 2169240Sjfv 3228386Sjfv Copyright (c) 2001-2011, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 228386 2011-12-10 06:55:02Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82571EB Gigabit Ethernet Controller 37185353Sjfv * 82571EB Gigabit Ethernet Controller (Copper) 38185353Sjfv * 82571EB Gigabit Ethernet Controller (Fiber) 39185353Sjfv * 82571EB Dual Port Gigabit Mezzanine Adapter 40185353Sjfv * 82571EB Quad Port Gigabit Mezzanine Adapter 41185353Sjfv * 82571PT Gigabit PT Quad Port Server ExpressModule 42185353Sjfv * 82572EI Gigabit Ethernet Controller (Copper) 43185353Sjfv * 82572EI Gigabit Ethernet Controller (Fiber) 44185353Sjfv * 82572EI Gigabit Ethernet Controller 45185353Sjfv * 82573V Gigabit Ethernet Controller (Copper) 46185353Sjfv * 82573E Gigabit Ethernet Controller (Copper) 47185353Sjfv * 82573L Gigabit Ethernet Controller 48185353Sjfv * 82574L Gigabit Network Connection 49194865Sjfv * 82583V Gigabit Network Connection 50169240Sjfv */ 51169240Sjfv 52169589Sjfv#include "e1000_api.h" 53169240Sjfv 54177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 55177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 56177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 57177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 58177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw); 59177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 60228386Sjfv u16 words, u16 *data); 61177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 62177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 63177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 64177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 65228386Sjfv bool active); 66177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw); 67177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw); 68177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw); 69181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw); 71177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw); 72177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 73190872Sjfvstatic s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 74177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 75177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 76177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 77169589Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 78169240Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 79169240Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 80169589Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 81213234Sjfvstatic s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); 82213234Sjfvstatic void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 83213234Sjfvstatic s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 84213234Sjfvstatic void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 85218588Sjfvstatic s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, 86228386Sjfv bool active); 87218588Sjfvstatic s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, 88228386Sjfv bool active); 89169240Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 90169240Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 91228386Sjfv u16 words, u16 *data); 92177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 93177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 94169240Sjfv 95169240Sjfv/** 96169240Sjfv * e1000_init_phy_params_82571 - Init PHY func ptrs. 97169589Sjfv * @hw: pointer to the HW structure 98169240Sjfv **/ 99177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 100169240Sjfv{ 101169240Sjfv struct e1000_phy_info *phy = &hw->phy; 102169240Sjfv s32 ret_val = E1000_SUCCESS; 103169240Sjfv 104169240Sjfv DEBUGFUNC("e1000_init_phy_params_82571"); 105169240Sjfv 106173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 107185353Sjfv phy->type = e1000_phy_none; 108169240Sjfv goto out; 109169240Sjfv } 110169240Sjfv 111228386Sjfv phy->addr = 1; 112228386Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 113228386Sjfv phy->reset_delay_us = 100; 114169240Sjfv 115228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 116228386Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 117228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 118228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119228386Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 120228386Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82571; 121169240Sjfv 122169240Sjfv switch (hw->mac.type) { 123169240Sjfv case e1000_82571: 124169240Sjfv case e1000_82572: 125228386Sjfv phy->type = e1000_phy_igp_2; 126228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 127228386Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 128228386Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 129177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 130228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 131228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 132228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 133228386Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 134228386Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 135169240Sjfv break; 136169240Sjfv case e1000_82573: 137228386Sjfv phy->type = e1000_phy_m88; 138228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 139228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 140228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 141228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 142177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 143228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 144228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_m88; 145228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_m88; 146228386Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 147228386Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 148169240Sjfv break; 149200243Sjfv case e1000_82574: 150194865Sjfv case e1000_82583: 151218588Sjfv E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex); 152213234Sjfv 153228386Sjfv phy->type = e1000_phy_bm; 154228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 155228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 156228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 157228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 158178523Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 159228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 160228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm2; 161228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm2; 162228386Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82574; 163228386Sjfv phy->ops.release = e1000_put_hw_semaphore_82574; 164228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 165228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 166218588Sjfv break; 167218588Sjfv default: 168218588Sjfv ret_val = -E1000_ERR_PHY; 169218588Sjfv goto out; 170218588Sjfv break; 171218588Sjfv } 172178523Sjfv 173218588Sjfv /* This can only be done after all function pointers are setup. */ 174218588Sjfv ret_val = e1000_get_phy_id_82571(hw); 175218588Sjfv if (ret_val) { 176218588Sjfv DEBUGOUT("Error getting PHY ID\n"); 177218588Sjfv goto out; 178218588Sjfv } 179218588Sjfv 180218588Sjfv /* Verify phy id */ 181218588Sjfv switch (hw->mac.type) { 182218588Sjfv case e1000_82571: 183218588Sjfv case e1000_82572: 184218588Sjfv if (phy->id != IGP01E1000_I_PHY_ID) 185178523Sjfv ret_val = -E1000_ERR_PHY; 186178523Sjfv break; 187218588Sjfv case e1000_82573: 188218588Sjfv if (phy->id != M88E1111_I_PHY_ID) 189218588Sjfv ret_val = -E1000_ERR_PHY; 190218588Sjfv break; 191218588Sjfv case e1000_82574: 192218588Sjfv case e1000_82583: 193218588Sjfv if (phy->id != BME1000_E_PHY_ID_R2) 194218588Sjfv ret_val = -E1000_ERR_PHY; 195218588Sjfv break; 196169240Sjfv default: 197169240Sjfv ret_val = -E1000_ERR_PHY; 198169240Sjfv break; 199169240Sjfv } 200169240Sjfv 201218588Sjfv if (ret_val) 202218588Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 203218588Sjfv 204169240Sjfvout: 205169240Sjfv return ret_val; 206169240Sjfv} 207169240Sjfv 208169240Sjfv/** 209169240Sjfv * e1000_init_nvm_params_82571 - Init NVM func ptrs. 210169589Sjfv * @hw: pointer to the HW structure 211169240Sjfv **/ 212177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 213169240Sjfv{ 214169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 215169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 216169240Sjfv u16 size; 217169240Sjfv 218169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82571"); 219169240Sjfv 220185353Sjfv nvm->opcode_bits = 8; 221185353Sjfv nvm->delay_usec = 1; 222169240Sjfv switch (nvm->override) { 223169240Sjfv case e1000_nvm_override_spi_large: 224185353Sjfv nvm->page_size = 32; 225169240Sjfv nvm->address_bits = 16; 226169240Sjfv break; 227169240Sjfv case e1000_nvm_override_spi_small: 228185353Sjfv nvm->page_size = 8; 229169240Sjfv nvm->address_bits = 8; 230169240Sjfv break; 231169240Sjfv default: 232185353Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 233169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 234169240Sjfv break; 235169240Sjfv } 236169240Sjfv 237169240Sjfv switch (hw->mac.type) { 238169240Sjfv case e1000_82573: 239178523Sjfv case e1000_82574: 240194865Sjfv case e1000_82583: 241169240Sjfv if (((eecd >> 15) & 0x3) == 0x3) { 242169240Sjfv nvm->type = e1000_nvm_flash_hw; 243169240Sjfv nvm->word_size = 2048; 244173788Sjfv /* 245173788Sjfv * Autonomous Flash update bit must be cleared due 246169240Sjfv * to Flash update issue. 247169240Sjfv */ 248169240Sjfv eecd &= ~E1000_EECD_AUPDEN; 249169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 250169240Sjfv break; 251169240Sjfv } 252169240Sjfv /* Fall Through */ 253169240Sjfv default: 254185353Sjfv nvm->type = e1000_nvm_eeprom_spi; 255169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 256228386Sjfv E1000_EECD_SIZE_EX_SHIFT); 257173788Sjfv /* 258173788Sjfv * Added to a constant, "size" becomes the left-shift value 259169240Sjfv * for setting word_size. 260169240Sjfv */ 261169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 262173788Sjfv 263173788Sjfv /* EEPROM access above 16k is unsupported */ 264173788Sjfv if (size > 14) 265173788Sjfv size = 14; 266228386Sjfv nvm->word_size = 1 << size; 267169240Sjfv break; 268169240Sjfv } 269169240Sjfv 270169240Sjfv /* Function Pointers */ 271213234Sjfv switch (hw->mac.type) { 272213234Sjfv case e1000_82574: 273213234Sjfv case e1000_82583: 274213234Sjfv nvm->ops.acquire = e1000_get_hw_semaphore_82574; 275213234Sjfv nvm->ops.release = e1000_put_hw_semaphore_82574; 276213234Sjfv break; 277213234Sjfv default: 278213234Sjfv nvm->ops.acquire = e1000_acquire_nvm_82571; 279213234Sjfv nvm->ops.release = e1000_release_nvm_82571; 280213234Sjfv break; 281213234Sjfv } 282228386Sjfv nvm->ops.read = e1000_read_nvm_eerd; 283228386Sjfv nvm->ops.update = e1000_update_nvm_checksum_82571; 284228386Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82571; 285177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82571; 286228386Sjfv nvm->ops.write = e1000_write_nvm_82571; 287169240Sjfv 288169240Sjfv return E1000_SUCCESS; 289169240Sjfv} 290169240Sjfv 291169240Sjfv/** 292169240Sjfv * e1000_init_mac_params_82571 - Init MAC func ptrs. 293169589Sjfv * @hw: pointer to the HW structure 294169240Sjfv **/ 295177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 296169240Sjfv{ 297169240Sjfv struct e1000_mac_info *mac = &hw->mac; 298194865Sjfv u32 swsm = 0; 299194865Sjfv u32 swsm2 = 0; 300194865Sjfv bool force_clear_smbi = FALSE; 301169240Sjfv 302169240Sjfv DEBUGFUNC("e1000_init_mac_params_82571"); 303169240Sjfv 304200243Sjfv /* Set media type and media-dependent function pointers */ 305169240Sjfv switch (hw->device_id) { 306169240Sjfv case E1000_DEV_ID_82571EB_FIBER: 307169240Sjfv case E1000_DEV_ID_82572EI_FIBER: 308169240Sjfv case E1000_DEV_ID_82571EB_QUAD_FIBER: 309173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 310200243Sjfv mac->ops.setup_physical_interface = 311200243Sjfv e1000_setup_fiber_serdes_link_82571; 312200243Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 313200243Sjfv mac->ops.get_link_up_info = 314200243Sjfv e1000_get_speed_and_duplex_fiber_serdes_generic; 315169240Sjfv break; 316169240Sjfv case E1000_DEV_ID_82571EB_SERDES: 317169589Sjfv case E1000_DEV_ID_82571EB_SERDES_DUAL: 318169589Sjfv case E1000_DEV_ID_82571EB_SERDES_QUAD: 319169240Sjfv case E1000_DEV_ID_82572EI_SERDES: 320173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 321200243Sjfv mac->ops.setup_physical_interface = 322200243Sjfv e1000_setup_fiber_serdes_link_82571; 323200243Sjfv mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 324200243Sjfv mac->ops.get_link_up_info = 325200243Sjfv e1000_get_speed_and_duplex_fiber_serdes_generic; 326169240Sjfv break; 327169240Sjfv default: 328173788Sjfv hw->phy.media_type = e1000_media_type_copper; 329200243Sjfv mac->ops.setup_physical_interface = 330200243Sjfv e1000_setup_copper_link_82571; 331200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 332200243Sjfv mac->ops.get_link_up_info = 333200243Sjfv e1000_get_speed_and_duplex_copper_generic; 334169240Sjfv break; 335169240Sjfv } 336169240Sjfv 337169240Sjfv /* Set mta register count */ 338169240Sjfv mac->mta_reg_count = 128; 339169240Sjfv /* Set rar entry count */ 340169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 341169240Sjfv /* Set if part includes ASF firmware */ 342169240Sjfv mac->asf_firmware_present = TRUE; 343200243Sjfv /* Adaptive IFS supported */ 344200243Sjfv mac->adaptive_ifs = TRUE; 345169240Sjfv 346169240Sjfv /* Function pointers */ 347169240Sjfv 348169240Sjfv /* bus type/speed/width */ 349177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 350169240Sjfv /* reset */ 351177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82571; 352169240Sjfv /* hw initialization */ 353177867Sjfv mac->ops.init_hw = e1000_init_hw_82571; 354169240Sjfv /* link setup */ 355177867Sjfv mac->ops.setup_link = e1000_setup_link_82571; 356169240Sjfv /* multicast address update */ 357190872Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 358169240Sjfv /* writing VFTA */ 359177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 360169240Sjfv /* clearing VFTA */ 361177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_82571; 362173788Sjfv /* read mac address */ 363177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 364190872Sjfv /* ID LED init */ 365190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 366169240Sjfv /* setup LED */ 367177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 368169240Sjfv /* cleanup LED */ 369177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 370200243Sjfv /* turn off LED */ 371200243Sjfv mac->ops.led_off = e1000_led_off_generic; 372200243Sjfv /* clear hardware counters */ 373200243Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 374200243Sjfv 375200243Sjfv /* MAC-specific function pointers */ 376181027Sjfv switch (hw->mac.type) { 377200243Sjfv case e1000_82573: 378200243Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 379200243Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 380200243Sjfv mac->ops.led_on = e1000_led_on_generic; 381228386Sjfv mac->ops.blink_led = e1000_blink_led_generic; 382205869Sjfv 383205869Sjfv /* FWSM register */ 384205869Sjfv mac->has_fwsm = TRUE; 385205869Sjfv /* 386205869Sjfv * ARC supported; valid only if manageability features are 387205869Sjfv * enabled. 388205869Sjfv */ 389228386Sjfv mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) & 390228386Sjfv E1000_FWSM_MODE_MASK) ? TRUE : FALSE; 391200243Sjfv break; 392181027Sjfv case e1000_82574: 393194865Sjfv case e1000_82583: 394200243Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 395200243Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 396181027Sjfv mac->ops.led_on = e1000_led_on_82574; 397181027Sjfv break; 398181027Sjfv default: 399200243Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 400181027Sjfv mac->ops.led_on = e1000_led_on_generic; 401228386Sjfv mac->ops.blink_led = e1000_blink_led_generic; 402205869Sjfv 403205869Sjfv /* FWSM register */ 404205869Sjfv mac->has_fwsm = TRUE; 405181027Sjfv break; 406181027Sjfv } 407169240Sjfv 408194865Sjfv /* 409194865Sjfv * Ensure that the inter-port SWSM.SMBI lock bit is clear before 410194865Sjfv * first NVM or PHY acess. This should be done for single-port 411194865Sjfv * devices, and for one port only on dual-port devices so that 412194865Sjfv * for those devices we can still use the SMBI lock to synchronize 413194865Sjfv * inter-port accesses to the PHY & NVM. 414194865Sjfv */ 415194865Sjfv switch (hw->mac.type) { 416194865Sjfv case e1000_82571: 417194865Sjfv case e1000_82572: 418194865Sjfv swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 419194865Sjfv 420194865Sjfv if (!(swsm2 & E1000_SWSM2_LOCK)) { 421194865Sjfv /* Only do this for the first interface on this card */ 422228386Sjfv E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | 423228386Sjfv E1000_SWSM2_LOCK); 424194865Sjfv force_clear_smbi = TRUE; 425194865Sjfv } else 426194865Sjfv force_clear_smbi = FALSE; 427194865Sjfv break; 428194865Sjfv default: 429194865Sjfv force_clear_smbi = TRUE; 430194865Sjfv break; 431194865Sjfv } 432194865Sjfv 433194865Sjfv if (force_clear_smbi) { 434194865Sjfv /* Make sure SWSM.SMBI is clear */ 435194865Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 436194865Sjfv if (swsm & E1000_SWSM_SMBI) { 437194865Sjfv /* This bit should not be set on a first interface, and 438194865Sjfv * indicates that the bootagent or EFI code has 439194865Sjfv * improperly left this bit enabled 440194865Sjfv */ 441194865Sjfv DEBUGOUT("Please update your 82571 Bootagent\n"); 442194865Sjfv } 443194865Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 444194865Sjfv } 445194865Sjfv 446194865Sjfv /* 447194865Sjfv * Initialze device specific counter of SMBI acquisition 448194865Sjfv * timeouts. 449194865Sjfv */ 450194865Sjfv hw->dev_spec._82571.smb_counter = 0; 451194865Sjfv 452200243Sjfv return E1000_SUCCESS; 453169240Sjfv} 454169240Sjfv 455169240Sjfv/** 456169240Sjfv * e1000_init_function_pointers_82571 - Init func ptrs. 457169589Sjfv * @hw: pointer to the HW structure 458169240Sjfv * 459185353Sjfv * Called to initialize all function pointers and parameters. 460169240Sjfv **/ 461173788Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 462169240Sjfv{ 463169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82571"); 464169240Sjfv 465177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82571; 466177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 467177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82571; 468169240Sjfv} 469169240Sjfv 470169240Sjfv/** 471169240Sjfv * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 472169589Sjfv * @hw: pointer to the HW structure 473169240Sjfv * 474169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 475169240Sjfv * revision in the hardware structure. 476169240Sjfv **/ 477173788Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 478169240Sjfv{ 479169240Sjfv struct e1000_phy_info *phy = &hw->phy; 480169240Sjfv s32 ret_val = E1000_SUCCESS; 481178523Sjfv u16 phy_id = 0; 482169240Sjfv 483169240Sjfv DEBUGFUNC("e1000_get_phy_id_82571"); 484169240Sjfv 485169240Sjfv switch (hw->mac.type) { 486169240Sjfv case e1000_82571: 487169240Sjfv case e1000_82572: 488173788Sjfv /* 489173788Sjfv * The 82571 firmware may still be configuring the PHY. 490169240Sjfv * In this case, we cannot access the PHY until the 491169240Sjfv * configuration is done. So we explicitly set the 492173788Sjfv * PHY ID. 493173788Sjfv */ 494169240Sjfv phy->id = IGP01E1000_I_PHY_ID; 495169240Sjfv break; 496169240Sjfv case e1000_82573: 497169240Sjfv ret_val = e1000_get_phy_id(hw); 498169240Sjfv break; 499178523Sjfv case e1000_82574: 500194865Sjfv case e1000_82583: 501178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 502178523Sjfv if (ret_val) 503178523Sjfv goto out; 504178523Sjfv 505178523Sjfv phy->id = (u32)(phy_id << 16); 506178523Sjfv usec_delay(20); 507178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 508178523Sjfv if (ret_val) 509178523Sjfv goto out; 510178523Sjfv 511178523Sjfv phy->id |= (u32)(phy_id); 512178523Sjfv phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 513178523Sjfv break; 514169240Sjfv default: 515169240Sjfv ret_val = -E1000_ERR_PHY; 516169240Sjfv break; 517169240Sjfv } 518178523Sjfvout: 519169240Sjfv return ret_val; 520169240Sjfv} 521169240Sjfv 522169240Sjfv/** 523169589Sjfv * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 524169589Sjfv * @hw: pointer to the HW structure 525169589Sjfv * 526169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 527169589Sjfv **/ 528200243Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 529169589Sjfv{ 530169589Sjfv u32 swsm; 531169589Sjfv s32 ret_val = E1000_SUCCESS; 532194865Sjfv s32 sw_timeout = hw->nvm.word_size + 1; 533194865Sjfv s32 fw_timeout = hw->nvm.word_size + 1; 534169589Sjfv s32 i = 0; 535169589Sjfv 536169589Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82571"); 537169589Sjfv 538194865Sjfv /* 539194865Sjfv * If we have timedout 3 times on trying to acquire 540194865Sjfv * the inter-port SMBI semaphore, there is old code 541194865Sjfv * operating on the other port, and it is not 542194865Sjfv * releasing SMBI. Modify the number of times that 543194865Sjfv * we try for the semaphore to interwork with this 544194865Sjfv * older code. 545194865Sjfv */ 546194865Sjfv if (hw->dev_spec._82571.smb_counter > 2) 547194865Sjfv sw_timeout = 1; 548194865Sjfv 549194865Sjfv /* Get the SW semaphore */ 550194865Sjfv while (i < sw_timeout) { 551194865Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 552194865Sjfv if (!(swsm & E1000_SWSM_SMBI)) 553194865Sjfv break; 554194865Sjfv 555194865Sjfv usec_delay(50); 556194865Sjfv i++; 557194865Sjfv } 558194865Sjfv 559194865Sjfv if (i == sw_timeout) { 560194865Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 561194865Sjfv hw->dev_spec._82571.smb_counter++; 562194865Sjfv } 563169589Sjfv /* Get the FW semaphore. */ 564194865Sjfv for (i = 0; i < fw_timeout; i++) { 565169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 566169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 567169589Sjfv 568169589Sjfv /* Semaphore acquired if bit latched */ 569169589Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 570169589Sjfv break; 571169589Sjfv 572169589Sjfv usec_delay(50); 573169589Sjfv } 574169589Sjfv 575194865Sjfv if (i == fw_timeout) { 576169589Sjfv /* Release semaphores */ 577194865Sjfv e1000_put_hw_semaphore_82571(hw); 578169589Sjfv DEBUGOUT("Driver can't access the NVM\n"); 579169589Sjfv ret_val = -E1000_ERR_NVM; 580169589Sjfv goto out; 581169589Sjfv } 582169589Sjfv 583169589Sjfvout: 584169589Sjfv return ret_val; 585169589Sjfv} 586169589Sjfv 587169589Sjfv/** 588169589Sjfv * e1000_put_hw_semaphore_82571 - Release hardware semaphore 589169589Sjfv * @hw: pointer to the HW structure 590169589Sjfv * 591169589Sjfv * Release hardware semaphore used to access the PHY or NVM 592169589Sjfv **/ 593200243Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 594169589Sjfv{ 595169589Sjfv u32 swsm; 596169589Sjfv 597194865Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 598169589Sjfv 599169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 600169589Sjfv 601194865Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 602169589Sjfv 603169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 604169589Sjfv} 605169589Sjfv 606169589Sjfv/** 607213234Sjfv * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 608213234Sjfv * @hw: pointer to the HW structure 609213234Sjfv * 610213234Sjfv * Acquire the HW semaphore during reset. 611213234Sjfv * 612213234Sjfv **/ 613213234Sjfvstatic s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 614213234Sjfv{ 615213234Sjfv u32 extcnf_ctrl; 616213234Sjfv s32 ret_val = E1000_SUCCESS; 617213234Sjfv s32 i = 0; 618213234Sjfv 619213234Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82573"); 620213234Sjfv 621213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 622213234Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 623213234Sjfv do { 624213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 625213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 626213234Sjfv 627213234Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 628213234Sjfv break; 629213234Sjfv 630213234Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 631213234Sjfv 632213234Sjfv msec_delay(2); 633213234Sjfv i++; 634213234Sjfv } while (i < MDIO_OWNERSHIP_TIMEOUT); 635213234Sjfv 636213234Sjfv if (i == MDIO_OWNERSHIP_TIMEOUT) { 637213234Sjfv /* Release semaphores */ 638213234Sjfv e1000_put_hw_semaphore_82573(hw); 639213234Sjfv DEBUGOUT("Driver can't access the PHY\n"); 640213234Sjfv ret_val = -E1000_ERR_PHY; 641213234Sjfv goto out; 642213234Sjfv } 643213234Sjfv 644213234Sjfvout: 645213234Sjfv return ret_val; 646213234Sjfv} 647213234Sjfv 648213234Sjfv/** 649213234Sjfv * e1000_put_hw_semaphore_82573 - Release hardware semaphore 650213234Sjfv * @hw: pointer to the HW structure 651213234Sjfv * 652213234Sjfv * Release hardware semaphore used during reset. 653213234Sjfv * 654213234Sjfv **/ 655213234Sjfvstatic void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 656213234Sjfv{ 657213234Sjfv u32 extcnf_ctrl; 658213234Sjfv 659213234Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82573"); 660213234Sjfv 661213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 662213234Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 663213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 664213234Sjfv} 665213234Sjfv 666213234Sjfv/** 667213234Sjfv * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 668213234Sjfv * @hw: pointer to the HW structure 669213234Sjfv * 670213234Sjfv * Acquire the HW semaphore to access the PHY or NVM. 671213234Sjfv * 672213234Sjfv **/ 673213234Sjfvstatic s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 674213234Sjfv{ 675214646Sjfv s32 ret_val; 676214646Sjfv 677213234Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82574"); 678213234Sjfv 679213234Sjfv E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex); 680214646Sjfv ret_val = e1000_get_hw_semaphore_82573(hw); 681214646Sjfv if (ret_val) 682214646Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 683214646Sjfv return ret_val; 684213234Sjfv} 685213234Sjfv 686213234Sjfv/** 687213234Sjfv * e1000_put_hw_semaphore_82574 - Release hardware semaphore 688213234Sjfv * @hw: pointer to the HW structure 689213234Sjfv * 690213234Sjfv * Release hardware semaphore used to access the PHY or NVM 691213234Sjfv * 692213234Sjfv **/ 693213234Sjfvstatic void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 694213234Sjfv{ 695213234Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82574"); 696213234Sjfv 697213234Sjfv e1000_put_hw_semaphore_82573(hw); 698213234Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 699213234Sjfv} 700213234Sjfv 701213234Sjfv/** 702218588Sjfv * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 703218588Sjfv * @hw: pointer to the HW structure 704218588Sjfv * @active: TRUE to enable LPLU, FALSE to disable 705218588Sjfv * 706218588Sjfv * Sets the LPLU D0 state according to the active flag. 707218588Sjfv * LPLU will not be activated unless the 708218588Sjfv * device autonegotiation advertisement meets standards of 709218588Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 710218588Sjfv * This is a function pointer entry point only called by 711218588Sjfv * PHY setup routines. 712218588Sjfv **/ 713218588Sjfvstatic s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 714218588Sjfv{ 715218588Sjfv u16 data = E1000_READ_REG(hw, E1000_POEMB); 716218588Sjfv 717218588Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82574"); 718218588Sjfv 719218588Sjfv if (active) 720218588Sjfv data |= E1000_PHY_CTRL_D0A_LPLU; 721218588Sjfv else 722218588Sjfv data &= ~E1000_PHY_CTRL_D0A_LPLU; 723218588Sjfv 724218588Sjfv E1000_WRITE_REG(hw, E1000_POEMB, data); 725218588Sjfv return E1000_SUCCESS; 726218588Sjfv} 727218588Sjfv 728218588Sjfv/** 729218588Sjfv * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 730218588Sjfv * @hw: pointer to the HW structure 731218588Sjfv * @active: boolean used to enable/disable lplu 732218588Sjfv * 733218588Sjfv * The low power link up (lplu) state is set to the power management level D3 734218588Sjfv * when active is TRUE, else clear lplu for D3. LPLU 735218588Sjfv * is used during Dx states where the power conservation is most important. 736218588Sjfv * During driver activity, SmartSpeed should be enabled so performance is 737218588Sjfv * maintained. 738218588Sjfv **/ 739218588Sjfvstatic s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 740218588Sjfv{ 741218588Sjfv u16 data = E1000_READ_REG(hw, E1000_POEMB); 742218588Sjfv 743218588Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_82574"); 744218588Sjfv 745218588Sjfv if (!active) { 746218588Sjfv data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 747218588Sjfv } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 748228386Sjfv (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 749228386Sjfv (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 750218588Sjfv data |= E1000_PHY_CTRL_NOND0A_LPLU; 751218588Sjfv } 752218588Sjfv 753218588Sjfv E1000_WRITE_REG(hw, E1000_POEMB, data); 754218588Sjfv return E1000_SUCCESS; 755218588Sjfv} 756218588Sjfv 757218588Sjfv/** 758169240Sjfv * e1000_acquire_nvm_82571 - Request for access to the EEPROM 759169589Sjfv * @hw: pointer to the HW structure 760169240Sjfv * 761169240Sjfv * To gain access to the EEPROM, first we must obtain a hardware semaphore. 762169240Sjfv * Then for non-82573 hardware, set the EEPROM access request bit and wait 763169240Sjfv * for EEPROM access grant bit. If the access grant bit is not set, release 764169240Sjfv * hardware semaphore. 765169240Sjfv **/ 766177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 767169240Sjfv{ 768169240Sjfv s32 ret_val; 769169240Sjfv 770169240Sjfv DEBUGFUNC("e1000_acquire_nvm_82571"); 771169240Sjfv 772169589Sjfv ret_val = e1000_get_hw_semaphore_82571(hw); 773169240Sjfv if (ret_val) 774169240Sjfv goto out; 775169240Sjfv 776190872Sjfv switch (hw->mac.type) { 777200243Sjfv case e1000_82573: 778190872Sjfv break; 779190872Sjfv default: 780169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 781190872Sjfv break; 782190872Sjfv } 783169240Sjfv 784169240Sjfv if (ret_val) 785169589Sjfv e1000_put_hw_semaphore_82571(hw); 786169240Sjfv 787169240Sjfvout: 788169240Sjfv return ret_val; 789169240Sjfv} 790169240Sjfv 791169240Sjfv/** 792169240Sjfv * e1000_release_nvm_82571 - Release exclusive access to EEPROM 793169589Sjfv * @hw: pointer to the HW structure 794169240Sjfv * 795169240Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit. 796169240Sjfv **/ 797177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw) 798169240Sjfv{ 799169240Sjfv DEBUGFUNC("e1000_release_nvm_82571"); 800169240Sjfv 801169240Sjfv e1000_release_nvm_generic(hw); 802169589Sjfv e1000_put_hw_semaphore_82571(hw); 803169240Sjfv} 804169240Sjfv 805169240Sjfv/** 806169240Sjfv * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 807169589Sjfv * @hw: pointer to the HW structure 808169589Sjfv * @offset: offset within the EEPROM to be written to 809169589Sjfv * @words: number of words to write 810169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 811169240Sjfv * 812169240Sjfv * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 813169240Sjfv * 814169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 815176667Sjfv * EEPROM will most likely contain an invalid checksum. 816169240Sjfv **/ 817177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 818228386Sjfv u16 *data) 819169240Sjfv{ 820169240Sjfv s32 ret_val = E1000_SUCCESS; 821169240Sjfv 822169240Sjfv DEBUGFUNC("e1000_write_nvm_82571"); 823169240Sjfv 824169240Sjfv switch (hw->mac.type) { 825169240Sjfv case e1000_82573: 826178523Sjfv case e1000_82574: 827194865Sjfv case e1000_82583: 828169240Sjfv ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 829169240Sjfv break; 830169240Sjfv case e1000_82571: 831169240Sjfv case e1000_82572: 832169240Sjfv ret_val = e1000_write_nvm_spi(hw, offset, words, data); 833169240Sjfv break; 834169240Sjfv default: 835169240Sjfv ret_val = -E1000_ERR_NVM; 836169240Sjfv break; 837169240Sjfv } 838169240Sjfv 839169240Sjfv return ret_val; 840169240Sjfv} 841169240Sjfv 842169240Sjfv/** 843169240Sjfv * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 844169589Sjfv * @hw: pointer to the HW structure 845169240Sjfv * 846169240Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 847169240Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 848169240Sjfv * value to the EEPROM. 849169240Sjfv **/ 850177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 851169240Sjfv{ 852169240Sjfv u32 eecd; 853169240Sjfv s32 ret_val; 854169240Sjfv u16 i; 855169240Sjfv 856169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82571"); 857169240Sjfv 858169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 859169240Sjfv if (ret_val) 860169240Sjfv goto out; 861169240Sjfv 862173788Sjfv /* 863173788Sjfv * If our nvm is an EEPROM, then we're done 864173788Sjfv * otherwise, commit the checksum to the flash NVM. 865173788Sjfv */ 866169240Sjfv if (hw->nvm.type != e1000_nvm_flash_hw) 867169240Sjfv goto out; 868169240Sjfv 869169240Sjfv /* Check for pending operations. */ 870169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 871169240Sjfv msec_delay(1); 872169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 873169240Sjfv break; 874169240Sjfv } 875169240Sjfv 876169240Sjfv if (i == E1000_FLASH_UPDATES) { 877169240Sjfv ret_val = -E1000_ERR_NVM; 878169240Sjfv goto out; 879169240Sjfv } 880169240Sjfv 881169240Sjfv /* Reset the firmware if using STM opcode. */ 882169240Sjfv if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 883173788Sjfv /* 884173788Sjfv * The enabling of and the actual reset must be done 885169240Sjfv * in two write cycles. 886169240Sjfv */ 887169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 888169240Sjfv E1000_WRITE_FLUSH(hw); 889169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 890169240Sjfv } 891169240Sjfv 892169240Sjfv /* Commit the write to flash */ 893169240Sjfv eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 894169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 895169240Sjfv 896169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 897169240Sjfv msec_delay(1); 898169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 899169240Sjfv break; 900169240Sjfv } 901169240Sjfv 902169240Sjfv if (i == E1000_FLASH_UPDATES) { 903169240Sjfv ret_val = -E1000_ERR_NVM; 904169240Sjfv goto out; 905169240Sjfv } 906169240Sjfv 907169240Sjfvout: 908169240Sjfv return ret_val; 909169240Sjfv} 910169240Sjfv 911169240Sjfv/** 912169240Sjfv * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 913169589Sjfv * @hw: pointer to the HW structure 914169240Sjfv * 915169240Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 916169240Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 917169240Sjfv **/ 918177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 919169240Sjfv{ 920169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 921169240Sjfv 922169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) 923169240Sjfv e1000_fix_nvm_checksum_82571(hw); 924169240Sjfv 925169240Sjfv return e1000_validate_nvm_checksum_generic(hw); 926169240Sjfv} 927169240Sjfv 928169240Sjfv/** 929169240Sjfv * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 930169589Sjfv * @hw: pointer to the HW structure 931169589Sjfv * @offset: offset within the EEPROM to be written to 932169589Sjfv * @words: number of words to write 933169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 934169240Sjfv * 935169240Sjfv * After checking for invalid values, poll the EEPROM to ensure the previous 936169240Sjfv * command has completed before trying to write the next word. After write 937169240Sjfv * poll for completion. 938169240Sjfv * 939169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 940176667Sjfv * EEPROM will most likely contain an invalid checksum. 941169240Sjfv **/ 942173788Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 943228386Sjfv u16 words, u16 *data) 944169240Sjfv{ 945169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 946169240Sjfv u32 i, eewr = 0; 947169240Sjfv s32 ret_val = 0; 948169240Sjfv 949169240Sjfv DEBUGFUNC("e1000_write_nvm_eewr_82571"); 950169240Sjfv 951173788Sjfv /* 952173788Sjfv * A check for invalid values: offset too large, too many words, 953173788Sjfv * and not enough words. 954173788Sjfv */ 955169240Sjfv if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 956169240Sjfv (words == 0)) { 957169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 958169240Sjfv ret_val = -E1000_ERR_NVM; 959169240Sjfv goto out; 960169240Sjfv } 961169240Sjfv 962169240Sjfv for (i = 0; i < words; i++) { 963169240Sjfv eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 964169240Sjfv ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 965169240Sjfv E1000_NVM_RW_REG_START; 966169240Sjfv 967169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 968169240Sjfv if (ret_val) 969169240Sjfv break; 970169240Sjfv 971169240Sjfv E1000_WRITE_REG(hw, E1000_EEWR, eewr); 972169240Sjfv 973169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 974169240Sjfv if (ret_val) 975169240Sjfv break; 976169240Sjfv } 977169240Sjfv 978169240Sjfvout: 979169240Sjfv return ret_val; 980169240Sjfv} 981169240Sjfv 982169240Sjfv/** 983169240Sjfv * e1000_get_cfg_done_82571 - Poll for configuration done 984169589Sjfv * @hw: pointer to the HW structure 985169240Sjfv * 986169240Sjfv * Reads the management control register for the config done bit to be set. 987169240Sjfv **/ 988177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 989169240Sjfv{ 990169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 991169240Sjfv s32 ret_val = E1000_SUCCESS; 992169240Sjfv 993169240Sjfv DEBUGFUNC("e1000_get_cfg_done_82571"); 994169240Sjfv 995169240Sjfv while (timeout) { 996200243Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 997200243Sjfv E1000_NVM_CFG_DONE_PORT_0) 998169240Sjfv break; 999169240Sjfv msec_delay(1); 1000169240Sjfv timeout--; 1001169240Sjfv } 1002169240Sjfv if (!timeout) { 1003169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 1004169240Sjfv ret_val = -E1000_ERR_RESET; 1005169240Sjfv goto out; 1006169240Sjfv } 1007169240Sjfv 1008169240Sjfvout: 1009169240Sjfv return ret_val; 1010169240Sjfv} 1011169240Sjfv 1012169240Sjfv/** 1013169240Sjfv * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 1014169589Sjfv * @hw: pointer to the HW structure 1015169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1016169240Sjfv * 1017169240Sjfv * Sets the LPLU D0 state according to the active flag. When activating LPLU 1018169240Sjfv * this function also disables smart speed and vice versa. LPLU will not be 1019169240Sjfv * activated unless the device autonegotiation advertisement meets standards 1020169240Sjfv * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 1021169240Sjfv * pointer entry point only called by PHY setup routines. 1022169240Sjfv **/ 1023177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 1024169240Sjfv{ 1025169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1026177867Sjfv s32 ret_val = E1000_SUCCESS; 1027169240Sjfv u16 data; 1028169240Sjfv 1029169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 1030169240Sjfv 1031177867Sjfv if (!(phy->ops.read_reg)) 1032177867Sjfv goto out; 1033177867Sjfv 1034177867Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1035169240Sjfv if (ret_val) 1036169240Sjfv goto out; 1037169240Sjfv 1038169240Sjfv if (active) { 1039169240Sjfv data |= IGP02E1000_PM_D0_LPLU; 1040177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1041228386Sjfv data); 1042169240Sjfv if (ret_val) 1043169240Sjfv goto out; 1044169240Sjfv 1045169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 1046177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1047228386Sjfv &data); 1048169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1049177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1050228386Sjfv data); 1051169240Sjfv if (ret_val) 1052169240Sjfv goto out; 1053169240Sjfv } else { 1054169240Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 1055177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1056228386Sjfv data); 1057173788Sjfv /* 1058173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1059169240Sjfv * during Dx states where the power conservation is most 1060169240Sjfv * important. During driver activity we should enable 1061173788Sjfv * SmartSpeed, so performance is maintained. 1062173788Sjfv */ 1063169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 1064177867Sjfv ret_val = phy->ops.read_reg(hw, 1065228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1066228386Sjfv &data); 1067169240Sjfv if (ret_val) 1068169240Sjfv goto out; 1069169240Sjfv 1070169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1071177867Sjfv ret_val = phy->ops.write_reg(hw, 1072228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1073228386Sjfv data); 1074169240Sjfv if (ret_val) 1075169240Sjfv goto out; 1076169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1077177867Sjfv ret_val = phy->ops.read_reg(hw, 1078228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1079228386Sjfv &data); 1080169240Sjfv if (ret_val) 1081169240Sjfv goto out; 1082169240Sjfv 1083169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1084177867Sjfv ret_val = phy->ops.write_reg(hw, 1085228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1086228386Sjfv data); 1087169240Sjfv if (ret_val) 1088169240Sjfv goto out; 1089169240Sjfv } 1090169240Sjfv } 1091169240Sjfv 1092169240Sjfvout: 1093169240Sjfv return ret_val; 1094169240Sjfv} 1095169240Sjfv 1096169240Sjfv/** 1097169240Sjfv * e1000_reset_hw_82571 - Reset hardware 1098169589Sjfv * @hw: pointer to the HW structure 1099169240Sjfv * 1100185353Sjfv * This resets the hardware into a known state. 1101169240Sjfv **/ 1102177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1103169240Sjfv{ 1104218588Sjfv u32 ctrl, ctrl_ext; 1105169240Sjfv s32 ret_val; 1106169240Sjfv 1107169240Sjfv DEBUGFUNC("e1000_reset_hw_82571"); 1108169240Sjfv 1109173788Sjfv /* 1110173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 1111169240Sjfv * on the last TLP read/write transaction when MAC is reset. 1112169240Sjfv */ 1113169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 1114185353Sjfv if (ret_val) 1115169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1116169240Sjfv 1117169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 1118169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1119169240Sjfv 1120169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 1121169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1122169240Sjfv E1000_WRITE_FLUSH(hw); 1123169240Sjfv 1124169240Sjfv msec_delay(10); 1125169240Sjfv 1126173788Sjfv /* 1127173788Sjfv * Must acquire the MDIO ownership before MAC reset. 1128173788Sjfv * Ownership defaults to firmware after a reset. 1129173788Sjfv */ 1130190872Sjfv switch (hw->mac.type) { 1131200243Sjfv case e1000_82573: 1132213234Sjfv ret_val = e1000_get_hw_semaphore_82573(hw); 1133213234Sjfv break; 1134190872Sjfv case e1000_82574: 1135194865Sjfv case e1000_82583: 1136213234Sjfv ret_val = e1000_get_hw_semaphore_82574(hw); 1137190872Sjfv break; 1138190872Sjfv default: 1139190872Sjfv break; 1140169240Sjfv } 1141213234Sjfv if (ret_val) 1142213234Sjfv DEBUGOUT("Cannot acquire MDIO ownership\n"); 1143169240Sjfv 1144169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1145169240Sjfv 1146169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 1147169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1148169240Sjfv 1149213234Sjfv /* Must release MDIO ownership and mutex after MAC reset. */ 1150213234Sjfv switch (hw->mac.type) { 1151213234Sjfv case e1000_82574: 1152213234Sjfv case e1000_82583: 1153213234Sjfv e1000_put_hw_semaphore_82574(hw); 1154213234Sjfv break; 1155213234Sjfv default: 1156213234Sjfv break; 1157213234Sjfv } 1158213234Sjfv 1159169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) { 1160169240Sjfv usec_delay(10); 1161169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1162169240Sjfv ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1163169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1164169240Sjfv E1000_WRITE_FLUSH(hw); 1165169240Sjfv } 1166169240Sjfv 1167169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1168169240Sjfv if (ret_val) 1169169240Sjfv /* We don't want to continue accessing MAC registers. */ 1170169240Sjfv goto out; 1171169240Sjfv 1172173788Sjfv /* 1173173788Sjfv * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1174169240Sjfv * Need to wait for Phy configuration completion before accessing 1175169240Sjfv * NVM and Phy. 1176169240Sjfv */ 1177190872Sjfv 1178190872Sjfv switch (hw->mac.type) { 1179200243Sjfv case e1000_82573: 1180190872Sjfv case e1000_82574: 1181194865Sjfv case e1000_82583: 1182169240Sjfv msec_delay(25); 1183190872Sjfv break; 1184190872Sjfv default: 1185190872Sjfv break; 1186190872Sjfv } 1187169240Sjfv 1188169240Sjfv /* Clear any pending interrupt events. */ 1189169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1190218588Sjfv E1000_READ_REG(hw, E1000_ICR); 1191169240Sjfv 1192213234Sjfv if (hw->mac.type == e1000_82571) { 1193213234Sjfv /* Install any alternate MAC address into RAR0 */ 1194213234Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1195213234Sjfv if (ret_val) 1196213234Sjfv goto out; 1197173788Sjfv 1198213234Sjfv e1000_set_laa_state_82571(hw, TRUE); 1199213234Sjfv } 1200190872Sjfv 1201190872Sjfv /* Reinitialize the 82571 serdes link state machine */ 1202190872Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes) 1203190872Sjfv hw->mac.serdes_link_state = e1000_serdes_link_down; 1204190872Sjfv 1205169240Sjfvout: 1206169240Sjfv return ret_val; 1207169240Sjfv} 1208169240Sjfv 1209169240Sjfv/** 1210169240Sjfv * e1000_init_hw_82571 - Initialize hardware 1211169589Sjfv * @hw: pointer to the HW structure 1212169240Sjfv * 1213169240Sjfv * This inits the hardware readying it for operation. 1214169240Sjfv **/ 1215177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw) 1216169240Sjfv{ 1217169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1218169240Sjfv u32 reg_data; 1219169240Sjfv s32 ret_val; 1220169240Sjfv u16 i, rar_count = mac->rar_entry_count; 1221169240Sjfv 1222169240Sjfv DEBUGFUNC("e1000_init_hw_82571"); 1223169240Sjfv 1224169240Sjfv e1000_initialize_hw_bits_82571(hw); 1225169240Sjfv 1226169240Sjfv /* Initialize identification LED */ 1227190872Sjfv ret_val = mac->ops.id_led_init(hw); 1228200243Sjfv if (ret_val) 1229169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 1230173788Sjfv /* This is not fatal and we should not stop init due to this */ 1231169240Sjfv 1232169240Sjfv /* Disabling VLAN filtering */ 1233169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 1234177867Sjfv mac->ops.clear_vfta(hw); 1235169240Sjfv 1236169240Sjfv /* Setup the receive address. */ 1237173788Sjfv /* 1238173788Sjfv * If, however, a locally administered address was assigned to the 1239169240Sjfv * 82571, we must reserve a RAR for it to work around an issue where 1240169240Sjfv * resetting one port will reload the MAC on the other port. 1241169240Sjfv */ 1242173788Sjfv if (e1000_get_laa_state_82571(hw)) 1243169240Sjfv rar_count--; 1244169240Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 1245169240Sjfv 1246169240Sjfv /* Zero out the Multicast HASH table */ 1247169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 1248169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 1249169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1250169240Sjfv 1251169240Sjfv /* Setup link and flow control */ 1252177867Sjfv ret_val = mac->ops.setup_link(hw); 1253169240Sjfv 1254169240Sjfv /* Set the transmit descriptor write-back policy */ 1255173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1256169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1257228386Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 1258173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1259169240Sjfv 1260169240Sjfv /* ...for both queues. */ 1261190872Sjfv switch (mac->type) { 1262200243Sjfv case e1000_82573: 1263205869Sjfv e1000_enable_tx_pkt_filtering_generic(hw); 1264205869Sjfv /* fall through */ 1265190872Sjfv case e1000_82574: 1266194865Sjfv case e1000_82583: 1267169240Sjfv reg_data = E1000_READ_REG(hw, E1000_GCR); 1268169240Sjfv reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1269169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1270190872Sjfv break; 1271190872Sjfv default: 1272190872Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1273190872Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1274228386Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 1275228386Sjfv E1000_TXDCTL_COUNT_DESC; 1276190872Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1277190872Sjfv break; 1278169240Sjfv } 1279169240Sjfv 1280173788Sjfv /* 1281173788Sjfv * Clear all of the statistics registers (clear on read). It is 1282169240Sjfv * important that we do this after we have tried to establish link 1283169240Sjfv * because the symbol error count will increment wildly if there 1284169240Sjfv * is no link. 1285169240Sjfv */ 1286169240Sjfv e1000_clear_hw_cntrs_82571(hw); 1287169240Sjfv 1288169240Sjfv return ret_val; 1289169240Sjfv} 1290169240Sjfv 1291169240Sjfv/** 1292169240Sjfv * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1293169589Sjfv * @hw: pointer to the HW structure 1294169240Sjfv * 1295169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 1296169240Sjfv **/ 1297173788Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1298169240Sjfv{ 1299169240Sjfv u32 reg; 1300169240Sjfv 1301169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1302169240Sjfv 1303169240Sjfv /* Transmit Descriptor Control 0 */ 1304173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1305169240Sjfv reg |= (1 << 22); 1306173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1307169240Sjfv 1308169240Sjfv /* Transmit Descriptor Control 1 */ 1309173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1310169240Sjfv reg |= (1 << 22); 1311173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1312169240Sjfv 1313169240Sjfv /* Transmit Arbitration Control 0 */ 1314173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 1315169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 1316169240Sjfv switch (hw->mac.type) { 1317169240Sjfv case e1000_82571: 1318169240Sjfv case e1000_82572: 1319169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1320169240Sjfv break; 1321228386Sjfv case e1000_82574: 1322228386Sjfv case e1000_82583: 1323228386Sjfv reg |= (1 << 26); 1324228386Sjfv break; 1325169240Sjfv default: 1326169240Sjfv break; 1327169240Sjfv } 1328173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1329169240Sjfv 1330169240Sjfv /* Transmit Arbitration Control 1 */ 1331173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1332169240Sjfv switch (hw->mac.type) { 1333169240Sjfv case e1000_82571: 1334169240Sjfv case e1000_82572: 1335169240Sjfv reg &= ~((1 << 29) | (1 << 30)); 1336169589Sjfv reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1337169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1338169240Sjfv reg &= ~(1 << 28); 1339169240Sjfv else 1340169240Sjfv reg |= (1 << 28); 1341173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1342169240Sjfv break; 1343169240Sjfv default: 1344169240Sjfv break; 1345169240Sjfv } 1346169240Sjfv 1347169240Sjfv /* Device Control */ 1348190872Sjfv switch (hw->mac.type) { 1349200243Sjfv case e1000_82573: 1350190872Sjfv case e1000_82574: 1351194865Sjfv case e1000_82583: 1352169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1353169240Sjfv reg &= ~(1 << 29); 1354169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1355190872Sjfv break; 1356190872Sjfv default: 1357190872Sjfv break; 1358169240Sjfv } 1359169240Sjfv 1360169240Sjfv /* Extended Device Control */ 1361190872Sjfv switch (hw->mac.type) { 1362200243Sjfv case e1000_82573: 1363190872Sjfv case e1000_82574: 1364194865Sjfv case e1000_82583: 1365169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1366169240Sjfv reg &= ~(1 << 23); 1367169240Sjfv reg |= (1 << 22); 1368169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1369190872Sjfv break; 1370190872Sjfv default: 1371190872Sjfv break; 1372169240Sjfv } 1373169240Sjfv 1374190872Sjfv if (hw->mac.type == e1000_82571) { 1375190872Sjfv reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1376190872Sjfv reg |= E1000_PBA_ECC_CORR_EN; 1377190872Sjfv E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1378190872Sjfv } 1379190872Sjfv 1380190872Sjfv /* 1381190872Sjfv * Workaround for hardware errata. 1382190872Sjfv * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1383190872Sjfv */ 1384190872Sjfv if ((hw->mac.type == e1000_82571) || 1385190872Sjfv (hw->mac.type == e1000_82572)) { 1386190872Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1387190872Sjfv reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1388190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1389190872Sjfv } 1390190872Sjfv 1391190872Sjfv /* PCI-Ex Control Registers */ 1392190872Sjfv switch (hw->mac.type) { 1393190872Sjfv case e1000_82574: 1394194865Sjfv case e1000_82583: 1395181027Sjfv reg = E1000_READ_REG(hw, E1000_GCR); 1396181027Sjfv reg |= (1 << 22); 1397185353Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg); 1398200243Sjfv 1399190872Sjfv /* 1400190872Sjfv * Workaround for hardware errata. 1401190872Sjfv * apply workaround for hardware errata documented in errata 1402190872Sjfv * docs Fixes issue where some error prone or unreliable PCIe 1403190872Sjfv * completions are occurring, particularly with ASPM enabled. 1404218588Sjfv * Without fix, issue can cause Tx timeouts. 1405190872Sjfv */ 1406190872Sjfv reg = E1000_READ_REG(hw, E1000_GCR2); 1407190872Sjfv reg |= 1; 1408190872Sjfv E1000_WRITE_REG(hw, E1000_GCR2, reg); 1409190872Sjfv break; 1410190872Sjfv default: 1411190872Sjfv break; 1412181027Sjfv } 1413181027Sjfv 1414169240Sjfv return; 1415169240Sjfv} 1416169240Sjfv 1417169240Sjfv/** 1418169240Sjfv * e1000_clear_vfta_82571 - Clear VLAN filter table 1419169589Sjfv * @hw: pointer to the HW structure 1420169240Sjfv * 1421169240Sjfv * Clears the register array which contains the VLAN filter table by 1422169240Sjfv * setting all the values to 0. 1423169240Sjfv **/ 1424177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw) 1425169240Sjfv{ 1426169240Sjfv u32 offset; 1427169240Sjfv u32 vfta_value = 0; 1428169240Sjfv u32 vfta_offset = 0; 1429169240Sjfv u32 vfta_bit_in_reg = 0; 1430169240Sjfv 1431169240Sjfv DEBUGFUNC("e1000_clear_vfta_82571"); 1432169240Sjfv 1433190872Sjfv switch (hw->mac.type) { 1434200243Sjfv case e1000_82573: 1435190872Sjfv case e1000_82574: 1436194865Sjfv case e1000_82583: 1437169240Sjfv if (hw->mng_cookie.vlan_id != 0) { 1438173788Sjfv /* 1439200243Sjfv * The VFTA is a 4096b bit-field, each identifying 1440200243Sjfv * a single VLAN ID. The following operations 1441200243Sjfv * determine which 32b entry (i.e. offset) into the 1442200243Sjfv * array we want to set the VLAN ID (i.e. bit) of 1443200243Sjfv * the manageability unit. 1444200243Sjfv */ 1445169240Sjfv vfta_offset = (hw->mng_cookie.vlan_id >> 1446190872Sjfv E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1447169240Sjfv vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1448190872Sjfv E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1449169240Sjfv } 1450190872Sjfv break; 1451190872Sjfv default: 1452190872Sjfv break; 1453169240Sjfv } 1454200243Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1455200243Sjfv /* 1456200243Sjfv * If the offset we want to clear is the same offset of the 1457200243Sjfv * manageability VLAN ID, then clear all bits except that of 1458200243Sjfv * the manageability unit. 1459200243Sjfv */ 1460200243Sjfv vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1461200243Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1462200243Sjfv E1000_WRITE_FLUSH(hw); 1463200243Sjfv } 1464169240Sjfv} 1465169240Sjfv 1466169240Sjfv/** 1467181027Sjfv * e1000_check_mng_mode_82574 - Check manageability is enabled 1468181027Sjfv * @hw: pointer to the HW structure 1469181027Sjfv * 1470181027Sjfv * Reads the NVM Initialization Control Word 2 and returns TRUE 1471181027Sjfv * (>0) if any manageability is enabled, else FALSE (0). 1472181027Sjfv **/ 1473181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1474181027Sjfv{ 1475181027Sjfv u16 data; 1476181027Sjfv 1477181027Sjfv DEBUGFUNC("e1000_check_mng_mode_82574"); 1478181027Sjfv 1479181027Sjfv hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1480185353Sjfv return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1481181027Sjfv} 1482181027Sjfv 1483181027Sjfv/** 1484181027Sjfv * e1000_led_on_82574 - Turn LED on 1485181027Sjfv * @hw: pointer to the HW structure 1486185353Sjfv * 1487181027Sjfv * Turn LED on. 1488181027Sjfv **/ 1489181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw) 1490181027Sjfv{ 1491181027Sjfv u32 ctrl; 1492181027Sjfv u32 i; 1493181027Sjfv 1494181027Sjfv DEBUGFUNC("e1000_led_on_82574"); 1495181027Sjfv 1496181027Sjfv ctrl = hw->mac.ledctl_mode2; 1497181027Sjfv if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1498185353Sjfv /* 1499185353Sjfv * If no link, then turn LED on by setting the invert bit 1500181027Sjfv * for each LED that's "on" (0x0E) in ledctl_mode2. 1501181027Sjfv */ 1502181027Sjfv for (i = 0; i < 4; i++) 1503181027Sjfv if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1504181027Sjfv E1000_LEDCTL_MODE_LED_ON) 1505181027Sjfv ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1506181027Sjfv } 1507181027Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1508181027Sjfv 1509181027Sjfv return E1000_SUCCESS; 1510181027Sjfv} 1511181027Sjfv 1512213234Sjfv/** 1513213234Sjfv * e1000_check_phy_82574 - check 82574 phy hung state 1514213234Sjfv * @hw: pointer to the HW structure 1515213234Sjfv * 1516213234Sjfv * Returns whether phy is hung or not 1517213234Sjfv **/ 1518213234Sjfvbool e1000_check_phy_82574(struct e1000_hw *hw) 1519213234Sjfv{ 1520213234Sjfv u16 status_1kbt = 0; 1521213234Sjfv u16 receive_errors = 0; 1522213234Sjfv bool phy_hung = FALSE; 1523213234Sjfv s32 ret_val = E1000_SUCCESS; 1524169240Sjfv 1525213234Sjfv DEBUGFUNC("e1000_check_phy_82574"); 1526213234Sjfv 1527213234Sjfv /* 1528213234Sjfv * Read PHY Receive Error counter first, if its is max - all F's then 1529213234Sjfv * read the Base1000T status register If both are max then PHY is hung. 1530213234Sjfv */ 1531213234Sjfv ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1532228386Sjfv &receive_errors); 1533213234Sjfv if (ret_val) 1534213234Sjfv goto out; 1535218588Sjfv if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1536213234Sjfv ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1537228386Sjfv &status_1kbt); 1538213234Sjfv if (ret_val) 1539213234Sjfv goto out; 1540213234Sjfv if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1541213234Sjfv E1000_IDLE_ERROR_COUNT_MASK) 1542213234Sjfv phy_hung = TRUE; 1543213234Sjfv } 1544213234Sjfvout: 1545213234Sjfv return phy_hung; 1546213234Sjfv} 1547213234Sjfv 1548213234Sjfv 1549169240Sjfv/** 1550169240Sjfv * e1000_setup_link_82571 - Setup flow control and link settings 1551169589Sjfv * @hw: pointer to the HW structure 1552169240Sjfv * 1553169240Sjfv * Determines which flow control settings to use, then configures flow 1554169240Sjfv * control. Calls the appropriate media-specific link configuration 1555169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1556169240Sjfv * should be established. Assumes the hardware has previously been reset 1557169240Sjfv * and the transmitter and receiver are not enabled. 1558169240Sjfv **/ 1559177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw) 1560169240Sjfv{ 1561169240Sjfv DEBUGFUNC("e1000_setup_link_82571"); 1562169240Sjfv 1563173788Sjfv /* 1564173788Sjfv * 82573 does not have a word in the NVM to determine 1565169240Sjfv * the default flow control setting, so we explicitly 1566169240Sjfv * set it to full. 1567169240Sjfv */ 1568190872Sjfv switch (hw->mac.type) { 1569200243Sjfv case e1000_82573: 1570190872Sjfv case e1000_82574: 1571194865Sjfv case e1000_82583: 1572190872Sjfv if (hw->fc.requested_mode == e1000_fc_default) 1573190872Sjfv hw->fc.requested_mode = e1000_fc_full; 1574190872Sjfv break; 1575190872Sjfv default: 1576190872Sjfv break; 1577190872Sjfv } 1578218588Sjfv 1579169240Sjfv return e1000_setup_link_generic(hw); 1580169240Sjfv} 1581169240Sjfv 1582169240Sjfv/** 1583169240Sjfv * e1000_setup_copper_link_82571 - Configure copper link settings 1584169589Sjfv * @hw: pointer to the HW structure 1585169240Sjfv * 1586169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1587169240Sjfv * for link, once link is established calls to configure collision distance 1588169240Sjfv * and flow control are called. 1589169240Sjfv **/ 1590177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1591169240Sjfv{ 1592194865Sjfv u32 ctrl; 1593205869Sjfv s32 ret_val; 1594169240Sjfv 1595169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82571"); 1596169240Sjfv 1597169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1598169240Sjfv ctrl |= E1000_CTRL_SLU; 1599169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1600169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1601169240Sjfv 1602169240Sjfv switch (hw->phy.type) { 1603169240Sjfv case e1000_phy_m88: 1604176667Sjfv case e1000_phy_bm: 1605169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1606169240Sjfv break; 1607169240Sjfv case e1000_phy_igp_2: 1608169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1609169240Sjfv break; 1610169240Sjfv default: 1611169240Sjfv ret_val = -E1000_ERR_PHY; 1612169240Sjfv break; 1613169240Sjfv } 1614169240Sjfv 1615169240Sjfv if (ret_val) 1616169240Sjfv goto out; 1617169240Sjfv 1618169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1619169240Sjfv 1620169240Sjfvout: 1621169240Sjfv return ret_val; 1622169240Sjfv} 1623169240Sjfv 1624169240Sjfv/** 1625169240Sjfv * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1626169589Sjfv * @hw: pointer to the HW structure 1627169240Sjfv * 1628169240Sjfv * Configures collision distance and flow control for fiber and serdes links. 1629169240Sjfv * Upon successful setup, poll for link. 1630169240Sjfv **/ 1631177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1632169240Sjfv{ 1633169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1634169240Sjfv 1635169240Sjfv switch (hw->mac.type) { 1636169240Sjfv case e1000_82571: 1637169240Sjfv case e1000_82572: 1638173788Sjfv /* 1639173788Sjfv * If SerDes loopback mode is entered, there is no form 1640169240Sjfv * of reset to take the adapter out of that mode. So we 1641169240Sjfv * have to explicitly take the adapter out of loopback 1642176667Sjfv * mode. This prevents drivers from twiddling their thumbs 1643169240Sjfv * if another tool failed to take it out of loopback mode. 1644169240Sjfv */ 1645228386Sjfv E1000_WRITE_REG(hw, E1000_SCTL, 1646228386Sjfv E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1647169240Sjfv break; 1648169240Sjfv default: 1649169240Sjfv break; 1650169240Sjfv } 1651169240Sjfv 1652169240Sjfv return e1000_setup_fiber_serdes_link_generic(hw); 1653169240Sjfv} 1654169240Sjfv 1655169240Sjfv/** 1656190872Sjfv * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1657190872Sjfv * @hw: pointer to the HW structure 1658190872Sjfv * 1659194865Sjfv * Reports the link state as up or down. 1660194865Sjfv * 1661194865Sjfv * If autonegotiation is supported by the link partner, the link state is 1662200243Sjfv * determined by the result of autonegotiation. This is the most likely case. 1663194865Sjfv * If autonegotiation is not supported by the link partner, and the link 1664194865Sjfv * has a valid signal, force the link up. 1665194865Sjfv * 1666194865Sjfv * The link state is represented internally here by 4 states: 1667194865Sjfv * 1668194865Sjfv * 1) down 1669194865Sjfv * 2) autoneg_progress 1670228386Sjfv * 3) autoneg_complete (the link successfully autonegotiated) 1671194865Sjfv * 4) forced_up (the link has been forced up, it did not autonegotiate) 1672194865Sjfv * 1673190872Sjfv **/ 1674200243Sjfvstatic s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1675190872Sjfv{ 1676190872Sjfv struct e1000_mac_info *mac = &hw->mac; 1677190872Sjfv u32 rxcw; 1678190872Sjfv u32 ctrl; 1679190872Sjfv u32 status; 1680213234Sjfv u32 txcw; 1681213234Sjfv u32 i; 1682190872Sjfv s32 ret_val = E1000_SUCCESS; 1683190872Sjfv 1684190872Sjfv DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1685190872Sjfv 1686190872Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1687190872Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1688190872Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1689190872Sjfv 1690190872Sjfv if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1691190872Sjfv 1692190872Sjfv /* Receiver is synchronized with no invalid bits. */ 1693190872Sjfv switch (mac->serdes_link_state) { 1694190872Sjfv case e1000_serdes_link_autoneg_complete: 1695190872Sjfv if (!(status & E1000_STATUS_LU)) { 1696190872Sjfv /* 1697190872Sjfv * We have lost link, retry autoneg before 1698190872Sjfv * reporting link failure 1699190872Sjfv */ 1700190872Sjfv mac->serdes_link_state = 1701190872Sjfv e1000_serdes_link_autoneg_progress; 1702194865Sjfv mac->serdes_has_link = FALSE; 1703190872Sjfv DEBUGOUT("AN_UP -> AN_PROG\n"); 1704213234Sjfv } else { 1705213234Sjfv mac->serdes_has_link = TRUE; 1706190872Sjfv } 1707213234Sjfv break; 1708190872Sjfv 1709190872Sjfv case e1000_serdes_link_forced_up: 1710190872Sjfv /* 1711190872Sjfv * If we are receiving /C/ ordered sets, re-enable 1712190872Sjfv * auto-negotiation in the TXCW register and disable 1713190872Sjfv * forced link in the Device Control register in an 1714190872Sjfv * attempt to auto-negotiate with our link partner. 1715218588Sjfv * If the partner code word is null, stop forcing 1716213234Sjfv * and restart auto negotiation. 1717190872Sjfv */ 1718213234Sjfv if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { 1719190872Sjfv /* Enable autoneg, and unforce link up */ 1720190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1721190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, 1722190872Sjfv (ctrl & ~E1000_CTRL_SLU)); 1723190872Sjfv mac->serdes_link_state = 1724190872Sjfv e1000_serdes_link_autoneg_progress; 1725194865Sjfv mac->serdes_has_link = FALSE; 1726190872Sjfv DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1727213234Sjfv } else { 1728213234Sjfv mac->serdes_has_link = TRUE; 1729190872Sjfv } 1730190872Sjfv break; 1731190872Sjfv 1732190872Sjfv case e1000_serdes_link_autoneg_progress: 1733194865Sjfv if (rxcw & E1000_RXCW_C) { 1734200243Sjfv /* 1735200243Sjfv * We received /C/ ordered sets, meaning the 1736194865Sjfv * link partner has autonegotiated, and we can 1737200243Sjfv * trust the Link Up (LU) status bit. 1738194865Sjfv */ 1739194865Sjfv if (status & E1000_STATUS_LU) { 1740194865Sjfv mac->serdes_link_state = 1741194865Sjfv e1000_serdes_link_autoneg_complete; 1742194865Sjfv DEBUGOUT("AN_PROG -> AN_UP\n"); 1743194865Sjfv mac->serdes_has_link = TRUE; 1744194865Sjfv } else { 1745200243Sjfv /* Autoneg completed, but failed. */ 1746194865Sjfv mac->serdes_link_state = 1747194865Sjfv e1000_serdes_link_down; 1748194865Sjfv DEBUGOUT("AN_PROG -> DOWN\n"); 1749194865Sjfv } 1750190872Sjfv } else { 1751200243Sjfv /* 1752200243Sjfv * The link partner did not autoneg. 1753194865Sjfv * Force link up and full duplex, and change 1754194865Sjfv * state to forced. 1755190872Sjfv */ 1756190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, 1757194865Sjfv (mac->txcw & ~E1000_TXCW_ANE)); 1758190872Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1759190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1760190872Sjfv 1761190872Sjfv /* Configure Flow Control after link up. */ 1762190872Sjfv ret_val = 1763190872Sjfv e1000_config_fc_after_link_up_generic(hw); 1764190872Sjfv if (ret_val) { 1765190872Sjfv DEBUGOUT("Error config flow control\n"); 1766190872Sjfv break; 1767190872Sjfv } 1768190872Sjfv mac->serdes_link_state = 1769228386Sjfv e1000_serdes_link_forced_up; 1770194865Sjfv mac->serdes_has_link = TRUE; 1771190872Sjfv DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1772190872Sjfv } 1773190872Sjfv break; 1774190872Sjfv 1775190872Sjfv case e1000_serdes_link_down: 1776190872Sjfv default: 1777200243Sjfv /* 1778200243Sjfv * The link was down but the receiver has now gained 1779190872Sjfv * valid sync, so lets see if we can bring the link 1780200243Sjfv * up. 1781200243Sjfv */ 1782190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1783228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & 1784228386Sjfv ~E1000_CTRL_SLU)); 1785190872Sjfv mac->serdes_link_state = 1786228386Sjfv e1000_serdes_link_autoneg_progress; 1787213234Sjfv mac->serdes_has_link = FALSE; 1788190872Sjfv DEBUGOUT("DOWN -> AN_PROG\n"); 1789190872Sjfv break; 1790190872Sjfv } 1791190872Sjfv } else { 1792190872Sjfv if (!(rxcw & E1000_RXCW_SYNCH)) { 1793190872Sjfv mac->serdes_has_link = FALSE; 1794190872Sjfv mac->serdes_link_state = e1000_serdes_link_down; 1795190872Sjfv DEBUGOUT("ANYSTATE -> DOWN\n"); 1796190872Sjfv } else { 1797190872Sjfv /* 1798213234Sjfv * Check several times, if Sync and Config 1799213234Sjfv * both are consistently 1 then simply ignore 1800213234Sjfv * the Invalid bit and restart Autoneg 1801190872Sjfv */ 1802213234Sjfv for (i = 0; i < AN_RETRY_COUNT; i++) { 1803213234Sjfv usec_delay(10); 1804213234Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1805213234Sjfv if ((rxcw & E1000_RXCW_IV) && 1806213234Sjfv !((rxcw & E1000_RXCW_SYNCH) && 1807213234Sjfv (rxcw & E1000_RXCW_C))) { 1808213234Sjfv mac->serdes_has_link = FALSE; 1809213234Sjfv mac->serdes_link_state = 1810228386Sjfv e1000_serdes_link_down; 1811213234Sjfv DEBUGOUT("ANYSTATE -> DOWN\n"); 1812213234Sjfv break; 1813213234Sjfv } 1814213234Sjfv } 1815213234Sjfv 1816213234Sjfv if (i == AN_RETRY_COUNT) { 1817213234Sjfv txcw = E1000_READ_REG(hw, E1000_TXCW); 1818213234Sjfv txcw |= E1000_TXCW_ANE; 1819213234Sjfv E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1820213234Sjfv mac->serdes_link_state = 1821228386Sjfv e1000_serdes_link_autoneg_progress; 1822190872Sjfv mac->serdes_has_link = FALSE; 1823213234Sjfv DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1824190872Sjfv } 1825190872Sjfv } 1826190872Sjfv } 1827190872Sjfv 1828190872Sjfv return ret_val; 1829190872Sjfv} 1830190872Sjfv 1831190872Sjfv/** 1832169240Sjfv * e1000_valid_led_default_82571 - Verify a valid default LED config 1833169589Sjfv * @hw: pointer to the HW structure 1834169589Sjfv * @data: pointer to the NVM (EEPROM) 1835169240Sjfv * 1836169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1837169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1838169240Sjfv **/ 1839177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1840169240Sjfv{ 1841169240Sjfv s32 ret_val; 1842169240Sjfv 1843169240Sjfv DEBUGFUNC("e1000_valid_led_default_82571"); 1844169240Sjfv 1845177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1846169240Sjfv if (ret_val) { 1847169240Sjfv DEBUGOUT("NVM Read Error\n"); 1848169240Sjfv goto out; 1849169240Sjfv } 1850169240Sjfv 1851190872Sjfv switch (hw->mac.type) { 1852200243Sjfv case e1000_82573: 1853190872Sjfv case e1000_82574: 1854194865Sjfv case e1000_82583: 1855200243Sjfv if (*data == ID_LED_RESERVED_F746) 1856190872Sjfv *data = ID_LED_DEFAULT_82573; 1857190872Sjfv break; 1858190872Sjfv default: 1859190872Sjfv if (*data == ID_LED_RESERVED_0000 || 1860200243Sjfv *data == ID_LED_RESERVED_FFFF) 1861190872Sjfv *data = ID_LED_DEFAULT; 1862190872Sjfv break; 1863190872Sjfv } 1864190872Sjfv 1865169240Sjfvout: 1866169240Sjfv return ret_val; 1867169240Sjfv} 1868169240Sjfv 1869169240Sjfv/** 1870169240Sjfv * e1000_get_laa_state_82571 - Get locally administered address state 1871169589Sjfv * @hw: pointer to the HW structure 1872169240Sjfv * 1873176667Sjfv * Retrieve and return the current locally administered address state. 1874169240Sjfv **/ 1875173788Sjfvbool e1000_get_laa_state_82571(struct e1000_hw *hw) 1876169240Sjfv{ 1877169240Sjfv DEBUGFUNC("e1000_get_laa_state_82571"); 1878169240Sjfv 1879169240Sjfv if (hw->mac.type != e1000_82571) 1880185353Sjfv return FALSE; 1881169240Sjfv 1882185353Sjfv return hw->dev_spec._82571.laa_is_present; 1883169240Sjfv} 1884169240Sjfv 1885169240Sjfv/** 1886169240Sjfv * e1000_set_laa_state_82571 - Set locally administered address state 1887169589Sjfv * @hw: pointer to the HW structure 1888169589Sjfv * @state: enable/disable locally administered address 1889169240Sjfv * 1890176667Sjfv * Enable/Disable the current locally administered address state. 1891169240Sjfv **/ 1892173788Sjfvvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1893169240Sjfv{ 1894169240Sjfv DEBUGFUNC("e1000_set_laa_state_82571"); 1895169240Sjfv 1896169240Sjfv if (hw->mac.type != e1000_82571) 1897185353Sjfv return; 1898169240Sjfv 1899185353Sjfv hw->dev_spec._82571.laa_is_present = state; 1900169240Sjfv 1901169240Sjfv /* If workaround is activated... */ 1902185353Sjfv if (state) 1903173788Sjfv /* 1904173788Sjfv * Hold a copy of the LAA in RAR[14] This is done so that 1905169240Sjfv * between the time RAR[0] gets clobbered and the time it 1906169240Sjfv * gets fixed, the actual LAA is in one of the RARs and no 1907169240Sjfv * incoming packets directed to this port are dropped. 1908169240Sjfv * Eventually the LAA will be in RAR[0] and RAR[14]. 1909169240Sjfv */ 1910169240Sjfv e1000_rar_set_generic(hw, hw->mac.addr, 1911228386Sjfv hw->mac.rar_entry_count - 1); 1912169240Sjfv return; 1913169240Sjfv} 1914169240Sjfv 1915169240Sjfv/** 1916169240Sjfv * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1917169589Sjfv * @hw: pointer to the HW structure 1918169240Sjfv * 1919169240Sjfv * Verifies that the EEPROM has completed the update. After updating the 1920169240Sjfv * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1921169240Sjfv * the checksum fix is not implemented, we need to set the bit and update 1922169240Sjfv * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1923169240Sjfv * we need to return bad checksum. 1924169240Sjfv **/ 1925173788Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1926169240Sjfv{ 1927169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1928169240Sjfv s32 ret_val = E1000_SUCCESS; 1929169240Sjfv u16 data; 1930169240Sjfv 1931169240Sjfv DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1932169240Sjfv 1933169240Sjfv if (nvm->type != e1000_nvm_flash_hw) 1934169240Sjfv goto out; 1935169240Sjfv 1936173788Sjfv /* 1937173788Sjfv * Check bit 4 of word 10h. If it is 0, firmware is done updating 1938169240Sjfv * 10h-12h. Checksum may need to be fixed. 1939169240Sjfv */ 1940177867Sjfv ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1941169240Sjfv if (ret_val) 1942169240Sjfv goto out; 1943169240Sjfv 1944169240Sjfv if (!(data & 0x10)) { 1945173788Sjfv /* 1946173788Sjfv * Read 0x23 and check bit 15. This bit is a 1 1947169240Sjfv * when the checksum has already been fixed. If 1948169240Sjfv * the checksum is still wrong and this bit is a 1949169240Sjfv * 1, we need to return bad checksum. Otherwise, 1950169240Sjfv * we need to set this bit to a 1 and update the 1951169240Sjfv * checksum. 1952169240Sjfv */ 1953177867Sjfv ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1954169240Sjfv if (ret_val) 1955169240Sjfv goto out; 1956169240Sjfv 1957169240Sjfv if (!(data & 0x8000)) { 1958169240Sjfv data |= 0x8000; 1959177867Sjfv ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1960169240Sjfv if (ret_val) 1961169240Sjfv goto out; 1962177867Sjfv ret_val = nvm->ops.update(hw); 1963169240Sjfv } 1964169240Sjfv } 1965169240Sjfv 1966169240Sjfvout: 1967169240Sjfv return ret_val; 1968169240Sjfv} 1969169240Sjfv 1970190872Sjfv 1971169240Sjfv/** 1972173788Sjfv * e1000_read_mac_addr_82571 - Read device MAC address 1973173788Sjfv * @hw: pointer to the HW structure 1974173788Sjfv **/ 1975177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1976173788Sjfv{ 1977173788Sjfv s32 ret_val = E1000_SUCCESS; 1978173788Sjfv 1979173788Sjfv DEBUGFUNC("e1000_read_mac_addr_82571"); 1980173788Sjfv 1981213234Sjfv if (hw->mac.type == e1000_82571) { 1982213234Sjfv /* 1983213234Sjfv * If there's an alternate MAC address place it in RAR0 1984213234Sjfv * so that it will override the Si installed default perm 1985213234Sjfv * address. 1986213234Sjfv */ 1987213234Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1988213234Sjfv if (ret_val) 1989213234Sjfv goto out; 1990213234Sjfv } 1991190872Sjfv 1992190872Sjfv ret_val = e1000_read_mac_addr_generic(hw); 1993190872Sjfv 1994190872Sjfvout: 1995173788Sjfv return ret_val; 1996173788Sjfv} 1997173788Sjfv 1998173788Sjfv/** 1999173788Sjfv * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 2000173788Sjfv * @hw: pointer to the HW structure 2001173788Sjfv * 2002173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 2003173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 2004173788Sjfv **/ 2005177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 2006173788Sjfv{ 2007177867Sjfv struct e1000_phy_info *phy = &hw->phy; 2008177867Sjfv struct e1000_mac_info *mac = &hw->mac; 2009177867Sjfv 2010177867Sjfv if (!(phy->ops.check_reset_block)) 2011177867Sjfv return; 2012177867Sjfv 2013173788Sjfv /* If the management interface is not enabled, then power down */ 2014177867Sjfv if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 2015173788Sjfv e1000_power_down_phy_copper(hw); 2016173788Sjfv 2017173788Sjfv return; 2018173788Sjfv} 2019173788Sjfv 2020173788Sjfv/** 2021169240Sjfv * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 2022169589Sjfv * @hw: pointer to the HW structure 2023169240Sjfv * 2024169240Sjfv * Clears the hardware counters by reading the counter registers. 2025169240Sjfv **/ 2026177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 2027169240Sjfv{ 2028169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 2029169240Sjfv 2030169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 2031169240Sjfv 2032185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 2033185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 2034185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 2035185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 2036185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 2037185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 2038185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 2039185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 2040185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 2041185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 2042185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 2043185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 2044169240Sjfv 2045185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 2046185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 2047185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 2048185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 2049185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 2050185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 2051169240Sjfv 2052185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 2053185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 2054185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 2055169240Sjfv 2056185353Sjfv E1000_READ_REG(hw, E1000_IAC); 2057185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 2058185353Sjfv 2059185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 2060185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 2061185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 2062185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 2063185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 2064185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 2065185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 2066169240Sjfv} 2067