e1000_82571.c revision 228386
1/****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 228386 2011-12-10 06:55:02Z jfv $*/ 34 35/* 36 * 82571EB Gigabit Ethernet Controller 37 * 82571EB Gigabit Ethernet Controller (Copper) 38 * 82571EB Gigabit Ethernet Controller (Fiber) 39 * 82571EB Dual Port Gigabit Mezzanine Adapter 40 * 82571EB Quad Port Gigabit Mezzanine Adapter 41 * 82571PT Gigabit PT Quad Port Server ExpressModule 42 * 82572EI Gigabit Ethernet Controller (Copper) 43 * 82572EI Gigabit Ethernet Controller (Fiber) 44 * 82572EI Gigabit Ethernet Controller 45 * 82573V Gigabit Ethernet Controller (Copper) 46 * 82573E Gigabit Ethernet Controller (Copper) 47 * 82573L Gigabit Ethernet Controller 48 * 82574L Gigabit Network Connection 49 * 82583V Gigabit Network Connection 50 */ 51 52#include "e1000_api.h" 53 54static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 55static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 56static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 57static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 58static void e1000_release_nvm_82571(struct e1000_hw *hw); 59static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 60 u16 words, u16 *data); 61static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 62static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 63static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 64static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 65 bool active); 66static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 67static s32 e1000_init_hw_82571(struct e1000_hw *hw); 68static void e1000_clear_vfta_82571(struct e1000_hw *hw); 69static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70static s32 e1000_led_on_82574(struct e1000_hw *hw); 71static s32 e1000_setup_link_82571(struct e1000_hw *hw); 72static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 73static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 74static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 75static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 76static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 77static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 78static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 79static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 80static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 81static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); 82static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 83static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 84static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 85static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, 86 bool active); 87static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, 88 bool active); 89static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 90static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 91 u16 words, u16 *data); 92static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 93static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 94 95/** 96 * e1000_init_phy_params_82571 - Init PHY func ptrs. 97 * @hw: pointer to the HW structure 98 **/ 99static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 100{ 101 struct e1000_phy_info *phy = &hw->phy; 102 s32 ret_val = E1000_SUCCESS; 103 104 DEBUGFUNC("e1000_init_phy_params_82571"); 105 106 if (hw->phy.media_type != e1000_media_type_copper) { 107 phy->type = e1000_phy_none; 108 goto out; 109 } 110 111 phy->addr = 1; 112 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 113 phy->reset_delay_us = 100; 114 115 phy->ops.check_reset_block = e1000_check_reset_block_generic; 116 phy->ops.reset = e1000_phy_hw_reset_generic; 117 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 118 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119 phy->ops.power_up = e1000_power_up_phy_copper; 120 phy->ops.power_down = e1000_power_down_phy_copper_82571; 121 122 switch (hw->mac.type) { 123 case e1000_82571: 124 case e1000_82572: 125 phy->type = e1000_phy_igp_2; 126 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 127 phy->ops.get_info = e1000_get_phy_info_igp; 128 phy->ops.check_polarity = e1000_check_polarity_igp; 129 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 130 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 131 phy->ops.read_reg = e1000_read_phy_reg_igp; 132 phy->ops.write_reg = e1000_write_phy_reg_igp; 133 phy->ops.acquire = e1000_get_hw_semaphore_82571; 134 phy->ops.release = e1000_put_hw_semaphore_82571; 135 break; 136 case e1000_82573: 137 phy->type = e1000_phy_m88; 138 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 139 phy->ops.get_info = e1000_get_phy_info_m88; 140 phy->ops.check_polarity = e1000_check_polarity_m88; 141 phy->ops.commit = e1000_phy_sw_reset_generic; 142 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 143 phy->ops.get_cable_length = e1000_get_cable_length_m88; 144 phy->ops.read_reg = e1000_read_phy_reg_m88; 145 phy->ops.write_reg = e1000_write_phy_reg_m88; 146 phy->ops.acquire = e1000_get_hw_semaphore_82571; 147 phy->ops.release = e1000_put_hw_semaphore_82571; 148 break; 149 case e1000_82574: 150 case e1000_82583: 151 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex); 152 153 phy->type = e1000_phy_bm; 154 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 155 phy->ops.get_info = e1000_get_phy_info_m88; 156 phy->ops.check_polarity = e1000_check_polarity_m88; 157 phy->ops.commit = e1000_phy_sw_reset_generic; 158 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 159 phy->ops.get_cable_length = e1000_get_cable_length_m88; 160 phy->ops.read_reg = e1000_read_phy_reg_bm2; 161 phy->ops.write_reg = e1000_write_phy_reg_bm2; 162 phy->ops.acquire = e1000_get_hw_semaphore_82574; 163 phy->ops.release = e1000_put_hw_semaphore_82574; 164 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 165 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 166 break; 167 default: 168 ret_val = -E1000_ERR_PHY; 169 goto out; 170 break; 171 } 172 173 /* This can only be done after all function pointers are setup. */ 174 ret_val = e1000_get_phy_id_82571(hw); 175 if (ret_val) { 176 DEBUGOUT("Error getting PHY ID\n"); 177 goto out; 178 } 179 180 /* Verify phy id */ 181 switch (hw->mac.type) { 182 case e1000_82571: 183 case e1000_82572: 184 if (phy->id != IGP01E1000_I_PHY_ID) 185 ret_val = -E1000_ERR_PHY; 186 break; 187 case e1000_82573: 188 if (phy->id != M88E1111_I_PHY_ID) 189 ret_val = -E1000_ERR_PHY; 190 break; 191 case e1000_82574: 192 case e1000_82583: 193 if (phy->id != BME1000_E_PHY_ID_R2) 194 ret_val = -E1000_ERR_PHY; 195 break; 196 default: 197 ret_val = -E1000_ERR_PHY; 198 break; 199 } 200 201 if (ret_val) 202 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 203 204out: 205 return ret_val; 206} 207 208/** 209 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 210 * @hw: pointer to the HW structure 211 **/ 212static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 213{ 214 struct e1000_nvm_info *nvm = &hw->nvm; 215 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 216 u16 size; 217 218 DEBUGFUNC("e1000_init_nvm_params_82571"); 219 220 nvm->opcode_bits = 8; 221 nvm->delay_usec = 1; 222 switch (nvm->override) { 223 case e1000_nvm_override_spi_large: 224 nvm->page_size = 32; 225 nvm->address_bits = 16; 226 break; 227 case e1000_nvm_override_spi_small: 228 nvm->page_size = 8; 229 nvm->address_bits = 8; 230 break; 231 default: 232 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 233 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 234 break; 235 } 236 237 switch (hw->mac.type) { 238 case e1000_82573: 239 case e1000_82574: 240 case e1000_82583: 241 if (((eecd >> 15) & 0x3) == 0x3) { 242 nvm->type = e1000_nvm_flash_hw; 243 nvm->word_size = 2048; 244 /* 245 * Autonomous Flash update bit must be cleared due 246 * to Flash update issue. 247 */ 248 eecd &= ~E1000_EECD_AUPDEN; 249 E1000_WRITE_REG(hw, E1000_EECD, eecd); 250 break; 251 } 252 /* Fall Through */ 253 default: 254 nvm->type = e1000_nvm_eeprom_spi; 255 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 256 E1000_EECD_SIZE_EX_SHIFT); 257 /* 258 * Added to a constant, "size" becomes the left-shift value 259 * for setting word_size. 260 */ 261 size += NVM_WORD_SIZE_BASE_SHIFT; 262 263 /* EEPROM access above 16k is unsupported */ 264 if (size > 14) 265 size = 14; 266 nvm->word_size = 1 << size; 267 break; 268 } 269 270 /* Function Pointers */ 271 switch (hw->mac.type) { 272 case e1000_82574: 273 case e1000_82583: 274 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 275 nvm->ops.release = e1000_put_hw_semaphore_82574; 276 break; 277 default: 278 nvm->ops.acquire = e1000_acquire_nvm_82571; 279 nvm->ops.release = e1000_release_nvm_82571; 280 break; 281 } 282 nvm->ops.read = e1000_read_nvm_eerd; 283 nvm->ops.update = e1000_update_nvm_checksum_82571; 284 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 285 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 286 nvm->ops.write = e1000_write_nvm_82571; 287 288 return E1000_SUCCESS; 289} 290 291/** 292 * e1000_init_mac_params_82571 - Init MAC func ptrs. 293 * @hw: pointer to the HW structure 294 **/ 295static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 296{ 297 struct e1000_mac_info *mac = &hw->mac; 298 u32 swsm = 0; 299 u32 swsm2 = 0; 300 bool force_clear_smbi = FALSE; 301 302 DEBUGFUNC("e1000_init_mac_params_82571"); 303 304 /* Set media type and media-dependent function pointers */ 305 switch (hw->device_id) { 306 case E1000_DEV_ID_82571EB_FIBER: 307 case E1000_DEV_ID_82572EI_FIBER: 308 case E1000_DEV_ID_82571EB_QUAD_FIBER: 309 hw->phy.media_type = e1000_media_type_fiber; 310 mac->ops.setup_physical_interface = 311 e1000_setup_fiber_serdes_link_82571; 312 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 313 mac->ops.get_link_up_info = 314 e1000_get_speed_and_duplex_fiber_serdes_generic; 315 break; 316 case E1000_DEV_ID_82571EB_SERDES: 317 case E1000_DEV_ID_82571EB_SERDES_DUAL: 318 case E1000_DEV_ID_82571EB_SERDES_QUAD: 319 case E1000_DEV_ID_82572EI_SERDES: 320 hw->phy.media_type = e1000_media_type_internal_serdes; 321 mac->ops.setup_physical_interface = 322 e1000_setup_fiber_serdes_link_82571; 323 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 324 mac->ops.get_link_up_info = 325 e1000_get_speed_and_duplex_fiber_serdes_generic; 326 break; 327 default: 328 hw->phy.media_type = e1000_media_type_copper; 329 mac->ops.setup_physical_interface = 330 e1000_setup_copper_link_82571; 331 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 332 mac->ops.get_link_up_info = 333 e1000_get_speed_and_duplex_copper_generic; 334 break; 335 } 336 337 /* Set mta register count */ 338 mac->mta_reg_count = 128; 339 /* Set rar entry count */ 340 mac->rar_entry_count = E1000_RAR_ENTRIES; 341 /* Set if part includes ASF firmware */ 342 mac->asf_firmware_present = TRUE; 343 /* Adaptive IFS supported */ 344 mac->adaptive_ifs = TRUE; 345 346 /* Function pointers */ 347 348 /* bus type/speed/width */ 349 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 350 /* reset */ 351 mac->ops.reset_hw = e1000_reset_hw_82571; 352 /* hw initialization */ 353 mac->ops.init_hw = e1000_init_hw_82571; 354 /* link setup */ 355 mac->ops.setup_link = e1000_setup_link_82571; 356 /* multicast address update */ 357 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 358 /* writing VFTA */ 359 mac->ops.write_vfta = e1000_write_vfta_generic; 360 /* clearing VFTA */ 361 mac->ops.clear_vfta = e1000_clear_vfta_82571; 362 /* read mac address */ 363 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 364 /* ID LED init */ 365 mac->ops.id_led_init = e1000_id_led_init_generic; 366 /* setup LED */ 367 mac->ops.setup_led = e1000_setup_led_generic; 368 /* cleanup LED */ 369 mac->ops.cleanup_led = e1000_cleanup_led_generic; 370 /* turn off LED */ 371 mac->ops.led_off = e1000_led_off_generic; 372 /* clear hardware counters */ 373 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 374 375 /* MAC-specific function pointers */ 376 switch (hw->mac.type) { 377 case e1000_82573: 378 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 379 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 380 mac->ops.led_on = e1000_led_on_generic; 381 mac->ops.blink_led = e1000_blink_led_generic; 382 383 /* FWSM register */ 384 mac->has_fwsm = TRUE; 385 /* 386 * ARC supported; valid only if manageability features are 387 * enabled. 388 */ 389 mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) & 390 E1000_FWSM_MODE_MASK) ? TRUE : FALSE; 391 break; 392 case e1000_82574: 393 case e1000_82583: 394 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 395 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 396 mac->ops.led_on = e1000_led_on_82574; 397 break; 398 default: 399 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 400 mac->ops.led_on = e1000_led_on_generic; 401 mac->ops.blink_led = e1000_blink_led_generic; 402 403 /* FWSM register */ 404 mac->has_fwsm = TRUE; 405 break; 406 } 407 408 /* 409 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 410 * first NVM or PHY acess. This should be done for single-port 411 * devices, and for one port only on dual-port devices so that 412 * for those devices we can still use the SMBI lock to synchronize 413 * inter-port accesses to the PHY & NVM. 414 */ 415 switch (hw->mac.type) { 416 case e1000_82571: 417 case e1000_82572: 418 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 419 420 if (!(swsm2 & E1000_SWSM2_LOCK)) { 421 /* Only do this for the first interface on this card */ 422 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | 423 E1000_SWSM2_LOCK); 424 force_clear_smbi = TRUE; 425 } else 426 force_clear_smbi = FALSE; 427 break; 428 default: 429 force_clear_smbi = TRUE; 430 break; 431 } 432 433 if (force_clear_smbi) { 434 /* Make sure SWSM.SMBI is clear */ 435 swsm = E1000_READ_REG(hw, E1000_SWSM); 436 if (swsm & E1000_SWSM_SMBI) { 437 /* This bit should not be set on a first interface, and 438 * indicates that the bootagent or EFI code has 439 * improperly left this bit enabled 440 */ 441 DEBUGOUT("Please update your 82571 Bootagent\n"); 442 } 443 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 444 } 445 446 /* 447 * Initialze device specific counter of SMBI acquisition 448 * timeouts. 449 */ 450 hw->dev_spec._82571.smb_counter = 0; 451 452 return E1000_SUCCESS; 453} 454 455/** 456 * e1000_init_function_pointers_82571 - Init func ptrs. 457 * @hw: pointer to the HW structure 458 * 459 * Called to initialize all function pointers and parameters. 460 **/ 461void e1000_init_function_pointers_82571(struct e1000_hw *hw) 462{ 463 DEBUGFUNC("e1000_init_function_pointers_82571"); 464 465 hw->mac.ops.init_params = e1000_init_mac_params_82571; 466 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 467 hw->phy.ops.init_params = e1000_init_phy_params_82571; 468} 469 470/** 471 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 472 * @hw: pointer to the HW structure 473 * 474 * Reads the PHY registers and stores the PHY ID and possibly the PHY 475 * revision in the hardware structure. 476 **/ 477static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 478{ 479 struct e1000_phy_info *phy = &hw->phy; 480 s32 ret_val = E1000_SUCCESS; 481 u16 phy_id = 0; 482 483 DEBUGFUNC("e1000_get_phy_id_82571"); 484 485 switch (hw->mac.type) { 486 case e1000_82571: 487 case e1000_82572: 488 /* 489 * The 82571 firmware may still be configuring the PHY. 490 * In this case, we cannot access the PHY until the 491 * configuration is done. So we explicitly set the 492 * PHY ID. 493 */ 494 phy->id = IGP01E1000_I_PHY_ID; 495 break; 496 case e1000_82573: 497 ret_val = e1000_get_phy_id(hw); 498 break; 499 case e1000_82574: 500 case e1000_82583: 501 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 502 if (ret_val) 503 goto out; 504 505 phy->id = (u32)(phy_id << 16); 506 usec_delay(20); 507 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 508 if (ret_val) 509 goto out; 510 511 phy->id |= (u32)(phy_id); 512 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 513 break; 514 default: 515 ret_val = -E1000_ERR_PHY; 516 break; 517 } 518out: 519 return ret_val; 520} 521 522/** 523 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 524 * @hw: pointer to the HW structure 525 * 526 * Acquire the HW semaphore to access the PHY or NVM 527 **/ 528static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 529{ 530 u32 swsm; 531 s32 ret_val = E1000_SUCCESS; 532 s32 sw_timeout = hw->nvm.word_size + 1; 533 s32 fw_timeout = hw->nvm.word_size + 1; 534 s32 i = 0; 535 536 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 537 538 /* 539 * If we have timedout 3 times on trying to acquire 540 * the inter-port SMBI semaphore, there is old code 541 * operating on the other port, and it is not 542 * releasing SMBI. Modify the number of times that 543 * we try for the semaphore to interwork with this 544 * older code. 545 */ 546 if (hw->dev_spec._82571.smb_counter > 2) 547 sw_timeout = 1; 548 549 /* Get the SW semaphore */ 550 while (i < sw_timeout) { 551 swsm = E1000_READ_REG(hw, E1000_SWSM); 552 if (!(swsm & E1000_SWSM_SMBI)) 553 break; 554 555 usec_delay(50); 556 i++; 557 } 558 559 if (i == sw_timeout) { 560 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 561 hw->dev_spec._82571.smb_counter++; 562 } 563 /* Get the FW semaphore. */ 564 for (i = 0; i < fw_timeout; i++) { 565 swsm = E1000_READ_REG(hw, E1000_SWSM); 566 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 567 568 /* Semaphore acquired if bit latched */ 569 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 570 break; 571 572 usec_delay(50); 573 } 574 575 if (i == fw_timeout) { 576 /* Release semaphores */ 577 e1000_put_hw_semaphore_82571(hw); 578 DEBUGOUT("Driver can't access the NVM\n"); 579 ret_val = -E1000_ERR_NVM; 580 goto out; 581 } 582 583out: 584 return ret_val; 585} 586 587/** 588 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 589 * @hw: pointer to the HW structure 590 * 591 * Release hardware semaphore used to access the PHY or NVM 592 **/ 593static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 594{ 595 u32 swsm; 596 597 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 598 599 swsm = E1000_READ_REG(hw, E1000_SWSM); 600 601 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 602 603 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 604} 605 606/** 607 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 608 * @hw: pointer to the HW structure 609 * 610 * Acquire the HW semaphore during reset. 611 * 612 **/ 613static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 614{ 615 u32 extcnf_ctrl; 616 s32 ret_val = E1000_SUCCESS; 617 s32 i = 0; 618 619 DEBUGFUNC("e1000_get_hw_semaphore_82573"); 620 621 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 622 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 623 do { 624 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 625 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 626 627 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 628 break; 629 630 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 631 632 msec_delay(2); 633 i++; 634 } while (i < MDIO_OWNERSHIP_TIMEOUT); 635 636 if (i == MDIO_OWNERSHIP_TIMEOUT) { 637 /* Release semaphores */ 638 e1000_put_hw_semaphore_82573(hw); 639 DEBUGOUT("Driver can't access the PHY\n"); 640 ret_val = -E1000_ERR_PHY; 641 goto out; 642 } 643 644out: 645 return ret_val; 646} 647 648/** 649 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 650 * @hw: pointer to the HW structure 651 * 652 * Release hardware semaphore used during reset. 653 * 654 **/ 655static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 656{ 657 u32 extcnf_ctrl; 658 659 DEBUGFUNC("e1000_put_hw_semaphore_82573"); 660 661 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 662 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 663 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 664} 665 666/** 667 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 668 * @hw: pointer to the HW structure 669 * 670 * Acquire the HW semaphore to access the PHY or NVM. 671 * 672 **/ 673static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 674{ 675 s32 ret_val; 676 677 DEBUGFUNC("e1000_get_hw_semaphore_82574"); 678 679 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex); 680 ret_val = e1000_get_hw_semaphore_82573(hw); 681 if (ret_val) 682 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 683 return ret_val; 684} 685 686/** 687 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 688 * @hw: pointer to the HW structure 689 * 690 * Release hardware semaphore used to access the PHY or NVM 691 * 692 **/ 693static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 694{ 695 DEBUGFUNC("e1000_put_hw_semaphore_82574"); 696 697 e1000_put_hw_semaphore_82573(hw); 698 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 699} 700 701/** 702 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 703 * @hw: pointer to the HW structure 704 * @active: TRUE to enable LPLU, FALSE to disable 705 * 706 * Sets the LPLU D0 state according to the active flag. 707 * LPLU will not be activated unless the 708 * device autonegotiation advertisement meets standards of 709 * either 10 or 10/100 or 10/100/1000 at all duplexes. 710 * This is a function pointer entry point only called by 711 * PHY setup routines. 712 **/ 713static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 714{ 715 u16 data = E1000_READ_REG(hw, E1000_POEMB); 716 717 DEBUGFUNC("e1000_set_d0_lplu_state_82574"); 718 719 if (active) 720 data |= E1000_PHY_CTRL_D0A_LPLU; 721 else 722 data &= ~E1000_PHY_CTRL_D0A_LPLU; 723 724 E1000_WRITE_REG(hw, E1000_POEMB, data); 725 return E1000_SUCCESS; 726} 727 728/** 729 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 730 * @hw: pointer to the HW structure 731 * @active: boolean used to enable/disable lplu 732 * 733 * The low power link up (lplu) state is set to the power management level D3 734 * when active is TRUE, else clear lplu for D3. LPLU 735 * is used during Dx states where the power conservation is most important. 736 * During driver activity, SmartSpeed should be enabled so performance is 737 * maintained. 738 **/ 739static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 740{ 741 u16 data = E1000_READ_REG(hw, E1000_POEMB); 742 743 DEBUGFUNC("e1000_set_d3_lplu_state_82574"); 744 745 if (!active) { 746 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 747 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 748 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 749 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 750 data |= E1000_PHY_CTRL_NOND0A_LPLU; 751 } 752 753 E1000_WRITE_REG(hw, E1000_POEMB, data); 754 return E1000_SUCCESS; 755} 756 757/** 758 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 759 * @hw: pointer to the HW structure 760 * 761 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 762 * Then for non-82573 hardware, set the EEPROM access request bit and wait 763 * for EEPROM access grant bit. If the access grant bit is not set, release 764 * hardware semaphore. 765 **/ 766static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 767{ 768 s32 ret_val; 769 770 DEBUGFUNC("e1000_acquire_nvm_82571"); 771 772 ret_val = e1000_get_hw_semaphore_82571(hw); 773 if (ret_val) 774 goto out; 775 776 switch (hw->mac.type) { 777 case e1000_82573: 778 break; 779 default: 780 ret_val = e1000_acquire_nvm_generic(hw); 781 break; 782 } 783 784 if (ret_val) 785 e1000_put_hw_semaphore_82571(hw); 786 787out: 788 return ret_val; 789} 790 791/** 792 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 793 * @hw: pointer to the HW structure 794 * 795 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 796 **/ 797static void e1000_release_nvm_82571(struct e1000_hw *hw) 798{ 799 DEBUGFUNC("e1000_release_nvm_82571"); 800 801 e1000_release_nvm_generic(hw); 802 e1000_put_hw_semaphore_82571(hw); 803} 804 805/** 806 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 807 * @hw: pointer to the HW structure 808 * @offset: offset within the EEPROM to be written to 809 * @words: number of words to write 810 * @data: 16 bit word(s) to be written to the EEPROM 811 * 812 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 813 * 814 * If e1000_update_nvm_checksum is not called after this function, the 815 * EEPROM will most likely contain an invalid checksum. 816 **/ 817static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 818 u16 *data) 819{ 820 s32 ret_val = E1000_SUCCESS; 821 822 DEBUGFUNC("e1000_write_nvm_82571"); 823 824 switch (hw->mac.type) { 825 case e1000_82573: 826 case e1000_82574: 827 case e1000_82583: 828 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 829 break; 830 case e1000_82571: 831 case e1000_82572: 832 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 833 break; 834 default: 835 ret_val = -E1000_ERR_NVM; 836 break; 837 } 838 839 return ret_val; 840} 841 842/** 843 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 844 * @hw: pointer to the HW structure 845 * 846 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 847 * up to the checksum. Then calculates the EEPROM checksum and writes the 848 * value to the EEPROM. 849 **/ 850static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 851{ 852 u32 eecd; 853 s32 ret_val; 854 u16 i; 855 856 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 857 858 ret_val = e1000_update_nvm_checksum_generic(hw); 859 if (ret_val) 860 goto out; 861 862 /* 863 * If our nvm is an EEPROM, then we're done 864 * otherwise, commit the checksum to the flash NVM. 865 */ 866 if (hw->nvm.type != e1000_nvm_flash_hw) 867 goto out; 868 869 /* Check for pending operations. */ 870 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 871 msec_delay(1); 872 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 873 break; 874 } 875 876 if (i == E1000_FLASH_UPDATES) { 877 ret_val = -E1000_ERR_NVM; 878 goto out; 879 } 880 881 /* Reset the firmware if using STM opcode. */ 882 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 883 /* 884 * The enabling of and the actual reset must be done 885 * in two write cycles. 886 */ 887 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 888 E1000_WRITE_FLUSH(hw); 889 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 890 } 891 892 /* Commit the write to flash */ 893 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 894 E1000_WRITE_REG(hw, E1000_EECD, eecd); 895 896 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 897 msec_delay(1); 898 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 899 break; 900 } 901 902 if (i == E1000_FLASH_UPDATES) { 903 ret_val = -E1000_ERR_NVM; 904 goto out; 905 } 906 907out: 908 return ret_val; 909} 910 911/** 912 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 913 * @hw: pointer to the HW structure 914 * 915 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 916 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 917 **/ 918static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 919{ 920 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 921 922 if (hw->nvm.type == e1000_nvm_flash_hw) 923 e1000_fix_nvm_checksum_82571(hw); 924 925 return e1000_validate_nvm_checksum_generic(hw); 926} 927 928/** 929 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 930 * @hw: pointer to the HW structure 931 * @offset: offset within the EEPROM to be written to 932 * @words: number of words to write 933 * @data: 16 bit word(s) to be written to the EEPROM 934 * 935 * After checking for invalid values, poll the EEPROM to ensure the previous 936 * command has completed before trying to write the next word. After write 937 * poll for completion. 938 * 939 * If e1000_update_nvm_checksum is not called after this function, the 940 * EEPROM will most likely contain an invalid checksum. 941 **/ 942static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 943 u16 words, u16 *data) 944{ 945 struct e1000_nvm_info *nvm = &hw->nvm; 946 u32 i, eewr = 0; 947 s32 ret_val = 0; 948 949 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 950 951 /* 952 * A check for invalid values: offset too large, too many words, 953 * and not enough words. 954 */ 955 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 956 (words == 0)) { 957 DEBUGOUT("nvm parameter(s) out of bounds\n"); 958 ret_val = -E1000_ERR_NVM; 959 goto out; 960 } 961 962 for (i = 0; i < words; i++) { 963 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 964 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 965 E1000_NVM_RW_REG_START; 966 967 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 968 if (ret_val) 969 break; 970 971 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 972 973 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 974 if (ret_val) 975 break; 976 } 977 978out: 979 return ret_val; 980} 981 982/** 983 * e1000_get_cfg_done_82571 - Poll for configuration done 984 * @hw: pointer to the HW structure 985 * 986 * Reads the management control register for the config done bit to be set. 987 **/ 988static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 989{ 990 s32 timeout = PHY_CFG_TIMEOUT; 991 s32 ret_val = E1000_SUCCESS; 992 993 DEBUGFUNC("e1000_get_cfg_done_82571"); 994 995 while (timeout) { 996 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 997 E1000_NVM_CFG_DONE_PORT_0) 998 break; 999 msec_delay(1); 1000 timeout--; 1001 } 1002 if (!timeout) { 1003 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1004 ret_val = -E1000_ERR_RESET; 1005 goto out; 1006 } 1007 1008out: 1009 return ret_val; 1010} 1011 1012/** 1013 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 1014 * @hw: pointer to the HW structure 1015 * @active: TRUE to enable LPLU, FALSE to disable 1016 * 1017 * Sets the LPLU D0 state according to the active flag. When activating LPLU 1018 * this function also disables smart speed and vice versa. LPLU will not be 1019 * activated unless the device autonegotiation advertisement meets standards 1020 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 1021 * pointer entry point only called by PHY setup routines. 1022 **/ 1023static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 1024{ 1025 struct e1000_phy_info *phy = &hw->phy; 1026 s32 ret_val = E1000_SUCCESS; 1027 u16 data; 1028 1029 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 1030 1031 if (!(phy->ops.read_reg)) 1032 goto out; 1033 1034 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1035 if (ret_val) 1036 goto out; 1037 1038 if (active) { 1039 data |= IGP02E1000_PM_D0_LPLU; 1040 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1041 data); 1042 if (ret_val) 1043 goto out; 1044 1045 /* When LPLU is enabled, we should disable SmartSpeed */ 1046 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1047 &data); 1048 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1049 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1050 data); 1051 if (ret_val) 1052 goto out; 1053 } else { 1054 data &= ~IGP02E1000_PM_D0_LPLU; 1055 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1056 data); 1057 /* 1058 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1059 * during Dx states where the power conservation is most 1060 * important. During driver activity we should enable 1061 * SmartSpeed, so performance is maintained. 1062 */ 1063 if (phy->smart_speed == e1000_smart_speed_on) { 1064 ret_val = phy->ops.read_reg(hw, 1065 IGP01E1000_PHY_PORT_CONFIG, 1066 &data); 1067 if (ret_val) 1068 goto out; 1069 1070 data |= IGP01E1000_PSCFR_SMART_SPEED; 1071 ret_val = phy->ops.write_reg(hw, 1072 IGP01E1000_PHY_PORT_CONFIG, 1073 data); 1074 if (ret_val) 1075 goto out; 1076 } else if (phy->smart_speed == e1000_smart_speed_off) { 1077 ret_val = phy->ops.read_reg(hw, 1078 IGP01E1000_PHY_PORT_CONFIG, 1079 &data); 1080 if (ret_val) 1081 goto out; 1082 1083 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1084 ret_val = phy->ops.write_reg(hw, 1085 IGP01E1000_PHY_PORT_CONFIG, 1086 data); 1087 if (ret_val) 1088 goto out; 1089 } 1090 } 1091 1092out: 1093 return ret_val; 1094} 1095 1096/** 1097 * e1000_reset_hw_82571 - Reset hardware 1098 * @hw: pointer to the HW structure 1099 * 1100 * This resets the hardware into a known state. 1101 **/ 1102static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1103{ 1104 u32 ctrl, ctrl_ext; 1105 s32 ret_val; 1106 1107 DEBUGFUNC("e1000_reset_hw_82571"); 1108 1109 /* 1110 * Prevent the PCI-E bus from sticking if there is no TLP connection 1111 * on the last TLP read/write transaction when MAC is reset. 1112 */ 1113 ret_val = e1000_disable_pcie_master_generic(hw); 1114 if (ret_val) 1115 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1116 1117 DEBUGOUT("Masking off all interrupts\n"); 1118 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1119 1120 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1121 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1122 E1000_WRITE_FLUSH(hw); 1123 1124 msec_delay(10); 1125 1126 /* 1127 * Must acquire the MDIO ownership before MAC reset. 1128 * Ownership defaults to firmware after a reset. 1129 */ 1130 switch (hw->mac.type) { 1131 case e1000_82573: 1132 ret_val = e1000_get_hw_semaphore_82573(hw); 1133 break; 1134 case e1000_82574: 1135 case e1000_82583: 1136 ret_val = e1000_get_hw_semaphore_82574(hw); 1137 break; 1138 default: 1139 break; 1140 } 1141 if (ret_val) 1142 DEBUGOUT("Cannot acquire MDIO ownership\n"); 1143 1144 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1145 1146 DEBUGOUT("Issuing a global reset to MAC\n"); 1147 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1148 1149 /* Must release MDIO ownership and mutex after MAC reset. */ 1150 switch (hw->mac.type) { 1151 case e1000_82574: 1152 case e1000_82583: 1153 e1000_put_hw_semaphore_82574(hw); 1154 break; 1155 default: 1156 break; 1157 } 1158 1159 if (hw->nvm.type == e1000_nvm_flash_hw) { 1160 usec_delay(10); 1161 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1162 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1163 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1164 E1000_WRITE_FLUSH(hw); 1165 } 1166 1167 ret_val = e1000_get_auto_rd_done_generic(hw); 1168 if (ret_val) 1169 /* We don't want to continue accessing MAC registers. */ 1170 goto out; 1171 1172 /* 1173 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1174 * Need to wait for Phy configuration completion before accessing 1175 * NVM and Phy. 1176 */ 1177 1178 switch (hw->mac.type) { 1179 case e1000_82573: 1180 case e1000_82574: 1181 case e1000_82583: 1182 msec_delay(25); 1183 break; 1184 default: 1185 break; 1186 } 1187 1188 /* Clear any pending interrupt events. */ 1189 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1190 E1000_READ_REG(hw, E1000_ICR); 1191 1192 if (hw->mac.type == e1000_82571) { 1193 /* Install any alternate MAC address into RAR0 */ 1194 ret_val = e1000_check_alt_mac_addr_generic(hw); 1195 if (ret_val) 1196 goto out; 1197 1198 e1000_set_laa_state_82571(hw, TRUE); 1199 } 1200 1201 /* Reinitialize the 82571 serdes link state machine */ 1202 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1203 hw->mac.serdes_link_state = e1000_serdes_link_down; 1204 1205out: 1206 return ret_val; 1207} 1208 1209/** 1210 * e1000_init_hw_82571 - Initialize hardware 1211 * @hw: pointer to the HW structure 1212 * 1213 * This inits the hardware readying it for operation. 1214 **/ 1215static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1216{ 1217 struct e1000_mac_info *mac = &hw->mac; 1218 u32 reg_data; 1219 s32 ret_val; 1220 u16 i, rar_count = mac->rar_entry_count; 1221 1222 DEBUGFUNC("e1000_init_hw_82571"); 1223 1224 e1000_initialize_hw_bits_82571(hw); 1225 1226 /* Initialize identification LED */ 1227 ret_val = mac->ops.id_led_init(hw); 1228 if (ret_val) 1229 DEBUGOUT("Error initializing identification LED\n"); 1230 /* This is not fatal and we should not stop init due to this */ 1231 1232 /* Disabling VLAN filtering */ 1233 DEBUGOUT("Initializing the IEEE VLAN\n"); 1234 mac->ops.clear_vfta(hw); 1235 1236 /* Setup the receive address. */ 1237 /* 1238 * If, however, a locally administered address was assigned to the 1239 * 82571, we must reserve a RAR for it to work around an issue where 1240 * resetting one port will reload the MAC on the other port. 1241 */ 1242 if (e1000_get_laa_state_82571(hw)) 1243 rar_count--; 1244 e1000_init_rx_addrs_generic(hw, rar_count); 1245 1246 /* Zero out the Multicast HASH table */ 1247 DEBUGOUT("Zeroing the MTA\n"); 1248 for (i = 0; i < mac->mta_reg_count; i++) 1249 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1250 1251 /* Setup link and flow control */ 1252 ret_val = mac->ops.setup_link(hw); 1253 1254 /* Set the transmit descriptor write-back policy */ 1255 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1256 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1257 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 1258 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1259 1260 /* ...for both queues. */ 1261 switch (mac->type) { 1262 case e1000_82573: 1263 e1000_enable_tx_pkt_filtering_generic(hw); 1264 /* fall through */ 1265 case e1000_82574: 1266 case e1000_82583: 1267 reg_data = E1000_READ_REG(hw, E1000_GCR); 1268 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1269 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1270 break; 1271 default: 1272 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1273 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1274 E1000_TXDCTL_FULL_TX_DESC_WB | 1275 E1000_TXDCTL_COUNT_DESC; 1276 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1277 break; 1278 } 1279 1280 /* 1281 * Clear all of the statistics registers (clear on read). It is 1282 * important that we do this after we have tried to establish link 1283 * because the symbol error count will increment wildly if there 1284 * is no link. 1285 */ 1286 e1000_clear_hw_cntrs_82571(hw); 1287 1288 return ret_val; 1289} 1290 1291/** 1292 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1293 * @hw: pointer to the HW structure 1294 * 1295 * Initializes required hardware-dependent bits needed for normal operation. 1296 **/ 1297static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1298{ 1299 u32 reg; 1300 1301 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1302 1303 /* Transmit Descriptor Control 0 */ 1304 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1305 reg |= (1 << 22); 1306 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1307 1308 /* Transmit Descriptor Control 1 */ 1309 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1310 reg |= (1 << 22); 1311 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1312 1313 /* Transmit Arbitration Control 0 */ 1314 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1315 reg &= ~(0xF << 27); /* 30:27 */ 1316 switch (hw->mac.type) { 1317 case e1000_82571: 1318 case e1000_82572: 1319 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1320 break; 1321 case e1000_82574: 1322 case e1000_82583: 1323 reg |= (1 << 26); 1324 break; 1325 default: 1326 break; 1327 } 1328 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1329 1330 /* Transmit Arbitration Control 1 */ 1331 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1332 switch (hw->mac.type) { 1333 case e1000_82571: 1334 case e1000_82572: 1335 reg &= ~((1 << 29) | (1 << 30)); 1336 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1337 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1338 reg &= ~(1 << 28); 1339 else 1340 reg |= (1 << 28); 1341 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1342 break; 1343 default: 1344 break; 1345 } 1346 1347 /* Device Control */ 1348 switch (hw->mac.type) { 1349 case e1000_82573: 1350 case e1000_82574: 1351 case e1000_82583: 1352 reg = E1000_READ_REG(hw, E1000_CTRL); 1353 reg &= ~(1 << 29); 1354 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1355 break; 1356 default: 1357 break; 1358 } 1359 1360 /* Extended Device Control */ 1361 switch (hw->mac.type) { 1362 case e1000_82573: 1363 case e1000_82574: 1364 case e1000_82583: 1365 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1366 reg &= ~(1 << 23); 1367 reg |= (1 << 22); 1368 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1369 break; 1370 default: 1371 break; 1372 } 1373 1374 if (hw->mac.type == e1000_82571) { 1375 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1376 reg |= E1000_PBA_ECC_CORR_EN; 1377 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1378 } 1379 1380 /* 1381 * Workaround for hardware errata. 1382 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1383 */ 1384 if ((hw->mac.type == e1000_82571) || 1385 (hw->mac.type == e1000_82572)) { 1386 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1387 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1388 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1389 } 1390 1391 /* PCI-Ex Control Registers */ 1392 switch (hw->mac.type) { 1393 case e1000_82574: 1394 case e1000_82583: 1395 reg = E1000_READ_REG(hw, E1000_GCR); 1396 reg |= (1 << 22); 1397 E1000_WRITE_REG(hw, E1000_GCR, reg); 1398 1399 /* 1400 * Workaround for hardware errata. 1401 * apply workaround for hardware errata documented in errata 1402 * docs Fixes issue where some error prone or unreliable PCIe 1403 * completions are occurring, particularly with ASPM enabled. 1404 * Without fix, issue can cause Tx timeouts. 1405 */ 1406 reg = E1000_READ_REG(hw, E1000_GCR2); 1407 reg |= 1; 1408 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1409 break; 1410 default: 1411 break; 1412 } 1413 1414 return; 1415} 1416 1417/** 1418 * e1000_clear_vfta_82571 - Clear VLAN filter table 1419 * @hw: pointer to the HW structure 1420 * 1421 * Clears the register array which contains the VLAN filter table by 1422 * setting all the values to 0. 1423 **/ 1424static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1425{ 1426 u32 offset; 1427 u32 vfta_value = 0; 1428 u32 vfta_offset = 0; 1429 u32 vfta_bit_in_reg = 0; 1430 1431 DEBUGFUNC("e1000_clear_vfta_82571"); 1432 1433 switch (hw->mac.type) { 1434 case e1000_82573: 1435 case e1000_82574: 1436 case e1000_82583: 1437 if (hw->mng_cookie.vlan_id != 0) { 1438 /* 1439 * The VFTA is a 4096b bit-field, each identifying 1440 * a single VLAN ID. The following operations 1441 * determine which 32b entry (i.e. offset) into the 1442 * array we want to set the VLAN ID (i.e. bit) of 1443 * the manageability unit. 1444 */ 1445 vfta_offset = (hw->mng_cookie.vlan_id >> 1446 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1447 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1448 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1449 } 1450 break; 1451 default: 1452 break; 1453 } 1454 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1455 /* 1456 * If the offset we want to clear is the same offset of the 1457 * manageability VLAN ID, then clear all bits except that of 1458 * the manageability unit. 1459 */ 1460 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1461 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1462 E1000_WRITE_FLUSH(hw); 1463 } 1464} 1465 1466/** 1467 * e1000_check_mng_mode_82574 - Check manageability is enabled 1468 * @hw: pointer to the HW structure 1469 * 1470 * Reads the NVM Initialization Control Word 2 and returns TRUE 1471 * (>0) if any manageability is enabled, else FALSE (0). 1472 **/ 1473static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1474{ 1475 u16 data; 1476 1477 DEBUGFUNC("e1000_check_mng_mode_82574"); 1478 1479 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1480 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1481} 1482 1483/** 1484 * e1000_led_on_82574 - Turn LED on 1485 * @hw: pointer to the HW structure 1486 * 1487 * Turn LED on. 1488 **/ 1489static s32 e1000_led_on_82574(struct e1000_hw *hw) 1490{ 1491 u32 ctrl; 1492 u32 i; 1493 1494 DEBUGFUNC("e1000_led_on_82574"); 1495 1496 ctrl = hw->mac.ledctl_mode2; 1497 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1498 /* 1499 * If no link, then turn LED on by setting the invert bit 1500 * for each LED that's "on" (0x0E) in ledctl_mode2. 1501 */ 1502 for (i = 0; i < 4; i++) 1503 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1504 E1000_LEDCTL_MODE_LED_ON) 1505 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1506 } 1507 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1508 1509 return E1000_SUCCESS; 1510} 1511 1512/** 1513 * e1000_check_phy_82574 - check 82574 phy hung state 1514 * @hw: pointer to the HW structure 1515 * 1516 * Returns whether phy is hung or not 1517 **/ 1518bool e1000_check_phy_82574(struct e1000_hw *hw) 1519{ 1520 u16 status_1kbt = 0; 1521 u16 receive_errors = 0; 1522 bool phy_hung = FALSE; 1523 s32 ret_val = E1000_SUCCESS; 1524 1525 DEBUGFUNC("e1000_check_phy_82574"); 1526 1527 /* 1528 * Read PHY Receive Error counter first, if its is max - all F's then 1529 * read the Base1000T status register If both are max then PHY is hung. 1530 */ 1531 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1532 &receive_errors); 1533 if (ret_val) 1534 goto out; 1535 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1536 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1537 &status_1kbt); 1538 if (ret_val) 1539 goto out; 1540 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1541 E1000_IDLE_ERROR_COUNT_MASK) 1542 phy_hung = TRUE; 1543 } 1544out: 1545 return phy_hung; 1546} 1547 1548 1549/** 1550 * e1000_setup_link_82571 - Setup flow control and link settings 1551 * @hw: pointer to the HW structure 1552 * 1553 * Determines which flow control settings to use, then configures flow 1554 * control. Calls the appropriate media-specific link configuration 1555 * function. Assuming the adapter has a valid link partner, a valid link 1556 * should be established. Assumes the hardware has previously been reset 1557 * and the transmitter and receiver are not enabled. 1558 **/ 1559static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1560{ 1561 DEBUGFUNC("e1000_setup_link_82571"); 1562 1563 /* 1564 * 82573 does not have a word in the NVM to determine 1565 * the default flow control setting, so we explicitly 1566 * set it to full. 1567 */ 1568 switch (hw->mac.type) { 1569 case e1000_82573: 1570 case e1000_82574: 1571 case e1000_82583: 1572 if (hw->fc.requested_mode == e1000_fc_default) 1573 hw->fc.requested_mode = e1000_fc_full; 1574 break; 1575 default: 1576 break; 1577 } 1578 1579 return e1000_setup_link_generic(hw); 1580} 1581 1582/** 1583 * e1000_setup_copper_link_82571 - Configure copper link settings 1584 * @hw: pointer to the HW structure 1585 * 1586 * Configures the link for auto-neg or forced speed and duplex. Then we check 1587 * for link, once link is established calls to configure collision distance 1588 * and flow control are called. 1589 **/ 1590static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1591{ 1592 u32 ctrl; 1593 s32 ret_val; 1594 1595 DEBUGFUNC("e1000_setup_copper_link_82571"); 1596 1597 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1598 ctrl |= E1000_CTRL_SLU; 1599 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1600 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1601 1602 switch (hw->phy.type) { 1603 case e1000_phy_m88: 1604 case e1000_phy_bm: 1605 ret_val = e1000_copper_link_setup_m88(hw); 1606 break; 1607 case e1000_phy_igp_2: 1608 ret_val = e1000_copper_link_setup_igp(hw); 1609 break; 1610 default: 1611 ret_val = -E1000_ERR_PHY; 1612 break; 1613 } 1614 1615 if (ret_val) 1616 goto out; 1617 1618 ret_val = e1000_setup_copper_link_generic(hw); 1619 1620out: 1621 return ret_val; 1622} 1623 1624/** 1625 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1626 * @hw: pointer to the HW structure 1627 * 1628 * Configures collision distance and flow control for fiber and serdes links. 1629 * Upon successful setup, poll for link. 1630 **/ 1631static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1632{ 1633 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1634 1635 switch (hw->mac.type) { 1636 case e1000_82571: 1637 case e1000_82572: 1638 /* 1639 * If SerDes loopback mode is entered, there is no form 1640 * of reset to take the adapter out of that mode. So we 1641 * have to explicitly take the adapter out of loopback 1642 * mode. This prevents drivers from twiddling their thumbs 1643 * if another tool failed to take it out of loopback mode. 1644 */ 1645 E1000_WRITE_REG(hw, E1000_SCTL, 1646 E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1647 break; 1648 default: 1649 break; 1650 } 1651 1652 return e1000_setup_fiber_serdes_link_generic(hw); 1653} 1654 1655/** 1656 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1657 * @hw: pointer to the HW structure 1658 * 1659 * Reports the link state as up or down. 1660 * 1661 * If autonegotiation is supported by the link partner, the link state is 1662 * determined by the result of autonegotiation. This is the most likely case. 1663 * If autonegotiation is not supported by the link partner, and the link 1664 * has a valid signal, force the link up. 1665 * 1666 * The link state is represented internally here by 4 states: 1667 * 1668 * 1) down 1669 * 2) autoneg_progress 1670 * 3) autoneg_complete (the link successfully autonegotiated) 1671 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1672 * 1673 **/ 1674static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1675{ 1676 struct e1000_mac_info *mac = &hw->mac; 1677 u32 rxcw; 1678 u32 ctrl; 1679 u32 status; 1680 u32 txcw; 1681 u32 i; 1682 s32 ret_val = E1000_SUCCESS; 1683 1684 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1685 1686 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1687 status = E1000_READ_REG(hw, E1000_STATUS); 1688 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1689 1690 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1691 1692 /* Receiver is synchronized with no invalid bits. */ 1693 switch (mac->serdes_link_state) { 1694 case e1000_serdes_link_autoneg_complete: 1695 if (!(status & E1000_STATUS_LU)) { 1696 /* 1697 * We have lost link, retry autoneg before 1698 * reporting link failure 1699 */ 1700 mac->serdes_link_state = 1701 e1000_serdes_link_autoneg_progress; 1702 mac->serdes_has_link = FALSE; 1703 DEBUGOUT("AN_UP -> AN_PROG\n"); 1704 } else { 1705 mac->serdes_has_link = TRUE; 1706 } 1707 break; 1708 1709 case e1000_serdes_link_forced_up: 1710 /* 1711 * If we are receiving /C/ ordered sets, re-enable 1712 * auto-negotiation in the TXCW register and disable 1713 * forced link in the Device Control register in an 1714 * attempt to auto-negotiate with our link partner. 1715 * If the partner code word is null, stop forcing 1716 * and restart auto negotiation. 1717 */ 1718 if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { 1719 /* Enable autoneg, and unforce link up */ 1720 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1721 E1000_WRITE_REG(hw, E1000_CTRL, 1722 (ctrl & ~E1000_CTRL_SLU)); 1723 mac->serdes_link_state = 1724 e1000_serdes_link_autoneg_progress; 1725 mac->serdes_has_link = FALSE; 1726 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1727 } else { 1728 mac->serdes_has_link = TRUE; 1729 } 1730 break; 1731 1732 case e1000_serdes_link_autoneg_progress: 1733 if (rxcw & E1000_RXCW_C) { 1734 /* 1735 * We received /C/ ordered sets, meaning the 1736 * link partner has autonegotiated, and we can 1737 * trust the Link Up (LU) status bit. 1738 */ 1739 if (status & E1000_STATUS_LU) { 1740 mac->serdes_link_state = 1741 e1000_serdes_link_autoneg_complete; 1742 DEBUGOUT("AN_PROG -> AN_UP\n"); 1743 mac->serdes_has_link = TRUE; 1744 } else { 1745 /* Autoneg completed, but failed. */ 1746 mac->serdes_link_state = 1747 e1000_serdes_link_down; 1748 DEBUGOUT("AN_PROG -> DOWN\n"); 1749 } 1750 } else { 1751 /* 1752 * The link partner did not autoneg. 1753 * Force link up and full duplex, and change 1754 * state to forced. 1755 */ 1756 E1000_WRITE_REG(hw, E1000_TXCW, 1757 (mac->txcw & ~E1000_TXCW_ANE)); 1758 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1759 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1760 1761 /* Configure Flow Control after link up. */ 1762 ret_val = 1763 e1000_config_fc_after_link_up_generic(hw); 1764 if (ret_val) { 1765 DEBUGOUT("Error config flow control\n"); 1766 break; 1767 } 1768 mac->serdes_link_state = 1769 e1000_serdes_link_forced_up; 1770 mac->serdes_has_link = TRUE; 1771 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1772 } 1773 break; 1774 1775 case e1000_serdes_link_down: 1776 default: 1777 /* 1778 * The link was down but the receiver has now gained 1779 * valid sync, so lets see if we can bring the link 1780 * up. 1781 */ 1782 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1783 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & 1784 ~E1000_CTRL_SLU)); 1785 mac->serdes_link_state = 1786 e1000_serdes_link_autoneg_progress; 1787 mac->serdes_has_link = FALSE; 1788 DEBUGOUT("DOWN -> AN_PROG\n"); 1789 break; 1790 } 1791 } else { 1792 if (!(rxcw & E1000_RXCW_SYNCH)) { 1793 mac->serdes_has_link = FALSE; 1794 mac->serdes_link_state = e1000_serdes_link_down; 1795 DEBUGOUT("ANYSTATE -> DOWN\n"); 1796 } else { 1797 /* 1798 * Check several times, if Sync and Config 1799 * both are consistently 1 then simply ignore 1800 * the Invalid bit and restart Autoneg 1801 */ 1802 for (i = 0; i < AN_RETRY_COUNT; i++) { 1803 usec_delay(10); 1804 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1805 if ((rxcw & E1000_RXCW_IV) && 1806 !((rxcw & E1000_RXCW_SYNCH) && 1807 (rxcw & E1000_RXCW_C))) { 1808 mac->serdes_has_link = FALSE; 1809 mac->serdes_link_state = 1810 e1000_serdes_link_down; 1811 DEBUGOUT("ANYSTATE -> DOWN\n"); 1812 break; 1813 } 1814 } 1815 1816 if (i == AN_RETRY_COUNT) { 1817 txcw = E1000_READ_REG(hw, E1000_TXCW); 1818 txcw |= E1000_TXCW_ANE; 1819 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1820 mac->serdes_link_state = 1821 e1000_serdes_link_autoneg_progress; 1822 mac->serdes_has_link = FALSE; 1823 DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1824 } 1825 } 1826 } 1827 1828 return ret_val; 1829} 1830 1831/** 1832 * e1000_valid_led_default_82571 - Verify a valid default LED config 1833 * @hw: pointer to the HW structure 1834 * @data: pointer to the NVM (EEPROM) 1835 * 1836 * Read the EEPROM for the current default LED configuration. If the 1837 * LED configuration is not valid, set to a valid LED configuration. 1838 **/ 1839static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1840{ 1841 s32 ret_val; 1842 1843 DEBUGFUNC("e1000_valid_led_default_82571"); 1844 1845 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1846 if (ret_val) { 1847 DEBUGOUT("NVM Read Error\n"); 1848 goto out; 1849 } 1850 1851 switch (hw->mac.type) { 1852 case e1000_82573: 1853 case e1000_82574: 1854 case e1000_82583: 1855 if (*data == ID_LED_RESERVED_F746) 1856 *data = ID_LED_DEFAULT_82573; 1857 break; 1858 default: 1859 if (*data == ID_LED_RESERVED_0000 || 1860 *data == ID_LED_RESERVED_FFFF) 1861 *data = ID_LED_DEFAULT; 1862 break; 1863 } 1864 1865out: 1866 return ret_val; 1867} 1868 1869/** 1870 * e1000_get_laa_state_82571 - Get locally administered address state 1871 * @hw: pointer to the HW structure 1872 * 1873 * Retrieve and return the current locally administered address state. 1874 **/ 1875bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1876{ 1877 DEBUGFUNC("e1000_get_laa_state_82571"); 1878 1879 if (hw->mac.type != e1000_82571) 1880 return FALSE; 1881 1882 return hw->dev_spec._82571.laa_is_present; 1883} 1884 1885/** 1886 * e1000_set_laa_state_82571 - Set locally administered address state 1887 * @hw: pointer to the HW structure 1888 * @state: enable/disable locally administered address 1889 * 1890 * Enable/Disable the current locally administered address state. 1891 **/ 1892void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1893{ 1894 DEBUGFUNC("e1000_set_laa_state_82571"); 1895 1896 if (hw->mac.type != e1000_82571) 1897 return; 1898 1899 hw->dev_spec._82571.laa_is_present = state; 1900 1901 /* If workaround is activated... */ 1902 if (state) 1903 /* 1904 * Hold a copy of the LAA in RAR[14] This is done so that 1905 * between the time RAR[0] gets clobbered and the time it 1906 * gets fixed, the actual LAA is in one of the RARs and no 1907 * incoming packets directed to this port are dropped. 1908 * Eventually the LAA will be in RAR[0] and RAR[14]. 1909 */ 1910 e1000_rar_set_generic(hw, hw->mac.addr, 1911 hw->mac.rar_entry_count - 1); 1912 return; 1913} 1914 1915/** 1916 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1917 * @hw: pointer to the HW structure 1918 * 1919 * Verifies that the EEPROM has completed the update. After updating the 1920 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1921 * the checksum fix is not implemented, we need to set the bit and update 1922 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1923 * we need to return bad checksum. 1924 **/ 1925static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1926{ 1927 struct e1000_nvm_info *nvm = &hw->nvm; 1928 s32 ret_val = E1000_SUCCESS; 1929 u16 data; 1930 1931 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1932 1933 if (nvm->type != e1000_nvm_flash_hw) 1934 goto out; 1935 1936 /* 1937 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1938 * 10h-12h. Checksum may need to be fixed. 1939 */ 1940 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1941 if (ret_val) 1942 goto out; 1943 1944 if (!(data & 0x10)) { 1945 /* 1946 * Read 0x23 and check bit 15. This bit is a 1 1947 * when the checksum has already been fixed. If 1948 * the checksum is still wrong and this bit is a 1949 * 1, we need to return bad checksum. Otherwise, 1950 * we need to set this bit to a 1 and update the 1951 * checksum. 1952 */ 1953 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1954 if (ret_val) 1955 goto out; 1956 1957 if (!(data & 0x8000)) { 1958 data |= 0x8000; 1959 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1960 if (ret_val) 1961 goto out; 1962 ret_val = nvm->ops.update(hw); 1963 } 1964 } 1965 1966out: 1967 return ret_val; 1968} 1969 1970 1971/** 1972 * e1000_read_mac_addr_82571 - Read device MAC address 1973 * @hw: pointer to the HW structure 1974 **/ 1975static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1976{ 1977 s32 ret_val = E1000_SUCCESS; 1978 1979 DEBUGFUNC("e1000_read_mac_addr_82571"); 1980 1981 if (hw->mac.type == e1000_82571) { 1982 /* 1983 * If there's an alternate MAC address place it in RAR0 1984 * so that it will override the Si installed default perm 1985 * address. 1986 */ 1987 ret_val = e1000_check_alt_mac_addr_generic(hw); 1988 if (ret_val) 1989 goto out; 1990 } 1991 1992 ret_val = e1000_read_mac_addr_generic(hw); 1993 1994out: 1995 return ret_val; 1996} 1997 1998/** 1999 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 2000 * @hw: pointer to the HW structure 2001 * 2002 * In the case of a PHY power down to save power, or to turn off link during a 2003 * driver unload, or wake on lan is not enabled, remove the link. 2004 **/ 2005static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 2006{ 2007 struct e1000_phy_info *phy = &hw->phy; 2008 struct e1000_mac_info *mac = &hw->mac; 2009 2010 if (!(phy->ops.check_reset_block)) 2011 return; 2012 2013 /* If the management interface is not enabled, then power down */ 2014 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 2015 e1000_power_down_phy_copper(hw); 2016 2017 return; 2018} 2019 2020/** 2021 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 2022 * @hw: pointer to the HW structure 2023 * 2024 * Clears the hardware counters by reading the counter registers. 2025 **/ 2026static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 2027{ 2028 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 2029 2030 e1000_clear_hw_cntrs_base_generic(hw); 2031 2032 E1000_READ_REG(hw, E1000_PRC64); 2033 E1000_READ_REG(hw, E1000_PRC127); 2034 E1000_READ_REG(hw, E1000_PRC255); 2035 E1000_READ_REG(hw, E1000_PRC511); 2036 E1000_READ_REG(hw, E1000_PRC1023); 2037 E1000_READ_REG(hw, E1000_PRC1522); 2038 E1000_READ_REG(hw, E1000_PTC64); 2039 E1000_READ_REG(hw, E1000_PTC127); 2040 E1000_READ_REG(hw, E1000_PTC255); 2041 E1000_READ_REG(hw, E1000_PTC511); 2042 E1000_READ_REG(hw, E1000_PTC1023); 2043 E1000_READ_REG(hw, E1000_PTC1522); 2044 2045 E1000_READ_REG(hw, E1000_ALGNERRC); 2046 E1000_READ_REG(hw, E1000_RXERRC); 2047 E1000_READ_REG(hw, E1000_TNCRS); 2048 E1000_READ_REG(hw, E1000_CEXTERR); 2049 E1000_READ_REG(hw, E1000_TSCTC); 2050 E1000_READ_REG(hw, E1000_TSCTFC); 2051 2052 E1000_READ_REG(hw, E1000_MGTPRC); 2053 E1000_READ_REG(hw, E1000_MGTPDC); 2054 E1000_READ_REG(hw, E1000_MGTPTC); 2055 2056 E1000_READ_REG(hw, E1000_IAC); 2057 E1000_READ_REG(hw, E1000_ICRXOC); 2058 2059 E1000_READ_REG(hw, E1000_ICRXPTC); 2060 E1000_READ_REG(hw, E1000_ICRXATC); 2061 E1000_READ_REG(hw, E1000_ICTXPTC); 2062 E1000_READ_REG(hw, E1000_ICTXATC); 2063 E1000_READ_REG(hw, E1000_ICTXQEC); 2064 E1000_READ_REG(hw, E1000_ICTXQMTC); 2065 E1000_READ_REG(hw, E1000_ICRXDMTC); 2066} 2067